Merge branch 'remotes/lorenzo/pci/risc-v'
[linux-2.6-microblaze.git] / include / dt-bindings / clock / qcom,gcc-ipq806x.h
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4  */
5
6 #ifndef _DT_BINDINGS_CLK_GCC_IPQ806X_H
7 #define _DT_BINDINGS_CLK_GCC_IPQ806X_H
8
9 #define AFAB_CLK_SRC                            0
10 #define QDSS_STM_CLK                            1
11 #define SCSS_A_CLK                              2
12 #define SCSS_H_CLK                              3
13 #define AFAB_CORE_CLK                           4
14 #define SCSS_XO_SRC_CLK                         5
15 #define AFAB_EBI1_CH0_A_CLK                     6
16 #define AFAB_EBI1_CH1_A_CLK                     7
17 #define AFAB_AXI_S0_FCLK                        8
18 #define AFAB_AXI_S1_FCLK                        9
19 #define AFAB_AXI_S2_FCLK                        10
20 #define AFAB_AXI_S3_FCLK                        11
21 #define AFAB_AXI_S4_FCLK                        12
22 #define SFAB_CORE_CLK                           13
23 #define SFAB_AXI_S0_FCLK                        14
24 #define SFAB_AXI_S1_FCLK                        15
25 #define SFAB_AXI_S2_FCLK                        16
26 #define SFAB_AXI_S3_FCLK                        17
27 #define SFAB_AXI_S4_FCLK                        18
28 #define SFAB_AXI_S5_FCLK                        19
29 #define SFAB_AHB_S0_FCLK                        20
30 #define SFAB_AHB_S1_FCLK                        21
31 #define SFAB_AHB_S2_FCLK                        22
32 #define SFAB_AHB_S3_FCLK                        23
33 #define SFAB_AHB_S4_FCLK                        24
34 #define SFAB_AHB_S5_FCLK                        25
35 #define SFAB_AHB_S6_FCLK                        26
36 #define SFAB_AHB_S7_FCLK                        27
37 #define QDSS_AT_CLK_SRC                         28
38 #define QDSS_AT_CLK                             29
39 #define QDSS_TRACECLKIN_CLK_SRC                 30
40 #define QDSS_TRACECLKIN_CLK                     31
41 #define QDSS_TSCTR_CLK_SRC                      32
42 #define QDSS_TSCTR_CLK                          33
43 #define SFAB_ADM0_M0_A_CLK                      34
44 #define SFAB_ADM0_M1_A_CLK                      35
45 #define SFAB_ADM0_M2_H_CLK                      36
46 #define ADM0_CLK                                37
47 #define ADM0_PBUS_CLK                           38
48 #define IMEM0_A_CLK                             39
49 #define QDSS_H_CLK                              40
50 #define PCIE_A_CLK                              41
51 #define PCIE_AUX_CLK                            42
52 #define PCIE_H_CLK                              43
53 #define PCIE_PHY_CLK                            44
54 #define SFAB_CLK_SRC                            45
55 #define SFAB_LPASS_Q6_A_CLK                     46
56 #define SFAB_AFAB_M_A_CLK                       47
57 #define AFAB_SFAB_M0_A_CLK                      48
58 #define AFAB_SFAB_M1_A_CLK                      49
59 #define SFAB_SATA_S_H_CLK                       50
60 #define DFAB_CLK_SRC                            51
61 #define DFAB_CLK                                52
62 #define SFAB_DFAB_M_A_CLK                       53
63 #define DFAB_SFAB_M_A_CLK                       54
64 #define DFAB_SWAY0_H_CLK                        55
65 #define DFAB_SWAY1_H_CLK                        56
66 #define DFAB_ARB0_H_CLK                         57
67 #define DFAB_ARB1_H_CLK                         58
68 #define PPSS_H_CLK                              59
69 #define PPSS_PROC_CLK                           60
70 #define PPSS_TIMER0_CLK                         61
71 #define PPSS_TIMER1_CLK                         62
72 #define PMEM_A_CLK                              63
73 #define DMA_BAM_H_CLK                           64
74 #define SIC_H_CLK                               65
75 #define SPS_TIC_H_CLK                           66
76 #define CFPB_2X_CLK_SRC                         67
77 #define CFPB_CLK                                68
78 #define CFPB0_H_CLK                             69
79 #define CFPB1_H_CLK                             70
80 #define CFPB2_H_CLK                             71
81 #define SFAB_CFPB_M_H_CLK                       72
82 #define CFPB_MASTER_H_CLK                       73
83 #define SFAB_CFPB_S_H_CLK                       74
84 #define CFPB_SPLITTER_H_CLK                     75
85 #define TSIF_H_CLK                              76
86 #define TSIF_INACTIVITY_TIMERS_CLK              77
87 #define TSIF_REF_SRC                            78
88 #define TSIF_REF_CLK                            79
89 #define CE1_H_CLK                               80
90 #define CE1_CORE_CLK                            81
91 #define CE1_SLEEP_CLK                           82
92 #define CE2_H_CLK                               83
93 #define CE2_CORE_CLK                            84
94 #define SFPB_H_CLK_SRC                          85
95 #define SFPB_H_CLK                              86
96 #define SFAB_SFPB_M_H_CLK                       87
97 #define SFAB_SFPB_S_H_CLK                       88
98 #define RPM_PROC_CLK                            89
99 #define RPM_BUS_H_CLK                           90
100 #define RPM_SLEEP_CLK                           91
101 #define RPM_TIMER_CLK                           92
102 #define RPM_MSG_RAM_H_CLK                       93
103 #define PMIC_ARB0_H_CLK                         94
104 #define PMIC_ARB1_H_CLK                         95
105 #define PMIC_SSBI2_SRC                          96
106 #define PMIC_SSBI2_CLK                          97
107 #define SDC1_H_CLK                              98
108 #define SDC2_H_CLK                              99
109 #define SDC3_H_CLK                              100
110 #define SDC4_H_CLK                              101
111 #define SDC1_SRC                                102
112 #define SDC1_CLK                                103
113 #define SDC2_SRC                                104
114 #define SDC2_CLK                                105
115 #define SDC3_SRC                                106
116 #define SDC3_CLK                                107
117 #define SDC4_SRC                                108
118 #define SDC4_CLK                                109
119 #define USB_HS1_H_CLK                           110
120 #define USB_HS1_XCVR_SRC                        111
121 #define USB_HS1_XCVR_CLK                        112
122 #define USB_HSIC_H_CLK                          113
123 #define USB_HSIC_XCVR_SRC                       114
124 #define USB_HSIC_XCVR_CLK                       115
125 #define USB_HSIC_SYSTEM_CLK_SRC                 116
126 #define USB_HSIC_SYSTEM_CLK                     117
127 #define CFPB0_C0_H_CLK                          118
128 #define CFPB0_D0_H_CLK                          119
129 #define CFPB0_C1_H_CLK                          120
130 #define CFPB0_D1_H_CLK                          121
131 #define USB_FS1_H_CLK                           122
132 #define USB_FS1_XCVR_SRC                        123
133 #define USB_FS1_XCVR_CLK                        124
134 #define USB_FS1_SYSTEM_CLK                      125
135 #define GSBI_COMMON_SIM_SRC                     126
136 #define GSBI1_H_CLK                             127
137 #define GSBI2_H_CLK                             128
138 #define GSBI3_H_CLK                             129
139 #define GSBI4_H_CLK                             130
140 #define GSBI5_H_CLK                             131
141 #define GSBI6_H_CLK                             132
142 #define GSBI7_H_CLK                             133
143 #define GSBI1_QUP_SRC                           134
144 #define GSBI1_QUP_CLK                           135
145 #define GSBI2_QUP_SRC                           136
146 #define GSBI2_QUP_CLK                           137
147 #define GSBI3_QUP_SRC                           138
148 #define GSBI3_QUP_CLK                           139
149 #define GSBI4_QUP_SRC                           140
150 #define GSBI4_QUP_CLK                           141
151 #define GSBI5_QUP_SRC                           142
152 #define GSBI5_QUP_CLK                           143
153 #define GSBI6_QUP_SRC                           144
154 #define GSBI6_QUP_CLK                           145
155 #define GSBI7_QUP_SRC                           146
156 #define GSBI7_QUP_CLK                           147
157 #define GSBI1_UART_SRC                          148
158 #define GSBI1_UART_CLK                          149
159 #define GSBI2_UART_SRC                          150
160 #define GSBI2_UART_CLK                          151
161 #define GSBI3_UART_SRC                          152
162 #define GSBI3_UART_CLK                          153
163 #define GSBI4_UART_SRC                          154
164 #define GSBI4_UART_CLK                          155
165 #define GSBI5_UART_SRC                          156
166 #define GSBI5_UART_CLK                          157
167 #define GSBI6_UART_SRC                          158
168 #define GSBI6_UART_CLK                          159
169 #define GSBI7_UART_SRC                          160
170 #define GSBI7_UART_CLK                          161
171 #define GSBI1_SIM_CLK                           162
172 #define GSBI2_SIM_CLK                           163
173 #define GSBI3_SIM_CLK                           164
174 #define GSBI4_SIM_CLK                           165
175 #define GSBI5_SIM_CLK                           166
176 #define GSBI6_SIM_CLK                           167
177 #define GSBI7_SIM_CLK                           168
178 #define USB_HSIC_HSIC_CLK_SRC                   169
179 #define USB_HSIC_HSIC_CLK                       170
180 #define USB_HSIC_HSIO_CAL_CLK                   171
181 #define SPDM_CFG_H_CLK                          172
182 #define SPDM_MSTR_H_CLK                         173
183 #define SPDM_FF_CLK_SRC                         174
184 #define SPDM_FF_CLK                             175
185 #define SEC_CTRL_CLK                            176
186 #define SEC_CTRL_ACC_CLK_SRC                    177
187 #define SEC_CTRL_ACC_CLK                        178
188 #define TLMM_H_CLK                              179
189 #define TLMM_CLK                                180
190 #define SATA_H_CLK                              181
191 #define SATA_CLK_SRC                            182
192 #define SATA_RXOOB_CLK                          183
193 #define SATA_PMALIVE_CLK                        184
194 #define SATA_PHY_REF_CLK                        185
195 #define SATA_A_CLK                              186
196 #define SATA_PHY_CFG_CLK                        187
197 #define TSSC_CLK_SRC                            188
198 #define TSSC_CLK                                189
199 #define PDM_SRC                                 190
200 #define PDM_CLK                                 191
201 #define GP0_SRC                                 192
202 #define GP0_CLK                                 193
203 #define GP1_SRC                                 194
204 #define GP1_CLK                                 195
205 #define GP2_SRC                                 196
206 #define GP2_CLK                                 197
207 #define MPM_CLK                                 198
208 #define EBI1_CLK_SRC                            199
209 #define EBI1_CH0_CLK                            200
210 #define EBI1_CH1_CLK                            201
211 #define EBI1_2X_CLK                             202
212 #define EBI1_CH0_DQ_CLK                         203
213 #define EBI1_CH1_DQ_CLK                         204
214 #define EBI1_CH0_CA_CLK                         205
215 #define EBI1_CH1_CA_CLK                         206
216 #define EBI1_XO_CLK                             207
217 #define SFAB_SMPSS_S_H_CLK                      208
218 #define PRNG_SRC                                209
219 #define PRNG_CLK                                210
220 #define PXO_SRC                                 211
221 #define SPDM_CY_PORT0_CLK                       212
222 #define SPDM_CY_PORT1_CLK                       213
223 #define SPDM_CY_PORT2_CLK                       214
224 #define SPDM_CY_PORT3_CLK                       215
225 #define SPDM_CY_PORT4_CLK                       216
226 #define SPDM_CY_PORT5_CLK                       217
227 #define SPDM_CY_PORT6_CLK                       218
228 #define SPDM_CY_PORT7_CLK                       219
229 #define PLL0                                    220
230 #define PLL0_VOTE                               221
231 #define PLL3                                    222
232 #define PLL3_VOTE                               223
233 #define PLL4_VOTE                               225
234 #define PLL8                                    226
235 #define PLL8_VOTE                               227
236 #define PLL9                                    228
237 #define PLL10                                   229
238 #define PLL11                                   230
239 #define PLL12                                   231
240 #define PLL14                                   232
241 #define PLL14_VOTE                              233
242 #define PLL18                                   234
243 #define CE5_SRC                                 235
244 #define CE5_H_CLK                               236
245 #define CE5_CORE_CLK                            237
246 #define CE3_SLEEP_CLK                           238
247 #define SFAB_AHB_S8_FCLK                        239
248 #define SPDM_CY_PORT8_CLK                       246
249 #define PCIE_ALT_REF_SRC                        247
250 #define PCIE_ALT_REF_CLK                        248
251 #define PCIE_1_A_CLK                            249
252 #define PCIE_1_AUX_CLK                          250
253 #define PCIE_1_H_CLK                            251
254 #define PCIE_1_PHY_CLK                          252
255 #define PCIE_1_ALT_REF_SRC                      253
256 #define PCIE_1_ALT_REF_CLK                      254
257 #define PCIE_2_A_CLK                            255
258 #define PCIE_2_AUX_CLK                          256
259 #define PCIE_2_H_CLK                            257
260 #define PCIE_2_PHY_CLK                          258
261 #define PCIE_2_ALT_REF_SRC                      259
262 #define PCIE_2_ALT_REF_CLK                      260
263 #define EBI2_CLK                                261
264 #define USB30_SLEEP_CLK                         262
265 #define USB30_UTMI_SRC                          263
266 #define USB30_0_UTMI_CLK                        264
267 #define USB30_1_UTMI_CLK                        265
268 #define USB30_MASTER_SRC                        266
269 #define USB30_0_MASTER_CLK                      267
270 #define USB30_1_MASTER_CLK                      268
271 #define GMAC_CORE1_CLK_SRC                      269
272 #define GMAC_CORE2_CLK_SRC                      270
273 #define GMAC_CORE3_CLK_SRC                      271
274 #define GMAC_CORE4_CLK_SRC                      272
275 #define GMAC_CORE1_CLK                          273
276 #define GMAC_CORE2_CLK                          274
277 #define GMAC_CORE3_CLK                          275
278 #define GMAC_CORE4_CLK                          276
279 #define UBI32_CORE1_CLK_SRC                     277
280 #define UBI32_CORE2_CLK_SRC                     278
281 #define UBI32_CORE1_CLK                         279
282 #define UBI32_CORE2_CLK                         280
283 #define EBI2_AON_CLK                            281
284 #define NSSTCM_CLK_SRC                          282
285 #define NSSTCM_CLK                              283
286
287 #endif