2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Weiyi Lu <weiyi.lu@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #ifndef _DT_BINDINGS_CLK_MT2712_H
16 #define _DT_BINDINGS_CLK_MT2712_H
20 #define CLK_APMIXED_MAINPLL 0
21 #define CLK_APMIXED_UNIVPLL 1
22 #define CLK_APMIXED_VCODECPLL 2
23 #define CLK_APMIXED_VENCPLL 3
24 #define CLK_APMIXED_APLL1 4
25 #define CLK_APMIXED_APLL2 5
26 #define CLK_APMIXED_LVDSPLL 6
27 #define CLK_APMIXED_LVDSPLL2 7
28 #define CLK_APMIXED_MSDCPLL 8
29 #define CLK_APMIXED_MSDCPLL2 9
30 #define CLK_APMIXED_TVDPLL 10
31 #define CLK_APMIXED_MMPLL 11
32 #define CLK_APMIXED_ARMCA35PLL 12
33 #define CLK_APMIXED_ARMCA72PLL 13
34 #define CLK_APMIXED_ETHERPLL 14
35 #define CLK_APMIXED_NR_CLK 15
39 #define CLK_TOP_ARMCA35PLL 0
40 #define CLK_TOP_ARMCA35PLL_600M 1
41 #define CLK_TOP_ARMCA35PLL_400M 2
42 #define CLK_TOP_ARMCA72PLL 3
43 #define CLK_TOP_SYSPLL 4
44 #define CLK_TOP_SYSPLL_D2 5
45 #define CLK_TOP_SYSPLL1_D2 6
46 #define CLK_TOP_SYSPLL1_D4 7
47 #define CLK_TOP_SYSPLL1_D8 8
48 #define CLK_TOP_SYSPLL1_D16 9
49 #define CLK_TOP_SYSPLL_D3 10
50 #define CLK_TOP_SYSPLL2_D2 11
51 #define CLK_TOP_SYSPLL2_D4 12
52 #define CLK_TOP_SYSPLL_D5 13
53 #define CLK_TOP_SYSPLL3_D2 14
54 #define CLK_TOP_SYSPLL3_D4 15
55 #define CLK_TOP_SYSPLL_D7 16
56 #define CLK_TOP_SYSPLL4_D2 17
57 #define CLK_TOP_SYSPLL4_D4 18
58 #define CLK_TOP_UNIVPLL 19
59 #define CLK_TOP_UNIVPLL_D7 20
60 #define CLK_TOP_UNIVPLL_D26 21
61 #define CLK_TOP_UNIVPLL_D52 22
62 #define CLK_TOP_UNIVPLL_D104 23
63 #define CLK_TOP_UNIVPLL_D208 24
64 #define CLK_TOP_UNIVPLL_D2 25
65 #define CLK_TOP_UNIVPLL1_D2 26
66 #define CLK_TOP_UNIVPLL1_D4 27
67 #define CLK_TOP_UNIVPLL1_D8 28
68 #define CLK_TOP_UNIVPLL_D3 29
69 #define CLK_TOP_UNIVPLL2_D2 30
70 #define CLK_TOP_UNIVPLL2_D4 31
71 #define CLK_TOP_UNIVPLL2_D8 32
72 #define CLK_TOP_UNIVPLL_D5 33
73 #define CLK_TOP_UNIVPLL3_D2 34
74 #define CLK_TOP_UNIVPLL3_D4 35
75 #define CLK_TOP_UNIVPLL3_D8 36
76 #define CLK_TOP_F_MP0_PLL1 37
77 #define CLK_TOP_F_MP0_PLL2 38
78 #define CLK_TOP_F_BIG_PLL1 39
79 #define CLK_TOP_F_BIG_PLL2 40
80 #define CLK_TOP_F_BUS_PLL1 41
81 #define CLK_TOP_F_BUS_PLL2 42
82 #define CLK_TOP_APLL1 43
83 #define CLK_TOP_APLL1_D2 44
84 #define CLK_TOP_APLL1_D4 45
85 #define CLK_TOP_APLL1_D8 46
86 #define CLK_TOP_APLL1_D16 47
87 #define CLK_TOP_APLL2 48
88 #define CLK_TOP_APLL2_D2 49
89 #define CLK_TOP_APLL2_D4 50
90 #define CLK_TOP_APLL2_D8 51
91 #define CLK_TOP_APLL2_D16 52
92 #define CLK_TOP_LVDSPLL 53
93 #define CLK_TOP_LVDSPLL_D2 54
94 #define CLK_TOP_LVDSPLL_D4 55
95 #define CLK_TOP_LVDSPLL_D8 56
96 #define CLK_TOP_LVDSPLL2 57
97 #define CLK_TOP_LVDSPLL2_D2 58
98 #define CLK_TOP_LVDSPLL2_D4 59
99 #define CLK_TOP_LVDSPLL2_D8 60
100 #define CLK_TOP_ETHERPLL_125M 61
101 #define CLK_TOP_ETHERPLL_50M 62
102 #define CLK_TOP_CVBS 63
103 #define CLK_TOP_CVBS_D2 64
104 #define CLK_TOP_SYS_26M 65
105 #define CLK_TOP_MMPLL 66
106 #define CLK_TOP_MMPLL_D2 67
107 #define CLK_TOP_VENCPLL 68
108 #define CLK_TOP_VENCPLL_D2 69
109 #define CLK_TOP_VCODECPLL 70
110 #define CLK_TOP_VCODECPLL_D2 71
111 #define CLK_TOP_TVDPLL 72
112 #define CLK_TOP_TVDPLL_D2 73
113 #define CLK_TOP_TVDPLL_D4 74
114 #define CLK_TOP_TVDPLL_D8 75
115 #define CLK_TOP_TVDPLL_429M 76
116 #define CLK_TOP_TVDPLL_429M_D2 77
117 #define CLK_TOP_TVDPLL_429M_D4 78
118 #define CLK_TOP_MSDCPLL 79
119 #define CLK_TOP_MSDCPLL_D2 80
120 #define CLK_TOP_MSDCPLL_D4 81
121 #define CLK_TOP_MSDCPLL2 82
122 #define CLK_TOP_MSDCPLL2_D2 83
123 #define CLK_TOP_MSDCPLL2_D4 84
124 #define CLK_TOP_CLK26M_D2 85
125 #define CLK_TOP_D2A_ULCLK_6P5M 86
126 #define CLK_TOP_VPLL3_DPIX 87
127 #define CLK_TOP_VPLL_DPIX 88
128 #define CLK_TOP_LTEPLL_FS26M 89
129 #define CLK_TOP_DMPLL 90
130 #define CLK_TOP_DSI0_LNTC 91
131 #define CLK_TOP_DSI1_LNTC 92
132 #define CLK_TOP_LVDSTX3_CLKDIG_CTS 93
133 #define CLK_TOP_LVDSTX_CLKDIG_CTS 94
134 #define CLK_TOP_CLKRTC_EXT 95
135 #define CLK_TOP_CLKRTC_INT 96
136 #define CLK_TOP_CSI0 97
137 #define CLK_TOP_CVBSPLL 98
138 #define CLK_TOP_AXI_SEL 99
139 #define CLK_TOP_MEM_SEL 100
140 #define CLK_TOP_MM_SEL 101
141 #define CLK_TOP_PWM_SEL 102
142 #define CLK_TOP_VDEC_SEL 103
143 #define CLK_TOP_VENC_SEL 104
144 #define CLK_TOP_MFG_SEL 105
145 #define CLK_TOP_CAMTG_SEL 106
146 #define CLK_TOP_UART_SEL 107
147 #define CLK_TOP_SPI_SEL 108
148 #define CLK_TOP_USB20_SEL 109
149 #define CLK_TOP_USB30_SEL 110
150 #define CLK_TOP_MSDC50_0_HCLK_SEL 111
151 #define CLK_TOP_MSDC50_0_SEL 112
152 #define CLK_TOP_MSDC30_1_SEL 113
153 #define CLK_TOP_MSDC30_2_SEL 114
154 #define CLK_TOP_MSDC30_3_SEL 115
155 #define CLK_TOP_AUDIO_SEL 116
156 #define CLK_TOP_AUD_INTBUS_SEL 117
157 #define CLK_TOP_PMICSPI_SEL 118
158 #define CLK_TOP_DPILVDS1_SEL 119
159 #define CLK_TOP_ATB_SEL 120
160 #define CLK_TOP_NR_SEL 121
161 #define CLK_TOP_NFI2X_SEL 122
162 #define CLK_TOP_IRDA_SEL 123
163 #define CLK_TOP_CCI400_SEL 124
164 #define CLK_TOP_AUD_1_SEL 125
165 #define CLK_TOP_AUD_2_SEL 126
166 #define CLK_TOP_MEM_MFG_IN_AS_SEL 127
167 #define CLK_TOP_AXI_MFG_IN_AS_SEL 128
168 #define CLK_TOP_SCAM_SEL 129
169 #define CLK_TOP_NFIECC_SEL 130
170 #define CLK_TOP_PE2_MAC_P0_SEL 131
171 #define CLK_TOP_PE2_MAC_P1_SEL 132
172 #define CLK_TOP_DPILVDS_SEL 133
173 #define CLK_TOP_MSDC50_3_HCLK_SEL 134
174 #define CLK_TOP_HDCP_SEL 135
175 #define CLK_TOP_HDCP_24M_SEL 136
176 #define CLK_TOP_RTC_SEL 137
177 #define CLK_TOP_SPINOR_SEL 138
178 #define CLK_TOP_APLL_SEL 139
179 #define CLK_TOP_APLL2_SEL 140
180 #define CLK_TOP_A1SYS_HP_SEL 141
181 #define CLK_TOP_A2SYS_HP_SEL 142
182 #define CLK_TOP_ASM_L_SEL 143
183 #define CLK_TOP_ASM_M_SEL 144
184 #define CLK_TOP_ASM_H_SEL 145
185 #define CLK_TOP_I2SO1_SEL 146
186 #define CLK_TOP_I2SO2_SEL 147
187 #define CLK_TOP_I2SO3_SEL 148
188 #define CLK_TOP_TDMO0_SEL 149
189 #define CLK_TOP_TDMO1_SEL 150
190 #define CLK_TOP_I2SI1_SEL 151
191 #define CLK_TOP_I2SI2_SEL 152
192 #define CLK_TOP_I2SI3_SEL 153
193 #define CLK_TOP_ETHER_125M_SEL 154
194 #define CLK_TOP_ETHER_50M_SEL 155
195 #define CLK_TOP_JPGDEC_SEL 156
196 #define CLK_TOP_SPISLV_SEL 157
197 #define CLK_TOP_ETHER_50M_RMII_SEL 158
198 #define CLK_TOP_CAM2TG_SEL 159
199 #define CLK_TOP_DI_SEL 160
200 #define CLK_TOP_TVD_SEL 161
201 #define CLK_TOP_I2C_SEL 162
202 #define CLK_TOP_PWM_INFRA_SEL 163
203 #define CLK_TOP_MSDC0P_AES_SEL 164
204 #define CLK_TOP_CMSYS_SEL 165
205 #define CLK_TOP_GCPU_SEL 166
206 #define CLK_TOP_AUD_APLL1_SEL 167
207 #define CLK_TOP_AUD_APLL2_SEL 168
208 #define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL 169
209 #define CLK_TOP_APLL_DIV0 170
210 #define CLK_TOP_APLL_DIV1 171
211 #define CLK_TOP_APLL_DIV2 172
212 #define CLK_TOP_APLL_DIV3 173
213 #define CLK_TOP_APLL_DIV4 174
214 #define CLK_TOP_APLL_DIV5 175
215 #define CLK_TOP_APLL_DIV6 176
216 #define CLK_TOP_APLL_DIV7 177
217 #define CLK_TOP_APLL_DIV_PDN0 178
218 #define CLK_TOP_APLL_DIV_PDN1 179
219 #define CLK_TOP_APLL_DIV_PDN2 180
220 #define CLK_TOP_APLL_DIV_PDN3 181
221 #define CLK_TOP_APLL_DIV_PDN4 182
222 #define CLK_TOP_APLL_DIV_PDN5 183
223 #define CLK_TOP_APLL_DIV_PDN6 184
224 #define CLK_TOP_APLL_DIV_PDN7 185
225 #define CLK_TOP_APLL1_D3 186
226 #define CLK_TOP_APLL1_REF_SEL 187
227 #define CLK_TOP_APLL2_REF_SEL 188
228 #define CLK_TOP_NFI2X_EN 189
229 #define CLK_TOP_NFIECC_EN 190
230 #define CLK_TOP_NFI1X_CK_EN 191
231 #define CLK_TOP_APLL2_D3 192
232 #define CLK_TOP_NR_CLK 193
236 #define CLK_INFRA_DBGCLK 0
237 #define CLK_INFRA_GCE 1
238 #define CLK_INFRA_M4U 2
239 #define CLK_INFRA_KP 3
240 #define CLK_INFRA_AO_SPI0 4
241 #define CLK_INFRA_AO_SPI1 5
242 #define CLK_INFRA_AO_UART5 6
243 #define CLK_INFRA_NR_CLK 7
247 #define CLK_PERI_NFI 0
248 #define CLK_PERI_THERM 1
249 #define CLK_PERI_PWM0 2
250 #define CLK_PERI_PWM1 3
251 #define CLK_PERI_PWM2 4
252 #define CLK_PERI_PWM3 5
253 #define CLK_PERI_PWM4 6
254 #define CLK_PERI_PWM5 7
255 #define CLK_PERI_PWM6 8
256 #define CLK_PERI_PWM7 9
257 #define CLK_PERI_PWM 10
258 #define CLK_PERI_AP_DMA 11
259 #define CLK_PERI_MSDC30_0 12
260 #define CLK_PERI_MSDC30_1 13
261 #define CLK_PERI_MSDC30_2 14
262 #define CLK_PERI_MSDC30_3 15
263 #define CLK_PERI_UART0 16
264 #define CLK_PERI_UART1 17
265 #define CLK_PERI_UART2 18
266 #define CLK_PERI_UART3 19
267 #define CLK_PERI_I2C0 20
268 #define CLK_PERI_I2C1 21
269 #define CLK_PERI_I2C2 22
270 #define CLK_PERI_I2C3 23
271 #define CLK_PERI_I2C4 24
272 #define CLK_PERI_AUXADC 25
273 #define CLK_PERI_SPI0 26
274 #define CLK_PERI_SPI 27
275 #define CLK_PERI_I2C5 28
276 #define CLK_PERI_SPI2 29
277 #define CLK_PERI_SPI3 30
278 #define CLK_PERI_SPI5 31
279 #define CLK_PERI_UART4 32
280 #define CLK_PERI_SFLASH 33
281 #define CLK_PERI_GMAC 34
282 #define CLK_PERI_PCIE0 35
283 #define CLK_PERI_PCIE1 36
284 #define CLK_PERI_GMAC_PCLK 37
285 #define CLK_PERI_MSDC50_0_EN 38
286 #define CLK_PERI_MSDC30_1_EN 39
287 #define CLK_PERI_MSDC30_2_EN 40
288 #define CLK_PERI_MSDC30_3_EN 41
289 #define CLK_PERI_MSDC50_0_HCLK_EN 42
290 #define CLK_PERI_MSDC50_3_HCLK_EN 43
291 #define CLK_PERI_MSDC30_0_QTR_EN 44
292 #define CLK_PERI_MSDC30_3_QTR_EN 45
293 #define CLK_PERI_NR_CLK 46
297 #define CLK_MCU_MP0_SEL 0
298 #define CLK_MCU_MP2_SEL 1
299 #define CLK_MCU_BUS_SEL 2
300 #define CLK_MCU_NR_CLK 3
304 #define CLK_MFG_BG3D 0
305 #define CLK_MFG_NR_CLK 1
309 #define CLK_MM_SMI_COMMON 0
310 #define CLK_MM_SMI_LARB0 1
311 #define CLK_MM_CAM_MDP 2
312 #define CLK_MM_MDP_RDMA0 3
313 #define CLK_MM_MDP_RDMA1 4
314 #define CLK_MM_MDP_RSZ0 5
315 #define CLK_MM_MDP_RSZ1 6
316 #define CLK_MM_MDP_RSZ2 7
317 #define CLK_MM_MDP_TDSHP0 8
318 #define CLK_MM_MDP_TDSHP1 9
319 #define CLK_MM_MDP_CROP 10
320 #define CLK_MM_MDP_WDMA 11
321 #define CLK_MM_MDP_WROT0 12
322 #define CLK_MM_MDP_WROT1 13
323 #define CLK_MM_FAKE_ENG 14
324 #define CLK_MM_MUTEX_32K 15
325 #define CLK_MM_DISP_OVL0 16
326 #define CLK_MM_DISP_OVL1 17
327 #define CLK_MM_DISP_RDMA0 18
328 #define CLK_MM_DISP_RDMA1 19
329 #define CLK_MM_DISP_RDMA2 20
330 #define CLK_MM_DISP_WDMA0 21
331 #define CLK_MM_DISP_WDMA1 22
332 #define CLK_MM_DISP_COLOR0 23
333 #define CLK_MM_DISP_COLOR1 24
334 #define CLK_MM_DISP_AAL 25
335 #define CLK_MM_DISP_GAMMA 26
336 #define CLK_MM_DISP_UFOE 27
337 #define CLK_MM_DISP_SPLIT0 28
338 #define CLK_MM_DISP_OD 29
339 #define CLK_MM_DISP_PWM0_MM 30
340 #define CLK_MM_DISP_PWM0_26M 31
341 #define CLK_MM_DISP_PWM1_MM 32
342 #define CLK_MM_DISP_PWM1_26M 33
343 #define CLK_MM_DSI0_ENGINE 34
344 #define CLK_MM_DSI0_DIGITAL 35
345 #define CLK_MM_DSI1_ENGINE 36
346 #define CLK_MM_DSI1_DIGITAL 37
347 #define CLK_MM_DPI_PIXEL 38
348 #define CLK_MM_DPI_ENGINE 39
349 #define CLK_MM_DPI1_PIXEL 40
350 #define CLK_MM_DPI1_ENGINE 41
351 #define CLK_MM_LVDS_PIXEL 42
352 #define CLK_MM_LVDS_CTS 43
353 #define CLK_MM_SMI_LARB4 44
354 #define CLK_MM_SMI_COMMON1 45
355 #define CLK_MM_SMI_LARB5 46
356 #define CLK_MM_MDP_RDMA2 47
357 #define CLK_MM_MDP_TDSHP2 48
358 #define CLK_MM_DISP_OVL2 49
359 #define CLK_MM_DISP_WDMA2 50
360 #define CLK_MM_DISP_COLOR2 51
361 #define CLK_MM_DISP_AAL1 52
362 #define CLK_MM_DISP_OD1 53
363 #define CLK_MM_LVDS1_PIXEL 54
364 #define CLK_MM_LVDS1_CTS 55
365 #define CLK_MM_SMI_LARB7 56
366 #define CLK_MM_MDP_RDMA3 57
367 #define CLK_MM_MDP_WROT2 58
368 #define CLK_MM_DSI2 59
369 #define CLK_MM_DSI2_DIGITAL 60
370 #define CLK_MM_DSI3 61
371 #define CLK_MM_DSI3_DIGITAL 62
372 #define CLK_MM_NR_CLK 63
376 #define CLK_IMG_SMI_LARB2 0
377 #define CLK_IMG_SENINF_SCAM_EN 1
378 #define CLK_IMG_SENINF_CAM_EN 2
379 #define CLK_IMG_CAM_SV_EN 3
380 #define CLK_IMG_CAM_SV1_EN 4
381 #define CLK_IMG_CAM_SV2_EN 5
382 #define CLK_IMG_NR_CLK 6
386 #define CLK_BDP_BRIDGE_B 0
387 #define CLK_BDP_BRIDGE_DRAM 1
388 #define CLK_BDP_LARB_DRAM 2
389 #define CLK_BDP_WR_CHANNEL_VDI_PXL 3
390 #define CLK_BDP_WR_CHANNEL_VDI_DRAM 4
391 #define CLK_BDP_WR_CHANNEL_VDI_B 5
392 #define CLK_BDP_MT_B 6
393 #define CLK_BDP_DISPFMT_27M 7
394 #define CLK_BDP_DISPFMT_27M_VDOUT 8
395 #define CLK_BDP_DISPFMT_27_74_74 9
396 #define CLK_BDP_DISPFMT_2FS 10
397 #define CLK_BDP_DISPFMT_2FS_2FS74_148 11
398 #define CLK_BDP_DISPFMT_B 12
399 #define CLK_BDP_VDO_DRAM 13
400 #define CLK_BDP_VDO_2FS 14
401 #define CLK_BDP_VDO_B 15
402 #define CLK_BDP_WR_CHANNEL_DI_PXL 16
403 #define CLK_BDP_WR_CHANNEL_DI_DRAM 17
404 #define CLK_BDP_WR_CHANNEL_DI_B 18
405 #define CLK_BDP_NR_AGENT 19
406 #define CLK_BDP_NR_DRAM 20
407 #define CLK_BDP_NR_B 21
408 #define CLK_BDP_BRIDGE_RT_B 22
409 #define CLK_BDP_BRIDGE_RT_DRAM 23
410 #define CLK_BDP_LARB_RT_DRAM 24
411 #define CLK_BDP_TVD_TDC 25
412 #define CLK_BDP_TVD_54 26
413 #define CLK_BDP_TVD_CBUS 27
414 #define CLK_BDP_NR_CLK 28
418 #define CLK_VDEC_CKEN 0
419 #define CLK_VDEC_LARB1_CKEN 1
420 #define CLK_VDEC_IMGRZ_CKEN 2
421 #define CLK_VDEC_NR_CLK 3
425 #define CLK_VENC_SMI_COMMON_CON 0
426 #define CLK_VENC_VENC 1
427 #define CLK_VENC_SMI_LARB6 2
428 #define CLK_VENC_NR_CLK 3
432 #define CLK_JPGDEC_JPGDEC1 0
433 #define CLK_JPGDEC_JPGDEC 1
434 #define CLK_JPGDEC_NR_CLK 2
436 #endif /* _DT_BINDINGS_CLK_MT2712_H */