1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Dong Aisheng <aisheng.dong@nxp.com>
7 #ifndef __DT_BINDINGS_CLOCK_IMX_H
8 #define __DT_BINDINGS_CLOCK_IMX_H
12 #define IMX_CLK_DUMMY 0
18 #define IMX_LSIO_MEM_CLK 2
19 #define IMX_LSIO_BUS_CLK 3
20 #define IMX_LSIO_PWM0_CLK 10
21 #define IMX_LSIO_PWM1_CLK 11
22 #define IMX_LSIO_PWM2_CLK 12
23 #define IMX_LSIO_PWM3_CLK 13
24 #define IMX_LSIO_PWM4_CLK 14
25 #define IMX_LSIO_PWM5_CLK 15
26 #define IMX_LSIO_PWM6_CLK 16
27 #define IMX_LSIO_PWM7_CLK 17
28 #define IMX_LSIO_GPT0_CLK 18
29 #define IMX_LSIO_GPT1_CLK 19
30 #define IMX_LSIO_GPT2_CLK 20
31 #define IMX_LSIO_GPT3_CLK 21
32 #define IMX_LSIO_GPT4_CLK 22
33 #define IMX_LSIO_FSPI0_CLK 23
34 #define IMX_LSIO_FSPI1_CLK 24
37 #define IMX_CONN_AXI_CLK_ROOT 30
38 #define IMX_CONN_AHB_CLK_ROOT 31
39 #define IMX_CONN_IPG_CLK_ROOT 32
40 #define IMX_CONN_SDHC0_CLK 40
41 #define IMX_CONN_SDHC1_CLK 41
42 #define IMX_CONN_SDHC2_CLK 42
43 #define IMX_CONN_ENET0_ROOT_CLK 43
44 #define IMX_CONN_ENET0_BYPASS_CLK 44
45 #define IMX_CONN_ENET0_RGMII_CLK 45
46 #define IMX_CONN_ENET1_ROOT_CLK 46
47 #define IMX_CONN_ENET1_BYPASS_CLK 47
48 #define IMX_CONN_ENET1_RGMII_CLK 48
49 #define IMX_CONN_GPMI_BCH_IO_CLK 49
50 #define IMX_CONN_GPMI_BCH_CLK 50
51 #define IMX_CONN_USB2_ACLK 51
52 #define IMX_CONN_USB2_BUS_CLK 52
53 #define IMX_CONN_USB2_LPM_CLK 53
56 #define IMX_HSIO_AXI_CLK 60
57 #define IMX_HSIO_PER_CLK 61
59 /* Display controller SS */
60 #define IMX_DC_AXI_EXT_CLK 70
61 #define IMX_DC_AXI_INT_CLK 71
62 #define IMX_DC_CFG_CLK 72
63 #define IMX_DC0_PLL0_CLK 80
64 #define IMX_DC0_PLL1_CLK 81
65 #define IMX_DC0_DISP0_CLK 82
66 #define IMX_DC0_DISP1_CLK 83
67 #define IMX_DC0_BYPASS0_CLK 84
68 #define IMX_DC0_BYPASS1_CLK 85
71 #define IMX_MIPI_IPG_CLK 90
72 #define IMX_MIPI0_PIXEL_CLK 100
73 #define IMX_MIPI0_BYPASS_CLK 101
74 #define IMX_MIPI0_LVDS_PIXEL_CLK 102
75 #define IMX_MIPI0_LVDS_BYPASS_CLK 103
76 #define IMX_MIPI0_LVDS_PHY_CLK 104
77 #define IMX_MIPI0_I2C0_CLK 105
78 #define IMX_MIPI0_I2C1_CLK 106
79 #define IMX_MIPI0_PWM0_CLK 107
80 #define IMX_MIPI1_PIXEL_CLK 108
81 #define IMX_MIPI1_BYPASS_CLK 109
82 #define IMX_MIPI1_LVDS_PIXEL_CLK 110
83 #define IMX_MIPI1_LVDS_BYPASS_CLK 111
84 #define IMX_MIPI1_LVDS_PHY_CLK 112
85 #define IMX_MIPI1_I2C0_CLK 113
86 #define IMX_MIPI1_I2C1_CLK 114
87 #define IMX_MIPI1_PWM0_CLK 115
90 #define IMX_IMG_AXI_CLK 120
91 #define IMX_IMG_IPG_CLK 121
92 #define IMX_IMG_PXL_CLK 122
95 #define IMX_CSI0_CORE_CLK 130
96 #define IMX_CSI0_ESC_CLK 131
97 #define IMX_CSI0_PWM0_CLK 132
98 #define IMX_CSI0_I2C0_CLK 133
100 /* PARALLER CSI SS */
101 #define IMX_PARALLEL_CSI_DPLL_CLK 140
102 #define IMX_PARALLEL_CSI_PIXEL_CLK 141
103 #define IMX_PARALLEL_CSI_MCLK_CLK 142
106 #define IMX_VPU_ENC_CLK 150
107 #define IMX_VPU_DEC_CLK 151
110 #define IMX_GPU0_CORE_CLK 160
111 #define IMX_GPU0_SHADER_CLK 161
114 #define IMX_ADMA_IPG_CLK_ROOT 165
115 #define IMX_ADMA_UART0_CLK 170
116 #define IMX_ADMA_UART1_CLK 171
117 #define IMX_ADMA_UART2_CLK 172
118 #define IMX_ADMA_UART3_CLK 173
119 #define IMX_ADMA_SPI0_CLK 174
120 #define IMX_ADMA_SPI1_CLK 175
121 #define IMX_ADMA_SPI2_CLK 176
122 #define IMX_ADMA_SPI3_CLK 177
123 #define IMX_ADMA_CAN0_CLK 178
124 #define IMX_ADMA_CAN1_CLK 179
125 #define IMX_ADMA_CAN2_CLK 180
126 #define IMX_ADMA_I2C0_CLK 181
127 #define IMX_ADMA_I2C1_CLK 182
128 #define IMX_ADMA_I2C2_CLK 183
129 #define IMX_ADMA_I2C3_CLK 184
130 #define IMX_ADMA_FTM0_CLK 185
131 #define IMX_ADMA_FTM1_CLK 186
132 #define IMX_ADMA_ADC0_CLK 187
133 #define IMX_ADMA_PWM_CLK 188
134 #define IMX_ADMA_LCD_CLK 189
136 #define IMX_SCU_CLK_END 190
141 #define IMX_LSIO_LPCG_PWM0_IPG_CLK 0
142 #define IMX_LSIO_LPCG_PWM0_IPG_S_CLK 1
143 #define IMX_LSIO_LPCG_PWM0_IPG_HF_CLK 2
144 #define IMX_LSIO_LPCG_PWM0_IPG_SLV_CLK 3
145 #define IMX_LSIO_LPCG_PWM0_IPG_MSTR_CLK 4
146 #define IMX_LSIO_LPCG_PWM1_IPG_CLK 5
147 #define IMX_LSIO_LPCG_PWM1_IPG_S_CLK 6
148 #define IMX_LSIO_LPCG_PWM1_IPG_HF_CLK 7
149 #define IMX_LSIO_LPCG_PWM1_IPG_SLV_CLK 8
150 #define IMX_LSIO_LPCG_PWM1_IPG_MSTR_CLK 9
151 #define IMX_LSIO_LPCG_PWM2_IPG_CLK 10
152 #define IMX_LSIO_LPCG_PWM2_IPG_S_CLK 11
153 #define IMX_LSIO_LPCG_PWM2_IPG_HF_CLK 12
154 #define IMX_LSIO_LPCG_PWM2_IPG_SLV_CLK 13
155 #define IMX_LSIO_LPCG_PWM2_IPG_MSTR_CLK 14
156 #define IMX_LSIO_LPCG_PWM3_IPG_CLK 15
157 #define IMX_LSIO_LPCG_PWM3_IPG_S_CLK 16
158 #define IMX_LSIO_LPCG_PWM3_IPG_HF_CLK 17
159 #define IMX_LSIO_LPCG_PWM3_IPG_SLV_CLK 18
160 #define IMX_LSIO_LPCG_PWM3_IPG_MSTR_CLK 19
161 #define IMX_LSIO_LPCG_PWM4_IPG_CLK 20
162 #define IMX_LSIO_LPCG_PWM4_IPG_S_CLK 21
163 #define IMX_LSIO_LPCG_PWM4_IPG_HF_CLK 22
164 #define IMX_LSIO_LPCG_PWM4_IPG_SLV_CLK 23
165 #define IMX_LSIO_LPCG_PWM4_IPG_MSTR_CLK 24
166 #define IMX_LSIO_LPCG_PWM5_IPG_CLK 25
167 #define IMX_LSIO_LPCG_PWM5_IPG_S_CLK 26
168 #define IMX_LSIO_LPCG_PWM5_IPG_HF_CLK 27
169 #define IMX_LSIO_LPCG_PWM5_IPG_SLV_CLK 28
170 #define IMX_LSIO_LPCG_PWM5_IPG_MSTR_CLK 29
171 #define IMX_LSIO_LPCG_PWM6_IPG_CLK 30
172 #define IMX_LSIO_LPCG_PWM6_IPG_S_CLK 31
173 #define IMX_LSIO_LPCG_PWM6_IPG_HF_CLK 32
174 #define IMX_LSIO_LPCG_PWM6_IPG_SLV_CLK 33
175 #define IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK 34
176 #define IMX_LSIO_LPCG_PWM7_IPG_CLK 35
177 #define IMX_LSIO_LPCG_PWM7_IPG_S_CLK 36
178 #define IMX_LSIO_LPCG_PWM7_IPG_HF_CLK 37
179 #define IMX_LSIO_LPCG_PWM7_IPG_SLV_CLK 38
180 #define IMX_LSIO_LPCG_PWM7_IPG_MSTR_CLK 39
181 #define IMX_LSIO_LPCG_GPT0_IPG_CLK 40
182 #define IMX_LSIO_LPCG_GPT0_IPG_S_CLK 41
183 #define IMX_LSIO_LPCG_GPT0_IPG_HF_CLK 42
184 #define IMX_LSIO_LPCG_GPT0_IPG_SLV_CLK 43
185 #define IMX_LSIO_LPCG_GPT0_IPG_MSTR_CLK 44
186 #define IMX_LSIO_LPCG_GPT1_IPG_CLK 45
187 #define IMX_LSIO_LPCG_GPT1_IPG_S_CLK 46
188 #define IMX_LSIO_LPCG_GPT1_IPG_HF_CLK 47
189 #define IMX_LSIO_LPCG_GPT1_IPG_SLV_CLK 48
190 #define IMX_LSIO_LPCG_GPT1_IPG_MSTR_CLK 49
191 #define IMX_LSIO_LPCG_GPT2_IPG_CLK 50
192 #define IMX_LSIO_LPCG_GPT2_IPG_S_CLK 51
193 #define IMX_LSIO_LPCG_GPT2_IPG_HF_CLK 52
194 #define IMX_LSIO_LPCG_GPT2_IPG_SLV_CLK 53
195 #define IMX_LSIO_LPCG_GPT2_IPG_MSTR_CLK 54
196 #define IMX_LSIO_LPCG_GPT3_IPG_CLK 55
197 #define IMX_LSIO_LPCG_GPT3_IPG_S_CLK 56
198 #define IMX_LSIO_LPCG_GPT3_IPG_HF_CLK 57
199 #define IMX_LSIO_LPCG_GPT3_IPG_SLV_CLK 58
200 #define IMX_LSIO_LPCG_GPT3_IPG_MSTR_CLK 59
201 #define IMX_LSIO_LPCG_GPT4_IPG_CLK 60
202 #define IMX_LSIO_LPCG_GPT4_IPG_S_CLK 61
203 #define IMX_LSIO_LPCG_GPT4_IPG_HF_CLK 62
204 #define IMX_LSIO_LPCG_GPT4_IPG_SLV_CLK 63
205 #define IMX_LSIO_LPCG_GPT4_IPG_MSTR_CLK 64
206 #define IMX_LSIO_LPCG_FSPI0_HCLK 65
207 #define IMX_LSIO_LPCG_FSPI0_IPG_CLK 66
208 #define IMX_LSIO_LPCG_FSPI0_IPG_S_CLK 67
209 #define IMX_LSIO_LPCG_FSPI0_IPG_SFCK 68
210 #define IMX_LSIO_LPCG_FSPI1_HCLK 69
211 #define IMX_LSIO_LPCG_FSPI1_IPG_CLK 70
212 #define IMX_LSIO_LPCG_FSPI1_IPG_S_CLK 71
213 #define IMX_LSIO_LPCG_FSPI1_IPG_SFCK 72
215 #define IMX_LSIO_LPCG_CLK_END 73
217 /* Connectivity SS LPCG */
218 #define IMX_CONN_LPCG_SDHC0_IPG_CLK 0
219 #define IMX_CONN_LPCG_SDHC0_PER_CLK 1
220 #define IMX_CONN_LPCG_SDHC0_HCLK 2
221 #define IMX_CONN_LPCG_SDHC1_IPG_CLK 3
222 #define IMX_CONN_LPCG_SDHC1_PER_CLK 4
223 #define IMX_CONN_LPCG_SDHC1_HCLK 5
224 #define IMX_CONN_LPCG_SDHC2_IPG_CLK 6
225 #define IMX_CONN_LPCG_SDHC2_PER_CLK 7
226 #define IMX_CONN_LPCG_SDHC2_HCLK 8
227 #define IMX_CONN_LPCG_GPMI_APB_CLK 9
228 #define IMX_CONN_LPCG_GPMI_BCH_APB_CLK 10
229 #define IMX_CONN_LPCG_GPMI_BCH_IO_CLK 11
230 #define IMX_CONN_LPCG_GPMI_BCH_CLK 12
231 #define IMX_CONN_LPCG_APBHDMA_CLK 13
232 #define IMX_CONN_LPCG_ENET0_ROOT_CLK 14
233 #define IMX_CONN_LPCG_ENET0_TX_CLK 15
234 #define IMX_CONN_LPCG_ENET0_AHB_CLK 16
235 #define IMX_CONN_LPCG_ENET0_IPG_S_CLK 17
236 #define IMX_CONN_LPCG_ENET0_IPG_CLK 18
238 #define IMX_CONN_LPCG_ENET1_ROOT_CLK 19
239 #define IMX_CONN_LPCG_ENET1_TX_CLK 20
240 #define IMX_CONN_LPCG_ENET1_AHB_CLK 21
241 #define IMX_CONN_LPCG_ENET1_IPG_S_CLK 22
242 #define IMX_CONN_LPCG_ENET1_IPG_CLK 23
244 #define IMX_CONN_LPCG_CLK_END 24
247 #define IMX_ADMA_LPCG_UART0_IPG_CLK 0
248 #define IMX_ADMA_LPCG_UART0_BAUD_CLK 1
249 #define IMX_ADMA_LPCG_UART1_IPG_CLK 2
250 #define IMX_ADMA_LPCG_UART1_BAUD_CLK 3
251 #define IMX_ADMA_LPCG_UART2_IPG_CLK 4
252 #define IMX_ADMA_LPCG_UART2_BAUD_CLK 5
253 #define IMX_ADMA_LPCG_UART3_IPG_CLK 6
254 #define IMX_ADMA_LPCG_UART3_BAUD_CLK 7
255 #define IMX_ADMA_LPCG_SPI0_IPG_CLK 8
256 #define IMX_ADMA_LPCG_SPI1_IPG_CLK 9
257 #define IMX_ADMA_LPCG_SPI2_IPG_CLK 10
258 #define IMX_ADMA_LPCG_SPI3_IPG_CLK 11
259 #define IMX_ADMA_LPCG_SPI0_CLK 12
260 #define IMX_ADMA_LPCG_SPI1_CLK 13
261 #define IMX_ADMA_LPCG_SPI2_CLK 14
262 #define IMX_ADMA_LPCG_SPI3_CLK 15
263 #define IMX_ADMA_LPCG_CAN0_IPG_CLK 16
264 #define IMX_ADMA_LPCG_CAN0_IPG_PE_CLK 17
265 #define IMX_ADMA_LPCG_CAN0_IPG_CHI_CLK 18
266 #define IMX_ADMA_LPCG_CAN1_IPG_CLK 19
267 #define IMX_ADMA_LPCG_CAN1_IPG_PE_CLK 20
268 #define IMX_ADMA_LPCG_CAN1_IPG_CHI_CLK 21
269 #define IMX_ADMA_LPCG_CAN2_IPG_CLK 22
270 #define IMX_ADMA_LPCG_CAN2_IPG_PE_CLK 23
271 #define IMX_ADMA_LPCG_CAN2_IPG_CHI_CLK 24
272 #define IMX_ADMA_LPCG_I2C0_CLK 25
273 #define IMX_ADMA_LPCG_I2C1_CLK 26
274 #define IMX_ADMA_LPCG_I2C2_CLK 27
275 #define IMX_ADMA_LPCG_I2C3_CLK 28
276 #define IMX_ADMA_LPCG_I2C0_IPG_CLK 29
277 #define IMX_ADMA_LPCG_I2C1_IPG_CLK 30
278 #define IMX_ADMA_LPCG_I2C2_IPG_CLK 31
279 #define IMX_ADMA_LPCG_I2C3_IPG_CLK 32
280 #define IMX_ADMA_LPCG_FTM0_CLK 33
281 #define IMX_ADMA_LPCG_FTM1_CLK 34
282 #define IMX_ADMA_LPCG_FTM0_IPG_CLK 35
283 #define IMX_ADMA_LPCG_FTM1_IPG_CLK 36
284 #define IMX_ADMA_LPCG_PWM_HI_CLK 37
285 #define IMX_ADMA_LPCG_PWM_IPG_CLK 38
286 #define IMX_ADMA_LPCG_LCD_PIX_CLK 39
287 #define IMX_ADMA_LPCG_LCD_APB_CLK 40
288 #define IMX_ADMA_LPCG_DSP_ADB_CLK 41
289 #define IMX_ADMA_LPCG_DSP_IPG_CLK 42
290 #define IMX_ADMA_LPCG_DSP_CORE_CLK 43
291 #define IMX_ADMA_LPCG_OCRAM_IPG_CLK 44
293 #define IMX_ADMA_LPCG_CLK_END 45
295 #endif /* __DT_BINDINGS_CLOCK_IMX_H */