include/dt-bindings/clock/exynos7-clk.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   4  * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
   5  */
   6
   7 #ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
   8 #define _DT_BINDINGS_CLOCK_EXYNOS7_H
   9
  10 /* TOPC */
  11 #define DOUT_ACLK_PERIS                 1
  12 #define DOUT_SCLK_BUS0_PLL              2
  13 #define DOUT_SCLK_BUS1_PLL              3
  14 #define DOUT_SCLK_CC_PLL                4
  15 #define DOUT_SCLK_MFC_PLL               5
  16 #define DOUT_ACLK_CCORE_133             6
  17 #define DOUT_ACLK_MSCL_532              7
  18 #define ACLK_MSCL_532                   8
  19 #define DOUT_SCLK_AUD_PLL               9
  20 #define FOUT_AUD_PLL                    10
  21 #define SCLK_AUD_PLL                    11
  22 #define SCLK_MFC_PLL_B                  12
  23 #define SCLK_MFC_PLL_A                  13
  24 #define SCLK_BUS1_PLL_B                 14
  25 #define SCLK_BUS1_PLL_A                 15
  26 #define SCLK_BUS0_PLL_B                 16
  27 #define SCLK_BUS0_PLL_A                 17
  28 #define SCLK_CC_PLL_B                   18
  29 #define SCLK_CC_PLL_A                   19
  30 #define ACLK_CCORE_133                  20
  31 #define ACLK_PERIS_66                   21
  32 #define TOPC_NR_CLK                     22
  33
  34 /* TOP0 */
  35 #define DOUT_ACLK_PERIC1                1
  36 #define DOUT_ACLK_PERIC0                2
  37 #define CLK_SCLK_UART0                  3
  38 #define CLK_SCLK_UART1                  4
  39 #define CLK_SCLK_UART2                  5
  40 #define CLK_SCLK_UART3                  6
  41 #define CLK_SCLK_SPI0                   7
  42 #define CLK_SCLK_SPI1                   8
  43 #define CLK_SCLK_SPI2                   9
  44 #define CLK_SCLK_SPI3                   10
  45 #define CLK_SCLK_SPI4                   11
  46 #define CLK_SCLK_SPDIF                  12
  47 #define CLK_SCLK_PCM1                   13
  48 #define CLK_SCLK_I2S1                   14
  49 #define CLK_ACLK_PERIC0_66              15
  50 #define CLK_ACLK_PERIC1_66              16
  51 #define TOP0_NR_CLK                     17
  52
  53 /* TOP1 */
  54 #define DOUT_ACLK_FSYS1_200             1
  55 #define DOUT_ACLK_FSYS0_200             2
  56 #define DOUT_SCLK_MMC2                  3
  57 #define DOUT_SCLK_MMC1                  4
  58 #define DOUT_SCLK_MMC0                  5
  59 #define CLK_SCLK_MMC2                   6
  60 #define CLK_SCLK_MMC1                   7
  61 #define CLK_SCLK_MMC0                   8
  62 #define CLK_ACLK_FSYS0_200              9
  63 #define CLK_ACLK_FSYS1_200              10
  64 #define CLK_SCLK_PHY_FSYS1              11
  65 #define CLK_SCLK_PHY_FSYS1_26M          12
  66 #define MOUT_SCLK_UFSUNIPRO20           13
  67 #define DOUT_SCLK_UFSUNIPRO20           14
  68 #define CLK_SCLK_UFSUNIPRO20            15
  69 #define DOUT_SCLK_PHY_FSYS1             16
  70 #define DOUT_SCLK_PHY_FSYS1_26M         17
  71 #define TOP1_NR_CLK                     18
  72
  73 /* CCORE */
  74 #define PCLK_RTC                        1
  75 #define CCORE_NR_CLK                    2
  76
  77 /* PERIC0 */
  78 #define PCLK_UART0                      1
  79 #define SCLK_UART0                      2
  80 #define PCLK_HSI2C0                     3
  81 #define PCLK_HSI2C1                     4
  82 #define PCLK_HSI2C4                     5
  83 #define PCLK_HSI2C5                     6
  84 #define PCLK_HSI2C9                     7
  85 #define PCLK_HSI2C10                    8
  86 #define PCLK_HSI2C11                    9
  87 #define PCLK_PWM                        10
  88 #define SCLK_PWM                        11
  89 #define PCLK_ADCIF                      12
  90 #define PERIC0_NR_CLK                   13
  91
  92 /* PERIC1 */
  93 #define PCLK_UART1                      1
  94 #define PCLK_UART2                      2
  95 #define PCLK_UART3                      3
  96 #define SCLK_UART1                      4
  97 #define SCLK_UART2                      5
  98 #define SCLK_UART3                      6
  99 #define PCLK_HSI2C2                     7
 100 #define PCLK_HSI2C3                     8
 101 #define PCLK_HSI2C6                     9
 102 #define PCLK_HSI2C7                     10
 103 #define PCLK_HSI2C8                     11
 104 #define PCLK_SPI0                       12
 105 #define PCLK_SPI1                       13
 106 #define PCLK_SPI2                       14
 107 #define PCLK_SPI3                       15
 108 #define PCLK_SPI4                       16
 109 #define SCLK_SPI0                       17
 110 #define SCLK_SPI1                       18
 111 #define SCLK_SPI2                       19
 112 #define SCLK_SPI3                       20
 113 #define SCLK_SPI4                       21
 114 #define PCLK_I2S1                       22
 115 #define PCLK_PCM1                       23
 116 #define PCLK_SPDIF                      24
 117 #define SCLK_I2S1                       25
 118 #define SCLK_PCM1                       26
 119 #define SCLK_SPDIF                      27
 120 #define PERIC1_NR_CLK                   28
 121
 122 /* PERIS */
 123 #define PCLK_CHIPID                     1
 124 #define SCLK_CHIPID                     2
 125 #define PCLK_WDT                        3
 126 #define PCLK_TMU                        4
 127 #define SCLK_TMU                        5
 128 #define PERIS_NR_CLK                    6
 129
 130 /* FSYS0 */
 131 #define ACLK_MMC2                       1
 132 #define ACLK_AXIUS_USBDRD30X_FSYS0X     2
 133 #define ACLK_USBDRD300                  3
 134 #define SCLK_USBDRD300_SUSPENDCLK       4
 135 #define SCLK_USBDRD300_REFCLK           5
 136 #define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER          6
 137 #define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER             7
 138 #define OSCCLK_PHY_CLKOUT_USB30_PHY             8
 139 #define ACLK_PDMA0                      9
 140 #define ACLK_PDMA1                      10
 141 #define FSYS0_NR_CLK                    11
 142
 143 /* FSYS1 */
 144 #define ACLK_MMC1                       1
 145 #define ACLK_MMC0                       2
 146 #define PHYCLK_UFS20_TX0_SYMBOL         3
 147 #define PHYCLK_UFS20_RX0_SYMBOL         4
 148 #define PHYCLK_UFS20_RX1_SYMBOL         5
 149 #define ACLK_UFS20_LINK                 6
 150 #define SCLK_UFSUNIPRO20_USER           7
 151 #define PHYCLK_UFS20_RX1_SYMBOL_USER    8
 152 #define PHYCLK_UFS20_RX0_SYMBOL_USER    9
 153 #define PHYCLK_UFS20_TX0_SYMBOL_USER    10
 154 #define OSCCLK_PHY_CLKOUT_EMBEDDED_COMBO_PHY    11
 155 #define SCLK_COMBO_PHY_EMBEDDED_26M     12
 156 #define DOUT_PCLK_FSYS1                 13
 157 #define PCLK_GPIO_FSYS1                 14
 158 #define MOUT_FSYS1_PHYCLK_SEL1          15
 159 #define FSYS1_NR_CLK                    16
 160
 161 /* MSCL */
 162 #define USERMUX_ACLK_MSCL_532           1
 163 #define DOUT_PCLK_MSCL                  2
 164 #define ACLK_MSCL_0                     3
 165 #define ACLK_MSCL_1                     4
 166 #define ACLK_JPEG                       5
 167 #define ACLK_G2D                        6
 168 #define ACLK_LH_ASYNC_SI_MSCL_0         7
 169 #define ACLK_LH_ASYNC_SI_MSCL_1         8
 170 #define ACLK_AXI2ACEL_BRIDGE            9
 171 #define ACLK_XIU_MSCLX_0                10
 172 #define ACLK_XIU_MSCLX_1                11
 173 #define ACLK_QE_MSCL_0                  12
 174 #define ACLK_QE_MSCL_1                  13
 175 #define ACLK_QE_JPEG                    14
 176 #define ACLK_QE_G2D                     15
 177 #define ACLK_PPMU_MSCL_0                16
 178 #define ACLK_PPMU_MSCL_1                17
 179 #define ACLK_MSCLNP_133                 18
 180 #define ACLK_AHB2APB_MSCL0P             19
 181 #define ACLK_AHB2APB_MSCL1P             20
 182
 183 #define PCLK_MSCL_0                     21
 184 #define PCLK_MSCL_1                     22
 185 #define PCLK_JPEG                       23
 186 #define PCLK_G2D                        24
 187 #define PCLK_QE_MSCL_0                  25
 188 #define PCLK_QE_MSCL_1                  26
 189 #define PCLK_QE_JPEG                    27
 190 #define PCLK_QE_G2D                     28
 191 #define PCLK_PPMU_MSCL_0                29
 192 #define PCLK_PPMU_MSCL_1                30
 193 #define PCLK_AXI2ACEL_BRIDGE            31
 194 #define PCLK_PMU_MSCL                   32
 195 #define MSCL_NR_CLK                     33
 196
 197 /* AUD */
 198 #define SCLK_I2S                        1
 199 #define SCLK_PCM                        2
 200 #define PCLK_I2S                        3
 201 #define PCLK_PCM                        4
 202 #define ACLK_ADMA                       5
 203 #define AUD_NR_CLK                      6
 204 #endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */