1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
4 * Author: Andrzej Hajda <a.hajda@samsung.com>
6 * Device Tree binding constants for Exynos5420 clock controller.
9 #ifndef _DT_BINDINGS_CLOCK_EXYNOS_5420_H
10 #define _DT_BINDINGS_CLOCK_EXYNOS_5420_H
14 #define CLK_FOUT_APLL 2
15 #define CLK_FOUT_CPLL 3
16 #define CLK_FOUT_DPLL 4
17 #define CLK_FOUT_EPLL 5
18 #define CLK_FOUT_RPLL 6
19 #define CLK_FOUT_IPLL 7
20 #define CLK_FOUT_SPLL 8
21 #define CLK_FOUT_VPLL 9
22 #define CLK_FOUT_MPLL 10
23 #define CLK_FOUT_BPLL 11
24 #define CLK_FOUT_KPLL 12
25 #define CLK_ARM_CLK 13
26 #define CLK_KFC_CLK 14
28 /* gate for special clocks (sclk) */
29 #define CLK_SCLK_UART0 128
30 #define CLK_SCLK_UART1 129
31 #define CLK_SCLK_UART2 130
32 #define CLK_SCLK_UART3 131
33 #define CLK_SCLK_MMC0 132
34 #define CLK_SCLK_MMC1 133
35 #define CLK_SCLK_MMC2 134
36 #define CLK_SCLK_SPI0 135
37 #define CLK_SCLK_SPI1 136
38 #define CLK_SCLK_SPI2 137
39 #define CLK_SCLK_I2S1 138
40 #define CLK_SCLK_I2S2 139
41 #define CLK_SCLK_PCM1 140
42 #define CLK_SCLK_PCM2 141
43 #define CLK_SCLK_SPDIF 142
44 #define CLK_SCLK_HDMI 143
45 #define CLK_SCLK_PIXEL 144
46 #define CLK_SCLK_DP1 145
47 #define CLK_SCLK_MIPI1 146
48 #define CLK_SCLK_FIMD1 147
49 #define CLK_SCLK_MAUDIO0 148
50 #define CLK_SCLK_MAUPCM0 149
51 #define CLK_SCLK_USBD300 150
52 #define CLK_SCLK_USBD301 151
53 #define CLK_SCLK_USBPHY300 152
54 #define CLK_SCLK_USBPHY301 153
55 #define CLK_SCLK_UNIPRO 154
56 #define CLK_SCLK_PWM 155
57 #define CLK_SCLK_GSCL_WA 156
58 #define CLK_SCLK_GSCL_WB 157
59 #define CLK_SCLK_HDMIPHY 158
60 #define CLK_MAU_EPLL 159
61 #define CLK_SCLK_HSIC_12M 160
62 #define CLK_SCLK_MPHY_IXTAL24 161
77 #define CLK_I2C_HDMI 269
92 #define CLK_ACLK66_PSGEN 300
93 #define CLK_CHIPID 301
94 #define CLK_SYSREG 302
100 #define CLK_TZPC5 308
101 #define CLK_TZPC6 309
102 #define CLK_TZPC7 310
103 #define CLK_TZPC8 311
104 #define CLK_TZPC9 312
105 #define CLK_HDMI_CEC 313
106 #define CLK_SECKEY 314
111 #define CLK_TMU_GPU 319
112 #define CLK_PCLK66_GPIO 330
113 #define CLK_ACLK200_FSYS2 350
117 #define CLK_SROMC 354
119 #define CLK_ACLK200_FSYS 360
121 #define CLK_PDMA0 362
122 #define CLK_PDMA1 363
124 #define CLK_USBH20 365
125 #define CLK_USBD300 366
126 #define CLK_USBD301 367
127 #define CLK_ACLK400_MSCL 380
128 #define CLK_MSCL0 381
129 #define CLK_MSCL1 382
130 #define CLK_MSCL2 383
131 #define CLK_SMMU_MSCL0 384
132 #define CLK_SMMU_MSCL1 385
133 #define CLK_SMMU_MSCL2 386
134 #define CLK_ACLK333 400
136 #define CLK_SMMU_MFCL 402
137 #define CLK_SMMU_MFCR 403
138 #define CLK_ACLK200_DISP1 410
139 #define CLK_DSIM1 411
142 #define CLK_ACLK300_DISP1 420
143 #define CLK_FIMD1 421
144 #define CLK_SMMU_FIMD1M0 422
145 #define CLK_SMMU_FIMD1M1 423
146 #define CLK_ACLK166 430
147 #define CLK_MIXER 431
148 #define CLK_ACLK266 440
149 #define CLK_ROTATOR 441
150 #define CLK_MDMA1 442
151 #define CLK_SMMU_ROTATOR 443
152 #define CLK_SMMU_MDMA1 444
153 #define CLK_ACLK300_JPEG 450
155 #define CLK_JPEG2 452
156 #define CLK_SMMU_JPEG 453
157 #define CLK_SMMU_JPEG2 454
158 #define CLK_ACLK300_GSCL 460
159 #define CLK_SMMU_GSCL0 461
160 #define CLK_SMMU_GSCL1 462
161 #define CLK_GSCL_WA 463
162 #define CLK_GSCL_WB 464
163 #define CLK_GSCL0 465
164 #define CLK_GSCL1 466
165 #define CLK_FIMC_3AA 467
166 #define CLK_ACLK266_G2D 470
168 #define CLK_SLIM_SSS 472
169 #define CLK_MDMA0 473
170 #define CLK_ACLK333_G2D 480
172 #define CLK_ACLK333_432_GSCL 490
173 #define CLK_SMMU_3AA 491
174 #define CLK_SMMU_FIMCL0 492
175 #define CLK_SMMU_FIMCL1 493
176 #define CLK_SMMU_FIMCL3 494
177 #define CLK_FIMC_LITE3 495
178 #define CLK_FIMC_LITE0 496
179 #define CLK_FIMC_LITE1 497
180 #define CLK_ACLK_G3D 500
182 #define CLK_SMMU_MIXER 502
183 #define CLK_SMMU_G2D 503
184 #define CLK_SMMU_MDMA0 504
186 #define CLK_TOP_RTC 506
187 #define CLK_SCLK_UART_ISP 510
188 #define CLK_SCLK_SPI0_ISP 511
189 #define CLK_SCLK_SPI1_ISP 512
190 #define CLK_SCLK_PWM_ISP 513
191 #define CLK_SCLK_ISP_SENSOR0 514
192 #define CLK_SCLK_ISP_SENSOR1 515
193 #define CLK_SCLK_ISP_SENSOR2 516
194 #define CLK_ACLK432_SCALER 517
195 #define CLK_ACLK432_CAM 518
196 #define CLK_ACLK_FL1550_CAM 519
197 #define CLK_ACLK550_CAM 520
200 #define CLK_MOUT_HDMI 640
201 #define CLK_MOUT_G3D 641
202 #define CLK_MOUT_VPLL 642
203 #define CLK_MOUT_MAUDIO0 643
204 #define CLK_MOUT_USER_ACLK333 644
205 #define CLK_MOUT_SW_ACLK333 645
206 #define CLK_MOUT_USER_ACLK200_DISP1 646
207 #define CLK_MOUT_SW_ACLK200 647
208 #define CLK_MOUT_USER_ACLK300_DISP1 648
209 #define CLK_MOUT_SW_ACLK300 649
210 #define CLK_MOUT_USER_ACLK400_DISP1 650
211 #define CLK_MOUT_SW_ACLK400 651
212 #define CLK_MOUT_USER_ACLK300_GSCL 652
213 #define CLK_MOUT_SW_ACLK300_GSCL 653
214 #define CLK_MOUT_MCLK_CDREX 654
215 #define CLK_MOUT_BPLL 655
216 #define CLK_MOUT_MX_MSPLL_CCORE 656
217 #define CLK_MOUT_EPLL 657
218 #define CLK_MOUT_MAU_EPLL 658
219 #define CLK_MOUT_USER_MAU_EPLL 659
222 #define CLK_DOUT_PIXEL 768
223 #define CLK_DOUT_ACLK400_WCORE 769
224 #define CLK_DOUT_ACLK400_ISP 770
225 #define CLK_DOUT_ACLK400_MSCL 771
226 #define CLK_DOUT_ACLK200 772
227 #define CLK_DOUT_ACLK200_FSYS2 773
228 #define CLK_DOUT_ACLK100_NOC 774
229 #define CLK_DOUT_PCLK200_FSYS 775
230 #define CLK_DOUT_ACLK200_FSYS 776
231 #define CLK_DOUT_ACLK333_432_GSCL 777
232 #define CLK_DOUT_ACLK333_432_ISP 778
233 #define CLK_DOUT_ACLK66 779
234 #define CLK_DOUT_ACLK333_432_ISP0 780
235 #define CLK_DOUT_ACLK266 781
236 #define CLK_DOUT_ACLK166 782
237 #define CLK_DOUT_ACLK333 783
238 #define CLK_DOUT_ACLK333_G2D 784
239 #define CLK_DOUT_ACLK266_G2D 785
240 #define CLK_DOUT_ACLK_G3D 786
241 #define CLK_DOUT_ACLK300_JPEG 787
242 #define CLK_DOUT_ACLK300_DISP1 788
243 #define CLK_DOUT_ACLK300_GSCL 789
244 #define CLK_DOUT_ACLK400_DISP1 790
245 #define CLK_DOUT_PCLK_CDREX 791
246 #define CLK_DOUT_SCLK_CDREX 792
247 #define CLK_DOUT_ACLK_CDREX1 793
248 #define CLK_DOUT_CCLK_DREX0 794
249 #define CLK_DOUT_CLK2X_PHY0 795
250 #define CLK_DOUT_PCLK_CORE_MEM 796
252 /* must be greater than maximal clock id */
253 #define CLK_NR_CLKS 797
255 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */