1 #ifndef __ASM_MACH_APIC_H
2 #define __ASM_MACH_APIC_H
5 #include <linux/mmzone.h>
6 #include <linux/nodemask.h>
8 #define APIC_DFR_VALUE (APIC_DFR_CLUSTER)
10 static inline cpumask_t target_cpus(void)
15 #define TARGET_CPUS (target_cpus())
17 #define NO_BALANCE_IRQ (1)
18 #define esr_disable (1)
20 #define NO_IOAPIC_CHECK (0)
22 #define INT_DELIVERY_MODE dest_LowestPrio
23 #define INT_DEST_MODE 0 /* physical delivery on LOCAL quad */
25 #define check_apicid_used(bitmap, apicid) physid_isset(apicid, bitmap)
26 #define check_apicid_present(bit) physid_isset(bit, phys_cpu_present_map)
27 #define apicid_cluster(apicid) (apicid & 0xF0)
29 static inline int apic_id_registered(void)
34 static inline void init_apic_ldr(void)
36 /* Already done in NUMA-Q firmware */
39 static inline void clustered_apic_check(void)
41 printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
42 "NUMA-Q", nr_ioapics);
46 * Skip adding the timer int on secondary nodes, which causes
47 * a small but painful rift in the time-space continuum.
49 static inline int multi_timer_check(int apic, int irq)
51 return apic != 0 && irq == 0;
54 static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
56 /* We don't have a good way to do this yet - hack */
57 return physids_promote(0xFUL);
60 /* Mapping from cpu number to logical apicid */
61 extern u8 cpu_2_logical_apicid[];
62 static inline int cpu_to_logical_apicid(int cpu)
66 return (int)cpu_2_logical_apicid[cpu];
70 * Supporting over 60 cpus on NUMA-Q requires a locality-dependent
71 * cpu to APIC ID relation to properly interact with the intelligent
72 * mode of the cluster controller.
74 static inline int cpu_present_to_apicid(int mps_cpu)
77 return ((mps_cpu >> 2) << 4) | (1 << (mps_cpu & 0x3));
82 static inline int generate_logical_apicid(int quad, int phys_apicid)
84 return (quad << 4) + (phys_apicid ? phys_apicid << 1 : 1);
87 static inline int apicid_to_node(int logical_apicid)
89 return logical_apicid >> 4;
92 static inline physid_mask_t apicid_to_cpu_present(int logical_apicid)
94 int node = apicid_to_node(logical_apicid);
95 int cpu = __ffs(logical_apicid & 0xf);
97 return physid_mask_of_physid(cpu + 4*node);
100 static inline int mpc_apic_id(struct mpc_config_processor *m,
101 struct mpc_config_translation *translation_record)
103 int quad = translation_record->trans_quad;
104 int logical_apicid = generate_logical_apicid(quad, m->mpc_apicid);
106 printk("Processor #%d %ld:%ld APIC version %d (quad %d, apic %d)\n",
108 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
109 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
110 m->mpc_apicver, quad, logical_apicid);
111 return logical_apicid;
114 static inline void setup_portio_remap(void)
116 int num_quads = num_online_nodes();
121 printk("Remapping cross-quad port I/O for %d quads\n", num_quads);
122 xquad_portio = ioremap(XQUAD_PORTIO_BASE, num_quads*XQUAD_PORTIO_QUAD);
123 printk("xquad_portio vaddr 0x%08lx, len %08lx\n",
124 (u_long) xquad_portio, (u_long) num_quads*XQUAD_PORTIO_QUAD);
127 static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
132 static inline void enable_apic_mode(void)
137 * We use physical apicids here, not logical, so just return the default
138 * physical broadcast to stop people from breaking us
140 static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
145 /* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */
146 static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
148 return cpuid_apic >> index_msb;
151 #endif /* __ASM_MACH_APIC_H */