1 // SPDX-License-Identifier: GPL-2.0
3 * Watchdog driver for Renesas WDT watchdog
5 * Copyright (C) 2015-17 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
6 * Copyright (C) 2015-17 Renesas Electronics Corporation
8 #include <linux/bitops.h>
10 #include <linux/delay.h>
12 #include <linux/iopoll.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/smp.h>
19 #include <linux/sys_soc.h>
20 #include <linux/watchdog.h>
24 #define RWTCSRA_WOVF BIT(4)
25 #define RWTCSRA_WRFLG BIT(5)
26 #define RWTCSRA_TME BIT(7)
29 #define RWDT_DEFAULT_TIMEOUT 60U
32 * In probe, clk_rate is checked to be not more than 16 bit * biggest clock
33 * divider (12 bits). d is only a factor to fully utilize the WDT counter and
34 * will not exceed its 16 bits. Thus, no overflow, we stay below 32 bits.
36 #define MUL_BY_CLKS_PER_SEC(p, d) \
37 DIV_ROUND_UP((d) * (p)->clk_rate, clk_divs[(p)->cks])
39 /* d is 16 bit, clk_divs 12 bit -> no 32 bit overflow */
40 #define DIV_BY_CLKS_PER_SEC(p, d) ((d) * clk_divs[(p)->cks] / (p)->clk_rate)
42 static const unsigned int clk_divs[] = { 1, 4, 16, 32, 64, 128, 1024, 4096 };
44 static bool nowayout = WATCHDOG_NOWAYOUT;
45 module_param(nowayout, bool, 0);
46 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
47 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
51 struct watchdog_device wdev;
52 unsigned long clk_rate;
57 static void rwdt_write(struct rwdt_priv *priv, u32 val, unsigned int reg)
64 writel_relaxed(val, priv->base + reg);
67 static int rwdt_init_timeout(struct watchdog_device *wdev)
69 struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
71 rwdt_write(priv, 65536 - MUL_BY_CLKS_PER_SEC(priv, wdev->timeout), RWTCNT);
76 static void rwdt_wait_cycles(struct rwdt_priv *priv, unsigned int cycles)
80 delay = DIV_ROUND_UP(cycles * 1000000, priv->clk_rate);
82 usleep_range(delay, 2 * delay);
85 static int rwdt_start(struct watchdog_device *wdev)
87 struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
90 pm_runtime_get_sync(wdev->parent);
92 /* Stop the timer before we modify any register */
93 val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
94 rwdt_write(priv, val, RWTCSRA);
95 /* Delay 2 cycles before setting watchdog counter */
96 rwdt_wait_cycles(priv, 2);
98 rwdt_init_timeout(wdev);
99 rwdt_write(priv, priv->cks, RWTCSRA);
100 rwdt_write(priv, 0, RWTCSRB);
102 while (readb_relaxed(priv->base + RWTCSRA) & RWTCSRA_WRFLG)
105 rwdt_write(priv, priv->cks | RWTCSRA_TME, RWTCSRA);
110 static int rwdt_stop(struct watchdog_device *wdev)
112 struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
114 rwdt_write(priv, priv->cks, RWTCSRA);
115 /* Delay 3 cycles before disabling module clock */
116 rwdt_wait_cycles(priv, 3);
117 pm_runtime_put(wdev->parent);
122 static unsigned int rwdt_get_timeleft(struct watchdog_device *wdev)
124 struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
125 u16 val = readw_relaxed(priv->base + RWTCNT);
127 return DIV_BY_CLKS_PER_SEC(priv, 65536 - val);
130 /* needs to be atomic - no RPM, no usleep_range, no scheduling! */
131 static int rwdt_restart(struct watchdog_device *wdev, unsigned long action,
134 struct rwdt_priv *priv = watchdog_get_drvdata(wdev);
137 clk_prepare_enable(priv->clk);
139 /* Stop the timer before we modify any register */
140 val = readb_relaxed(priv->base + RWTCSRA) & ~RWTCSRA_TME;
141 rwdt_write(priv, val, RWTCSRA);
142 /* Delay 2 cycles before setting watchdog counter */
143 udelay(DIV_ROUND_UP(2 * 1000000, priv->clk_rate));
145 rwdt_write(priv, 0xffff, RWTCNT);
146 /* smallest divider to reboot soon */
147 rwdt_write(priv, 0, RWTCSRA);
149 readb_poll_timeout_atomic(priv->base + RWTCSRA, val,
150 !(val & RWTCSRA_WRFLG), 1, 100);
152 rwdt_write(priv, RWTCSRA_TME, RWTCSRA);
154 /* wait 2 cycles, so watchdog will trigger */
155 udelay(DIV_ROUND_UP(2 * 1000000, priv->clk_rate));
160 static const struct watchdog_info rwdt_ident = {
161 .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
163 .identity = "Renesas WDT Watchdog",
166 static const struct watchdog_ops rwdt_ops = {
167 .owner = THIS_MODULE,
170 .ping = rwdt_init_timeout,
171 .get_timeleft = rwdt_get_timeleft,
172 .restart = rwdt_restart,
175 #if defined(CONFIG_ARCH_RCAR_GEN2) && defined(CONFIG_SMP)
177 * Watchdog-reset integration is broken on early revisions of R-Car Gen2 SoCs
179 static const struct soc_device_attribute rwdt_quirks_match[] = {
183 .data = (void *)1, /* needs single CPU */
187 .data = (void *)1, /* needs single CPU */
190 .data = (void *)0, /* needs SMP disabled */
195 static bool rwdt_blacklisted(struct device *dev)
197 const struct soc_device_attribute *attr;
199 attr = soc_device_match(rwdt_quirks_match);
200 if (attr && setup_max_cpus > (uintptr_t)attr->data) {
201 dev_info(dev, "Watchdog blacklisted on %s %s\n", attr->soc_id,
208 #else /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */
209 static inline bool rwdt_blacklisted(struct device *dev) { return false; }
210 #endif /* !CONFIG_ARCH_RCAR_GEN2 || !CONFIG_SMP */
212 static int rwdt_probe(struct platform_device *pdev)
214 struct device *dev = &pdev->dev;
215 struct rwdt_priv *priv;
216 unsigned long clks_per_sec;
220 if (rwdt_blacklisted(dev))
223 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
227 priv->base = devm_platform_ioremap_resource(pdev, 0);
228 if (IS_ERR(priv->base))
229 return PTR_ERR(priv->base);
231 priv->clk = devm_clk_get(dev, NULL);
232 if (IS_ERR(priv->clk))
233 return PTR_ERR(priv->clk);
235 pm_runtime_enable(dev);
236 pm_runtime_get_sync(dev);
237 priv->clk_rate = clk_get_rate(priv->clk);
238 csra = readb_relaxed(priv->base + RWTCSRA);
239 priv->wdev.bootstatus = csra & RWTCSRA_WOVF ? WDIOF_CARDRESET : 0;
242 if (!priv->clk_rate) {
247 for (i = ARRAY_SIZE(clk_divs) - 1; i >= 0; i--) {
248 clks_per_sec = priv->clk_rate / clk_divs[i];
249 if (clks_per_sec && clks_per_sec < 65536) {
256 dev_err(dev, "Can't find suitable clock divider\n");
261 priv->wdev.info = &rwdt_ident;
262 priv->wdev.ops = &rwdt_ops;
263 priv->wdev.parent = dev;
264 priv->wdev.min_timeout = 1;
265 priv->wdev.max_timeout = DIV_BY_CLKS_PER_SEC(priv, 65536);
266 priv->wdev.timeout = min(priv->wdev.max_timeout, RWDT_DEFAULT_TIMEOUT);
268 platform_set_drvdata(pdev, priv);
269 watchdog_set_drvdata(&priv->wdev, priv);
270 watchdog_set_nowayout(&priv->wdev, nowayout);
271 watchdog_set_restart_priority(&priv->wdev, 0);
272 watchdog_stop_on_unregister(&priv->wdev);
274 /* This overrides the default timeout only if DT configuration was found */
275 watchdog_init_timeout(&priv->wdev, 0, dev);
277 /* Check if FW enabled the watchdog */
278 if (csra & RWTCSRA_TME) {
279 /* Ensure properly initialized dividers */
280 rwdt_start(&priv->wdev);
281 set_bit(WDOG_HW_RUNNING, &priv->wdev.status);
284 ret = watchdog_register_device(&priv->wdev);
291 pm_runtime_disable(dev);
295 static int rwdt_remove(struct platform_device *pdev)
297 struct rwdt_priv *priv = platform_get_drvdata(pdev);
299 watchdog_unregister_device(&priv->wdev);
300 pm_runtime_disable(&pdev->dev);
305 static int __maybe_unused rwdt_suspend(struct device *dev)
307 struct rwdt_priv *priv = dev_get_drvdata(dev);
309 if (watchdog_active(&priv->wdev))
310 rwdt_stop(&priv->wdev);
315 static int __maybe_unused rwdt_resume(struct device *dev)
317 struct rwdt_priv *priv = dev_get_drvdata(dev);
319 if (watchdog_active(&priv->wdev))
320 rwdt_start(&priv->wdev);
325 static SIMPLE_DEV_PM_OPS(rwdt_pm_ops, rwdt_suspend, rwdt_resume);
327 static const struct of_device_id rwdt_ids[] = {
328 { .compatible = "renesas,rcar-gen2-wdt", },
329 { .compatible = "renesas,rcar-gen3-wdt", },
332 MODULE_DEVICE_TABLE(of, rwdt_ids);
334 static struct platform_driver rwdt_driver = {
336 .name = "renesas_wdt",
337 .of_match_table = rwdt_ids,
341 .remove = rwdt_remove,
343 module_platform_driver(rwdt_driver);
345 MODULE_DESCRIPTION("Renesas WDT Watchdog Driver");
346 MODULE_LICENSE("GPL v2");
347 MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");