1 // SPDX-License-Identifier: GPL-2.0+
3 * Mediatek Watchdog Driver
5 * Copyright (C) 2014 Matthias Brugger
7 * Matthias Brugger <matthias.bgg@gmail.com>
12 #include <dt-bindings/reset-controller/mt2712-resets.h>
13 #include <dt-bindings/reset-controller/mt8183-resets.h>
14 #include <dt-bindings/reset-controller/mt8192-resets.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
23 #include <linux/of_device.h>
24 #include <linux/platform_device.h>
25 #include <linux/reset-controller.h>
26 #include <linux/types.h>
27 #include <linux/watchdog.h>
28 #include <linux/interrupt.h>
30 #define WDT_MAX_TIMEOUT 31
31 #define WDT_MIN_TIMEOUT 2
32 #define WDT_LENGTH_TIMEOUT(n) ((n) << 5)
34 #define WDT_LENGTH 0x04
35 #define WDT_LENGTH_KEY 0x8
38 #define WDT_RST_RELOAD 0x1971
41 #define WDT_MODE_EN (1 << 0)
42 #define WDT_MODE_EXT_POL_LOW (0 << 1)
43 #define WDT_MODE_EXT_POL_HIGH (1 << 1)
44 #define WDT_MODE_EXRST_EN (1 << 2)
45 #define WDT_MODE_IRQ_EN (1 << 3)
46 #define WDT_MODE_AUTO_START (1 << 4)
47 #define WDT_MODE_DUAL_EN (1 << 6)
48 #define WDT_MODE_KEY 0x22000000
50 #define WDT_SWRST 0x14
51 #define WDT_SWRST_KEY 0x1209
53 #define WDT_SWSYSRST 0x18U
54 #define WDT_SWSYS_RST_KEY 0x88000000
56 #define DRV_NAME "mtk-wdt"
57 #define DRV_VERSION "1.0"
59 static bool nowayout = WATCHDOG_NOWAYOUT;
60 static unsigned int timeout;
63 struct watchdog_device wdt_dev;
64 void __iomem *wdt_base;
65 spinlock_t lock; /* protects WDT_SWSYSRST reg */
66 struct reset_controller_dev rcdev;
70 int toprgu_sw_rst_num;
73 static const struct mtk_wdt_data mt2712_data = {
74 .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM,
77 static const struct mtk_wdt_data mt8183_data = {
78 .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
81 static const struct mtk_wdt_data mt8192_data = {
82 .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM,
85 static int toprgu_reset_update(struct reset_controller_dev *rcdev,
86 unsigned long id, bool assert)
90 struct mtk_wdt_dev *data =
91 container_of(rcdev, struct mtk_wdt_dev, rcdev);
93 spin_lock_irqsave(&data->lock, flags);
95 tmp = readl(data->wdt_base + WDT_SWSYSRST);
100 tmp |= WDT_SWSYS_RST_KEY;
101 writel(tmp, data->wdt_base + WDT_SWSYSRST);
103 spin_unlock_irqrestore(&data->lock, flags);
108 static int toprgu_reset_assert(struct reset_controller_dev *rcdev,
111 return toprgu_reset_update(rcdev, id, true);
114 static int toprgu_reset_deassert(struct reset_controller_dev *rcdev,
117 return toprgu_reset_update(rcdev, id, false);
120 static int toprgu_reset(struct reset_controller_dev *rcdev,
125 ret = toprgu_reset_assert(rcdev, id);
129 return toprgu_reset_deassert(rcdev, id);
132 static const struct reset_control_ops toprgu_reset_ops = {
133 .assert = toprgu_reset_assert,
134 .deassert = toprgu_reset_deassert,
135 .reset = toprgu_reset,
138 static int toprgu_register_reset_controller(struct platform_device *pdev,
142 struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
144 spin_lock_init(&mtk_wdt->lock);
146 mtk_wdt->rcdev.owner = THIS_MODULE;
147 mtk_wdt->rcdev.nr_resets = rst_num;
148 mtk_wdt->rcdev.ops = &toprgu_reset_ops;
149 mtk_wdt->rcdev.of_node = pdev->dev.of_node;
150 ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev);
153 "couldn't register wdt reset controller: %d\n", ret);
157 static int mtk_wdt_restart(struct watchdog_device *wdt_dev,
158 unsigned long action, void *data)
160 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
161 void __iomem *wdt_base;
163 wdt_base = mtk_wdt->wdt_base;
166 writel(WDT_SWRST_KEY, wdt_base + WDT_SWRST);
173 static int mtk_wdt_ping(struct watchdog_device *wdt_dev)
175 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
176 void __iomem *wdt_base = mtk_wdt->wdt_base;
178 iowrite32(WDT_RST_RELOAD, wdt_base + WDT_RST);
183 static int mtk_wdt_set_timeout(struct watchdog_device *wdt_dev,
184 unsigned int timeout)
186 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
187 void __iomem *wdt_base = mtk_wdt->wdt_base;
190 wdt_dev->timeout = timeout;
192 * In dual mode, irq will be triggered at timeout / 2
193 * the real timeout occurs at timeout
195 if (wdt_dev->pretimeout)
196 wdt_dev->pretimeout = timeout / 2;
199 * One bit is the value of 512 ticks
200 * The clock has 32 KHz
202 reg = WDT_LENGTH_TIMEOUT((timeout - wdt_dev->pretimeout) << 6)
204 iowrite32(reg, wdt_base + WDT_LENGTH);
206 mtk_wdt_ping(wdt_dev);
211 static void mtk_wdt_init(struct watchdog_device *wdt_dev)
213 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
214 void __iomem *wdt_base;
216 wdt_base = mtk_wdt->wdt_base;
218 if (readl(wdt_base + WDT_MODE) & WDT_MODE_EN) {
219 set_bit(WDOG_HW_RUNNING, &wdt_dev->status);
220 mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
224 static int mtk_wdt_stop(struct watchdog_device *wdt_dev)
226 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
227 void __iomem *wdt_base = mtk_wdt->wdt_base;
230 reg = readl(wdt_base + WDT_MODE);
233 iowrite32(reg, wdt_base + WDT_MODE);
238 static int mtk_wdt_start(struct watchdog_device *wdt_dev)
241 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
242 void __iomem *wdt_base = mtk_wdt->wdt_base;
245 ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
249 reg = ioread32(wdt_base + WDT_MODE);
250 if (wdt_dev->pretimeout)
251 reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
253 reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
254 reg |= (WDT_MODE_EN | WDT_MODE_KEY);
255 iowrite32(reg, wdt_base + WDT_MODE);
260 static int mtk_wdt_set_pretimeout(struct watchdog_device *wdd,
261 unsigned int timeout)
263 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdd);
264 void __iomem *wdt_base = mtk_wdt->wdt_base;
265 u32 reg = ioread32(wdt_base + WDT_MODE);
267 if (timeout && !wdd->pretimeout) {
268 wdd->pretimeout = wdd->timeout / 2;
269 reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
270 } else if (!timeout && wdd->pretimeout) {
272 reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
278 iowrite32(reg, wdt_base + WDT_MODE);
280 return mtk_wdt_set_timeout(wdd, wdd->timeout);
283 static irqreturn_t mtk_wdt_isr(int irq, void *arg)
285 struct watchdog_device *wdd = arg;
287 watchdog_notify_pretimeout(wdd);
292 static const struct watchdog_info mtk_wdt_info = {
293 .identity = DRV_NAME,
294 .options = WDIOF_SETTIMEOUT |
295 WDIOF_KEEPALIVEPING |
299 static const struct watchdog_info mtk_wdt_pt_info = {
300 .identity = DRV_NAME,
301 .options = WDIOF_SETTIMEOUT |
303 WDIOF_KEEPALIVEPING |
307 static const struct watchdog_ops mtk_wdt_ops = {
308 .owner = THIS_MODULE,
309 .start = mtk_wdt_start,
310 .stop = mtk_wdt_stop,
311 .ping = mtk_wdt_ping,
312 .set_timeout = mtk_wdt_set_timeout,
313 .set_pretimeout = mtk_wdt_set_pretimeout,
314 .restart = mtk_wdt_restart,
317 static int mtk_wdt_probe(struct platform_device *pdev)
319 struct device *dev = &pdev->dev;
320 struct mtk_wdt_dev *mtk_wdt;
321 const struct mtk_wdt_data *wdt_data;
324 mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL);
328 platform_set_drvdata(pdev, mtk_wdt);
330 mtk_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0);
331 if (IS_ERR(mtk_wdt->wdt_base))
332 return PTR_ERR(mtk_wdt->wdt_base);
334 irq = platform_get_irq(pdev, 0);
336 err = devm_request_irq(&pdev->dev, irq, mtk_wdt_isr, 0, "wdt_bark",
341 mtk_wdt->wdt_dev.info = &mtk_wdt_pt_info;
342 mtk_wdt->wdt_dev.pretimeout = WDT_MAX_TIMEOUT / 2;
344 if (irq == -EPROBE_DEFER)
345 return -EPROBE_DEFER;
347 mtk_wdt->wdt_dev.info = &mtk_wdt_info;
350 mtk_wdt->wdt_dev.ops = &mtk_wdt_ops;
351 mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;
352 mtk_wdt->wdt_dev.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT * 1000;
353 mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;
354 mtk_wdt->wdt_dev.parent = dev;
356 watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, dev);
357 watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout);
358 watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128);
360 watchdog_set_drvdata(&mtk_wdt->wdt_dev, mtk_wdt);
362 mtk_wdt_init(&mtk_wdt->wdt_dev);
364 watchdog_stop_on_reboot(&mtk_wdt->wdt_dev);
365 err = devm_watchdog_register_device(dev, &mtk_wdt->wdt_dev);
369 dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n",
370 mtk_wdt->wdt_dev.timeout, nowayout);
372 wdt_data = of_device_get_match_data(dev);
374 err = toprgu_register_reset_controller(pdev,
375 wdt_data->toprgu_sw_rst_num);
382 #ifdef CONFIG_PM_SLEEP
383 static int mtk_wdt_suspend(struct device *dev)
385 struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
387 if (watchdog_active(&mtk_wdt->wdt_dev))
388 mtk_wdt_stop(&mtk_wdt->wdt_dev);
393 static int mtk_wdt_resume(struct device *dev)
395 struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
397 if (watchdog_active(&mtk_wdt->wdt_dev)) {
398 mtk_wdt_start(&mtk_wdt->wdt_dev);
399 mtk_wdt_ping(&mtk_wdt->wdt_dev);
406 static const struct of_device_id mtk_wdt_dt_ids[] = {
407 { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
408 { .compatible = "mediatek,mt6589-wdt" },
409 { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
410 { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
413 MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
415 static const struct dev_pm_ops mtk_wdt_pm_ops = {
416 SET_SYSTEM_SLEEP_PM_OPS(mtk_wdt_suspend,
420 static struct platform_driver mtk_wdt_driver = {
421 .probe = mtk_wdt_probe,
424 .pm = &mtk_wdt_pm_ops,
425 .of_match_table = mtk_wdt_dt_ids,
429 module_platform_driver(mtk_wdt_driver);
431 module_param(timeout, uint, 0);
432 MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");
434 module_param(nowayout, bool, 0);
435 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
436 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
438 MODULE_LICENSE("GPL");
439 MODULE_AUTHOR("Matthias Brugger <matthias.bgg@gmail.com>");
440 MODULE_DESCRIPTION("Mediatek WatchDog Timer Driver");
441 MODULE_VERSION(DRV_VERSION);