1 // SPDX-License-Identifier: GPL-2.0+
3 * Mediatek Watchdog Driver
5 * Copyright (C) 2014 Matthias Brugger
7 * Matthias Brugger <matthias.bgg@gmail.com>
12 #include <dt-bindings/reset-controller/mt2712-resets.h>
13 #include <dt-bindings/reset-controller/mt8183-resets.h>
14 #include <dt-bindings/reset-controller/mt8192-resets.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
23 #include <linux/of_device.h>
24 #include <linux/platform_device.h>
25 #include <linux/reset-controller.h>
26 #include <linux/types.h>
27 #include <linux/watchdog.h>
29 #define WDT_MAX_TIMEOUT 31
30 #define WDT_MIN_TIMEOUT 1
31 #define WDT_LENGTH_TIMEOUT(n) ((n) << 5)
33 #define WDT_LENGTH 0x04
34 #define WDT_LENGTH_KEY 0x8
37 #define WDT_RST_RELOAD 0x1971
40 #define WDT_MODE_EN (1 << 0)
41 #define WDT_MODE_EXT_POL_LOW (0 << 1)
42 #define WDT_MODE_EXT_POL_HIGH (1 << 1)
43 #define WDT_MODE_EXRST_EN (1 << 2)
44 #define WDT_MODE_IRQ_EN (1 << 3)
45 #define WDT_MODE_AUTO_START (1 << 4)
46 #define WDT_MODE_DUAL_EN (1 << 6)
47 #define WDT_MODE_KEY 0x22000000
49 #define WDT_SWRST 0x14
50 #define WDT_SWRST_KEY 0x1209
52 #define WDT_SWSYSRST 0x18U
53 #define WDT_SWSYS_RST_KEY 0x88000000
55 #define DRV_NAME "mtk-wdt"
56 #define DRV_VERSION "1.0"
58 static bool nowayout = WATCHDOG_NOWAYOUT;
59 static unsigned int timeout;
62 struct watchdog_device wdt_dev;
63 void __iomem *wdt_base;
64 spinlock_t lock; /* protects WDT_SWSYSRST reg */
65 struct reset_controller_dev rcdev;
69 int toprgu_sw_rst_num;
72 static const struct mtk_wdt_data mt2712_data = {
73 .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM,
76 static const struct mtk_wdt_data mt8183_data = {
77 .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
80 static const struct mtk_wdt_data mt8192_data = {
81 .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM,
84 static int toprgu_reset_update(struct reset_controller_dev *rcdev,
85 unsigned long id, bool assert)
89 struct mtk_wdt_dev *data =
90 container_of(rcdev, struct mtk_wdt_dev, rcdev);
92 spin_lock_irqsave(&data->lock, flags);
94 tmp = readl(data->wdt_base + WDT_SWSYSRST);
99 tmp |= WDT_SWSYS_RST_KEY;
100 writel(tmp, data->wdt_base + WDT_SWSYSRST);
102 spin_unlock_irqrestore(&data->lock, flags);
107 static int toprgu_reset_assert(struct reset_controller_dev *rcdev,
110 return toprgu_reset_update(rcdev, id, true);
113 static int toprgu_reset_deassert(struct reset_controller_dev *rcdev,
116 return toprgu_reset_update(rcdev, id, false);
119 static int toprgu_reset(struct reset_controller_dev *rcdev,
124 ret = toprgu_reset_assert(rcdev, id);
128 return toprgu_reset_deassert(rcdev, id);
131 static const struct reset_control_ops toprgu_reset_ops = {
132 .assert = toprgu_reset_assert,
133 .deassert = toprgu_reset_deassert,
134 .reset = toprgu_reset,
137 static int toprgu_register_reset_controller(struct platform_device *pdev,
141 struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
143 spin_lock_init(&mtk_wdt->lock);
145 mtk_wdt->rcdev.owner = THIS_MODULE;
146 mtk_wdt->rcdev.nr_resets = rst_num;
147 mtk_wdt->rcdev.ops = &toprgu_reset_ops;
148 mtk_wdt->rcdev.of_node = pdev->dev.of_node;
149 ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev);
152 "couldn't register wdt reset controller: %d\n", ret);
156 static int mtk_wdt_restart(struct watchdog_device *wdt_dev,
157 unsigned long action, void *data)
159 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
160 void __iomem *wdt_base;
162 wdt_base = mtk_wdt->wdt_base;
165 writel(WDT_SWRST_KEY, wdt_base + WDT_SWRST);
172 static int mtk_wdt_ping(struct watchdog_device *wdt_dev)
174 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
175 void __iomem *wdt_base = mtk_wdt->wdt_base;
177 iowrite32(WDT_RST_RELOAD, wdt_base + WDT_RST);
182 static int mtk_wdt_set_timeout(struct watchdog_device *wdt_dev,
183 unsigned int timeout)
185 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
186 void __iomem *wdt_base = mtk_wdt->wdt_base;
189 wdt_dev->timeout = timeout;
192 * One bit is the value of 512 ticks
193 * The clock has 32 KHz
195 reg = WDT_LENGTH_TIMEOUT(timeout << 6) | WDT_LENGTH_KEY;
196 iowrite32(reg, wdt_base + WDT_LENGTH);
198 mtk_wdt_ping(wdt_dev);
203 static void mtk_wdt_init(struct watchdog_device *wdt_dev)
205 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
206 void __iomem *wdt_base;
208 wdt_base = mtk_wdt->wdt_base;
210 if (readl(wdt_base + WDT_MODE) & WDT_MODE_EN) {
211 set_bit(WDOG_HW_RUNNING, &wdt_dev->status);
212 mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
216 static int mtk_wdt_stop(struct watchdog_device *wdt_dev)
218 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
219 void __iomem *wdt_base = mtk_wdt->wdt_base;
222 reg = readl(wdt_base + WDT_MODE);
225 iowrite32(reg, wdt_base + WDT_MODE);
230 static int mtk_wdt_start(struct watchdog_device *wdt_dev)
233 struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
234 void __iomem *wdt_base = mtk_wdt->wdt_base;
237 ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
241 reg = ioread32(wdt_base + WDT_MODE);
242 reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
243 reg |= (WDT_MODE_EN | WDT_MODE_KEY);
244 iowrite32(reg, wdt_base + WDT_MODE);
249 static const struct watchdog_info mtk_wdt_info = {
250 .identity = DRV_NAME,
251 .options = WDIOF_SETTIMEOUT |
252 WDIOF_KEEPALIVEPING |
256 static const struct watchdog_ops mtk_wdt_ops = {
257 .owner = THIS_MODULE,
258 .start = mtk_wdt_start,
259 .stop = mtk_wdt_stop,
260 .ping = mtk_wdt_ping,
261 .set_timeout = mtk_wdt_set_timeout,
262 .restart = mtk_wdt_restart,
265 static int mtk_wdt_probe(struct platform_device *pdev)
267 struct device *dev = &pdev->dev;
268 struct mtk_wdt_dev *mtk_wdt;
269 const struct mtk_wdt_data *wdt_data;
272 mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL);
276 platform_set_drvdata(pdev, mtk_wdt);
278 mtk_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0);
279 if (IS_ERR(mtk_wdt->wdt_base))
280 return PTR_ERR(mtk_wdt->wdt_base);
282 mtk_wdt->wdt_dev.info = &mtk_wdt_info;
283 mtk_wdt->wdt_dev.ops = &mtk_wdt_ops;
284 mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;
285 mtk_wdt->wdt_dev.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT * 1000;
286 mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;
287 mtk_wdt->wdt_dev.parent = dev;
289 watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, dev);
290 watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout);
291 watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128);
293 watchdog_set_drvdata(&mtk_wdt->wdt_dev, mtk_wdt);
295 mtk_wdt_init(&mtk_wdt->wdt_dev);
297 watchdog_stop_on_reboot(&mtk_wdt->wdt_dev);
298 err = devm_watchdog_register_device(dev, &mtk_wdt->wdt_dev);
302 dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n",
303 mtk_wdt->wdt_dev.timeout, nowayout);
305 wdt_data = of_device_get_match_data(dev);
307 err = toprgu_register_reset_controller(pdev,
308 wdt_data->toprgu_sw_rst_num);
315 #ifdef CONFIG_PM_SLEEP
316 static int mtk_wdt_suspend(struct device *dev)
318 struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
320 if (watchdog_active(&mtk_wdt->wdt_dev))
321 mtk_wdt_stop(&mtk_wdt->wdt_dev);
326 static int mtk_wdt_resume(struct device *dev)
328 struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
330 if (watchdog_active(&mtk_wdt->wdt_dev)) {
331 mtk_wdt_start(&mtk_wdt->wdt_dev);
332 mtk_wdt_ping(&mtk_wdt->wdt_dev);
339 static const struct of_device_id mtk_wdt_dt_ids[] = {
340 { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
341 { .compatible = "mediatek,mt6589-wdt" },
342 { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
343 { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
346 MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
348 static const struct dev_pm_ops mtk_wdt_pm_ops = {
349 SET_SYSTEM_SLEEP_PM_OPS(mtk_wdt_suspend,
353 static struct platform_driver mtk_wdt_driver = {
354 .probe = mtk_wdt_probe,
357 .pm = &mtk_wdt_pm_ops,
358 .of_match_table = mtk_wdt_dt_ids,
362 module_platform_driver(mtk_wdt_driver);
364 module_param(timeout, uint, 0);
365 MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");
367 module_param(nowayout, bool, 0);
368 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
369 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
371 MODULE_LICENSE("GPL");
372 MODULE_AUTHOR("Matthias Brugger <matthias.bgg@gmail.com>");
373 MODULE_DESCRIPTION("Mediatek WatchDog Timer Driver");
374 MODULE_VERSION(DRV_VERSION);