drivers/watchdog/mlx_wdt.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Mellanox watchdog driver
   4  *
   5  * Copyright (C) 2019 Mellanox Technologies
   6  * Copyright (C) 2019 Michael Shych <mshych@mellanox.com>
   7  */
   8
   9 #include <linux/bitops.h>
  10 #include <linux/device.h>
  11 #include <linux/errno.h>
  12 #include <linux/log2.h>
  13 #include <linux/module.h>
  14 #include <linux/platform_data/mlxreg.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/regmap.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/types.h>
  19 #include <linux/watchdog.h>
  20
  21 #define MLXREG_WDT_CLOCK_SCALE          1000
  22 #define MLXREG_WDT_MAX_TIMEOUT_TYPE1    32
  23 #define MLXREG_WDT_MAX_TIMEOUT_TYPE2    255
  24 #define MLXREG_WDT_MAX_TIMEOUT_TYPE3    65535
  25 #define MLXREG_WDT_MIN_TIMEOUT          1
  26 #define MLXREG_WDT_OPTIONS_BASE (WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE | \
  27                                  WDIOF_SETTIMEOUT)
  28
  29 /**
  30  * struct mlxreg_wdt - wd private data:
  31  *
  32  * @wdd:        watchdog device;
  33  * @pdata:      data received from platform driver;
  34  * @regmap:     register map of parent device;
  35  * @action_idx: index for direct access to action register;
  36  * @timeout_idx:index for direct access to TO register;
  37  * @tleft_idx:  index for direct access to time left register;
  38  * @ping_idx:   index for direct access to ping register;
  39  * @reset_idx:  index for direct access to reset cause register;
  40  * @regmap_val_sz: size of value in register map;
  41  * @wdt_type:   watchdog HW type;
  42  */
  43 struct mlxreg_wdt {
  44         struct watchdog_device wdd;
  45         struct mlxreg_core_platform_data *pdata;
  46         void *regmap;
  47         int action_idx;
  48         int timeout_idx;
  49         int tleft_idx;
  50         int ping_idx;
  51         int reset_idx;
  52         int regmap_val_sz;
  53         enum mlxreg_wdt_type wdt_type;
  54 };
  55
  56 static void mlxreg_wdt_check_card_reset(struct mlxreg_wdt *wdt)
  57 {
  58         struct mlxreg_core_data *reg_data;
  59         u32 regval;
  60         int rc;
  61
  62         if (wdt->reset_idx == -EINVAL)
  63                 return;
  64
  65         if (!(wdt->wdd.info->options & WDIOF_CARDRESET))
  66                 return;
  67
  68         reg_data = &wdt->pdata->data[wdt->reset_idx];
  69         rc = regmap_read(wdt->regmap, reg_data->reg, &regval);
  70         if (!rc) {
  71                 if (regval & ~reg_data->mask) {
  72                         wdt->wdd.bootstatus = WDIOF_CARDRESET;
  73                         dev_info(wdt->wdd.parent,
  74                                  "watchdog previously reset the CPU\n");
  75                 }
  76         }
  77 }
  78
  79 static int mlxreg_wdt_start(struct watchdog_device *wdd)
  80 {
  81         struct mlxreg_wdt *wdt = watchdog_get_drvdata(wdd);
  82         struct mlxreg_core_data *reg_data = &wdt->pdata->data[wdt->action_idx];
  83
  84         return regmap_update_bits(wdt->regmap, reg_data->reg, ~reg_data->mask,
  85                                   BIT(reg_data->bit));
  86 }
  87
  88 static int mlxreg_wdt_stop(struct watchdog_device *wdd)
  89 {
  90         struct mlxreg_wdt *wdt = watchdog_get_drvdata(wdd);
  91         struct mlxreg_core_data *reg_data = &wdt->pdata->data[wdt->action_idx];
  92
  93         return regmap_update_bits(wdt->regmap, reg_data->reg, ~reg_data->mask,
  94                                   ~BIT(reg_data->bit));
  95 }
  96
  97 static int mlxreg_wdt_ping(struct watchdog_device *wdd)
  98 {
  99         struct mlxreg_wdt *wdt = watchdog_get_drvdata(wdd);
 100         struct mlxreg_core_data *reg_data = &wdt->pdata->data[wdt->ping_idx];
 101
 102         return regmap_write_bits(wdt->regmap, reg_data->reg, ~reg_data->mask,
 103                                  BIT(reg_data->bit));
 104 }
 105
 106 static int mlxreg_wdt_set_timeout(struct watchdog_device *wdd,
 107                                   unsigned int timeout)
 108 {
 109         struct mlxreg_wdt *wdt = watchdog_get_drvdata(wdd);
 110         struct mlxreg_core_data *reg_data = &wdt->pdata->data[wdt->timeout_idx];
 111         u32 regval, set_time, hw_timeout;
 112         int rc;
 113
 114         switch (wdt->wdt_type) {
 115         case MLX_WDT_TYPE1:
 116                 rc = regmap_read(wdt->regmap, reg_data->reg, &regval);
 117                 if (rc)
 118                         return rc;
 119
 120                 hw_timeout = order_base_2(timeout * MLXREG_WDT_CLOCK_SCALE);
 121                 regval = (regval & reg_data->mask) | hw_timeout;
 122                 /* Rowndown to actual closest number of sec. */
 123                 set_time = BIT(hw_timeout) / MLXREG_WDT_CLOCK_SCALE;
 124                 rc = regmap_write(wdt->regmap, reg_data->reg, regval);
 125                 break;
 126         case MLX_WDT_TYPE2:
 127                 set_time = timeout;
 128                 rc = regmap_write(wdt->regmap, reg_data->reg, timeout);
 129                 break;
 130         case MLX_WDT_TYPE3:
 131                 /* WD_TYPE3 has 2B set time register */
 132                 set_time = timeout;
 133                 if (wdt->regmap_val_sz == 1) {
 134                         regval = timeout & 0xff;
 135                         rc = regmap_write(wdt->regmap, reg_data->reg, regval);
 136                         if (!rc) {
 137                                 regval = (timeout & 0xff00) >> 8;
 138                                 rc = regmap_write(wdt->regmap,
 139                                                 reg_data->reg + 1, regval);
 140                         }
 141                 } else {
 142                         rc = regmap_write(wdt->regmap, reg_data->reg, timeout);
 143                 }
 144                 break;
 145         default:
 146                 return -EINVAL;
 147         }
 148
 149         wdd->timeout = set_time;
 150         if (!rc) {
 151                 /*
 152                  * Restart watchdog with new timeout period
 153                  * if watchdog is already started.
 154                  */
 155                 if (watchdog_active(wdd)) {
 156                         rc = mlxreg_wdt_stop(wdd);
 157                         if (!rc)
 158                                 rc = mlxreg_wdt_start(wdd);
 159                 }
 160         }
 161
 162         return rc;
 163 }
 164
 165 static unsigned int mlxreg_wdt_get_timeleft(struct watchdog_device *wdd)
 166 {
 167         struct mlxreg_wdt *wdt = watchdog_get_drvdata(wdd);
 168         struct mlxreg_core_data *reg_data = &wdt->pdata->data[wdt->tleft_idx];
 169         u32 regval, msb, lsb;
 170         int rc;
 171
 172         if (wdt->wdt_type == MLX_WDT_TYPE2) {
 173                 rc = regmap_read(wdt->regmap, reg_data->reg, &regval);
 174         } else {
 175                 /* WD_TYPE3 has 2 byte timeleft register */
 176                 if (wdt->regmap_val_sz == 1) {
 177                         rc = regmap_read(wdt->regmap, reg_data->reg, &lsb);
 178                         if (!rc) {
 179                                 rc = regmap_read(wdt->regmap,
 180                                                 reg_data->reg + 1, &msb);
 181                                 regval = (msb & 0xff) << 8 | (lsb & 0xff);
 182                         }
 183                 } else {
 184                         rc = regmap_read(wdt->regmap, reg_data->reg, &regval);
 185                 }
 186         }
 187
 188         /* Return 0 timeleft in case of failure register read. */
 189         return rc == 0 ? regval : 0;
 190 }
 191
 192 static const struct watchdog_ops mlxreg_wdt_ops_type1 = {
 193         .start          = mlxreg_wdt_start,
 194         .stop           = mlxreg_wdt_stop,
 195         .ping           = mlxreg_wdt_ping,
 196         .set_timeout    = mlxreg_wdt_set_timeout,
 197         .owner          = THIS_MODULE,
 198 };
 199
 200 static const struct watchdog_ops mlxreg_wdt_ops_type2 = {
 201         .start          = mlxreg_wdt_start,
 202         .stop           = mlxreg_wdt_stop,
 203         .ping           = mlxreg_wdt_ping,
 204         .set_timeout    = mlxreg_wdt_set_timeout,
 205         .get_timeleft   = mlxreg_wdt_get_timeleft,
 206         .owner          = THIS_MODULE,
 207 };
 208
 209 static const struct watchdog_info mlxreg_wdt_main_info = {
 210         .options        = MLXREG_WDT_OPTIONS_BASE
 211                         | WDIOF_CARDRESET,
 212         .identity       = "mlx-wdt-main",
 213 };
 214
 215 static const struct watchdog_info mlxreg_wdt_aux_info = {
 216         .options        = MLXREG_WDT_OPTIONS_BASE
 217                         | WDIOF_ALARMONLY,
 218         .identity       = "mlx-wdt-aux",
 219 };
 220
 221 static void mlxreg_wdt_config(struct mlxreg_wdt *wdt,
 222                               struct mlxreg_core_platform_data *pdata)
 223 {
 224         struct mlxreg_core_data *data = pdata->data;
 225         int i;
 226
 227         wdt->reset_idx = -EINVAL;
 228         for (i = 0; i < pdata->counter; i++, data++) {
 229                 if (strnstr(data->label, "action", sizeof(data->label)))
 230                         wdt->action_idx = i;
 231                 else if (strnstr(data->label, "timeout", sizeof(data->label)))
 232                         wdt->timeout_idx = i;
 233                 else if (strnstr(data->label, "timeleft", sizeof(data->label)))
 234                         wdt->tleft_idx = i;
 235                 else if (strnstr(data->label, "ping", sizeof(data->label)))
 236                         wdt->ping_idx = i;
 237                 else if (strnstr(data->label, "reset", sizeof(data->label)))
 238                         wdt->reset_idx = i;
 239         }
 240
 241         wdt->pdata = pdata;
 242         if (strnstr(pdata->identity, mlxreg_wdt_main_info.identity,
 243                     sizeof(mlxreg_wdt_main_info.identity)))
 244                 wdt->wdd.info = &mlxreg_wdt_main_info;
 245         else
 246                 wdt->wdd.info = &mlxreg_wdt_aux_info;
 247
 248         wdt->wdt_type = pdata->version;
 249         switch (wdt->wdt_type) {
 250         case MLX_WDT_TYPE1:
 251                 wdt->wdd.ops = &mlxreg_wdt_ops_type1;
 252                 wdt->wdd.max_timeout = MLXREG_WDT_MAX_TIMEOUT_TYPE1;
 253                 break;
 254         case MLX_WDT_TYPE2:
 255                 wdt->wdd.ops = &mlxreg_wdt_ops_type2;
 256                 wdt->wdd.max_timeout = MLXREG_WDT_MAX_TIMEOUT_TYPE2;
 257                 break;
 258         case MLX_WDT_TYPE3:
 259                 wdt->wdd.ops = &mlxreg_wdt_ops_type2;
 260                 wdt->wdd.max_timeout = MLXREG_WDT_MAX_TIMEOUT_TYPE3;
 261                 break;
 262         default:
 263                 break;
 264         }
 265
 266         wdt->wdd.min_timeout = MLXREG_WDT_MIN_TIMEOUT;
 267 }
 268
 269 static int mlxreg_wdt_init_timeout(struct mlxreg_wdt *wdt,
 270                                    struct mlxreg_core_platform_data *pdata)
 271 {
 272         u32 timeout;
 273
 274         timeout = pdata->data[wdt->timeout_idx].health_cntr;
 275         return mlxreg_wdt_set_timeout(&wdt->wdd, timeout);
 276 }
 277
 278 static int mlxreg_wdt_probe(struct platform_device *pdev)
 279 {
 280         struct device *dev = &pdev->dev;
 281         struct mlxreg_core_platform_data *pdata;
 282         struct mlxreg_wdt *wdt;
 283         int rc;
 284
 285         pdata = dev_get_platdata(dev);
 286         if (!pdata) {
 287                 dev_err(dev, "Failed to get platform data.\n");
 288                 return -EINVAL;
 289         }
 290         wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
 291         if (!wdt)
 292                 return -ENOMEM;
 293
 294         wdt->wdd.parent = dev;
 295         wdt->regmap = pdata->regmap;
 296         rc = regmap_get_val_bytes(wdt->regmap);
 297         if (rc < 0)
 298                 return -EINVAL;
 299
 300         wdt->regmap_val_sz = rc;
 301         mlxreg_wdt_config(wdt, pdata);
 302
 303         if ((pdata->features & MLXREG_CORE_WD_FEATURE_NOWAYOUT))
 304                 watchdog_set_nowayout(&wdt->wdd, WATCHDOG_NOWAYOUT);
 305         watchdog_stop_on_reboot(&wdt->wdd);
 306         watchdog_stop_on_unregister(&wdt->wdd);
 307         watchdog_set_drvdata(&wdt->wdd, wdt);
 308         rc = mlxreg_wdt_init_timeout(wdt, pdata);
 309         if (rc)
 310                 goto register_error;
 311
 312         if ((pdata->features & MLXREG_CORE_WD_FEATURE_START_AT_BOOT)) {
 313                 rc = mlxreg_wdt_start(&wdt->wdd);
 314                 if (rc)
 315                         goto register_error;
 316                 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
 317         }
 318         mlxreg_wdt_check_card_reset(wdt);
 319         rc = devm_watchdog_register_device(dev, &wdt->wdd);
 320
 321 register_error:
 322         if (rc)
 323                 dev_err(dev, "Cannot register watchdog device (err=%d)\n", rc);
 324         return rc;
 325 }
 326
 327 static struct platform_driver mlxreg_wdt_driver = {
 328         .probe  = mlxreg_wdt_probe,
 329         .driver = {
 330                         .name = "mlx-wdt",
 331         },
 332 };
 333
 334 module_platform_driver(mlxreg_wdt_driver);
 335
 336 MODULE_AUTHOR("Michael Shych <michaelsh@mellanox.com>");
 337 MODULE_DESCRIPTION("Mellanox watchdog driver");
 338 MODULE_LICENSE("GPL");
 339 MODULE_ALIAS("platform:mlx-wdt");