drivers/watchdog/keembay_wdt.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Watchdog driver for Intel Keem Bay non-secure watchdog.
   4  *
   5  * Copyright (C) 2020 Intel Corporation
   6  */
   7
   8 #include <linux/arm-smccc.h>
   9 #include <linux/bits.h>
  10 #include <linux/clk.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/io.h>
  13 #include <linux/limits.h>
  14 #include <linux/module.h>
  15 #include <linux/mod_devicetable.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/reboot.h>
  18 #include <linux/watchdog.h>
  19
  20 /* Non-secure watchdog register offsets */
  21 #define TIM_WATCHDOG            0x0
  22 #define TIM_WATCHDOG_INT_THRES  0x4
  23 #define TIM_WDOG_EN             0x8
  24 #define TIM_SAFE                0xc
  25
  26 #define WDT_TH_INT_MASK         BIT(8)
  27 #define WDT_TO_INT_MASK         BIT(9)
  28 #define WDT_ISR_CLEAR           0x8200ff18
  29 #define WDT_UNLOCK              0xf1d0dead
  30 #define WDT_LOAD_MAX            U32_MAX
  31 #define WDT_LOAD_MIN            1
  32 #define WDT_TIMEOUT             5
  33 #define WDT_PRETIMEOUT          4
  34
  35 static unsigned int timeout = WDT_TIMEOUT;
  36 module_param(timeout, int, 0);
  37 MODULE_PARM_DESC(timeout, "Watchdog timeout period in seconds (default = "
  38                  __MODULE_STRING(WDT_TIMEOUT) ")");
  39
  40 static bool nowayout = WATCHDOG_NOWAYOUT;
  41 module_param(nowayout, bool, 0);
  42 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default = "
  43                  __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  44
  45 struct keembay_wdt {
  46         struct watchdog_device  wdd;
  47         struct clk              *clk;
  48         unsigned int            rate;
  49         int                     to_irq;
  50         int                     th_irq;
  51         void __iomem            *base;
  52 };
  53
  54 static inline u32 keembay_wdt_readl(struct keembay_wdt *wdt, u32 offset)
  55 {
  56         return readl(wdt->base + offset);
  57 }
  58
  59 static inline void keembay_wdt_writel(struct keembay_wdt *wdt, u32 offset, u32 val)
  60 {
  61         writel(WDT_UNLOCK, wdt->base + TIM_SAFE);
  62         writel(val, wdt->base + offset);
  63 }
  64
  65 static void keembay_wdt_set_timeout_reg(struct watchdog_device *wdog)
  66 {
  67         struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
  68
  69         keembay_wdt_writel(wdt, TIM_WATCHDOG, wdog->timeout * wdt->rate);
  70 }
  71
  72 static void keembay_wdt_set_pretimeout_reg(struct watchdog_device *wdog)
  73 {
  74         struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
  75         u32 th_val = 0;
  76
  77         if (wdog->pretimeout)
  78                 th_val = wdog->timeout - wdog->pretimeout;
  79
  80         keembay_wdt_writel(wdt, TIM_WATCHDOG_INT_THRES, th_val * wdt->rate);
  81 }
  82
  83 static int keembay_wdt_start(struct watchdog_device *wdog)
  84 {
  85         struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
  86
  87         keembay_wdt_set_timeout_reg(wdog);
  88         keembay_wdt_writel(wdt, TIM_WDOG_EN, 1);
  89
  90         return 0;
  91 }
  92
  93 static int keembay_wdt_stop(struct watchdog_device *wdog)
  94 {
  95         struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
  96
  97         keembay_wdt_writel(wdt, TIM_WDOG_EN, 0);
  98
  99         return 0;
 100 }
 101
 102 static int keembay_wdt_ping(struct watchdog_device *wdog)
 103 {
 104         keembay_wdt_set_timeout_reg(wdog);
 105
 106         return 0;
 107 }
 108
 109 static int keembay_wdt_set_timeout(struct watchdog_device *wdog, u32 t)
 110 {
 111         wdog->timeout = t;
 112         keembay_wdt_set_timeout_reg(wdog);
 113         keembay_wdt_set_pretimeout_reg(wdog);
 114
 115         return 0;
 116 }
 117
 118 static int keembay_wdt_set_pretimeout(struct watchdog_device *wdog, u32 t)
 119 {
 120         if (t > wdog->timeout)
 121                 return -EINVAL;
 122
 123         wdog->pretimeout = t;
 124         keembay_wdt_set_pretimeout_reg(wdog);
 125
 126         return 0;
 127 }
 128
 129 static unsigned int keembay_wdt_get_timeleft(struct watchdog_device *wdog)
 130 {
 131         struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
 132
 133         return keembay_wdt_readl(wdt, TIM_WATCHDOG) / wdt->rate;
 134 }
 135
 136 /*
 137  * SMC call is used to clear the interrupt bits, because the TIM_GEN_CONFIG
 138  * register is in the secure bank.
 139  */
 140 static irqreturn_t keembay_wdt_to_isr(int irq, void *dev_id)
 141 {
 142         struct keembay_wdt *wdt = dev_id;
 143         struct arm_smccc_res res;
 144
 145         keembay_wdt_writel(wdt, TIM_WATCHDOG, 1);
 146         arm_smccc_smc(WDT_ISR_CLEAR, WDT_TO_INT_MASK, 0, 0, 0, 0, 0, 0, &res);
 147         dev_crit(wdt->wdd.parent, "Intel Keem Bay non-sec wdt timeout.\n");
 148         emergency_restart();
 149
 150         return IRQ_HANDLED;
 151 }
 152
 153 static irqreturn_t keembay_wdt_th_isr(int irq, void *dev_id)
 154 {
 155         struct keembay_wdt *wdt = dev_id;
 156         struct arm_smccc_res res;
 157
 158         keembay_wdt_set_pretimeout(&wdt->wdd, 0x0);
 159
 160         arm_smccc_smc(WDT_ISR_CLEAR, WDT_TH_INT_MASK, 0, 0, 0, 0, 0, 0, &res);
 161         dev_crit(wdt->wdd.parent, "Intel Keem Bay non-sec wdt pre-timeout.\n");
 162         watchdog_notify_pretimeout(&wdt->wdd);
 163
 164         return IRQ_HANDLED;
 165 }
 166
 167 static const struct watchdog_info keembay_wdt_info = {
 168         .identity       = "Intel Keem Bay Watchdog Timer",
 169         .options        = WDIOF_SETTIMEOUT |
 170                           WDIOF_PRETIMEOUT |
 171                           WDIOF_MAGICCLOSE |
 172                           WDIOF_KEEPALIVEPING,
 173 };
 174
 175 static const struct watchdog_ops keembay_wdt_ops = {
 176         .owner          = THIS_MODULE,
 177         .start          = keembay_wdt_start,
 178         .stop           = keembay_wdt_stop,
 179         .ping           = keembay_wdt_ping,
 180         .set_timeout    = keembay_wdt_set_timeout,
 181         .set_pretimeout = keembay_wdt_set_pretimeout,
 182         .get_timeleft   = keembay_wdt_get_timeleft,
 183 };
 184
 185 static int keembay_wdt_probe(struct platform_device *pdev)
 186 {
 187         struct device *dev = &pdev->dev;
 188         struct keembay_wdt *wdt;
 189         int ret;
 190
 191         wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
 192         if (!wdt)
 193                 return -ENOMEM;
 194
 195         wdt->base = devm_platform_ioremap_resource(pdev, 0);
 196         if (IS_ERR(wdt->base))
 197                 return PTR_ERR(wdt->base);
 198
 199         /* we do not need to enable the clock as it is enabled by default */
 200         wdt->clk = devm_clk_get(dev, NULL);
 201         if (IS_ERR(wdt->clk))
 202                 return dev_err_probe(dev, PTR_ERR(wdt->clk), "Failed to get clock\n");
 203
 204         wdt->rate = clk_get_rate(wdt->clk);
 205         if (!wdt->rate)
 206                 return dev_err_probe(dev, -EINVAL, "Failed to get clock rate\n");
 207
 208         wdt->th_irq = platform_get_irq_byname(pdev, "threshold");
 209         if (wdt->th_irq < 0)
 210                 return dev_err_probe(dev, wdt->th_irq, "Failed to get IRQ for threshold\n");
 211
 212         ret = devm_request_irq(dev, wdt->th_irq, keembay_wdt_th_isr, 0,
 213                                "keembay-wdt", wdt);
 214         if (ret)
 215                 return dev_err_probe(dev, ret, "Failed to request IRQ for threshold\n");
 216
 217         wdt->to_irq = platform_get_irq_byname(pdev, "timeout");
 218         if (wdt->to_irq < 0)
 219                 return dev_err_probe(dev, wdt->to_irq, "Failed to get IRQ for timeout\n");
 220
 221         ret = devm_request_irq(dev, wdt->to_irq, keembay_wdt_to_isr, 0,
 222                                "keembay-wdt", wdt);
 223         if (ret)
 224                 return dev_err_probe(dev, ret, "Failed to request IRQ for timeout\n");
 225
 226         wdt->wdd.parent         = dev;
 227         wdt->wdd.info           = &keembay_wdt_info;
 228         wdt->wdd.ops            = &keembay_wdt_ops;
 229         wdt->wdd.min_timeout    = WDT_LOAD_MIN;
 230         wdt->wdd.max_timeout    = WDT_LOAD_MAX / wdt->rate;
 231         wdt->wdd.timeout        = WDT_TIMEOUT;
 232         wdt->wdd.pretimeout     = WDT_PRETIMEOUT;
 233
 234         watchdog_set_drvdata(&wdt->wdd, wdt);
 235         watchdog_set_nowayout(&wdt->wdd, nowayout);
 236         watchdog_init_timeout(&wdt->wdd, timeout, dev);
 237         keembay_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout);
 238         keembay_wdt_set_pretimeout(&wdt->wdd, wdt->wdd.pretimeout);
 239
 240         ret = devm_watchdog_register_device(dev, &wdt->wdd);
 241         if (ret)
 242                 return dev_err_probe(dev, ret, "Failed to register watchdog device.\n");
 243
 244         platform_set_drvdata(pdev, wdt);
 245         dev_info(dev, "Initial timeout %d sec%s.\n",
 246                  wdt->wdd.timeout, nowayout ? ", nowayout" : "");
 247
 248         return 0;
 249 }
 250
 251 static int __maybe_unused keembay_wdt_suspend(struct device *dev)
 252 {
 253         struct keembay_wdt *wdt = dev_get_drvdata(dev);
 254
 255         if (watchdog_active(&wdt->wdd))
 256                 return keembay_wdt_stop(&wdt->wdd);
 257
 258         return 0;
 259 }
 260
 261 static int __maybe_unused keembay_wdt_resume(struct device *dev)
 262 {
 263         struct keembay_wdt *wdt = dev_get_drvdata(dev);
 264
 265         if (watchdog_active(&wdt->wdd))
 266                 return keembay_wdt_start(&wdt->wdd);
 267
 268         return 0;
 269 }
 270
 271 static SIMPLE_DEV_PM_OPS(keembay_wdt_pm_ops, keembay_wdt_suspend,
 272                          keembay_wdt_resume);
 273
 274 static const struct of_device_id keembay_wdt_match[] = {
 275         { .compatible = "intel,keembay-wdt" },
 276         { }
 277 };
 278 MODULE_DEVICE_TABLE(of, keembay_wdt_match);
 279
 280 static struct platform_driver keembay_wdt_driver = {
 281         .probe          = keembay_wdt_probe,
 282         .driver         = {
 283                 .name           = "keembay_wdt",
 284                 .of_match_table = keembay_wdt_match,
 285                 .pm             = &keembay_wdt_pm_ops,
 286         },
 287 };
 288
 289 module_platform_driver(keembay_wdt_driver);
 290
 291 MODULE_DESCRIPTION("Intel Keem Bay SoC watchdog driver");
 292 MODULE_AUTHOR("Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com");
 293 MODULE_LICENSE("GPL v2");