1 // SPDX-License-Identifier: GPL-2.0-only
3 * Watchdog driver for Intel Keem Bay non-secure watchdog.
5 * Copyright (C) 2020 Intel Corporation
8 #include <linux/arm-smccc.h>
9 #include <linux/bits.h>
10 #include <linux/clk.h>
11 #include <linux/interrupt.h>
13 #include <linux/limits.h>
14 #include <linux/module.h>
15 #include <linux/mod_devicetable.h>
16 #include <linux/platform_device.h>
17 #include <linux/reboot.h>
18 #include <linux/watchdog.h>
20 /* Non-secure watchdog register offsets */
21 #define TIM_WATCHDOG 0x0
22 #define TIM_WATCHDOG_INT_THRES 0x4
23 #define TIM_WDOG_EN 0x8
26 #define WDT_ISR_MASK GENMASK(9, 8)
27 #define WDT_ISR_CLEAR 0x8200ff18
28 #define WDT_UNLOCK 0xf1d0dead
29 #define WDT_LOAD_MAX U32_MAX
30 #define WDT_LOAD_MIN 1
33 static unsigned int timeout = WDT_TIMEOUT;
34 module_param(timeout, int, 0);
35 MODULE_PARM_DESC(timeout, "Watchdog timeout period in seconds (default = "
36 __MODULE_STRING(WDT_TIMEOUT) ")");
38 static bool nowayout = WATCHDOG_NOWAYOUT;
39 module_param(nowayout, bool, 0);
40 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default = "
41 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
44 struct watchdog_device wdd;
52 static inline u32 keembay_wdt_readl(struct keembay_wdt *wdt, u32 offset)
54 return readl(wdt->base + offset);
57 static inline void keembay_wdt_writel(struct keembay_wdt *wdt, u32 offset, u32 val)
59 writel(WDT_UNLOCK, wdt->base + TIM_SAFE);
60 writel(val, wdt->base + offset);
63 static void keembay_wdt_set_timeout_reg(struct watchdog_device *wdog)
65 struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
67 keembay_wdt_writel(wdt, TIM_WATCHDOG, wdog->timeout * wdt->rate);
70 static void keembay_wdt_set_pretimeout_reg(struct watchdog_device *wdog)
72 struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
76 th_val = wdog->timeout - wdog->pretimeout;
78 keembay_wdt_writel(wdt, TIM_WATCHDOG_INT_THRES, th_val * wdt->rate);
81 static int keembay_wdt_start(struct watchdog_device *wdog)
83 struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
85 keembay_wdt_set_timeout_reg(wdog);
86 keembay_wdt_writel(wdt, TIM_WDOG_EN, 1);
91 static int keembay_wdt_stop(struct watchdog_device *wdog)
93 struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
95 keembay_wdt_writel(wdt, TIM_WDOG_EN, 0);
100 static int keembay_wdt_ping(struct watchdog_device *wdog)
102 keembay_wdt_set_timeout_reg(wdog);
107 static int keembay_wdt_set_timeout(struct watchdog_device *wdog, u32 t)
110 keembay_wdt_set_timeout_reg(wdog);
115 static int keembay_wdt_set_pretimeout(struct watchdog_device *wdog, u32 t)
117 if (t > wdog->timeout)
120 wdog->pretimeout = t;
121 keembay_wdt_set_pretimeout_reg(wdog);
126 static unsigned int keembay_wdt_get_timeleft(struct watchdog_device *wdog)
128 struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
130 return keembay_wdt_readl(wdt, TIM_WATCHDOG) / wdt->rate;
134 * SMC call is used to clear the interrupt bits, because the TIM_GEN_CONFIG
135 * register is in the secure bank.
137 static irqreturn_t keembay_wdt_to_isr(int irq, void *dev_id)
139 struct keembay_wdt *wdt = dev_id;
140 struct arm_smccc_res res;
142 keembay_wdt_writel(wdt, TIM_WATCHDOG, 1);
143 arm_smccc_smc(WDT_ISR_CLEAR, WDT_ISR_MASK, 0, 0, 0, 0, 0, 0, &res);
144 dev_crit(wdt->wdd.parent, "Intel Keem Bay non-sec wdt timeout.\n");
150 static irqreturn_t keembay_wdt_th_isr(int irq, void *dev_id)
152 struct keembay_wdt *wdt = dev_id;
153 struct arm_smccc_res res;
155 arm_smccc_smc(WDT_ISR_CLEAR, WDT_ISR_MASK, 0, 0, 0, 0, 0, 0, &res);
156 dev_crit(wdt->wdd.parent, "Intel Keem Bay non-sec wdt pre-timeout.\n");
157 watchdog_notify_pretimeout(&wdt->wdd);
162 static const struct watchdog_info keembay_wdt_info = {
163 .identity = "Intel Keem Bay Watchdog Timer",
164 .options = WDIOF_SETTIMEOUT |
170 static const struct watchdog_ops keembay_wdt_ops = {
171 .owner = THIS_MODULE,
172 .start = keembay_wdt_start,
173 .stop = keembay_wdt_stop,
174 .ping = keembay_wdt_ping,
175 .set_timeout = keembay_wdt_set_timeout,
176 .set_pretimeout = keembay_wdt_set_pretimeout,
177 .get_timeleft = keembay_wdt_get_timeleft,
180 static int keembay_wdt_probe(struct platform_device *pdev)
182 struct device *dev = &pdev->dev;
183 struct keembay_wdt *wdt;
186 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
190 wdt->base = devm_platform_ioremap_resource(pdev, 0);
191 if (IS_ERR(wdt->base))
192 return PTR_ERR(wdt->base);
194 /* we do not need to enable the clock as it is enabled by default */
195 wdt->clk = devm_clk_get(dev, NULL);
196 if (IS_ERR(wdt->clk))
197 return dev_err_probe(dev, PTR_ERR(wdt->clk), "Failed to get clock\n");
199 wdt->rate = clk_get_rate(wdt->clk);
201 return dev_err_probe(dev, -EINVAL, "Failed to get clock rate\n");
203 wdt->th_irq = platform_get_irq_byname(pdev, "threshold");
205 return dev_err_probe(dev, wdt->th_irq, "Failed to get IRQ for threshold\n");
207 ret = devm_request_irq(dev, wdt->th_irq, keembay_wdt_th_isr, 0,
210 return dev_err_probe(dev, ret, "Failed to request IRQ for threshold\n");
212 wdt->to_irq = platform_get_irq_byname(pdev, "timeout");
214 return dev_err_probe(dev, wdt->to_irq, "Failed to get IRQ for timeout\n");
216 ret = devm_request_irq(dev, wdt->to_irq, keembay_wdt_to_isr, 0,
219 return dev_err_probe(dev, ret, "Failed to request IRQ for timeout\n");
221 wdt->wdd.parent = dev;
222 wdt->wdd.info = &keembay_wdt_info;
223 wdt->wdd.ops = &keembay_wdt_ops;
224 wdt->wdd.min_timeout = WDT_LOAD_MIN;
225 wdt->wdd.max_timeout = WDT_LOAD_MAX / wdt->rate;
226 wdt->wdd.timeout = WDT_TIMEOUT;
228 watchdog_set_drvdata(&wdt->wdd, wdt);
229 watchdog_set_nowayout(&wdt->wdd, nowayout);
230 watchdog_init_timeout(&wdt->wdd, timeout, dev);
231 keembay_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout);
233 ret = devm_watchdog_register_device(dev, &wdt->wdd);
235 return dev_err_probe(dev, ret, "Failed to register watchdog device.\n");
237 platform_set_drvdata(pdev, wdt);
238 dev_info(dev, "Initial timeout %d sec%s.\n",
239 wdt->wdd.timeout, nowayout ? ", nowayout" : "");
244 static int __maybe_unused keembay_wdt_suspend(struct device *dev)
246 struct keembay_wdt *wdt = dev_get_drvdata(dev);
248 if (watchdog_active(&wdt->wdd))
249 return keembay_wdt_stop(&wdt->wdd);
254 static int __maybe_unused keembay_wdt_resume(struct device *dev)
256 struct keembay_wdt *wdt = dev_get_drvdata(dev);
258 if (watchdog_active(&wdt->wdd))
259 return keembay_wdt_start(&wdt->wdd);
264 static SIMPLE_DEV_PM_OPS(keembay_wdt_pm_ops, keembay_wdt_suspend,
267 static const struct of_device_id keembay_wdt_match[] = {
268 { .compatible = "intel,keembay-wdt" },
271 MODULE_DEVICE_TABLE(of, keembay_wdt_match);
273 static struct platform_driver keembay_wdt_driver = {
274 .probe = keembay_wdt_probe,
276 .name = "keembay_wdt",
277 .of_match_table = keembay_wdt_match,
278 .pm = &keembay_wdt_pm_ops,
282 module_platform_driver(keembay_wdt_driver);
284 MODULE_DESCRIPTION("Intel Keem Bay SoC watchdog driver");
285 MODULE_AUTHOR("Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com");
286 MODULE_LICENSE("GPL v2");