1 // SPDX-License-Identifier: GPL-2.0+
3 * intel TCO Watchdog Driver
5 * (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
7 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
8 * provide warranty for any of this software. This material is
9 * provided "AS-IS" and at no charge.
11 * The TCO watchdog is implemented in the following I/O controller hubs:
12 * (See the intel documentation on http://developer.intel.com.)
13 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
14 * document number 290687-002, 298242-027: 82801BA (ICH2)
15 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
16 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
17 * document number 290744-001, 290745-025: 82801DB (ICH4)
18 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
19 * document number 273599-001, 273645-002: 82801E (C-ICH)
20 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
21 * document number 300641-004, 300884-013: 6300ESB
22 * document number 301473-002, 301474-026: 82801F (ICH6)
23 * document number 313082-001, 313075-006: 631xESB, 632xESB
24 * document number 307013-003, 307014-024: 82801G (ICH7)
25 * document number 322896-001, 322897-001: NM10
26 * document number 313056-003, 313057-017: 82801H (ICH8)
27 * document number 316972-004, 316973-012: 82801I (ICH9)
28 * document number 319973-002, 319974-002: 82801J (ICH10)
29 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
30 * document number 320066-003, 320257-008: EP80597 (IICH)
31 * document number 324645-001, 324646-001: Cougar Point (CPT)
32 * document number TBD : Patsburg (PBG)
33 * document number TBD : DH89xxCC
34 * document number TBD : Panther Point
35 * document number TBD : Lynx Point
36 * document number TBD : Lynx Point-LP
40 * Includes, defines, variables, module parameters, ...
43 /* Module and version information */
44 #define DRV_NAME "iTCO_wdt"
45 #define DRV_VERSION "1.11"
48 #include <linux/acpi.h> /* For ACPI support */
49 #include <linux/bits.h> /* For BIT() */
50 #include <linux/module.h> /* For module specific items */
51 #include <linux/moduleparam.h> /* For new moduleparam's */
52 #include <linux/types.h> /* For standard types (like size_t) */
53 #include <linux/errno.h> /* For the -ENODEV/... values */
54 #include <linux/kernel.h> /* For printk/panic/... */
55 #include <linux/watchdog.h> /* For the watchdog specific items */
56 #include <linux/init.h> /* For __init/__exit/... */
57 #include <linux/fs.h> /* For file operations */
58 #include <linux/platform_device.h> /* For platform_driver framework */
59 #include <linux/pci.h> /* For pci functions */
60 #include <linux/ioport.h> /* For io-port access */
61 #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
62 #include <linux/uaccess.h> /* For copy_to_user/put_user/... */
63 #include <linux/io.h> /* For inb/outb/... */
64 #include <linux/platform_data/itco_wdt.h>
65 #include <linux/mfd/intel_pmc_bxt.h>
67 #include "iTCO_vendor.h"
69 /* Address definitions for the TCO */
70 /* TCO base address */
71 #define TCOBASE(p) ((p)->tco_res->start)
72 /* SMI Control and Enable Register */
73 #define SMI_EN(p) ((p)->smi_res->start)
74 #define TCO_EN (1 << 13)
75 #define GBL_SMI_EN (1 << 0)
77 #define TCO_RLD(p) (TCOBASE(p) + 0x00) /* TCO Timer Reload/Curr. Value */
78 #define TCOv1_TMR(p) (TCOBASE(p) + 0x01) /* TCOv1 Timer Initial Value*/
79 #define TCO_DAT_IN(p) (TCOBASE(p) + 0x02) /* TCO Data In Register */
80 #define TCO_DAT_OUT(p) (TCOBASE(p) + 0x03) /* TCO Data Out Register */
81 #define TCO1_STS(p) (TCOBASE(p) + 0x04) /* TCO1 Status Register */
82 #define TCO2_STS(p) (TCOBASE(p) + 0x06) /* TCO2 Status Register */
83 #define TCO1_CNT(p) (TCOBASE(p) + 0x08) /* TCO1 Control Register */
84 #define TCO2_CNT(p) (TCOBASE(p) + 0x0a) /* TCO2 Control Register */
85 #define TCOv2_TMR(p) (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/
87 /* internal variables */
88 struct iTCO_wdt_private {
89 struct watchdog_device wddev;
91 /* TCO version/generation */
92 unsigned int iTCO_version;
93 struct resource *tco_res;
94 struct resource *smi_res;
96 * NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2),
97 * or memory-mapped PMC register bit 4 (TCO version 3).
99 struct resource *gcs_pmc_res;
100 unsigned long __iomem *gcs_pmc;
101 /* the lock for io operations */
104 struct pci_dev *pci_dev;
105 /* whether or not the watchdog has been suspended */
107 /* no reboot API private data */
108 void *no_reboot_priv;
109 /* no reboot update function pointer */
110 int (*update_no_reboot_bit)(void *p, bool set);
113 /* module parameters */
114 #define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */
115 static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */
116 module_param(heartbeat, int, 0);
117 MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
118 "5..76 (TCO v1) or 3..614 (TCO v2), default="
119 __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
121 static bool nowayout = WATCHDOG_NOWAYOUT;
122 module_param(nowayout, bool, 0);
123 MODULE_PARM_DESC(nowayout,
124 "Watchdog cannot be stopped once started (default="
125 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
127 static int turn_SMI_watchdog_clear_off = 1;
128 module_param(turn_SMI_watchdog_clear_off, int, 0);
129 MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
130 "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
133 * Some TCO specific functions
137 * The iTCO v1 and v2's internal timer is stored as ticks which decrement
138 * every 0.6 seconds. v3's internal timer is stored as seconds (some
139 * datasheets incorrectly state 0.6 seconds).
141 static inline unsigned int seconds_to_ticks(struct iTCO_wdt_private *p,
144 return p->iTCO_version == 3 ? secs : (secs * 10) / 6;
147 static inline unsigned int ticks_to_seconds(struct iTCO_wdt_private *p,
150 return p->iTCO_version == 3 ? ticks : (ticks * 6) / 10;
153 static inline u32 no_reboot_bit(struct iTCO_wdt_private *p)
157 switch (p->iTCO_version) {
160 enable_bit = 0x00000010;
163 enable_bit = 0x00000020;
168 enable_bit = 0x00000002;
175 static int update_no_reboot_bit_def(void *priv, bool set)
180 static int update_no_reboot_bit_pci(void *priv, bool set)
182 struct iTCO_wdt_private *p = priv;
183 u32 val32 = 0, newval32 = 0;
185 pci_read_config_dword(p->pci_dev, 0xd4, &val32);
187 val32 |= no_reboot_bit(p);
189 val32 &= ~no_reboot_bit(p);
190 pci_write_config_dword(p->pci_dev, 0xd4, val32);
191 pci_read_config_dword(p->pci_dev, 0xd4, &newval32);
193 /* make sure the update is successful */
194 if (val32 != newval32)
200 static int update_no_reboot_bit_mem(void *priv, bool set)
202 struct iTCO_wdt_private *p = priv;
203 u32 val32 = 0, newval32 = 0;
205 val32 = readl(p->gcs_pmc);
207 val32 |= no_reboot_bit(p);
209 val32 &= ~no_reboot_bit(p);
210 writel(val32, p->gcs_pmc);
211 newval32 = readl(p->gcs_pmc);
213 /* make sure the update is successful */
214 if (val32 != newval32)
220 static int update_no_reboot_bit_cnt(void *priv, bool set)
222 struct iTCO_wdt_private *p = priv;
225 val = inw(TCO1_CNT(p));
230 outw(val, TCO1_CNT(p));
231 newval = inw(TCO1_CNT(p));
233 /* make sure the update is successful */
234 return val != newval ? -EIO : 0;
237 static int update_no_reboot_bit_pmc(void *priv, bool set)
239 struct intel_pmc_dev *pmc = priv;
240 u32 bits = PMC_CFG_NO_REBOOT_EN;
241 u32 value = set ? bits : 0;
243 return intel_pmc_gcr_update(pmc, PMC_GCR_PMC_CFG_REG, bits, value);
246 static void iTCO_wdt_no_reboot_bit_setup(struct iTCO_wdt_private *p,
247 struct platform_device *pdev,
248 struct itco_wdt_platform_data *pdata)
250 if (pdata->no_reboot_use_pmc) {
251 struct intel_pmc_dev *pmc = dev_get_drvdata(pdev->dev.parent);
253 p->update_no_reboot_bit = update_no_reboot_bit_pmc;
254 p->no_reboot_priv = pmc;
258 if (p->iTCO_version >= 6)
259 p->update_no_reboot_bit = update_no_reboot_bit_cnt;
260 else if (p->iTCO_version >= 2)
261 p->update_no_reboot_bit = update_no_reboot_bit_mem;
262 else if (p->iTCO_version == 1)
263 p->update_no_reboot_bit = update_no_reboot_bit_pci;
265 p->update_no_reboot_bit = update_no_reboot_bit_def;
267 p->no_reboot_priv = p;
270 static int iTCO_wdt_start(struct watchdog_device *wd_dev)
272 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
275 spin_lock(&p->io_lock);
277 iTCO_vendor_pre_start(p->smi_res, wd_dev->timeout);
279 /* disable chipset's NO_REBOOT bit */
280 if (p->update_no_reboot_bit(p->no_reboot_priv, false)) {
281 spin_unlock(&p->io_lock);
282 dev_err(wd_dev->parent, "failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
286 /* Force the timer to its reload value by writing to the TCO_RLD
288 if (p->iTCO_version >= 2)
289 outw(0x01, TCO_RLD(p));
290 else if (p->iTCO_version == 1)
291 outb(0x01, TCO_RLD(p));
293 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
294 val = inw(TCO1_CNT(p));
296 outw(val, TCO1_CNT(p));
297 val = inw(TCO1_CNT(p));
298 spin_unlock(&p->io_lock);
305 static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
307 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
310 spin_lock(&p->io_lock);
312 iTCO_vendor_pre_stop(p->smi_res);
314 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
315 val = inw(TCO1_CNT(p));
317 outw(val, TCO1_CNT(p));
318 val = inw(TCO1_CNT(p));
320 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
321 p->update_no_reboot_bit(p->no_reboot_priv, true);
323 spin_unlock(&p->io_lock);
325 if ((val & 0x0800) == 0)
330 static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
332 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
334 spin_lock(&p->io_lock);
336 /* Reload the timer by writing to the TCO Timer Counter register */
337 if (p->iTCO_version >= 2) {
338 outw(0x01, TCO_RLD(p));
339 } else if (p->iTCO_version == 1) {
340 /* Reset the timeout status bit so that the timer
341 * needs to count down twice again before rebooting */
342 outw(0x0008, TCO1_STS(p)); /* write 1 to clear bit */
344 outb(0x01, TCO_RLD(p));
347 spin_unlock(&p->io_lock);
351 static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
353 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
358 tmrval = seconds_to_ticks(p, t);
361 * If TCO SMIs are off, the timer counts down twice before rebooting.
362 * Otherwise, the BIOS generally reboots when the SMI triggers.
365 (inl(SMI_EN(p)) & (TCO_EN | GBL_SMI_EN)) != (TCO_EN | GBL_SMI_EN))
368 /* from the specs: */
369 /* "Values of 0h-3h are ignored and should not be attempted" */
372 if ((p->iTCO_version >= 2 && tmrval > 0x3ff) ||
373 (p->iTCO_version == 1 && tmrval > 0x03f))
376 /* Write new heartbeat to watchdog */
377 if (p->iTCO_version >= 2) {
378 spin_lock(&p->io_lock);
379 val16 = inw(TCOv2_TMR(p));
382 outw(val16, TCOv2_TMR(p));
383 val16 = inw(TCOv2_TMR(p));
384 spin_unlock(&p->io_lock);
386 if ((val16 & 0x3ff) != tmrval)
388 } else if (p->iTCO_version == 1) {
389 spin_lock(&p->io_lock);
390 val8 = inb(TCOv1_TMR(p));
392 val8 |= (tmrval & 0xff);
393 outb(val8, TCOv1_TMR(p));
394 val8 = inb(TCOv1_TMR(p));
395 spin_unlock(&p->io_lock);
397 if ((val8 & 0x3f) != tmrval)
405 static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
407 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
410 unsigned int time_left = 0;
412 /* read the TCO Timer */
413 if (p->iTCO_version >= 2) {
414 spin_lock(&p->io_lock);
415 val16 = inw(TCO_RLD(p));
417 spin_unlock(&p->io_lock);
419 time_left = ticks_to_seconds(p, val16);
420 } else if (p->iTCO_version == 1) {
421 spin_lock(&p->io_lock);
422 val8 = inb(TCO_RLD(p));
424 if (!(inw(TCO1_STS(p)) & 0x0008))
425 val8 += (inb(TCOv1_TMR(p)) & 0x3f);
426 spin_unlock(&p->io_lock);
428 time_left = ticks_to_seconds(p, val8);
437 static const struct watchdog_info ident = {
438 .options = WDIOF_SETTIMEOUT |
439 WDIOF_KEEPALIVEPING |
441 .firmware_version = 0,
442 .identity = DRV_NAME,
445 static const struct watchdog_ops iTCO_wdt_ops = {
446 .owner = THIS_MODULE,
447 .start = iTCO_wdt_start,
448 .stop = iTCO_wdt_stop,
449 .ping = iTCO_wdt_ping,
450 .set_timeout = iTCO_wdt_set_timeout,
451 .get_timeleft = iTCO_wdt_get_timeleft,
455 * Init & exit routines
458 static int iTCO_wdt_probe(struct platform_device *pdev)
460 struct device *dev = &pdev->dev;
461 struct itco_wdt_platform_data *pdata = dev_get_platdata(dev);
462 struct iTCO_wdt_private *p;
469 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
473 spin_lock_init(&p->io_lock);
475 p->tco_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_TCO);
479 p->iTCO_version = pdata->version;
480 p->pci_dev = to_pci_dev(dev->parent);
482 p->smi_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_SMI);
484 /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
485 if (!devm_request_region(dev, p->smi_res->start,
486 resource_size(p->smi_res),
488 dev_err(dev, "I/O address 0x%04llx already in use, device disabled\n",
492 } else if (iTCO_vendorsupport ||
493 turn_SMI_watchdog_clear_off >= p->iTCO_version) {
494 dev_err(dev, "SMI I/O resource is missing\n");
498 iTCO_wdt_no_reboot_bit_setup(p, pdev, pdata);
501 * Get the Memory-Mapped GCS or PMC register, we need it for the
502 * NO_REBOOT flag (TCO v2 and v3).
504 if (p->iTCO_version >= 2 && p->iTCO_version < 6 &&
505 !pdata->no_reboot_use_pmc) {
506 p->gcs_pmc_res = platform_get_resource(pdev,
508 ICH_RES_MEM_GCS_PMC);
509 p->gcs_pmc = devm_ioremap_resource(dev, p->gcs_pmc_res);
510 if (IS_ERR(p->gcs_pmc))
511 return PTR_ERR(p->gcs_pmc);
514 /* Check chipset's NO_REBOOT bit */
515 if (p->update_no_reboot_bit(p->no_reboot_priv, false) &&
516 iTCO_vendor_check_noreboot_on()) {
517 dev_info(dev, "unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
518 return -ENODEV; /* Cannot reset NO_REBOOT bit */
521 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
522 p->update_no_reboot_bit(p->no_reboot_priv, true);
524 if (turn_SMI_watchdog_clear_off >= p->iTCO_version) {
526 * Bit 13: TCO_EN -> 0
527 * Disables TCO logic generating an SMI#
529 val32 = inl(SMI_EN(p));
530 val32 &= ~TCO_EN; /* Turn off SMI clearing watchdog */
531 outl(val32, SMI_EN(p));
534 if (!devm_request_region(dev, p->tco_res->start,
535 resource_size(p->tco_res),
537 dev_err(dev, "I/O address 0x%04llx already in use, device disabled\n",
542 dev_info(dev, "Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
543 pdata->name, pdata->version, (u64)TCOBASE(p));
545 /* Clear out the (probably old) status */
546 switch (p->iTCO_version) {
550 outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
551 outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
554 outl(0x20008, TCO1_STS(p));
559 outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
560 outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
561 outw(0x0004, TCO2_STS(p)); /* Clear BOOT_STS bit */
565 p->wddev.info = &ident,
566 p->wddev.ops = &iTCO_wdt_ops,
567 p->wddev.bootstatus = 0;
568 p->wddev.timeout = WATCHDOG_TIMEOUT;
569 watchdog_set_nowayout(&p->wddev, nowayout);
570 p->wddev.parent = dev;
572 watchdog_set_drvdata(&p->wddev, p);
573 platform_set_drvdata(pdev, p);
575 /* Make sure the watchdog is not running */
576 iTCO_wdt_stop(&p->wddev);
578 /* Check that the heartbeat value is within it's range;
579 if not reset to the default */
580 if (iTCO_wdt_set_timeout(&p->wddev, heartbeat)) {
581 iTCO_wdt_set_timeout(&p->wddev, WATCHDOG_TIMEOUT);
582 dev_info(dev, "timeout value out of range, using %d\n",
586 watchdog_stop_on_reboot(&p->wddev);
587 watchdog_stop_on_unregister(&p->wddev);
588 ret = devm_watchdog_register_device(dev, &p->wddev);
590 dev_err(dev, "cannot register watchdog device (err=%d)\n", ret);
594 dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
595 heartbeat, nowayout);
600 #ifdef CONFIG_PM_SLEEP
602 * Suspend-to-idle requires this, because it stops the ticks and timekeeping, so
603 * the watchdog cannot be pinged while in that state. In ACPI sleep states the
604 * watchdog is stopped by the platform firmware.
608 static inline bool need_suspend(void)
610 return acpi_target_system_state() == ACPI_STATE_S0;
613 static inline bool need_suspend(void) { return true; }
616 static int iTCO_wdt_suspend_noirq(struct device *dev)
618 struct iTCO_wdt_private *p = dev_get_drvdata(dev);
621 p->suspended = false;
622 if (watchdog_active(&p->wddev) && need_suspend()) {
623 ret = iTCO_wdt_stop(&p->wddev);
630 static int iTCO_wdt_resume_noirq(struct device *dev)
632 struct iTCO_wdt_private *p = dev_get_drvdata(dev);
635 iTCO_wdt_start(&p->wddev);
640 static const struct dev_pm_ops iTCO_wdt_pm = {
641 .suspend_noirq = iTCO_wdt_suspend_noirq,
642 .resume_noirq = iTCO_wdt_resume_noirq,
645 #define ITCO_WDT_PM_OPS (&iTCO_wdt_pm)
647 #define ITCO_WDT_PM_OPS NULL
648 #endif /* CONFIG_PM_SLEEP */
650 static struct platform_driver iTCO_wdt_driver = {
651 .probe = iTCO_wdt_probe,
654 .pm = ITCO_WDT_PM_OPS,
658 module_platform_driver(iTCO_wdt_driver);
660 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
661 MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
662 MODULE_VERSION(DRV_VERSION);
663 MODULE_LICENSE("GPL");
664 MODULE_ALIAS("platform:" DRV_NAME);