virtio-mem: simplify high-level unplug handling in Sub Block Mode
[linux-2.6-microblaze.git] / drivers / watchdog / dw_wdt.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright 2010-2011 Picochip Ltd., Jamie Iles
4  * https://www.picochip.com
5  *
6  * This file implements a driver for the Synopsys DesignWare watchdog device
7  * in the many subsystems. The watchdog has 16 different timeout periods
8  * and these are a function of the input clock frequency.
9  *
10  * The DesignWare watchdog cannot be stopped once it has been started so we
11  * do not implement a stop function. The watchdog core will continue to send
12  * heartbeat requests after the watchdog device has been closed.
13  */
14
15 #include <linux/bitops.h>
16 #include <linux/limits.h>
17 #include <linux/kernel.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/io.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/interrupt.h>
26 #include <linux/of.h>
27 #include <linux/pm.h>
28 #include <linux/platform_device.h>
29 #include <linux/reset.h>
30 #include <linux/watchdog.h>
31 #include <linux/debugfs.h>
32
33 #define WDOG_CONTROL_REG_OFFSET             0x00
34 #define WDOG_CONTROL_REG_WDT_EN_MASK        0x01
35 #define WDOG_CONTROL_REG_RESP_MODE_MASK     0x02
36 #define WDOG_TIMEOUT_RANGE_REG_OFFSET       0x04
37 #define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT    4
38 #define WDOG_CURRENT_COUNT_REG_OFFSET       0x08
39 #define WDOG_COUNTER_RESTART_REG_OFFSET     0x0c
40 #define WDOG_COUNTER_RESTART_KICK_VALUE     0x76
41 #define WDOG_INTERRUPT_STATUS_REG_OFFSET    0x10
42 #define WDOG_INTERRUPT_CLEAR_REG_OFFSET     0x14
43 #define WDOG_COMP_PARAMS_5_REG_OFFSET       0xe4
44 #define WDOG_COMP_PARAMS_4_REG_OFFSET       0xe8
45 #define WDOG_COMP_PARAMS_3_REG_OFFSET       0xec
46 #define WDOG_COMP_PARAMS_2_REG_OFFSET       0xf0
47 #define WDOG_COMP_PARAMS_1_REG_OFFSET       0xf4
48 #define WDOG_COMP_PARAMS_1_USE_FIX_TOP      BIT(6)
49 #define WDOG_COMP_VERSION_REG_OFFSET        0xf8
50 #define WDOG_COMP_TYPE_REG_OFFSET           0xfc
51
52 /* There are sixteen TOPs (timeout periods) that can be set in the watchdog. */
53 #define DW_WDT_NUM_TOPS         16
54 #define DW_WDT_FIX_TOP(_idx)    (1U << (16 + _idx))
55
56 #define DW_WDT_DEFAULT_SECONDS  30
57
58 static const u32 dw_wdt_fix_tops[DW_WDT_NUM_TOPS] = {
59         DW_WDT_FIX_TOP(0), DW_WDT_FIX_TOP(1), DW_WDT_FIX_TOP(2),
60         DW_WDT_FIX_TOP(3), DW_WDT_FIX_TOP(4), DW_WDT_FIX_TOP(5),
61         DW_WDT_FIX_TOP(6), DW_WDT_FIX_TOP(7), DW_WDT_FIX_TOP(8),
62         DW_WDT_FIX_TOP(9), DW_WDT_FIX_TOP(10), DW_WDT_FIX_TOP(11),
63         DW_WDT_FIX_TOP(12), DW_WDT_FIX_TOP(13), DW_WDT_FIX_TOP(14),
64         DW_WDT_FIX_TOP(15)
65 };
66
67 static bool nowayout = WATCHDOG_NOWAYOUT;
68 module_param(nowayout, bool, 0);
69 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
70                  "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
71
72 enum dw_wdt_rmod {
73         DW_WDT_RMOD_RESET = 1,
74         DW_WDT_RMOD_IRQ = 2
75 };
76
77 struct dw_wdt_timeout {
78         u32 top_val;
79         unsigned int sec;
80         unsigned int msec;
81 };
82
83 struct dw_wdt {
84         void __iomem            *regs;
85         struct clk              *clk;
86         struct clk              *pclk;
87         unsigned long           rate;
88         enum dw_wdt_rmod        rmod;
89         struct dw_wdt_timeout   timeouts[DW_WDT_NUM_TOPS];
90         struct watchdog_device  wdd;
91         struct reset_control    *rst;
92         /* Save/restore */
93         u32                     control;
94         u32                     timeout;
95
96 #ifdef CONFIG_DEBUG_FS
97         struct dentry           *dbgfs_dir;
98 #endif
99 };
100
101 #define to_dw_wdt(wdd)  container_of(wdd, struct dw_wdt, wdd)
102
103 static inline int dw_wdt_is_enabled(struct dw_wdt *dw_wdt)
104 {
105         return readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET) &
106                 WDOG_CONTROL_REG_WDT_EN_MASK;
107 }
108
109 static void dw_wdt_update_mode(struct dw_wdt *dw_wdt, enum dw_wdt_rmod rmod)
110 {
111         u32 val;
112
113         val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
114         if (rmod == DW_WDT_RMOD_IRQ)
115                 val |= WDOG_CONTROL_REG_RESP_MODE_MASK;
116         else
117                 val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK;
118         writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
119
120         dw_wdt->rmod = rmod;
121 }
122
123 static unsigned int dw_wdt_find_best_top(struct dw_wdt *dw_wdt,
124                                          unsigned int timeout, u32 *top_val)
125 {
126         int idx;
127
128         /*
129          * Find a TOP with timeout greater or equal to the requested number.
130          * Note we'll select a TOP with maximum timeout if the requested
131          * timeout couldn't be reached.
132          */
133         for (idx = 0; idx < DW_WDT_NUM_TOPS; ++idx) {
134                 if (dw_wdt->timeouts[idx].sec >= timeout)
135                         break;
136         }
137
138         if (idx == DW_WDT_NUM_TOPS)
139                 --idx;
140
141         *top_val = dw_wdt->timeouts[idx].top_val;
142
143         return dw_wdt->timeouts[idx].sec;
144 }
145
146 static unsigned int dw_wdt_get_min_timeout(struct dw_wdt *dw_wdt)
147 {
148         int idx;
149
150         /*
151          * We'll find a timeout greater or equal to one second anyway because
152          * the driver probe would have failed if there was none.
153          */
154         for (idx = 0; idx < DW_WDT_NUM_TOPS; ++idx) {
155                 if (dw_wdt->timeouts[idx].sec)
156                         break;
157         }
158
159         return dw_wdt->timeouts[idx].sec;
160 }
161
162 static unsigned int dw_wdt_get_max_timeout_ms(struct dw_wdt *dw_wdt)
163 {
164         struct dw_wdt_timeout *timeout = &dw_wdt->timeouts[DW_WDT_NUM_TOPS - 1];
165         u64 msec;
166
167         msec = (u64)timeout->sec * MSEC_PER_SEC + timeout->msec;
168
169         return msec < UINT_MAX ? msec : UINT_MAX;
170 }
171
172 static unsigned int dw_wdt_get_timeout(struct dw_wdt *dw_wdt)
173 {
174         int top_val = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF;
175         int idx;
176
177         for (idx = 0; idx < DW_WDT_NUM_TOPS; ++idx) {
178                 if (dw_wdt->timeouts[idx].top_val == top_val)
179                         break;
180         }
181
182         /*
183          * In IRQ mode due to the two stages counter, the actual timeout is
184          * twice greater than the TOP setting.
185          */
186         return dw_wdt->timeouts[idx].sec * dw_wdt->rmod;
187 }
188
189 static int dw_wdt_ping(struct watchdog_device *wdd)
190 {
191         struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
192
193         writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs +
194                WDOG_COUNTER_RESTART_REG_OFFSET);
195
196         return 0;
197 }
198
199 static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s)
200 {
201         struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
202         unsigned int timeout;
203         u32 top_val;
204
205         /*
206          * Note IRQ mode being enabled means having a non-zero pre-timeout
207          * setup. In this case we try to find a TOP as close to the half of the
208          * requested timeout as possible since DW Watchdog IRQ mode is designed
209          * in two stages way - first timeout rises the pre-timeout interrupt,
210          * second timeout performs the system reset. So basically the effective
211          * watchdog-caused reset happens after two watchdog TOPs elapsed.
212          */
213         timeout = dw_wdt_find_best_top(dw_wdt, DIV_ROUND_UP(top_s, dw_wdt->rmod),
214                                        &top_val);
215         if (dw_wdt->rmod == DW_WDT_RMOD_IRQ)
216                 wdd->pretimeout = timeout;
217         else
218                 wdd->pretimeout = 0;
219
220         /*
221          * Set the new value in the watchdog.  Some versions of dw_wdt
222          * have have TOPINIT in the TIMEOUT_RANGE register (as per
223          * CP_WDT_DUAL_TOP in WDT_COMP_PARAMS_1).  On those we
224          * effectively get a pat of the watchdog right here.
225          */
226         writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT,
227                dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
228
229         /* Kick new TOP value into the watchdog counter if activated. */
230         if (watchdog_active(wdd))
231                 dw_wdt_ping(wdd);
232
233         /*
234          * In case users set bigger timeout value than HW can support,
235          * kernel(watchdog_dev.c) helps to feed watchdog before
236          * wdd->max_hw_heartbeat_ms
237          */
238         if (top_s * 1000 <= wdd->max_hw_heartbeat_ms)
239                 wdd->timeout = timeout * dw_wdt->rmod;
240         else
241                 wdd->timeout = top_s;
242
243         return 0;
244 }
245
246 static int dw_wdt_set_pretimeout(struct watchdog_device *wdd, unsigned int req)
247 {
248         struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
249
250         /*
251          * We ignore actual value of the timeout passed from user-space
252          * using it as a flag whether the pretimeout functionality is intended
253          * to be activated.
254          */
255         dw_wdt_update_mode(dw_wdt, req ? DW_WDT_RMOD_IRQ : DW_WDT_RMOD_RESET);
256         dw_wdt_set_timeout(wdd, wdd->timeout);
257
258         return 0;
259 }
260
261 static void dw_wdt_arm_system_reset(struct dw_wdt *dw_wdt)
262 {
263         u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
264
265         /* Disable/enable interrupt mode depending on the RMOD flag. */
266         if (dw_wdt->rmod == DW_WDT_RMOD_IRQ)
267                 val |= WDOG_CONTROL_REG_RESP_MODE_MASK;
268         else
269                 val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK;
270         /* Enable watchdog. */
271         val |= WDOG_CONTROL_REG_WDT_EN_MASK;
272         writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
273 }
274
275 static int dw_wdt_start(struct watchdog_device *wdd)
276 {
277         struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
278
279         dw_wdt_set_timeout(wdd, wdd->timeout);
280         dw_wdt_ping(&dw_wdt->wdd);
281         dw_wdt_arm_system_reset(dw_wdt);
282
283         return 0;
284 }
285
286 static int dw_wdt_stop(struct watchdog_device *wdd)
287 {
288         struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
289
290         if (!dw_wdt->rst) {
291                 set_bit(WDOG_HW_RUNNING, &wdd->status);
292                 return 0;
293         }
294
295         reset_control_assert(dw_wdt->rst);
296         reset_control_deassert(dw_wdt->rst);
297
298         return 0;
299 }
300
301 static int dw_wdt_restart(struct watchdog_device *wdd,
302                           unsigned long action, void *data)
303 {
304         struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
305
306         writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
307         dw_wdt_update_mode(dw_wdt, DW_WDT_RMOD_RESET);
308         if (dw_wdt_is_enabled(dw_wdt))
309                 writel(WDOG_COUNTER_RESTART_KICK_VALUE,
310                        dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET);
311         else
312                 dw_wdt_arm_system_reset(dw_wdt);
313
314         /* wait for reset to assert... */
315         mdelay(500);
316
317         return 0;
318 }
319
320 static unsigned int dw_wdt_get_timeleft(struct watchdog_device *wdd)
321 {
322         struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
323         unsigned int sec;
324         u32 val;
325
326         val = readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET);
327         sec = val / dw_wdt->rate;
328
329         if (dw_wdt->rmod == DW_WDT_RMOD_IRQ) {
330                 val = readl(dw_wdt->regs + WDOG_INTERRUPT_STATUS_REG_OFFSET);
331                 if (!val)
332                         sec += wdd->pretimeout;
333         }
334
335         return sec;
336 }
337
338 static const struct watchdog_info dw_wdt_ident = {
339         .options        = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
340                           WDIOF_MAGICCLOSE,
341         .identity       = "Synopsys DesignWare Watchdog",
342 };
343
344 static const struct watchdog_info dw_wdt_pt_ident = {
345         .options        = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
346                           WDIOF_PRETIMEOUT | WDIOF_MAGICCLOSE,
347         .identity       = "Synopsys DesignWare Watchdog",
348 };
349
350 static const struct watchdog_ops dw_wdt_ops = {
351         .owner          = THIS_MODULE,
352         .start          = dw_wdt_start,
353         .stop           = dw_wdt_stop,
354         .ping           = dw_wdt_ping,
355         .set_timeout    = dw_wdt_set_timeout,
356         .set_pretimeout = dw_wdt_set_pretimeout,
357         .get_timeleft   = dw_wdt_get_timeleft,
358         .restart        = dw_wdt_restart,
359 };
360
361 static irqreturn_t dw_wdt_irq(int irq, void *devid)
362 {
363         struct dw_wdt *dw_wdt = devid;
364         u32 val;
365
366         /*
367          * We don't clear the IRQ status. It's supposed to be done by the
368          * following ping operations.
369          */
370         val = readl(dw_wdt->regs + WDOG_INTERRUPT_STATUS_REG_OFFSET);
371         if (!val)
372                 return IRQ_NONE;
373
374         watchdog_notify_pretimeout(&dw_wdt->wdd);
375
376         return IRQ_HANDLED;
377 }
378
379 #ifdef CONFIG_PM_SLEEP
380 static int dw_wdt_suspend(struct device *dev)
381 {
382         struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
383
384         dw_wdt->control = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
385         dw_wdt->timeout = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
386
387         clk_disable_unprepare(dw_wdt->pclk);
388         clk_disable_unprepare(dw_wdt->clk);
389
390         return 0;
391 }
392
393 static int dw_wdt_resume(struct device *dev)
394 {
395         struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
396         int err = clk_prepare_enable(dw_wdt->clk);
397
398         if (err)
399                 return err;
400
401         err = clk_prepare_enable(dw_wdt->pclk);
402         if (err) {
403                 clk_disable_unprepare(dw_wdt->clk);
404                 return err;
405         }
406
407         writel(dw_wdt->timeout, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
408         writel(dw_wdt->control, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
409
410         dw_wdt_ping(&dw_wdt->wdd);
411
412         return 0;
413 }
414 #endif /* CONFIG_PM_SLEEP */
415
416 static SIMPLE_DEV_PM_OPS(dw_wdt_pm_ops, dw_wdt_suspend, dw_wdt_resume);
417
418 /*
419  * In case if DW WDT IP core is synthesized with fixed TOP feature disabled the
420  * TOPs array can be arbitrary ordered with nearly any sixteen uint numbers
421  * depending on the system engineer imagination. The next method handles the
422  * passed TOPs array to pre-calculate the effective timeouts and to sort the
423  * TOP items out in the ascending order with respect to the timeouts.
424  */
425
426 static void dw_wdt_handle_tops(struct dw_wdt *dw_wdt, const u32 *tops)
427 {
428         struct dw_wdt_timeout tout, *dst;
429         int val, tidx;
430         u64 msec;
431
432         /*
433          * We walk over the passed TOPs array and calculate corresponding
434          * timeouts in seconds and milliseconds. The milliseconds granularity
435          * is needed to distinguish the TOPs with very close timeouts and to
436          * set the watchdog max heartbeat setting further.
437          */
438         for (val = 0; val < DW_WDT_NUM_TOPS; ++val) {
439                 tout.top_val = val;
440                 tout.sec = tops[val] / dw_wdt->rate;
441                 msec = (u64)tops[val] * MSEC_PER_SEC;
442                 do_div(msec, dw_wdt->rate);
443                 tout.msec = msec - ((u64)tout.sec * MSEC_PER_SEC);
444
445                 /*
446                  * Find a suitable place for the current TOP in the timeouts
447                  * array so that the list is remained in the ascending order.
448                  */
449                 for (tidx = 0; tidx < val; ++tidx) {
450                         dst = &dw_wdt->timeouts[tidx];
451                         if (tout.sec > dst->sec || (tout.sec == dst->sec &&
452                             tout.msec >= dst->msec))
453                                 continue;
454                         else
455                                 swap(*dst, tout);
456                 }
457
458                 dw_wdt->timeouts[val] = tout;
459         }
460 }
461
462 static int dw_wdt_init_timeouts(struct dw_wdt *dw_wdt, struct device *dev)
463 {
464         u32 data, of_tops[DW_WDT_NUM_TOPS];
465         const u32 *tops;
466         int ret;
467
468         /*
469          * Retrieve custom or fixed counter values depending on the
470          * WDT_USE_FIX_TOP flag found in the component specific parameters
471          * #1 register.
472          */
473         data = readl(dw_wdt->regs + WDOG_COMP_PARAMS_1_REG_OFFSET);
474         if (data & WDOG_COMP_PARAMS_1_USE_FIX_TOP) {
475                 tops = dw_wdt_fix_tops;
476         } else {
477                 ret = of_property_read_variable_u32_array(dev_of_node(dev),
478                         "snps,watchdog-tops", of_tops, DW_WDT_NUM_TOPS,
479                         DW_WDT_NUM_TOPS);
480                 if (ret < 0) {
481                         dev_warn(dev, "No valid TOPs array specified\n");
482                         tops = dw_wdt_fix_tops;
483                 } else {
484                         tops = of_tops;
485                 }
486         }
487
488         /* Convert the specified TOPs into an array of watchdog timeouts. */
489         dw_wdt_handle_tops(dw_wdt, tops);
490         if (!dw_wdt->timeouts[DW_WDT_NUM_TOPS - 1].sec) {
491                 dev_err(dev, "No any valid TOP detected\n");
492                 return -EINVAL;
493         }
494
495         return 0;
496 }
497
498 #ifdef CONFIG_DEBUG_FS
499
500 #define DW_WDT_DBGFS_REG(_name, _off) \
501 {                                     \
502         .name = _name,                \
503         .offset = _off                \
504 }
505
506 static const struct debugfs_reg32 dw_wdt_dbgfs_regs[] = {
507         DW_WDT_DBGFS_REG("cr", WDOG_CONTROL_REG_OFFSET),
508         DW_WDT_DBGFS_REG("torr", WDOG_TIMEOUT_RANGE_REG_OFFSET),
509         DW_WDT_DBGFS_REG("ccvr", WDOG_CURRENT_COUNT_REG_OFFSET),
510         DW_WDT_DBGFS_REG("crr", WDOG_COUNTER_RESTART_REG_OFFSET),
511         DW_WDT_DBGFS_REG("stat", WDOG_INTERRUPT_STATUS_REG_OFFSET),
512         DW_WDT_DBGFS_REG("param5", WDOG_COMP_PARAMS_5_REG_OFFSET),
513         DW_WDT_DBGFS_REG("param4", WDOG_COMP_PARAMS_4_REG_OFFSET),
514         DW_WDT_DBGFS_REG("param3", WDOG_COMP_PARAMS_3_REG_OFFSET),
515         DW_WDT_DBGFS_REG("param2", WDOG_COMP_PARAMS_2_REG_OFFSET),
516         DW_WDT_DBGFS_REG("param1", WDOG_COMP_PARAMS_1_REG_OFFSET),
517         DW_WDT_DBGFS_REG("version", WDOG_COMP_VERSION_REG_OFFSET),
518         DW_WDT_DBGFS_REG("type", WDOG_COMP_TYPE_REG_OFFSET)
519 };
520
521 static void dw_wdt_dbgfs_init(struct dw_wdt *dw_wdt)
522 {
523         struct device *dev = dw_wdt->wdd.parent;
524         struct debugfs_regset32 *regset;
525
526         regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
527         if (!regset)
528                 return;
529
530         regset->regs = dw_wdt_dbgfs_regs;
531         regset->nregs = ARRAY_SIZE(dw_wdt_dbgfs_regs);
532         regset->base = dw_wdt->regs;
533
534         dw_wdt->dbgfs_dir = debugfs_create_dir(dev_name(dev), NULL);
535
536         debugfs_create_regset32("registers", 0444, dw_wdt->dbgfs_dir, regset);
537 }
538
539 static void dw_wdt_dbgfs_clear(struct dw_wdt *dw_wdt)
540 {
541         debugfs_remove_recursive(dw_wdt->dbgfs_dir);
542 }
543
544 #else /* !CONFIG_DEBUG_FS */
545
546 static void dw_wdt_dbgfs_init(struct dw_wdt *dw_wdt) {}
547 static void dw_wdt_dbgfs_clear(struct dw_wdt *dw_wdt) {}
548
549 #endif /* !CONFIG_DEBUG_FS */
550
551 static int dw_wdt_drv_probe(struct platform_device *pdev)
552 {
553         struct device *dev = &pdev->dev;
554         struct watchdog_device *wdd;
555         struct dw_wdt *dw_wdt;
556         int ret;
557
558         dw_wdt = devm_kzalloc(dev, sizeof(*dw_wdt), GFP_KERNEL);
559         if (!dw_wdt)
560                 return -ENOMEM;
561
562         dw_wdt->regs = devm_platform_ioremap_resource(pdev, 0);
563         if (IS_ERR(dw_wdt->regs))
564                 return PTR_ERR(dw_wdt->regs);
565
566         /*
567          * Try to request the watchdog dedicated timer clock source. It must
568          * be supplied if asynchronous mode is enabled. Otherwise fallback
569          * to the common timer/bus clocks configuration, in which the very
570          * first found clock supply both timer and APB signals.
571          */
572         dw_wdt->clk = devm_clk_get(dev, "tclk");
573         if (IS_ERR(dw_wdt->clk)) {
574                 dw_wdt->clk = devm_clk_get(dev, NULL);
575                 if (IS_ERR(dw_wdt->clk))
576                         return PTR_ERR(dw_wdt->clk);
577         }
578
579         ret = clk_prepare_enable(dw_wdt->clk);
580         if (ret)
581                 return ret;
582
583         dw_wdt->rate = clk_get_rate(dw_wdt->clk);
584         if (dw_wdt->rate == 0) {
585                 ret = -EINVAL;
586                 goto out_disable_clk;
587         }
588
589         /*
590          * Request APB clock if device is configured with async clocks mode.
591          * In this case both tclk and pclk clocks are supposed to be specified.
592          * Alas we can't know for sure whether async mode was really activated,
593          * so the pclk phandle reference is left optional. If it couldn't be
594          * found we consider the device configured in synchronous clocks mode.
595          */
596         dw_wdt->pclk = devm_clk_get_optional(dev, "pclk");
597         if (IS_ERR(dw_wdt->pclk)) {
598                 ret = PTR_ERR(dw_wdt->pclk);
599                 goto out_disable_clk;
600         }
601
602         ret = clk_prepare_enable(dw_wdt->pclk);
603         if (ret)
604                 goto out_disable_clk;
605
606         dw_wdt->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
607         if (IS_ERR(dw_wdt->rst)) {
608                 ret = PTR_ERR(dw_wdt->rst);
609                 goto out_disable_pclk;
610         }
611
612         /* Enable normal reset without pre-timeout by default. */
613         dw_wdt_update_mode(dw_wdt, DW_WDT_RMOD_RESET);
614
615         /*
616          * Pre-timeout IRQ is optional, since some hardware may lack support
617          * of it. Note we must request rising-edge IRQ, since the lane is left
618          * pending either until the next watchdog kick event or up to the
619          * system reset.
620          */
621         ret = platform_get_irq_optional(pdev, 0);
622         if (ret > 0) {
623                 ret = devm_request_irq(dev, ret, dw_wdt_irq,
624                                        IRQF_SHARED | IRQF_TRIGGER_RISING,
625                                        pdev->name, dw_wdt);
626                 if (ret)
627                         goto out_disable_pclk;
628
629                 dw_wdt->wdd.info = &dw_wdt_pt_ident;
630         } else {
631                 if (ret == -EPROBE_DEFER)
632                         goto out_disable_pclk;
633
634                 dw_wdt->wdd.info = &dw_wdt_ident;
635         }
636
637         reset_control_deassert(dw_wdt->rst);
638
639         ret = dw_wdt_init_timeouts(dw_wdt, dev);
640         if (ret)
641                 goto out_disable_clk;
642
643         wdd = &dw_wdt->wdd;
644         wdd->ops = &dw_wdt_ops;
645         wdd->min_timeout = dw_wdt_get_min_timeout(dw_wdt);
646         wdd->max_hw_heartbeat_ms = dw_wdt_get_max_timeout_ms(dw_wdt);
647         wdd->parent = dev;
648
649         watchdog_set_drvdata(wdd, dw_wdt);
650         watchdog_set_nowayout(wdd, nowayout);
651         watchdog_init_timeout(wdd, 0, dev);
652
653         /*
654          * If the watchdog is already running, use its already configured
655          * timeout. Otherwise use the default or the value provided through
656          * devicetree.
657          */
658         if (dw_wdt_is_enabled(dw_wdt)) {
659                 wdd->timeout = dw_wdt_get_timeout(dw_wdt);
660                 set_bit(WDOG_HW_RUNNING, &wdd->status);
661         } else {
662                 wdd->timeout = DW_WDT_DEFAULT_SECONDS;
663                 watchdog_init_timeout(wdd, 0, dev);
664         }
665
666         platform_set_drvdata(pdev, dw_wdt);
667
668         watchdog_set_restart_priority(wdd, 128);
669
670         ret = watchdog_register_device(wdd);
671         if (ret)
672                 goto out_disable_pclk;
673
674         dw_wdt_dbgfs_init(dw_wdt);
675
676         return 0;
677
678 out_disable_pclk:
679         clk_disable_unprepare(dw_wdt->pclk);
680
681 out_disable_clk:
682         clk_disable_unprepare(dw_wdt->clk);
683         return ret;
684 }
685
686 static int dw_wdt_drv_remove(struct platform_device *pdev)
687 {
688         struct dw_wdt *dw_wdt = platform_get_drvdata(pdev);
689
690         dw_wdt_dbgfs_clear(dw_wdt);
691
692         watchdog_unregister_device(&dw_wdt->wdd);
693         reset_control_assert(dw_wdt->rst);
694         clk_disable_unprepare(dw_wdt->pclk);
695         clk_disable_unprepare(dw_wdt->clk);
696
697         return 0;
698 }
699
700 #ifdef CONFIG_OF
701 static const struct of_device_id dw_wdt_of_match[] = {
702         { .compatible = "snps,dw-wdt", },
703         { /* sentinel */ }
704 };
705 MODULE_DEVICE_TABLE(of, dw_wdt_of_match);
706 #endif
707
708 static struct platform_driver dw_wdt_driver = {
709         .probe          = dw_wdt_drv_probe,
710         .remove         = dw_wdt_drv_remove,
711         .driver         = {
712                 .name   = "dw_wdt",
713                 .of_match_table = of_match_ptr(dw_wdt_of_match),
714                 .pm     = &dw_wdt_pm_ops,
715         },
716 };
717
718 module_platform_driver(dw_wdt_driver);
719
720 MODULE_AUTHOR("Jamie Iles");
721 MODULE_DESCRIPTION("Synopsys DesignWare Watchdog Driver");
722 MODULE_LICENSE("GPL");