2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device
4 * Copyright (C) 1995 Jay Estabrook
5 * Copyright (C) 1997 Geert Uytterhoeven
6 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
7 * Copyright (C) 2002 Richard Henderson
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/sched.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
20 #include <linux/tty.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/init.h>
25 #include <linux/pci.h>
26 #include <linux/selection.h>
28 #include <video/tgafb.h>
29 #include <linux/selection.h>
35 static int tgafb_check_var(struct fb_var_screeninfo *, struct fb_info *);
36 static int tgafb_set_par(struct fb_info *);
37 static void tgafb_set_pll(struct tga_par *, int);
38 static int tgafb_setcolreg(unsigned, unsigned, unsigned, unsigned,
39 unsigned, struct fb_info *);
40 static int tgafb_blank(int, struct fb_info *);
41 static void tgafb_init_fix(struct fb_info *);
43 static void tgafb_imageblit(struct fb_info *, const struct fb_image *);
44 static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *);
45 static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *);
47 static int tgafb_pci_register(struct pci_dev *, const struct pci_device_id *);
49 static void tgafb_pci_unregister(struct pci_dev *);
52 static const char *mode_option = "640x480@60";
56 * Frame buffer operations
59 static struct fb_ops tgafb_ops = {
61 .fb_check_var = tgafb_check_var,
62 .fb_set_par = tgafb_set_par,
63 .fb_setcolreg = tgafb_setcolreg,
64 .fb_blank = tgafb_blank,
65 .fb_fillrect = tgafb_fillrect,
66 .fb_copyarea = tgafb_copyarea,
67 .fb_imageblit = tgafb_imageblit,
68 .fb_cursor = soft_cursor,
73 * PCI registration operations
76 static struct pci_device_id const tgafb_pci_table[] = {
77 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA, PCI_ANY_ID, PCI_ANY_ID,
81 static struct pci_driver tgafb_driver = {
83 .id_table = tgafb_pci_table,
84 .probe = tgafb_pci_register,
85 .remove = __devexit_p(tgafb_pci_unregister),
90 * tgafb_check_var - Optional function. Validates a var passed in.
91 * @var: frame buffer variable screen structure
92 * @info: frame buffer structure that represents a single frame buffer
95 tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
97 struct tga_par *par = (struct tga_par *)info->par;
99 if (par->tga_type == TGA_TYPE_8PLANE) {
100 if (var->bits_per_pixel != 8)
103 if (var->bits_per_pixel != 32)
107 if (var->xres_virtual != var->xres || var->yres_virtual != var->yres)
111 if (1000000000 / var->pixclock > TGA_PLL_MAX_FREQ)
113 if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
116 /* Some of the acceleration routines assume the line width is
117 a multiple of 64 bytes. */
118 if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 64)
125 * tgafb_set_par - Optional function. Alters the hardware state.
126 * @info: frame buffer structure that represents a single frame buffer
129 tgafb_set_par(struct fb_info *info)
131 static unsigned int const deep_presets[4] = {
137 static unsigned int const rasterop_presets[4] = {
143 static unsigned int const mode_presets[4] = {
149 static unsigned int const base_addr_presets[4] = {
156 struct tga_par *par = (struct tga_par *) info->par;
157 u32 htimings, vtimings, pll_freq;
161 /* Encode video timings. */
162 htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
163 | (((info->var.xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB));
164 vtimings = (info->var.yres & TGA_VERT_ACTIVE);
165 htimings |= ((info->var.right_margin/4) << 9) & TGA_HORIZ_FP;
166 vtimings |= (info->var.lower_margin << 11) & TGA_VERT_FP;
167 htimings |= ((info->var.hsync_len/4) << 14) & TGA_HORIZ_SYNC;
168 vtimings |= (info->var.vsync_len << 16) & TGA_VERT_SYNC;
169 htimings |= ((info->var.left_margin/4) << 21) & TGA_HORIZ_BP;
170 vtimings |= (info->var.upper_margin << 22) & TGA_VERT_BP;
172 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
173 htimings |= TGA_HORIZ_POLARITY;
174 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
175 vtimings |= TGA_VERT_POLARITY;
177 par->htimings = htimings;
178 par->vtimings = vtimings;
180 par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN);
182 /* Store other useful values in par. */
183 par->xres = info->var.xres;
184 par->yres = info->var.yres;
185 par->pll_freq = pll_freq = 1000000000 / info->var.pixclock;
186 par->bits_per_pixel = info->var.bits_per_pixel;
188 tga_type = par->tga_type;
190 /* First, disable video. */
191 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
193 /* Write the DEEP register. */
194 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
197 TGA_WRITE_REG(par, deep_presets[tga_type], TGA_DEEP_REG);
198 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
202 /* Write some more registers. */
203 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
204 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
205 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
207 /* Calculate & write the PLL. */
208 tgafb_set_pll(par, pll_freq);
210 /* Write some more registers. */
211 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
212 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
214 /* Init video timing regs. */
215 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
216 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
218 /* Initalise RAMDAC. */
219 if (tga_type == TGA_TYPE_8PLANE) {
221 /* Init BT485 RAMDAC registers. */
222 BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0),
224 BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE);
225 BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */
226 BT485_WRITE(par, 0x40, BT485_CMD_1);
227 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
228 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
230 /* Fill palette registers. */
231 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
232 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
234 for (i = 0; i < 16; i++) {
236 TGA_WRITE_REG(par, default_red[j]|(BT485_DATA_PAL<<8),
238 TGA_WRITE_REG(par, default_grn[j]|(BT485_DATA_PAL<<8),
240 TGA_WRITE_REG(par, default_blu[j]|(BT485_DATA_PAL<<8),
243 for (i = 0; i < 240*3; i += 4) {
244 TGA_WRITE_REG(par, 0x55|(BT485_DATA_PAL<<8),
246 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
248 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
250 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
254 } else { /* 24-plane or 24plusZ */
256 /* Init BT463 registers. */
257 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
258 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
259 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
260 (par->sync_on_green ? 0x80 : 0x40));
262 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
263 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
264 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff);
265 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f);
267 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00);
268 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00);
269 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
270 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
272 /* Fill the palette. */
273 BT463_LOAD_ADDR(par, 0x0000);
274 TGA_WRITE_REG(par, BT463_PALETTE<<2, TGA_RAMDAC_REG);
276 for (i = 0; i < 16; i++) {
278 TGA_WRITE_REG(par, default_red[j]|(BT463_PALETTE<<10),
280 TGA_WRITE_REG(par, default_grn[j]|(BT463_PALETTE<<10),
282 TGA_WRITE_REG(par, default_blu[j]|(BT463_PALETTE<<10),
285 for (i = 0; i < 512*3; i += 4) {
286 TGA_WRITE_REG(par, 0x55|(BT463_PALETTE<<10),
288 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
290 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
292 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
296 /* Fill window type table after start of vertical retrace. */
297 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
299 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
301 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
303 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
305 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE);
306 TGA_WRITE_REG(par, BT463_REG_ACC<<2, TGA_RAMDAC_SETUP_REG);
308 for (i = 0; i < 16; i++) {
309 TGA_WRITE_REG(par, 0x00|(BT463_REG_ACC<<10),
311 TGA_WRITE_REG(par, 0x01|(BT463_REG_ACC<<10),
313 TGA_WRITE_REG(par, 0x80|(BT463_REG_ACC<<10),
319 /* Finally, enable video scan (and pray for the monitor... :-) */
320 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
325 #define DIFFCHECK(X) \
328 int delta = f - (TGA_PLL_BASE_FREQ * (X)) / (r << shift); \
331 if (delta < min_diff) \
332 min_diff = delta, vm = m, va = a, vr = r; \
337 tgafb_set_pll(struct tga_par *par, int f)
339 int n, shift, base, min_diff, target;
340 int r,a,m,vm = 34, va = 1, vr = 30;
342 for (r = 0 ; r < 12 ; r++)
343 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
345 if (f > TGA_PLL_MAX_FREQ)
346 f = TGA_PLL_MAX_FREQ;
348 if (f >= TGA_PLL_MAX_FREQ / 2)
350 else if (f >= TGA_PLL_MAX_FREQ / 4)
355 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
356 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
358 for (r = 0 ; r < 10 ; r++)
359 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
362 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
363 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
365 else if (f <= 200000) {
366 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
367 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
370 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
371 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
374 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
375 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
376 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
377 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
378 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
379 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
381 target = (f << shift) / TGA_PLL_BASE_FREQ;
382 min_diff = TGA_PLL_MAX_FREQ;
389 for (n = base < 7 ? 7 : base; n < base + target && n < 449; n++) {
390 m = ((n + 3) / 7) - 1;
392 DIFFCHECK((m + 1) * 7);
394 DIFFCHECK((m + 1) * 7);
405 for (r = 0; r < 8; r++)
406 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
407 for (r = 0; r < 8 ; r++)
408 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
409 for (r = 0; r < 7 ; r++)
410 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
411 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
416 * tgafb_setcolreg - Optional function. Sets a color register.
417 * @regno: boolean, 0 copy local, 1 get_user() function
418 * @red: frame buffer colormap structure
419 * @green: The green value which can be up to 16 bits wide
420 * @blue: The blue value which can be up to 16 bits wide.
421 * @transp: If supported the alpha value which can be up to 16 bits wide.
422 * @info: frame buffer info structure
425 tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
426 unsigned transp, struct fb_info *info)
428 struct tga_par *par = (struct tga_par *) info->par;
436 if (par->tga_type == TGA_TYPE_8PLANE) {
437 BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE);
438 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
439 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
440 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
441 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
442 } else if (regno < 16) {
443 u32 value = (red << 16) | (green << 8) | blue;
444 ((u32 *)info->pseudo_palette)[regno] = value;
452 * tgafb_blank - Optional function. Blanks the display.
453 * @blank_mode: the blank mode we want.
454 * @info: frame buffer structure that represents a single frame buffer
457 tgafb_blank(int blank, struct fb_info *info)
459 struct tga_par *par = (struct tga_par *) info->par;
460 u32 vhcr, vvcr, vvvr;
463 local_irq_save(flags);
465 vhcr = TGA_READ_REG(par, TGA_HORIZ_REG);
466 vvcr = TGA_READ_REG(par, TGA_VERT_REG);
467 vvvr = TGA_READ_REG(par, TGA_VALID_REG);
468 vvvr &= ~(TGA_VALID_VIDEO | TGA_VALID_BLANK);
471 case FB_BLANK_UNBLANK: /* Unblanking */
472 if (par->vesa_blanked) {
473 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
474 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
475 par->vesa_blanked = 0;
477 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
480 case FB_BLANK_NORMAL: /* Normal blanking */
481 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
485 case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
486 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
487 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
488 par->vesa_blanked = 1;
491 case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
492 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
493 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
494 par->vesa_blanked = 1;
497 case FB_BLANK_POWERDOWN: /* Poweroff */
498 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
499 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
500 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
501 par->vesa_blanked = 1;
505 local_irq_restore(flags);
515 * tgafb_imageblit - REQUIRED function. Can use generic routines if
516 * non acclerated hardware and packed pixel based.
517 * Copies a image from system memory to the screen.
519 * @info: frame buffer structure that represents a single frame buffer
520 * @image: structure defining the image.
523 tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
525 static unsigned char const bitrev[256] = {
526 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
527 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
528 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
529 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
530 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
531 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
532 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
533 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
534 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
535 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
536 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
537 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
538 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
539 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
540 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
541 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
542 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
543 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
544 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
545 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
546 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
547 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
548 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
549 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
550 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
551 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
552 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
553 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
554 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
555 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
556 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
557 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff
560 struct tga_par *par = (struct tga_par *) info->par;
561 u32 fgcolor, bgcolor, dx, dy, width, height, vxres, vyres, pixelmask;
562 unsigned long rincr, line_length, shift, pos, is8bpp;
564 const unsigned char *data;
565 void __iomem *regs_base;
566 void __iomem *fb_base;
570 width = image->width;
571 height = image->height;
572 vxres = info->var.xres_virtual;
573 vyres = info->var.yres_virtual;
574 line_length = info->fix.line_length;
575 rincr = (width + 7) / 8;
577 /* Crop the image to the screen. */
578 if (dx > vxres || dy > vyres)
580 if (dx + width > vxres)
582 if (dy + height > vyres)
585 /* For copies that aren't pixel expansion, there's little we
586 can do better than the generic code. */
587 /* ??? There is a DMA write mode; I wonder if that could be
588 made to pull the data from the image buffer... */
589 if (image->depth > 1) {
590 cfb_imageblit(info, image);
594 regs_base = par->tga_regs_base;
595 fb_base = par->tga_fb_base;
596 is8bpp = info->var.bits_per_pixel == 8;
598 /* Expand the color values to fill 32-bits. */
599 /* ??? Would be nice to notice colour changes elsewhere, so
600 that we can do this only when necessary. */
601 fgcolor = image->fg_color;
602 bgcolor = image->bg_color;
604 fgcolor |= fgcolor << 8;
605 fgcolor |= fgcolor << 16;
606 bgcolor |= bgcolor << 8;
607 bgcolor |= bgcolor << 16;
610 fgcolor = ((u32 *)info->pseudo_palette)[fgcolor];
612 bgcolor = ((u32 *)info->pseudo_palette)[bgcolor];
614 __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG);
615 __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG);
617 /* Acquire proper alignment; set up the PIXELMASK register
618 so that we only write the proper character cell. */
619 pos = dy * line_length;
626 shift = (pos & 7) >> 2;
630 data = (const unsigned char *) image->data;
632 /* Enable opaque stipple mode. */
634 ? TGA_MODE_SBM_8BPP | TGA_MODE_OPAQUE_STIPPLE
635 : TGA_MODE_SBM_24BPP | TGA_MODE_OPAQUE_STIPPLE),
636 regs_base + TGA_MODE_REG);
638 if (width + shift <= 32) {
639 unsigned long bwidth;
641 /* Handle common case of imaging a single character, in
642 a font less than 32 pixels wide. */
644 pixelmask = (1 << width) - 1;
646 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
649 bwidth = (width + 7) / 8;
651 for (i = 0; i < height; ++i) {
654 /* The image data is bit big endian; we need
656 for (j = 0; j < bwidth; ++j)
657 mask |= bitrev[data[j]] << (j * 8);
659 __raw_writel(mask << shift, fb_base + pos);
665 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
666 } else if (shift == 0) {
667 unsigned long pos0 = pos;
668 const unsigned char *data0 = data;
669 unsigned long bincr = (is8bpp ? 8 : 8*4);
670 unsigned long bwidth;
672 /* Handle another common case in which accel_putcs
673 generates a large bitmap, which happens to be aligned.
674 Allow the tail to be misaligned. This case is
675 interesting because we've not got to hold partial
676 bytes across the words being written. */
680 bwidth = (width / 8) & -4;
681 for (i = 0; i < height; ++i) {
682 for (j = 0; j < bwidth; j += 4) {
684 mask |= bitrev[data[j+0]] << (0 * 8);
685 mask |= bitrev[data[j+1]] << (1 * 8);
686 mask |= bitrev[data[j+2]] << (2 * 8);
687 mask |= bitrev[data[j+3]] << (3 * 8);
688 __raw_writel(mask, fb_base + pos + j*bincr);
695 pixelmask = (1ul << (width & 31)) - 1;
697 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
700 pos = pos0 + bwidth*bincr;
701 data = data0 + bwidth;
702 bwidth = ((width & 31) + 7) / 8;
704 for (i = 0; i < height; ++i) {
706 for (j = 0; j < bwidth; ++j)
707 mask |= bitrev[data[j]] << (j * 8);
708 __raw_writel(mask, fb_base + pos);
713 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
716 unsigned long pos0 = pos;
717 const unsigned char *data0 = data;
718 unsigned long bincr = (is8bpp ? 8 : 8*4);
719 unsigned long bwidth;
721 /* Finally, handle the generic case of misaligned start.
722 Here we split the write into 16-bit spans. This allows
723 us to use only one pixel mask, instead of four as would
724 be required by writing 24-bit spans. */
726 pixelmask = 0xffff << shift;
727 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
730 bwidth = (width / 8) & -2;
731 for (i = 0; i < height; ++i) {
732 for (j = 0; j < bwidth; j += 2) {
734 mask |= bitrev[data[j+0]] << (0 * 8);
735 mask |= bitrev[data[j+1]] << (1 * 8);
737 __raw_writel(mask, fb_base + pos + j*bincr);
744 pixelmask = ((1ul << (width & 15)) - 1) << shift;
746 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
749 pos = pos0 + bwidth*bincr;
750 data = data0 + bwidth;
751 bwidth = (width & 15) > 8;
753 for (i = 0; i < height; ++i) {
754 u32 mask = bitrev[data[0]];
756 mask |= bitrev[data[1]] << 8;
758 __raw_writel(mask, fb_base + pos);
764 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
767 /* Disable opaque stipple mode. */
769 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
770 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
771 regs_base + TGA_MODE_REG);
775 * tgafb_fillrect - REQUIRED function. Can use generic routines if
776 * non acclerated hardware and packed pixel based.
777 * Draws a rectangle on the screen.
779 * @info: frame buffer structure that represents a single frame buffer
780 * @rect: structure defining the rectagle and operation.
783 tgafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
785 struct tga_par *par = (struct tga_par *) info->par;
786 int is8bpp = info->var.bits_per_pixel == 8;
787 u32 dx, dy, width, height, vxres, vyres, color;
788 unsigned long pos, align, line_length, i, j;
789 void __iomem *regs_base;
790 void __iomem *fb_base;
795 height = rect->height;
796 vxres = info->var.xres_virtual;
797 vyres = info->var.yres_virtual;
798 line_length = info->fix.line_length;
799 regs_base = par->tga_regs_base;
800 fb_base = par->tga_fb_base;
802 /* Crop the rectangle to the screen. */
803 if (dx > vxres || dy > vyres || !width || !height)
805 if (dx + width > vxres)
807 if (dy + height > vyres)
810 pos = dy * line_length + dx * (is8bpp ? 1 : 4);
812 /* ??? We could implement ROP_XOR with opaque fill mode
813 and a RasterOp setting of GXxor, but as far as I can
814 tell, this mode is not actually used in the kernel.
815 Thus I am ignoring it for now. */
816 if (rect->rop != ROP_COPY) {
817 cfb_fillrect(info, rect);
821 /* Expand the color value to fill 8 pixels. */
825 color |= color << 16;
826 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
827 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
830 color = ((u32 *)info->pseudo_palette)[color];
831 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
832 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
833 __raw_writel(color, regs_base + TGA_BLOCK_COLOR2_REG);
834 __raw_writel(color, regs_base + TGA_BLOCK_COLOR3_REG);
835 __raw_writel(color, regs_base + TGA_BLOCK_COLOR4_REG);
836 __raw_writel(color, regs_base + TGA_BLOCK_COLOR5_REG);
837 __raw_writel(color, regs_base + TGA_BLOCK_COLOR6_REG);
838 __raw_writel(color, regs_base + TGA_BLOCK_COLOR7_REG);
841 /* The DATA register holds the fill mask for block fill mode.
842 Since we're not stippling, this is all ones. */
843 __raw_writel(0xffffffff, regs_base + TGA_DATA_REG);
845 /* Enable block fill mode. */
847 ? TGA_MODE_SBM_8BPP | TGA_MODE_BLOCK_FILL
848 : TGA_MODE_SBM_24BPP | TGA_MODE_BLOCK_FILL),
849 regs_base + TGA_MODE_REG);
852 /* We can fill 2k pixels per operation. Notice blocks that fit
853 the width of the screen so that we can take advantage of this
854 and fill more than one line per write. */
855 if (width == line_length)
856 width *= height, height = 1;
858 /* The write into the frame buffer must be aligned to 4 bytes,
859 but we are allowed to encode the offset within the word in
860 the data word written. */
861 align = (pos & 3) << 16;
867 data = (width - 1) | align;
869 for (i = 0; i < height; ++i) {
870 __raw_writel(data, fb_base + pos);
874 unsigned long Bpp = (is8bpp ? 1 : 4);
875 unsigned long nwidth = width & -2048;
878 fdata = (2048 - 1) | align;
879 ldata = ((width & 2047) - 1) | align;
881 for (i = 0; i < height; ++i) {
882 for (j = 0; j < nwidth; j += 2048)
883 __raw_writel(fdata, fb_base + pos + j*Bpp);
885 __raw_writel(ldata, fb_base + pos + j*Bpp);
891 /* Disable block fill mode. */
893 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
894 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
895 regs_base + TGA_MODE_REG);
899 * tgafb_copyarea - REQUIRED function. Can use generic routines if
900 * non acclerated hardware and packed pixel based.
901 * Copies on area of the screen to another area.
903 * @info: frame buffer structure that represents a single frame buffer
904 * @area: structure defining the source and destination.
907 /* Handle the special case of copying entire lines, e.g. during scrolling.
908 We can avoid a lot of needless computation in this case. In the 8bpp
909 case we need to use the COPY64 registers instead of mask writes into
910 the frame buffer to achieve maximum performance. */
913 copyarea_line_8bpp(struct fb_info *info, u32 dy, u32 sy,
914 u32 height, u32 width)
916 struct tga_par *par = (struct tga_par *) info->par;
917 void __iomem *tga_regs = par->tga_regs_base;
918 unsigned long dpos, spos, i, n64;
920 /* Set up the MODE and PIXELSHIFT registers. */
921 __raw_writel(TGA_MODE_SBM_8BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
922 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
925 n64 = (height * width) / 64;
928 spos = (sy + height) * width;
929 dpos = (dy + height) * width;
931 for (i = 0; i < n64; ++i) {
934 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
936 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
943 for (i = 0; i < n64; ++i) {
944 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
946 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
953 /* Reset the MODE register to normal. */
954 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
958 copyarea_line_32bpp(struct fb_info *info, u32 dy, u32 sy,
959 u32 height, u32 width)
961 struct tga_par *par = (struct tga_par *) info->par;
962 void __iomem *tga_regs = par->tga_regs_base;
963 void __iomem *tga_fb = par->tga_fb_base;
966 unsigned long i, n16;
968 /* Set up the MODE and PIXELSHIFT registers. */
969 __raw_writel(TGA_MODE_SBM_24BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
970 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
973 n16 = (height * width) / 16;
976 src = tga_fb + (sy + height) * width * 4;
977 dst = tga_fb + (dy + height) * width * 4;
979 for (i = 0; i < n16; ++i) {
982 __raw_writel(0xffff, src);
984 __raw_writel(0xffff, dst);
988 src = tga_fb + sy * width * 4;
989 dst = tga_fb + dy * width * 4;
991 for (i = 0; i < n16; ++i) {
992 __raw_writel(0xffff, src);
994 __raw_writel(0xffff, dst);
1001 /* Reset the MODE register to normal. */
1002 __raw_writel(TGA_MODE_SBM_24BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1005 /* The general case of forward copy in 8bpp mode. */
1007 copyarea_foreward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1008 u32 height, u32 width, u32 line_length)
1010 struct tga_par *par = (struct tga_par *) info->par;
1011 unsigned long i, copied, left;
1012 unsigned long dpos, spos, dalign, salign, yincr;
1013 u32 smask_first, dmask_first, dmask_last;
1014 int pixel_shift, need_prime, need_second;
1015 unsigned long n64, n32, xincr_first;
1016 void __iomem *tga_regs;
1017 void __iomem *tga_fb;
1019 yincr = line_length;
1026 /* Compute the offsets and alignments in the frame buffer.
1027 More than anything else, these control how we do copies. */
1028 dpos = dy * line_length + dx;
1029 spos = sy * line_length + sx;
1035 /* Compute the value for the PIXELSHIFT register. This controls
1036 both non-co-aligned source and destination and copy direction. */
1037 if (dalign >= salign)
1038 pixel_shift = dalign - salign;
1040 pixel_shift = 8 - (salign - dalign);
1042 /* Figure out if we need an additional priming step for the
1043 residue register. */
1044 need_prime = (salign > dalign);
1048 /* Begin by copying the leading unaligned destination. Copy enough
1049 to make the next destination address 32-byte aligned. */
1050 copied = 32 - (dalign + (dpos & 31));
1053 xincr_first = (copied + 7) & -8;
1054 smask_first = dmask_first = (1ul << copied) - 1;
1055 smask_first <<= salign;
1056 dmask_first <<= dalign + need_prime*8;
1057 if (need_prime && copied > 24)
1059 left = width - copied;
1061 /* Care for small copies. */
1062 if (copied > width) {
1064 t = (1ul << width) - 1;
1065 t <<= dalign + need_prime*8;
1070 /* Attempt to use 64-byte copies. This is only possible if the
1071 source and destination are co-aligned at 64 bytes. */
1072 n64 = need_second = 0;
1073 if ((dpos & 63) == (spos & 63)
1074 && (height == 1 || line_length % 64 == 0)) {
1075 /* We may need a 32-byte copy to ensure 64 byte alignment. */
1076 need_second = (dpos + xincr_first) & 63;
1077 if ((need_second & 32) != need_second)
1078 printk(KERN_ERR "tgafb: need_second wrong\n");
1079 if (left >= need_second + 64) {
1080 left -= need_second;
1087 /* Copy trailing full 32-byte sections. This will be the main
1088 loop if the 64 byte loop can't be used. */
1092 /* Copy the trailing unaligned destination. */
1093 dmask_last = (1ul << left) - 1;
1095 tga_regs = par->tga_regs_base;
1096 tga_fb = par->tga_fb_base;
1098 /* Set up the MODE and PIXELSHIFT registers. */
1099 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1100 __raw_writel(pixel_shift, tga_regs+TGA_PIXELSHIFT_REG);
1103 for (i = 0; i < height; ++i) {
1108 sfb = tga_fb + spos;
1109 dfb = tga_fb + dpos;
1111 __raw_writel(smask_first, sfb);
1113 __raw_writel(dmask_first, dfb);
1120 __raw_writel(0xffffffff, sfb);
1122 __raw_writel(0xffffffff, dfb);
1128 if (n64 && (((unsigned long)sfb | (unsigned long)dfb) & 63))
1130 "tgafb: misaligned copy64 (s:%p, d:%p)\n",
1133 for (j = 0; j < n64; ++j) {
1134 __raw_writel(sfb - tga_fb, tga_regs+TGA_COPY64_SRC);
1136 __raw_writel(dfb - tga_fb, tga_regs+TGA_COPY64_DST);
1142 for (j = 0; j < n32; ++j) {
1143 __raw_writel(0xffffffff, sfb);
1145 __raw_writel(0xffffffff, dfb);
1152 __raw_writel(0xffffffff, sfb);
1154 __raw_writel(dmask_last, dfb);
1162 /* Reset the MODE register to normal. */
1163 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1166 /* The (almost) general case of backward copy in 8bpp mode. */
1168 copyarea_backward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1169 u32 height, u32 width, u32 line_length,
1170 const struct fb_copyarea *area)
1172 struct tga_par *par = (struct tga_par *) info->par;
1173 unsigned long i, left, yincr;
1174 unsigned long depos, sepos, dealign, sealign;
1175 u32 mask_first, mask_last;
1177 void __iomem *tga_regs;
1178 void __iomem *tga_fb;
1180 yincr = line_length;
1187 /* Compute the offsets and alignments in the frame buffer.
1188 More than anything else, these control how we do copies. */
1189 depos = dy * line_length + dx + width;
1190 sepos = sy * line_length + sx + width;
1191 dealign = depos & 7;
1192 sealign = sepos & 7;
1194 /* ??? The documentation appears to be incorrect (or very
1195 misleading) wrt how pixel shifting works in backward copy
1196 mode, i.e. when PIXELSHIFT is negative. I give up for now.
1197 Do handle the common case of co-aligned backward copies,
1198 but frob everything else back on generic code. */
1199 if (dealign != sealign) {
1200 cfb_copyarea(info, area);
1204 /* We begin the copy with the trailing pixels of the
1205 unaligned destination. */
1206 mask_first = (1ul << dealign) - 1;
1207 left = width - dealign;
1209 /* Care for small copies. */
1210 if (dealign > width) {
1211 mask_first ^= (1ul << (dealign - width)) - 1;
1215 /* Next copy full words at a time. */
1219 /* Finally copy the unaligned head of the span. */
1220 mask_last = -1 << (32 - left);
1222 tga_regs = par->tga_regs_base;
1223 tga_fb = par->tga_fb_base;
1225 /* Set up the MODE and PIXELSHIFT registers. */
1226 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1227 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1230 for (i = 0; i < height; ++i) {
1235 sfb = tga_fb + sepos;
1236 dfb = tga_fb + depos;
1238 __raw_writel(mask_first, sfb);
1240 __raw_writel(mask_first, dfb);
1244 for (j = 0; j < n32; ++j) {
1247 __raw_writel(0xffffffff, sfb);
1249 __raw_writel(0xffffffff, dfb);
1256 __raw_writel(mask_last, sfb);
1258 __raw_writel(mask_last, dfb);
1266 /* Reset the MODE register to normal. */
1267 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1271 tgafb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1273 unsigned long dx, dy, width, height, sx, sy, vxres, vyres;
1274 unsigned long line_length, bpp;
1278 width = area->width;
1279 height = area->height;
1282 vxres = info->var.xres_virtual;
1283 vyres = info->var.yres_virtual;
1284 line_length = info->fix.line_length;
1286 /* The top left corners must be in the virtual screen. */
1287 if (dx > vxres || sx > vxres || dy > vyres || sy > vyres)
1290 /* Clip the destination. */
1291 if (dx + width > vxres)
1293 if (dy + height > vyres)
1294 height = vyres - dy;
1296 /* The source must be completely inside the virtual screen. */
1297 if (sx + width > vxres || sy + height > vyres)
1300 bpp = info->var.bits_per_pixel;
1302 /* Detect copies of the entire line. */
1303 if (width * (bpp >> 3) == line_length) {
1305 copyarea_line_8bpp(info, dy, sy, height, width);
1307 copyarea_line_32bpp(info, dy, sy, height, width);
1310 /* ??? The documentation is unclear to me exactly how the pixelshift
1311 register works in 32bpp mode. Since I don't have hardware to test,
1312 give up for now and fall back on the generic routines. */
1314 cfb_copyarea(info, area);
1316 /* Detect overlapping source and destination that requires
1318 else if (dy == sy && dx > sx && dx < sx + width)
1319 copyarea_backward_8bpp(info, dx, dy, sx, sy, height,
1320 width, line_length, area);
1322 copyarea_foreward_8bpp(info, dx, dy, sx, sy, height,
1323 width, line_length);
1332 tgafb_init_fix(struct fb_info *info)
1334 struct tga_par *par = (struct tga_par *)info->par;
1335 u8 tga_type = par->tga_type;
1336 const char *tga_type_name;
1339 case TGA_TYPE_8PLANE:
1340 tga_type_name = "Digital ZLXp-E1";
1342 case TGA_TYPE_24PLANE:
1343 tga_type_name = "Digital ZLXp-E2";
1345 case TGA_TYPE_24PLUSZ:
1346 tga_type_name = "Digital ZLXp-E3";
1349 tga_type_name = "Unknown";
1353 strlcpy(info->fix.id, tga_type_name, sizeof(info->fix.id));
1355 info->fix.type = FB_TYPE_PACKED_PIXELS;
1356 info->fix.type_aux = 0;
1357 info->fix.visual = (tga_type == TGA_TYPE_8PLANE
1358 ? FB_VISUAL_PSEUDOCOLOR
1359 : FB_VISUAL_TRUECOLOR);
1361 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3);
1362 info->fix.smem_start = (size_t) par->tga_fb_base;
1363 info->fix.smem_len = info->fix.line_length * par->yres;
1364 info->fix.mmio_start = (size_t) par->tga_regs_base;
1365 info->fix.mmio_len = 512;
1367 info->fix.xpanstep = 0;
1368 info->fix.ypanstep = 0;
1369 info->fix.ywrapstep = 0;
1371 info->fix.accel = FB_ACCEL_DEC_TGA;
1374 static __devinit int
1375 tgafb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent)
1377 static unsigned int const fb_offset_presets[4] = {
1378 TGA_8PLANE_FB_OFFSET,
1379 TGA_24PLANE_FB_OFFSET,
1381 TGA_24PLUSZ_FB_OFFSET
1385 struct fb_info info;
1387 u32 pseudo_palette[16];
1390 void __iomem *mem_base;
1391 unsigned long bar0_start, bar0_len;
1395 /* Enable device in PCI config. */
1396 if (pci_enable_device(pdev)) {
1397 printk(KERN_ERR "tgafb: Cannot enable PCI device\n");
1401 /* Allocate the fb and par structures. */
1402 all = kmalloc(sizeof(*all), GFP_KERNEL);
1404 printk(KERN_ERR "tgafb: Cannot allocate memory\n");
1407 memset(all, 0, sizeof(*all));
1408 pci_set_drvdata(pdev, all);
1410 /* Request the mem regions. */
1411 bar0_start = pci_resource_start(pdev, 0);
1412 bar0_len = pci_resource_len(pdev, 0);
1414 if (!request_mem_region (bar0_start, bar0_len, "tgafb")) {
1415 printk(KERN_ERR "tgafb: cannot reserve FB region\n");
1419 /* Map the framebuffer. */
1420 mem_base = ioremap(bar0_start, bar0_len);
1422 printk(KERN_ERR "tgafb: Cannot map MMIO\n");
1426 /* Grab info about the card. */
1427 tga_type = (readl(mem_base) >> 12) & 0x0f;
1428 all->par.pdev = pdev;
1429 all->par.tga_mem_base = mem_base;
1430 all->par.tga_fb_base = mem_base + fb_offset_presets[tga_type];
1431 all->par.tga_regs_base = mem_base + TGA_REGS_OFFSET;
1432 all->par.tga_type = tga_type;
1433 pci_read_config_byte(pdev, PCI_REVISION_ID, &all->par.tga_chip_rev);
1435 /* Setup framebuffer. */
1436 all->info.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
1437 FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT;
1438 all->info.fbops = &tgafb_ops;
1439 all->info.screen_base = all->par.tga_fb_base;
1440 all->info.par = &all->par;
1441 all->info.pseudo_palette = all->pseudo_palette;
1443 /* This should give a reasonable default video mode. */
1445 ret = fb_find_mode(&all->info.var, &all->info, mode_option,
1447 tga_type == TGA_TYPE_8PLANE ? 8 : 32);
1448 if (ret == 0 || ret == 4) {
1449 printk(KERN_ERR "tgafb: Could not find valid video mode\n");
1454 if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
1455 printk(KERN_ERR "tgafb: Could not allocate color map\n");
1460 tgafb_set_par(&all->info);
1461 tgafb_init_fix(&all->info);
1463 all->info.device = &pdev->dev;
1464 if (register_framebuffer(&all->info) < 0) {
1465 printk(KERN_ERR "tgafb: Could not register framebuffer\n");
1470 printk(KERN_INFO "tgafb: DC21030 [TGA] detected, rev=0x%02x\n",
1471 all->par.tga_chip_rev);
1472 printk(KERN_INFO "tgafb: at PCI bus %d, device %d, function %d\n",
1473 pdev->bus->number, PCI_SLOT(pdev->devfn),
1474 PCI_FUNC(pdev->devfn));
1475 printk(KERN_INFO "fb%d: %s frame buffer device at 0x%lx\n",
1476 all->info.node, all->info.fix.id, bar0_start);
1481 release_mem_region(bar0_start, bar0_len);
1489 tgafb_pci_unregister(struct pci_dev *pdev)
1491 struct fb_info *info = pci_get_drvdata(pdev);
1492 struct tga_par *par = info->par;
1496 unregister_framebuffer(info);
1497 iounmap(par->tga_mem_base);
1498 release_mem_region(pci_resource_start(pdev, 0),
1499 pci_resource_len(pdev, 0));
1506 pci_unregister_driver(&tgafb_driver);
1512 tgafb_setup(char *arg)
1517 while ((this_opt = strsep(&arg, ","))) {
1520 if (!strncmp(this_opt, "mode:", 5))
1521 mode_option = this_opt+5;
1524 "tgafb: unknown parameter %s\n",
1531 #endif /* !MODULE */
1537 char *option = NULL;
1539 if (fb_get_options("tgafb", &option))
1541 tgafb_setup(option);
1543 return pci_register_driver(&tgafb_driver);
1550 module_init(tgafb_init);
1553 module_exit(tgafb_exit);
1556 MODULE_DESCRIPTION("framebuffer driver for TGA chipset");
1557 MODULE_LICENSE("GPL");