drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c

   1 /*
   2  * ti_hdmi_4xxx_ip.c
   3  *
   4  * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
   6  * Authors: Yong Zhi
   7  *      Mythri pk <mythripk@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License version 2 as published by
  11  * the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along with
  19  * this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/err.h>
  25 #include <linux/io.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/mutex.h>
  28 #include <linux/delay.h>
  29 #include <linux/string.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/gpio.h>
  32
  33 #include "ti_hdmi_4xxx_ip.h"
  34 #include "dss.h"
  35
  36 static inline void hdmi_write_reg(void __iomem *base_addr,
  37                                 const u16 idx, u32 val)
  38 {
  39         __raw_writel(val, base_addr + idx);
  40 }
  41
  42 static inline u32 hdmi_read_reg(void __iomem *base_addr,
  43                                 const u16 idx)
  44 {
  45         return __raw_readl(base_addr + idx);
  46 }
  47
  48 static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data)
  49 {
  50         return ip_data->base_wp;
  51 }
  52
  53 static inline void __iomem *hdmi_phy_base(struct hdmi_ip_data *ip_data)
  54 {
  55         return ip_data->base_wp + ip_data->phy_offset;
  56 }
  57
  58 static inline void __iomem *hdmi_pll_base(struct hdmi_ip_data *ip_data)
  59 {
  60         return ip_data->base_wp + ip_data->pll_offset;
  61 }
  62
  63 static inline void __iomem *hdmi_av_base(struct hdmi_ip_data *ip_data)
  64 {
  65         return ip_data->base_wp + ip_data->core_av_offset;
  66 }
  67
  68 static inline void __iomem *hdmi_core_sys_base(struct hdmi_ip_data *ip_data)
  69 {
  70         return ip_data->base_wp + ip_data->core_sys_offset;
  71 }
  72
  73 static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
  74                                 const u16 idx,
  75                                 int b2, int b1, u32 val)
  76 {
  77         u32 t = 0;
  78         while (val != REG_GET(base_addr, idx, b2, b1)) {
  79                 udelay(1);
  80                 if (t++ > 10000)
  81                         return !val;
  82         }
  83         return val;
  84 }
  85
  86 static int hdmi_pll_init(struct hdmi_ip_data *ip_data)
  87 {
  88         u32 r;
  89         void __iomem *pll_base = hdmi_pll_base(ip_data);
  90         struct hdmi_pll_info *fmt = &ip_data->pll_data;
  91
  92         /* PLL start always use manual mode */
  93         REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
  94
  95         r = hdmi_read_reg(pll_base, PLLCTRL_CFG1);
  96         r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
  97         r = FLD_MOD(r, fmt->regn - 1, 8, 1);  /* CFG1_PLL_REGN */
  98
  99         hdmi_write_reg(pll_base, PLLCTRL_CFG1, r);
 100
 101         r = hdmi_read_reg(pll_base, PLLCTRL_CFG2);
 102
 103         r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
 104         r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
 105         r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
 106         r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */
 107
 108         if (fmt->dcofreq) {
 109                 /* divider programming for frequency beyond 1000Mhz */
 110                 REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
 111                 r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
 112         } else {
 113                 r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
 114         }
 115
 116         hdmi_write_reg(pll_base, PLLCTRL_CFG2, r);
 117
 118         r = hdmi_read_reg(pll_base, PLLCTRL_CFG4);
 119         r = FLD_MOD(r, fmt->regm2, 24, 18);
 120         r = FLD_MOD(r, fmt->regmf, 17, 0);
 121
 122         hdmi_write_reg(pll_base, PLLCTRL_CFG4, r);
 123
 124         /* go now */
 125         REG_FLD_MOD(pll_base, PLLCTRL_PLL_GO, 0x1, 0, 0);
 126
 127         /* wait for bit change */
 128         if (hdmi_wait_for_bit_change(pll_base, PLLCTRL_PLL_GO,
 129                                                         0, 0, 1) != 1) {
 130                 pr_err("PLL GO bit not set\n");
 131                 return -ETIMEDOUT;
 132         }
 133
 134         /* Wait till the lock bit is set in PLL status */
 135         if (hdmi_wait_for_bit_change(pll_base,
 136                                 PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) {
 137                 pr_err("cannot lock PLL\n");
 138                 pr_err("CFG1 0x%x\n",
 139                         hdmi_read_reg(pll_base, PLLCTRL_CFG1));
 140                 pr_err("CFG2 0x%x\n",
 141                         hdmi_read_reg(pll_base, PLLCTRL_CFG2));
 142                 pr_err("CFG4 0x%x\n",
 143                         hdmi_read_reg(pll_base, PLLCTRL_CFG4));
 144                 return -ETIMEDOUT;
 145         }
 146
 147         pr_debug("PLL locked!\n");
 148
 149         return 0;
 150 }
 151
 152 /* PHY_PWR_CMD */
 153 static int hdmi_set_phy_pwr(struct hdmi_ip_data *ip_data, enum hdmi_phy_pwr val)
 154 {
 155         /* Command for power control of HDMI PHY */
 156         REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 7, 6);
 157
 158         /* Status of the power control of HDMI PHY */
 159         if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data),
 160                                 HDMI_WP_PWR_CTRL, 5, 4, val) != val) {
 161                 pr_err("Failed to set PHY power mode to %d\n", val);
 162                 return -ETIMEDOUT;
 163         }
 164
 165         return 0;
 166 }
 167
 168 /* PLL_PWR_CMD */
 169 static int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val)
 170 {
 171         /* Command for power control of HDMI PLL */
 172         REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 3, 2);
 173
 174         /* wait till PHY_PWR_STATUS is set */
 175         if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL,
 176                                                 1, 0, val) != val) {
 177                 pr_err("Failed to set PLL_PWR_STATUS\n");
 178                 return -ETIMEDOUT;
 179         }
 180
 181         return 0;
 182 }
 183
 184 static int hdmi_pll_reset(struct hdmi_ip_data *ip_data)
 185 {
 186         /* SYSRESET  controlled by power FSM */
 187         REG_FLD_MOD(hdmi_pll_base(ip_data), PLLCTRL_PLL_CONTROL, 0x0, 3, 3);
 188
 189         /* READ 0x0 reset is in progress */
 190         if (hdmi_wait_for_bit_change(hdmi_pll_base(ip_data),
 191                                 PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) {
 192                 pr_err("Failed to sysreset PLL\n");
 193                 return -ETIMEDOUT;
 194         }
 195
 196         return 0;
 197 }
 198
 199 int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data)
 200 {
 201         u16 r = 0;
 202
 203         r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
 204         if (r)
 205                 return r;
 206
 207         r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
 208         if (r)
 209                 return r;
 210
 211         r = hdmi_pll_reset(ip_data);
 212         if (r)
 213                 return r;
 214
 215         r = hdmi_pll_init(ip_data);
 216         if (r)
 217                 return r;
 218
 219         return 0;
 220 }
 221
 222 void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data)
 223 {
 224         hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
 225 }
 226
 227 static int hdmi_check_hpd_state(struct hdmi_ip_data *ip_data)
 228 {
 229         unsigned long flags;
 230         bool hpd;
 231         int r;
 232         /* this should be in ti_hdmi_4xxx_ip private data */
 233         static DEFINE_SPINLOCK(phy_tx_lock);
 234
 235         spin_lock_irqsave(&phy_tx_lock, flags);
 236
 237         hpd = gpio_get_value(ip_data->hpd_gpio);
 238
 239         if (hpd == ip_data->phy_tx_enabled) {
 240                 spin_unlock_irqrestore(&phy_tx_lock, flags);
 241                 return 0;
 242         }
 243
 244         if (hpd)
 245                 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON);
 246         else
 247                 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
 248
 249         if (r) {
 250                 DSSERR("Failed to %s PHY TX power\n",
 251                                 hpd ? "enable" : "disable");
 252                 goto err;
 253         }
 254
 255         ip_data->phy_tx_enabled = hpd;
 256 err:
 257         spin_unlock_irqrestore(&phy_tx_lock, flags);
 258         return r;
 259 }
 260
 261 static irqreturn_t hpd_irq_handler(int irq, void *data)
 262 {
 263         struct hdmi_ip_data *ip_data = data;
 264
 265         hdmi_check_hpd_state(ip_data);
 266
 267         return IRQ_HANDLED;
 268 }
 269
 270 int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data)
 271 {
 272         u16 r = 0;
 273         void __iomem *phy_base = hdmi_phy_base(ip_data);
 274
 275         r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
 276         if (r)
 277                 return r;
 278
 279         /*
 280          * Read address 0 in order to get the SCP reset done completed
 281          * Dummy access performed to make sure reset is done
 282          */
 283         hdmi_read_reg(phy_base, HDMI_TXPHY_TX_CTRL);
 284
 285         /*
 286          * Write to phy address 0 to configure the clock
 287          * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
 288          */
 289         REG_FLD_MOD(phy_base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30);
 290
 291         /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
 292         hdmi_write_reg(phy_base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
 293
 294         /* Setup max LDO voltage */
 295         REG_FLD_MOD(phy_base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
 296
 297         /* Write to phy address 3 to change the polarity control */
 298         REG_FLD_MOD(phy_base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27);
 299
 300         r = request_threaded_irq(gpio_to_irq(ip_data->hpd_gpio),
 301                         NULL, hpd_irq_handler,
 302                         IRQF_DISABLED | IRQF_TRIGGER_RISING |
 303                         IRQF_TRIGGER_FALLING, "hpd", ip_data);
 304         if (r) {
 305                 DSSERR("HPD IRQ request failed\n");
 306                 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
 307                 return r;
 308         }
 309
 310         r = hdmi_check_hpd_state(ip_data);
 311         if (r) {
 312                 free_irq(gpio_to_irq(ip_data->hpd_gpio), ip_data);
 313                 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
 314                 return r;
 315         }
 316
 317         return 0;
 318 }
 319
 320 void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data)
 321 {
 322         free_irq(gpio_to_irq(ip_data->hpd_gpio), ip_data);
 323
 324         hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
 325         ip_data->phy_tx_enabled = false;
 326 }
 327
 328 static int hdmi_core_ddc_init(struct hdmi_ip_data *ip_data)
 329 {
 330         void __iomem *base = hdmi_core_sys_base(ip_data);
 331
 332         /* Turn on CLK for DDC */
 333         REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0);
 334
 335         /* IN_PROG */
 336         if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) {
 337                 /* Abort transaction */
 338                 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0);
 339                 /* IN_PROG */
 340                 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
 341                                         4, 4, 0) != 0) {
 342                         DSSERR("Timeout aborting DDC transaction\n");
 343                         return -ETIMEDOUT;
 344                 }
 345         }
 346
 347         /* Clk SCL Devices */
 348         REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0);
 349
 350         /* HDMI_CORE_DDC_STATUS_IN_PROG */
 351         if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
 352                                 4, 4, 0) != 0) {
 353                 DSSERR("Timeout starting SCL clock\n");
 354                 return -ETIMEDOUT;
 355         }
 356
 357         /* Clear FIFO */
 358         REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0);
 359
 360         /* HDMI_CORE_DDC_STATUS_IN_PROG */
 361         if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
 362                                 4, 4, 0) != 0) {
 363                 DSSERR("Timeout clearing DDC fifo\n");
 364                 return -ETIMEDOUT;
 365         }
 366
 367         return 0;
 368 }
 369
 370 static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data,
 371                 u8 *pedid, int ext)
 372 {
 373         void __iomem *base = hdmi_core_sys_base(ip_data);
 374         u32 i;
 375         char checksum;
 376         u32 offset = 0;
 377
 378         /* HDMI_CORE_DDC_STATUS_IN_PROG */
 379         if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
 380                                 4, 4, 0) != 0) {
 381                 DSSERR("Timeout waiting DDC to be ready\n");
 382                 return -ETIMEDOUT;
 383         }
 384
 385         if (ext % 2 != 0)
 386                 offset = 0x80;
 387
 388         /* Load Segment Address Register */
 389         REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0);
 390
 391         /* Load Slave Address Register */
 392         REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
 393
 394         /* Load Offset Address Register */
 395         REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0);
 396
 397         /* Load Byte Count */
 398         REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0);
 399         REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0);
 400
 401         /* Set DDC_CMD */
 402         if (ext)
 403                 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0);
 404         else
 405                 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
 406
 407         /* HDMI_CORE_DDC_STATUS_BUS_LOW */
 408         if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) {
 409                 pr_err("I2C Bus Low?\n");
 410                 return -EIO;
 411         }
 412         /* HDMI_CORE_DDC_STATUS_NO_ACK */
 413         if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) {
 414                 pr_err("I2C No Ack\n");
 415                 return -EIO;
 416         }
 417
 418         for (i = 0; i < 0x80; ++i) {
 419                 int t;
 420
 421                 /* IN_PROG */
 422                 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) {
 423                         DSSERR("operation stopped when reading edid\n");
 424                         return -EIO;
 425                 }
 426
 427                 t = 0;
 428                 /* FIFO_EMPTY */
 429                 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) {
 430                         if (t++ > 10000) {
 431                                 DSSERR("timeout reading edid\n");
 432                                 return -ETIMEDOUT;
 433                         }
 434                         udelay(1);
 435                 }
 436
 437                 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0);
 438         }
 439
 440         checksum = 0;
 441         for (i = 0; i < 0x80; ++i)
 442                 checksum += pedid[i];
 443
 444         if (checksum != 0) {
 445                 pr_err("E-EDID checksum failed!!\n");
 446                 return -EIO;
 447         }
 448
 449         return 0;
 450 }
 451
 452 int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data,
 453                                 u8 *edid, int len)
 454 {
 455         int r, l;
 456
 457         if (len < 128)
 458                 return -EINVAL;
 459
 460         r = hdmi_core_ddc_init(ip_data);
 461         if (r)
 462                 return r;
 463
 464         r = hdmi_core_ddc_edid(ip_data, edid, 0);
 465         if (r)
 466                 return r;
 467
 468         l = 128;
 469
 470         if (len >= 128 * 2 && edid[0x7e] > 0) {
 471                 r = hdmi_core_ddc_edid(ip_data, edid + 0x80, 1);
 472                 if (r)
 473                         return r;
 474                 l += 128;
 475         }
 476
 477         return l;
 478 }
 479
 480 bool ti_hdmi_4xxx_detect(struct hdmi_ip_data *ip_data)
 481 {
 482         int r;
 483
 484         void __iomem *base = hdmi_core_sys_base(ip_data);
 485
 486         /* HPD */
 487         r = REG_GET(base, HDMI_CORE_SYS_SYS_STAT, 1, 1);
 488
 489         return r == 1;
 490 }
 491
 492 static void hdmi_core_init(struct hdmi_core_video_config *video_cfg,
 493                         struct hdmi_core_infoframe_avi *avi_cfg,
 494                         struct hdmi_core_packet_enable_repeat *repeat_cfg)
 495 {
 496         pr_debug("Enter hdmi_core_init\n");
 497
 498         /* video core */
 499         video_cfg->ip_bus_width = HDMI_INPUT_8BIT;
 500         video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT;
 501         video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE;
 502         video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE;
 503         video_cfg->hdmi_dvi = HDMI_DVI;
 504         video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
 505
 506         /* info frame */
 507         avi_cfg->db1_format = 0;
 508         avi_cfg->db1_active_info = 0;
 509         avi_cfg->db1_bar_info_dv = 0;
 510         avi_cfg->db1_scan_info = 0;
 511         avi_cfg->db2_colorimetry = 0;
 512         avi_cfg->db2_aspect_ratio = 0;
 513         avi_cfg->db2_active_fmt_ar = 0;
 514         avi_cfg->db3_itc = 0;
 515         avi_cfg->db3_ec = 0;
 516         avi_cfg->db3_q_range = 0;
 517         avi_cfg->db3_nup_scaling = 0;
 518         avi_cfg->db4_videocode = 0;
 519         avi_cfg->db5_pixel_repeat = 0;
 520         avi_cfg->db6_7_line_eoftop = 0 ;
 521         avi_cfg->db8_9_line_sofbottom = 0;
 522         avi_cfg->db10_11_pixel_eofleft = 0;
 523         avi_cfg->db12_13_pixel_sofright = 0;
 524
 525         /* packet enable and repeat */
 526         repeat_cfg->audio_pkt = 0;
 527         repeat_cfg->audio_pkt_repeat = 0;
 528         repeat_cfg->avi_infoframe = 0;
 529         repeat_cfg->avi_infoframe_repeat = 0;
 530         repeat_cfg->gen_cntrl_pkt = 0;
 531         repeat_cfg->gen_cntrl_pkt_repeat = 0;
 532         repeat_cfg->generic_pkt = 0;
 533         repeat_cfg->generic_pkt_repeat = 0;
 534 }
 535
 536 static void hdmi_core_powerdown_disable(struct hdmi_ip_data *ip_data)
 537 {
 538         pr_debug("Enter hdmi_core_powerdown_disable\n");
 539         REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_CTRL1, 0x0, 0, 0);
 540 }
 541
 542 static void hdmi_core_swreset_release(struct hdmi_ip_data *ip_data)
 543 {
 544         pr_debug("Enter hdmi_core_swreset_release\n");
 545         REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x0, 0, 0);
 546 }
 547
 548 static void hdmi_core_swreset_assert(struct hdmi_ip_data *ip_data)
 549 {
 550         pr_debug("Enter hdmi_core_swreset_assert\n");
 551         REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x1, 0, 0);
 552 }
 553
 554 /* HDMI_CORE_VIDEO_CONFIG */
 555 static void hdmi_core_video_config(struct hdmi_ip_data *ip_data,
 556                                 struct hdmi_core_video_config *cfg)
 557 {
 558         u32 r = 0;
 559         void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
 560
 561         /* sys_ctrl1 default configuration not tunable */
 562         r = hdmi_read_reg(core_sys_base, HDMI_CORE_CTRL1);
 563         r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
 564         r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
 565         r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2);
 566         r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1);
 567         hdmi_write_reg(core_sys_base, HDMI_CORE_CTRL1, r);
 568
 569         REG_FLD_MOD(core_sys_base,
 570                         HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6);
 571
 572         /* Vid_Mode */
 573         r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE);
 574
 575         /* dither truncation configuration */
 576         if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) {
 577                 r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6);
 578                 r = FLD_MOD(r, 1, 5, 5);
 579         } else {
 580                 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6);
 581                 r = FLD_MOD(r, 0, 5, 5);
 582         }
 583         hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r);
 584
 585         /* HDMI_Ctrl */
 586         r = hdmi_read_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL);
 587         r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6);
 588         r = FLD_MOD(r, cfg->pkt_mode, 5, 3);
 589         r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0);
 590         hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL, r);
 591
 592         /* TMDS_CTRL */
 593         REG_FLD_MOD(core_sys_base,
 594                         HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5);
 595 }
 596
 597 static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data,
 598                 struct hdmi_core_infoframe_avi info_avi)
 599 {
 600         u32 val;
 601         char sum = 0, checksum = 0;
 602         void __iomem *av_base = hdmi_av_base(ip_data);
 603
 604         sum += 0x82 + 0x002 + 0x00D;
 605         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082);
 606         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_VERS, 0x002);
 607         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_LEN, 0x00D);
 608
 609         val = (info_avi.db1_format << 5) |
 610                 (info_avi.db1_active_info << 4) |
 611                 (info_avi.db1_bar_info_dv << 2) |
 612                 (info_avi.db1_scan_info);
 613         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(0), val);
 614         sum += val;
 615
 616         val = (info_avi.db2_colorimetry << 6) |
 617                 (info_avi.db2_aspect_ratio << 4) |
 618                 (info_avi.db2_active_fmt_ar);
 619         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(1), val);
 620         sum += val;
 621
 622         val = (info_avi.db3_itc << 7) |
 623                 (info_avi.db3_ec << 4) |
 624                 (info_avi.db3_q_range << 2) |
 625                 (info_avi.db3_nup_scaling);
 626         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(2), val);
 627         sum += val;
 628
 629         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(3),
 630                                         info_avi.db4_videocode);
 631         sum += info_avi.db4_videocode;
 632
 633         val = info_avi.db5_pixel_repeat;
 634         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(4), val);
 635         sum += val;
 636
 637         val = info_avi.db6_7_line_eoftop & 0x00FF;
 638         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(5), val);
 639         sum += val;
 640
 641         val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF);
 642         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(6), val);
 643         sum += val;
 644
 645         val = info_avi.db8_9_line_sofbottom & 0x00FF;
 646         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(7), val);
 647         sum += val;
 648
 649         val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF);
 650         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(8), val);
 651         sum += val;
 652
 653         val = info_avi.db10_11_pixel_eofleft & 0x00FF;
 654         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(9), val);
 655         sum += val;
 656
 657         val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF);
 658         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(10), val);
 659         sum += val;
 660
 661         val = info_avi.db12_13_pixel_sofright & 0x00FF;
 662         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(11), val);
 663         sum += val;
 664
 665         val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF);
 666         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(12), val);
 667         sum += val;
 668
 669         checksum = 0x100 - sum;
 670         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum);
 671 }
 672
 673 static void hdmi_core_av_packet_config(struct hdmi_ip_data *ip_data,
 674                 struct hdmi_core_packet_enable_repeat repeat_cfg)
 675 {
 676         /* enable/repeat the infoframe */
 677         hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL1,
 678                 (repeat_cfg.audio_pkt << 5) |
 679                 (repeat_cfg.audio_pkt_repeat << 4) |
 680                 (repeat_cfg.avi_infoframe << 1) |
 681                 (repeat_cfg.avi_infoframe_repeat));
 682
 683         /* enable/repeat the packet */
 684         hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL2,
 685                 (repeat_cfg.gen_cntrl_pkt << 3) |
 686                 (repeat_cfg.gen_cntrl_pkt_repeat << 2) |
 687                 (repeat_cfg.generic_pkt << 1) |
 688                 (repeat_cfg.generic_pkt_repeat));
 689 }
 690
 691 static void hdmi_wp_init(struct omap_video_timings *timings,
 692                         struct hdmi_video_format *video_fmt,
 693                         struct hdmi_video_interface *video_int)
 694 {
 695         pr_debug("Enter hdmi_wp_init\n");
 696
 697         timings->hbp = 0;
 698         timings->hfp = 0;
 699         timings->hsw = 0;
 700         timings->vbp = 0;
 701         timings->vfp = 0;
 702         timings->vsw = 0;
 703
 704         video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
 705         video_fmt->y_res = 0;
 706         video_fmt->x_res = 0;
 707
 708         video_int->vsp = 0;
 709         video_int->hsp = 0;
 710
 711         video_int->interlacing = 0;
 712         video_int->tm = 0; /* HDMI_TIMING_SLAVE */
 713
 714 }
 715
 716 void ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data, bool start)
 717 {
 718         REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, start, 31, 31);
 719 }
 720
 721 static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt,
 722         struct omap_video_timings *timings, struct hdmi_config *param)
 723 {
 724         pr_debug("Enter hdmi_wp_video_init_format\n");
 725
 726         video_fmt->y_res = param->timings.timings.y_res;
 727         video_fmt->x_res = param->timings.timings.x_res;
 728
 729         timings->hbp = param->timings.timings.hbp;
 730         timings->hfp = param->timings.timings.hfp;
 731         timings->hsw = param->timings.timings.hsw;
 732         timings->vbp = param->timings.timings.vbp;
 733         timings->vfp = param->timings.timings.vfp;
 734         timings->vsw = param->timings.timings.vsw;
 735 }
 736
 737 static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data,
 738                 struct hdmi_video_format *video_fmt)
 739 {
 740         u32 l = 0;
 741
 742         REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG,
 743                         video_fmt->packing_mode, 10, 8);
 744
 745         l |= FLD_VAL(video_fmt->y_res, 31, 16);
 746         l |= FLD_VAL(video_fmt->x_res, 15, 0);
 747         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_SIZE, l);
 748 }
 749
 750 static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data,
 751                 struct hdmi_video_interface *video_int)
 752 {
 753         u32 r;
 754         pr_debug("Enter hdmi_wp_video_config_interface\n");
 755
 756         r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG);
 757         r = FLD_MOD(r, video_int->vsp, 7, 7);
 758         r = FLD_MOD(r, video_int->hsp, 6, 6);
 759         r = FLD_MOD(r, video_int->interlacing, 3, 3);
 760         r = FLD_MOD(r, video_int->tm, 1, 0);
 761         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r);
 762 }
 763
 764 static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data,
 765                 struct omap_video_timings *timings)
 766 {
 767         u32 timing_h = 0;
 768         u32 timing_v = 0;
 769
 770         pr_debug("Enter hdmi_wp_video_config_timing\n");
 771
 772         timing_h |= FLD_VAL(timings->hbp, 31, 20);
 773         timing_h |= FLD_VAL(timings->hfp, 19, 8);
 774         timing_h |= FLD_VAL(timings->hsw, 7, 0);
 775         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_H, timing_h);
 776
 777         timing_v |= FLD_VAL(timings->vbp, 31, 20);
 778         timing_v |= FLD_VAL(timings->vfp, 19, 8);
 779         timing_v |= FLD_VAL(timings->vsw, 7, 0);
 780         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v);
 781 }
 782
 783 void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data)
 784 {
 785         /* HDMI */
 786         struct omap_video_timings video_timing;
 787         struct hdmi_video_format video_format;
 788         struct hdmi_video_interface video_interface;
 789         /* HDMI core */
 790         struct hdmi_core_infoframe_avi avi_cfg;
 791         struct hdmi_core_video_config v_core_cfg;
 792         struct hdmi_core_packet_enable_repeat repeat_cfg;
 793         struct hdmi_config *cfg = &ip_data->cfg;
 794
 795         hdmi_wp_init(&video_timing, &video_format,
 796                 &video_interface);
 797
 798         hdmi_core_init(&v_core_cfg,
 799                 &avi_cfg,
 800                 &repeat_cfg);
 801
 802         hdmi_wp_video_init_format(&video_format, &video_timing, cfg);
 803
 804         hdmi_wp_video_config_timing(ip_data, &video_timing);
 805
 806         /* video config */
 807         video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
 808
 809         hdmi_wp_video_config_format(ip_data, &video_format);
 810
 811         video_interface.vsp = cfg->timings.vsync_pol;
 812         video_interface.hsp = cfg->timings.hsync_pol;
 813         video_interface.interlacing = cfg->interlace;
 814         video_interface.tm = 1 ; /* HDMI_TIMING_MASTER_24BIT */
 815
 816         hdmi_wp_video_config_interface(ip_data, &video_interface);
 817
 818         /*
 819          * configure core video part
 820          * set software reset in the core
 821          */
 822         hdmi_core_swreset_assert(ip_data);
 823
 824         /* power down off */
 825         hdmi_core_powerdown_disable(ip_data);
 826
 827         v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
 828         v_core_cfg.hdmi_dvi = cfg->cm.mode;
 829
 830         hdmi_core_video_config(ip_data, &v_core_cfg);
 831
 832         /* release software reset in the core */
 833         hdmi_core_swreset_release(ip_data);
 834
 835         /*
 836          * configure packet
 837          * info frame video see doc CEA861-D page 65
 838          */
 839         avi_cfg.db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB;
 840         avi_cfg.db1_active_info =
 841                 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF;
 842         avi_cfg.db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO;
 843         avi_cfg.db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0;
 844         avi_cfg.db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO;
 845         avi_cfg.db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO;
 846         avi_cfg.db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME;
 847         avi_cfg.db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO;
 848         avi_cfg.db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601;
 849         avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT;
 850         avi_cfg.db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO;
 851         avi_cfg.db4_videocode = cfg->cm.code;
 852         avi_cfg.db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO;
 853         avi_cfg.db6_7_line_eoftop = 0;
 854         avi_cfg.db8_9_line_sofbottom = 0;
 855         avi_cfg.db10_11_pixel_eofleft = 0;
 856         avi_cfg.db12_13_pixel_sofright = 0;
 857
 858         hdmi_core_aux_infoframe_avi_config(ip_data, avi_cfg);
 859
 860         /* enable/repeat the infoframe */
 861         repeat_cfg.avi_infoframe = HDMI_PACKETENABLE;
 862         repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON;
 863         /* wakeup */
 864         repeat_cfg.audio_pkt = HDMI_PACKETENABLE;
 865         repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON;
 866         hdmi_core_av_packet_config(ip_data, repeat_cfg);
 867 }
 868
 869 void ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
 870 {
 871 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r,\
 872                 hdmi_read_reg(hdmi_wp_base(ip_data), r))
 873
 874         DUMPREG(HDMI_WP_REVISION);
 875         DUMPREG(HDMI_WP_SYSCONFIG);
 876         DUMPREG(HDMI_WP_IRQSTATUS_RAW);
 877         DUMPREG(HDMI_WP_IRQSTATUS);
 878         DUMPREG(HDMI_WP_PWR_CTRL);
 879         DUMPREG(HDMI_WP_IRQENABLE_SET);
 880         DUMPREG(HDMI_WP_VIDEO_CFG);
 881         DUMPREG(HDMI_WP_VIDEO_SIZE);
 882         DUMPREG(HDMI_WP_VIDEO_TIMING_H);
 883         DUMPREG(HDMI_WP_VIDEO_TIMING_V);
 884         DUMPREG(HDMI_WP_WP_CLK);
 885         DUMPREG(HDMI_WP_AUDIO_CFG);
 886         DUMPREG(HDMI_WP_AUDIO_CFG2);
 887         DUMPREG(HDMI_WP_AUDIO_CTRL);
 888         DUMPREG(HDMI_WP_AUDIO_DATA);
 889 }
 890
 891 void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
 892 {
 893 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
 894                 hdmi_read_reg(hdmi_pll_base(ip_data), r))
 895
 896         DUMPPLL(PLLCTRL_PLL_CONTROL);
 897         DUMPPLL(PLLCTRL_PLL_STATUS);
 898         DUMPPLL(PLLCTRL_PLL_GO);
 899         DUMPPLL(PLLCTRL_CFG1);
 900         DUMPPLL(PLLCTRL_CFG2);
 901         DUMPPLL(PLLCTRL_CFG3);
 902         DUMPPLL(PLLCTRL_CFG4);
 903 }
 904
 905 void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
 906 {
 907         int i;
 908
 909 #define CORE_REG(i, name) name(i)
 910 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
 911                 hdmi_read_reg(hdmi_pll_base(ip_data), r))
 912 #define DUMPCOREAV(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \
 913                 (i < 10) ? 32 - strlen(#r) : 31 - strlen(#r), " ", \
 914                 hdmi_read_reg(hdmi_pll_base(ip_data), CORE_REG(i, r)))
 915
 916         DUMPCORE(HDMI_CORE_SYS_VND_IDL);
 917         DUMPCORE(HDMI_CORE_SYS_DEV_IDL);
 918         DUMPCORE(HDMI_CORE_SYS_DEV_IDH);
 919         DUMPCORE(HDMI_CORE_SYS_DEV_REV);
 920         DUMPCORE(HDMI_CORE_SYS_SRST);
 921         DUMPCORE(HDMI_CORE_CTRL1);
 922         DUMPCORE(HDMI_CORE_SYS_SYS_STAT);
 923         DUMPCORE(HDMI_CORE_SYS_VID_ACEN);
 924         DUMPCORE(HDMI_CORE_SYS_VID_MODE);
 925         DUMPCORE(HDMI_CORE_SYS_INTR_STATE);
 926         DUMPCORE(HDMI_CORE_SYS_INTR1);
 927         DUMPCORE(HDMI_CORE_SYS_INTR2);
 928         DUMPCORE(HDMI_CORE_SYS_INTR3);
 929         DUMPCORE(HDMI_CORE_SYS_INTR4);
 930         DUMPCORE(HDMI_CORE_SYS_UMASK1);
 931         DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL);
 932         DUMPCORE(HDMI_CORE_SYS_DE_DLY);
 933         DUMPCORE(HDMI_CORE_SYS_DE_CTRL);
 934         DUMPCORE(HDMI_CORE_SYS_DE_TOP);
 935         DUMPCORE(HDMI_CORE_SYS_DE_CNTL);
 936         DUMPCORE(HDMI_CORE_SYS_DE_CNTH);
 937         DUMPCORE(HDMI_CORE_SYS_DE_LINL);
 938         DUMPCORE(HDMI_CORE_SYS_DE_LINH_1);
 939
 940         DUMPCORE(HDMI_CORE_DDC_CMD);
 941         DUMPCORE(HDMI_CORE_DDC_STATUS);
 942         DUMPCORE(HDMI_CORE_DDC_ADDR);
 943         DUMPCORE(HDMI_CORE_DDC_OFFSET);
 944         DUMPCORE(HDMI_CORE_DDC_COUNT1);
 945         DUMPCORE(HDMI_CORE_DDC_COUNT2);
 946         DUMPCORE(HDMI_CORE_DDC_DATA);
 947         DUMPCORE(HDMI_CORE_DDC_SEGM);
 948
 949         DUMPCORE(HDMI_CORE_AV_HDMI_CTRL);
 950         DUMPCORE(HDMI_CORE_AV_DPD);
 951         DUMPCORE(HDMI_CORE_AV_PB_CTRL1);
 952         DUMPCORE(HDMI_CORE_AV_PB_CTRL2);
 953         DUMPCORE(HDMI_CORE_AV_AVI_TYPE);
 954         DUMPCORE(HDMI_CORE_AV_AVI_VERS);
 955         DUMPCORE(HDMI_CORE_AV_AVI_LEN);
 956         DUMPCORE(HDMI_CORE_AV_AVI_CHSUM);
 957
 958         for (i = 0; i < HDMI_CORE_AV_AVI_DBYTE_NELEMS; i++)
 959                 DUMPCOREAV(i, HDMI_CORE_AV_AVI_DBYTE);
 960
 961         for (i = 0; i < HDMI_CORE_AV_SPD_DBYTE_NELEMS; i++)
 962                 DUMPCOREAV(i, HDMI_CORE_AV_SPD_DBYTE);
 963
 964         for (i = 0; i < HDMI_CORE_AV_AUD_DBYTE_NELEMS; i++)
 965                 DUMPCOREAV(i, HDMI_CORE_AV_AUD_DBYTE);
 966
 967         for (i = 0; i < HDMI_CORE_AV_MPEG_DBYTE_NELEMS; i++)
 968                 DUMPCOREAV(i, HDMI_CORE_AV_MPEG_DBYTE);
 969
 970         for (i = 0; i < HDMI_CORE_AV_GEN_DBYTE_NELEMS; i++)
 971                 DUMPCOREAV(i, HDMI_CORE_AV_GEN_DBYTE);
 972
 973         for (i = 0; i < HDMI_CORE_AV_GEN2_DBYTE_NELEMS; i++)
 974                 DUMPCOREAV(i, HDMI_CORE_AV_GEN2_DBYTE);
 975
 976         DUMPCORE(HDMI_CORE_AV_ACR_CTRL);
 977         DUMPCORE(HDMI_CORE_AV_FREQ_SVAL);
 978         DUMPCORE(HDMI_CORE_AV_N_SVAL1);
 979         DUMPCORE(HDMI_CORE_AV_N_SVAL2);
 980         DUMPCORE(HDMI_CORE_AV_N_SVAL3);
 981         DUMPCORE(HDMI_CORE_AV_CTS_SVAL1);
 982         DUMPCORE(HDMI_CORE_AV_CTS_SVAL2);
 983         DUMPCORE(HDMI_CORE_AV_CTS_SVAL3);
 984         DUMPCORE(HDMI_CORE_AV_CTS_HVAL1);
 985         DUMPCORE(HDMI_CORE_AV_CTS_HVAL2);
 986         DUMPCORE(HDMI_CORE_AV_CTS_HVAL3);
 987         DUMPCORE(HDMI_CORE_AV_AUD_MODE);
 988         DUMPCORE(HDMI_CORE_AV_SPDIF_CTRL);
 989         DUMPCORE(HDMI_CORE_AV_HW_SPDIF_FS);
 990         DUMPCORE(HDMI_CORE_AV_SWAP_I2S);
 991         DUMPCORE(HDMI_CORE_AV_SPDIF_ERTH);
 992         DUMPCORE(HDMI_CORE_AV_I2S_IN_MAP);
 993         DUMPCORE(HDMI_CORE_AV_I2S_IN_CTRL);
 994         DUMPCORE(HDMI_CORE_AV_I2S_CHST0);
 995         DUMPCORE(HDMI_CORE_AV_I2S_CHST1);
 996         DUMPCORE(HDMI_CORE_AV_I2S_CHST2);
 997         DUMPCORE(HDMI_CORE_AV_I2S_CHST4);
 998         DUMPCORE(HDMI_CORE_AV_I2S_CHST5);
 999         DUMPCORE(HDMI_CORE_AV_ASRC);
1000         DUMPCORE(HDMI_CORE_AV_I2S_IN_LEN);
1001         DUMPCORE(HDMI_CORE_AV_HDMI_CTRL);
1002         DUMPCORE(HDMI_CORE_AV_AUDO_TXSTAT);
1003         DUMPCORE(HDMI_CORE_AV_AUD_PAR_BUSCLK_1);
1004         DUMPCORE(HDMI_CORE_AV_AUD_PAR_BUSCLK_2);
1005         DUMPCORE(HDMI_CORE_AV_AUD_PAR_BUSCLK_3);
1006         DUMPCORE(HDMI_CORE_AV_TEST_TXCTRL);
1007         DUMPCORE(HDMI_CORE_AV_DPD);
1008         DUMPCORE(HDMI_CORE_AV_PB_CTRL1);
1009         DUMPCORE(HDMI_CORE_AV_PB_CTRL2);
1010         DUMPCORE(HDMI_CORE_AV_AVI_TYPE);
1011         DUMPCORE(HDMI_CORE_AV_AVI_VERS);
1012         DUMPCORE(HDMI_CORE_AV_AVI_LEN);
1013         DUMPCORE(HDMI_CORE_AV_AVI_CHSUM);
1014         DUMPCORE(HDMI_CORE_AV_SPD_TYPE);
1015         DUMPCORE(HDMI_CORE_AV_SPD_VERS);
1016         DUMPCORE(HDMI_CORE_AV_SPD_LEN);
1017         DUMPCORE(HDMI_CORE_AV_SPD_CHSUM);
1018         DUMPCORE(HDMI_CORE_AV_AUDIO_TYPE);
1019         DUMPCORE(HDMI_CORE_AV_AUDIO_VERS);
1020         DUMPCORE(HDMI_CORE_AV_AUDIO_LEN);
1021         DUMPCORE(HDMI_CORE_AV_AUDIO_CHSUM);
1022         DUMPCORE(HDMI_CORE_AV_MPEG_TYPE);
1023         DUMPCORE(HDMI_CORE_AV_MPEG_VERS);
1024         DUMPCORE(HDMI_CORE_AV_MPEG_LEN);
1025         DUMPCORE(HDMI_CORE_AV_MPEG_CHSUM);
1026         DUMPCORE(HDMI_CORE_AV_CP_BYTE1);
1027         DUMPCORE(HDMI_CORE_AV_CEC_ADDR_ID);
1028 }
1029
1030 void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
1031 {
1032 #define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\
1033                 hdmi_read_reg(hdmi_phy_base(ip_data), r))
1034
1035         DUMPPHY(HDMI_TXPHY_TX_CTRL);
1036         DUMPPHY(HDMI_TXPHY_DIGITAL_CTRL);
1037         DUMPPHY(HDMI_TXPHY_POWER_CTRL);
1038         DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL);
1039 }
1040
1041 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
1042         defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
1043 void hdmi_wp_audio_config_format(struct hdmi_ip_data *ip_data,
1044                                         struct hdmi_audio_format *aud_fmt)
1045 {
1046         u32 r;
1047
1048         DSSDBG("Enter hdmi_wp_audio_config_format\n");
1049
1050         r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG);
1051         r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);
1052         r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);
1053         r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);
1054         r = FLD_MOD(r, aud_fmt->type, 4, 4);
1055         r = FLD_MOD(r, aud_fmt->justification, 3, 3);
1056         r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);
1057         r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);
1058         r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);
1059         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG, r);
1060 }
1061
1062 void hdmi_wp_audio_config_dma(struct hdmi_ip_data *ip_data,
1063                                         struct hdmi_audio_dma *aud_dma)
1064 {
1065         u32 r;
1066
1067         DSSDBG("Enter hdmi_wp_audio_config_dma\n");
1068
1069         r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2);
1070         r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);
1071         r = FLD_MOD(r, aud_dma->block_size, 7, 0);
1072         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2, r);
1073
1074         r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL);
1075         r = FLD_MOD(r, aud_dma->mode, 9, 9);
1076         r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);
1077         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL, r);
1078 }
1079
1080 void hdmi_core_audio_config(struct hdmi_ip_data *ip_data,
1081                                         struct hdmi_core_audio_config *cfg)
1082 {
1083         u32 r;
1084         void __iomem *av_base = hdmi_av_base(ip_data);
1085
1086         /* audio clock recovery parameters */
1087         r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL);
1088         r = FLD_MOD(r, cfg->use_mclk, 2, 2);
1089         r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1);
1090         r = FLD_MOD(r, cfg->cts_mode, 0, 0);
1091         hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r);
1092
1093         REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0);
1094         REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0);
1095         REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0);
1096
1097         if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) {
1098                 REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0);
1099                 REG_FLD_MOD(av_base,
1100                                 HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0);
1101                 REG_FLD_MOD(av_base,
1102                                 HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0);
1103         } else {
1104                 /*
1105                  * HDMI IP uses this configuration to divide the MCLK to
1106                  * update CTS value.
1107                  */
1108                 REG_FLD_MOD(av_base,
1109                                 HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
1110
1111                 /* Configure clock for audio packets */
1112                 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1,
1113                                 cfg->aud_par_busclk, 7, 0);
1114                 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2,
1115                                 (cfg->aud_par_busclk >> 8), 7, 0);
1116                 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3,
1117                                 (cfg->aud_par_busclk >> 16), 7, 0);
1118         }
1119
1120         /* Override of SPDIF sample frequency with value in I2S_CHST4 */
1121         REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL,
1122                                                 cfg->fs_override, 1, 1);
1123
1124         /* I2S parameters */
1125         REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_CHST4,
1126                                                 cfg->freq_sample, 3, 0);
1127
1128         r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL);
1129         r = FLD_MOD(r, cfg->i2s_cfg.en_high_bitrate_aud, 7, 7);
1130         r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6);
1131         r = FLD_MOD(r, cfg->i2s_cfg.cbit_order, 5, 5);
1132         r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4);
1133         r = FLD_MOD(r, cfg->i2s_cfg.ws_polarity, 3, 3);
1134         r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2);
1135         r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1);
1136         r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0);
1137         hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r);
1138
1139         r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_CHST5);
1140         r = FLD_MOD(r, cfg->freq_sample, 7, 4);
1141         r = FLD_MOD(r, cfg->i2s_cfg.word_length, 3, 1);
1142         r = FLD_MOD(r, cfg->i2s_cfg.word_max_length, 0, 0);
1143         hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5, r);
1144
1145         REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN,
1146                         cfg->i2s_cfg.in_length_bits, 3, 0);
1147
1148         /* Audio channels and mode parameters */
1149         REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1);
1150         r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE);
1151         r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4);
1152         r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3);
1153         r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2);
1154         r = FLD_MOD(r, cfg->en_spdif, 1, 1);
1155         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r);
1156 }
1157
1158 void hdmi_core_audio_infoframe_config(struct hdmi_ip_data *ip_data,
1159                 struct hdmi_core_infoframe_audio *info_aud)
1160 {
1161         u8 val;
1162         u8 sum = 0, checksum = 0;
1163         void __iomem *av_base = hdmi_av_base(ip_data);
1164
1165         /*
1166          * Set audio info frame type, version and length as
1167          * described in HDMI 1.4a Section 8.2.2 specification.
1168          * Checksum calculation is defined in Section 5.3.5.
1169          */
1170         hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84);
1171         hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01);
1172         hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a);
1173         sum += 0x84 + 0x001 + 0x00a;
1174
1175         val = (info_aud->db1_coding_type << 4)
1176                         | (info_aud->db1_channel_count - 1);
1177         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0), val);
1178         sum += val;
1179
1180         val = (info_aud->db2_sample_freq << 2) | info_aud->db2_sample_size;
1181         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1), val);
1182         sum += val;
1183
1184         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), 0x00);
1185
1186         val = info_aud->db4_channel_alloc;
1187         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), val);
1188         sum += val;
1189
1190         val = (info_aud->db5_downmix_inh << 7) | (info_aud->db5_lsv << 3);
1191         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4), val);
1192         sum += val;
1193
1194         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00);
1195         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00);
1196         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00);
1197         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00);
1198         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00);
1199
1200         checksum = 0x100 - sum;
1201         hdmi_write_reg(av_base,
1202                                         HDMI_CORE_AV_AUDIO_CHSUM, checksum);
1203
1204         /*
1205          * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing
1206          * is available.
1207          */
1208 }
1209
1210 int hdmi_config_audio_acr(struct hdmi_ip_data *ip_data,
1211                                 u32 sample_freq, u32 *n, u32 *cts)
1212 {
1213         u32 r;
1214         u32 deep_color = 0;
1215         u32 pclk = ip_data->cfg.timings.timings.pixel_clock;
1216
1217         if (n == NULL || cts == NULL)
1218                 return -EINVAL;
1219         /*
1220          * Obtain current deep color configuration. This needed
1221          * to calculate the TMDS clock based on the pixel clock.
1222          */
1223         r = REG_GET(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, 1, 0);
1224         switch (r) {
1225         case 1: /* No deep color selected */
1226                 deep_color = 100;
1227                 break;
1228         case 2: /* 10-bit deep color selected */
1229                 deep_color = 125;
1230                 break;
1231         case 3: /* 12-bit deep color selected */
1232                 deep_color = 150;
1233                 break;
1234         default:
1235                 return -EINVAL;
1236         }
1237
1238         switch (sample_freq) {
1239         case 32000:
1240                 if ((deep_color == 125) && ((pclk == 54054)
1241                                 || (pclk == 74250)))
1242                         *n = 8192;
1243                 else
1244                         *n = 4096;
1245                 break;
1246         case 44100:
1247                 *n = 6272;
1248                 break;
1249         case 48000:
1250                 if ((deep_color == 125) && ((pclk == 54054)
1251                                 || (pclk == 74250)))
1252                         *n = 8192;
1253                 else
1254                         *n = 6144;
1255                 break;
1256         default:
1257                 *n = 0;
1258                 return -EINVAL;
1259         }
1260
1261         /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
1262         *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);
1263
1264         return 0;
1265 }
1266
1267 void ti_hdmi_4xxx_wp_audio_enable(struct hdmi_ip_data *ip_data, bool enable)
1268 {
1269         REG_FLD_MOD(hdmi_av_base(ip_data),
1270                                 HDMI_CORE_AV_AUD_MODE, enable, 0, 0);
1271         REG_FLD_MOD(hdmi_wp_base(ip_data),
1272                                 HDMI_WP_AUDIO_CTRL, enable, 31, 31);
1273         REG_FLD_MOD(hdmi_wp_base(ip_data),
1274                                 HDMI_WP_AUDIO_CTRL, enable, 30, 30);
1275 }
1276 #endif