drivers/video/omap2/dss/hdmi_pll.c

   1 /*
   2  * HDMI PLL
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/err.h>
  14 #include <linux/io.h>
  15 #include <linux/platform_device.h>
  16 #include <video/omapdss.h>
  17
  18 #include "dss.h"
  19 #include "hdmi.h"
  20
  21 #define HDMI_DEFAULT_REGN 16
  22 #define HDMI_DEFAULT_REGM2 1
  23
  24 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s)
  25 {
  26 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
  27                 hdmi_read_reg(pll->base, r))
  28
  29         DUMPPLL(PLLCTRL_PLL_CONTROL);
  30         DUMPPLL(PLLCTRL_PLL_STATUS);
  31         DUMPPLL(PLLCTRL_PLL_GO);
  32         DUMPPLL(PLLCTRL_CFG1);
  33         DUMPPLL(PLLCTRL_CFG2);
  34         DUMPPLL(PLLCTRL_CFG3);
  35         DUMPPLL(PLLCTRL_SSC_CFG1);
  36         DUMPPLL(PLLCTRL_SSC_CFG2);
  37         DUMPPLL(PLLCTRL_CFG4);
  38 }
  39
  40 void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy)
  41 {
  42         struct hdmi_pll_info *pi = &pll->info;
  43         unsigned long refclk;
  44         u32 mf;
  45
  46         /* use our funky units */
  47         clkin /= 10000;
  48
  49         /*
  50          * Input clock is predivided by N + 1
  51          * out put of which is reference clk
  52          */
  53
  54         pi->regn = HDMI_DEFAULT_REGN;
  55
  56         refclk = clkin / pi->regn;
  57
  58         pi->regm2 = HDMI_DEFAULT_REGM2;
  59
  60         /*
  61          * multiplier is pixel_clk/ref_clk
  62          * Multiplying by 100 to avoid fractional part removal
  63          */
  64         pi->regm = phy * pi->regm2 / refclk;
  65
  66         /*
  67          * fractional multiplier is remainder of the difference between
  68          * multiplier and actual phy(required pixel clock thus should be
  69          * multiplied by 2^18(262144) divided by the reference clock
  70          */
  71         mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
  72         pi->regmf = pi->regm2 * mf / refclk;
  73
  74         /*
  75          * Dcofreq should be set to 1 if required pixel clock
  76          * is greater than 1000MHz
  77          */
  78         pi->dcofreq = phy > 1000 * 100;
  79         pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
  80
  81         /* Set the reference clock to sysclk reference */
  82         pi->refsel = HDMI_REFSEL_SYSCLK;
  83
  84         DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
  85         DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
  86 }
  87
  88
  89 static int hdmi_pll_config(struct hdmi_pll_data *pll)
  90 {
  91         u32 r;
  92         struct hdmi_pll_info *fmt = &pll->info;
  93
  94         /* PLL start always use manual mode */
  95         REG_FLD_MOD(pll->base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
  96
  97         r = hdmi_read_reg(pll->base, PLLCTRL_CFG1);
  98         r = FLD_MOD(r, fmt->regm, 20, 9);       /* CFG1_PLL_REGM */
  99         r = FLD_MOD(r, fmt->regn - 1, 8, 1);    /* CFG1_PLL_REGN */
 100         hdmi_write_reg(pll->base, PLLCTRL_CFG1, r);
 101
 102         r = hdmi_read_reg(pll->base, PLLCTRL_CFG2);
 103
 104         r = FLD_MOD(r, 0x0, 12, 12);    /* PLL_HIGHFREQ divide by 2 */
 105         r = FLD_MOD(r, 0x1, 13, 13);    /* PLL_REFEN */
 106         r = FLD_MOD(r, 0x0, 14, 14);    /* PHY_CLKINEN de-assert during locking */
 107         r = FLD_MOD(r, fmt->refsel, 22, 21);    /* REFSEL */
 108
 109         if (fmt->dcofreq) {
 110                 /* divider programming for frequency beyond 1000Mhz */
 111                 REG_FLD_MOD(pll->base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
 112                 r = FLD_MOD(r, 0x4, 3, 1);      /* 1000MHz and 2000MHz */
 113         } else {
 114                 r = FLD_MOD(r, 0x2, 3, 1);      /* 500MHz and 1000MHz */
 115         }
 116
 117         hdmi_write_reg(pll->base, PLLCTRL_CFG2, r);
 118
 119         r = hdmi_read_reg(pll->base, PLLCTRL_CFG4);
 120         r = FLD_MOD(r, fmt->regm2, 24, 18);
 121         r = FLD_MOD(r, fmt->regmf, 17, 0);
 122         hdmi_write_reg(pll->base, PLLCTRL_CFG4, r);
 123
 124         /* go now */
 125         REG_FLD_MOD(pll->base, PLLCTRL_PLL_GO, 0x1, 0, 0);
 126
 127         /* wait for bit change */
 128         if (hdmi_wait_for_bit_change(pll->base, PLLCTRL_PLL_GO,
 129                         0, 0, 1) != 1) {
 130                 pr_err("PLL GO bit not set\n");
 131                 return -ETIMEDOUT;
 132         }
 133
 134         /* Wait till the lock bit is set in PLL status */
 135         if (hdmi_wait_for_bit_change(pll->base,
 136                         PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) {
 137                 pr_err("cannot lock PLL\n");
 138                 pr_err("CFG1 0x%x\n",
 139                         hdmi_read_reg(pll->base, PLLCTRL_CFG1));
 140                 pr_err("CFG2 0x%x\n",
 141                         hdmi_read_reg(pll->base, PLLCTRL_CFG2));
 142                 pr_err("CFG4 0x%x\n",
 143                         hdmi_read_reg(pll->base, PLLCTRL_CFG4));
 144                 return -ETIMEDOUT;
 145         }
 146
 147         pr_debug("PLL locked!\n");
 148
 149         return 0;
 150 }
 151
 152 static int hdmi_pll_reset(struct hdmi_pll_data *pll)
 153 {
 154         /* SYSRESET  controlled by power FSM */
 155         REG_FLD_MOD(pll->base, PLLCTRL_PLL_CONTROL, 0x0, 3, 3);
 156
 157         /* READ 0x0 reset is in progress */
 158         if (hdmi_wait_for_bit_change(pll->base, PLLCTRL_PLL_STATUS, 0, 0, 1)
 159                         != 1) {
 160                 pr_err("Failed to sysreset PLL\n");
 161                 return -ETIMEDOUT;
 162         }
 163
 164         return 0;
 165 }
 166
 167 int hdmi_pll_enable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp)
 168 {
 169         u16 r = 0;
 170
 171         r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);
 172         if (r)
 173                 return r;
 174
 175         r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
 176         if (r)
 177                 return r;
 178
 179         r = hdmi_pll_reset(pll);
 180         if (r)
 181                 return r;
 182
 183         r = hdmi_pll_config(pll);
 184         if (r)
 185                 return r;
 186
 187         return 0;
 188 }
 189
 190 void hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp)
 191 {
 192         hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);
 193 }
 194
 195 #define PLL_OFFSET      0x200
 196 #define PLL_SIZE        0x100
 197
 198 int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll)
 199 {
 200         struct resource *res;
 201         struct resource temp_res;
 202
 203         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi_pllctrl");
 204         if (!res) {
 205                 DSSDBG("can't get PLL mem resource by name\n");
 206                 /*
 207                  * if hwmod/DT doesn't have the memory resource information
 208                  * split into HDMI sub blocks by name, we try again by getting
 209                  * the platform's first resource. this code will be removed when
 210                  * the driver can get the mem resources by name
 211                  */
 212                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 213                 if (!res) {
 214                         DSSERR("can't get PLL mem resource\n");
 215                         return -EINVAL;
 216                 }
 217
 218                 temp_res.start = res->start + PLL_OFFSET;
 219                 temp_res.end = temp_res.start + PLL_SIZE - 1;
 220                 res = &temp_res;
 221         }
 222
 223         pll->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
 224         if (!pll->base) {
 225                 DSSERR("can't ioremap PLLCTRL\n");
 226                 return -ENOMEM;
 227         }
 228
 229         return 0;
 230 }