4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
7 * Mythri pk <mythripk@ti.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
22 #define DSS_SUBSYS_NAME "HDMI"
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/err.h>
28 #include <linux/interrupt.h>
29 #include <linux/mutex.h>
30 #include <linux/delay.h>
31 #include <linux/string.h>
32 #include <linux/platform_device.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/clk.h>
35 #include <linux/gpio.h>
36 #include <linux/regulator/consumer.h>
37 #include <video/omapdss.h>
41 #include "dss_features.h"
44 #define HDMI_CORE_SYS 0x400
45 #define HDMI_CORE_AV 0x900
46 #define HDMI_PLLCTRL 0x200
47 #define HDMI_PHY 0x300
49 /* HDMI EDID Length move this */
50 #define HDMI_EDID_MAX_LENGTH 256
51 #define EDID_TIMING_DESCRIPTOR_SIZE 0x12
52 #define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36
53 #define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80
54 #define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
55 #define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
57 #define HDMI_DEFAULT_REGN 16
58 #define HDMI_DEFAULT_REGM2 1
62 struct platform_device *pdev;
63 struct hdmi_ip_data ip_data;
66 struct regulator *vdda_hdmi_dac_reg;
72 struct omap_dss_output output;
76 * Logic for the below structure :
77 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
78 * There is a correspondence between CEA/VESA timing and code, please
79 * refer to section 6.3 in HDMI 1.3 specification for timing code.
81 * In the below structure, cea_vesa_timings corresponds to all OMAP4
82 * supported CEA and VESA timing values.code_cea corresponds to the CEA
83 * code, It is used to get the timing from cea_vesa_timing array.Similarly
84 * with code_vesa. Code_index is used for back mapping, that is once EDID
85 * is read from the TV, EDID is parsed to find the timing values and then
86 * map it to corresponding CEA or VESA index.
89 static const struct hdmi_config cea_timings[] = {
91 { 640, 480, 25200, 96, 16, 48, 2, 10, 33,
92 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
97 { 720, 480, 27027, 62, 16, 60, 6, 9, 30,
98 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
103 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
104 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
109 { 1920, 540, 74250, 44, 88, 148, 5, 2, 15,
110 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
115 { 1440, 240, 27027, 124, 38, 114, 3, 4, 15,
116 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
121 { 1920, 1080, 148500, 44, 88, 148, 5, 4, 36,
122 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
127 { 720, 576, 27000, 64, 12, 68, 5, 5, 39,
128 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
133 { 1280, 720, 74250, 40, 440, 220, 5, 5, 20,
134 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
139 { 1920, 540, 74250, 44, 528, 148, 5, 2, 15,
140 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
145 { 1440, 288, 27000, 126, 24, 138, 3, 2, 19,
146 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
151 { 1440, 576, 54000, 128, 24, 136, 5, 5, 39,
152 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
157 { 1920, 1080, 148500, 44, 528, 148, 5, 4, 36,
158 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
163 { 1920, 1080, 74250, 44, 638, 148, 5, 4, 36,
164 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
169 { 2880, 480, 108108, 248, 64, 240, 6, 9, 30,
170 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
175 { 2880, 576, 108000, 256, 48, 272, 5, 5, 39,
176 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
182 static const struct hdmi_config vesa_timings[] = {
185 { 640, 480, 25175, 96, 16, 48, 2, 11, 31,
186 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
191 { 800, 600, 40000, 128, 40, 88, 4, 1, 23,
192 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
197 { 848, 480, 33750, 112, 16, 112, 8, 6, 23,
198 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
203 { 1280, 768, 79500, 128, 64, 192, 7, 3, 20,
204 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
209 { 1280, 800, 83500, 128, 72, 200, 6, 3, 22,
210 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
215 { 1360, 768, 85500, 112, 64, 256, 6, 3, 18,
216 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
221 { 1280, 960, 108000, 112, 96, 312, 3, 1, 36,
222 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
227 { 1280, 1024, 108000, 112, 48, 248, 3, 1, 38,
228 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
233 { 1024, 768, 65000, 136, 24, 160, 6, 3, 29,
234 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_LOW,
239 { 1400, 1050, 121750, 144, 88, 232, 4, 3, 32,
240 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
245 { 1440, 900, 106500, 152, 80, 232, 6, 3, 25,
246 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
251 { 1680, 1050, 146250, 176 , 104, 280, 6, 3, 30,
252 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_LOW,
257 { 1366, 768, 85500, 143, 70, 213, 3, 3, 24,
258 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
263 { 1920, 1080, 148500, 44, 148, 80, 5, 4, 36,
264 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
269 { 1280, 768, 68250, 32, 48, 80, 7, 3, 12,
270 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
275 { 1400, 1050, 101000, 32, 48, 80, 4, 3, 23,
276 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
281 { 1680, 1050, 119000, 32, 48, 80, 6, 3, 21,
282 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
287 { 1280, 800, 79500, 32, 48, 80, 6, 3, 14,
288 OMAPDSS_SIG_ACTIVE_LOW, OMAPDSS_SIG_ACTIVE_HIGH,
293 { 1280, 720, 74250, 40, 110, 220, 5, 5, 20,
294 OMAPDSS_SIG_ACTIVE_HIGH, OMAPDSS_SIG_ACTIVE_HIGH,
300 static int hdmi_runtime_get(void)
304 DSSDBG("hdmi_runtime_get\n");
306 r = pm_runtime_get_sync(&hdmi.pdev->dev);
314 static void hdmi_runtime_put(void)
318 DSSDBG("hdmi_runtime_put\n");
320 r = pm_runtime_put_sync(&hdmi.pdev->dev);
321 WARN_ON(r < 0 && r != -ENOSYS);
324 static int __init hdmi_init_display(struct omap_dss_device *dssdev)
328 struct gpio gpios[] = {
329 { hdmi.ct_cp_hpd_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ct_cp_hpd" },
330 { hdmi.ls_oe_gpio, GPIOF_OUT_INIT_LOW, "hdmi_ls_oe" },
331 { hdmi.hpd_gpio, GPIOF_DIR_IN, "hdmi_hpd" },
334 DSSDBG("init_display\n");
336 dss_init_hdmi_ip_ops(&hdmi.ip_data);
338 if (hdmi.vdda_hdmi_dac_reg == NULL) {
339 struct regulator *reg;
341 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda_hdmi_dac");
344 DSSERR("can't get VDDA_HDMI_DAC regulator\n");
348 hdmi.vdda_hdmi_dac_reg = reg;
351 r = gpio_request_array(gpios, ARRAY_SIZE(gpios));
358 static void __exit hdmi_uninit_display(struct omap_dss_device *dssdev)
360 DSSDBG("uninit_display\n");
362 gpio_free(hdmi.ct_cp_hpd_gpio);
363 gpio_free(hdmi.ls_oe_gpio);
364 gpio_free(hdmi.hpd_gpio);
367 static const struct hdmi_config *hdmi_find_timing(
368 const struct hdmi_config *timings_arr,
373 for (i = 0; i < len; i++) {
374 if (timings_arr[i].cm.code == hdmi.ip_data.cfg.cm.code)
375 return &timings_arr[i];
380 static const struct hdmi_config *hdmi_get_timings(void)
382 const struct hdmi_config *arr;
385 if (hdmi.ip_data.cfg.cm.mode == HDMI_DVI) {
387 len = ARRAY_SIZE(vesa_timings);
390 len = ARRAY_SIZE(cea_timings);
393 return hdmi_find_timing(arr, len);
396 static bool hdmi_timings_compare(struct omap_video_timings *timing1,
397 const struct omap_video_timings *timing2)
399 int timing1_vsync, timing1_hsync, timing2_vsync, timing2_hsync;
401 if ((timing2->pixel_clock == timing1->pixel_clock) &&
402 (timing2->x_res == timing1->x_res) &&
403 (timing2->y_res == timing1->y_res)) {
405 timing2_hsync = timing2->hfp + timing2->hsw + timing2->hbp;
406 timing1_hsync = timing1->hfp + timing1->hsw + timing1->hbp;
407 timing2_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
408 timing1_vsync = timing2->vfp + timing2->vsw + timing2->vbp;
410 DSSDBG("timing1_hsync = %d timing1_vsync = %d"\
411 "timing2_hsync = %d timing2_vsync = %d\n",
412 timing1_hsync, timing1_vsync,
413 timing2_hsync, timing2_vsync);
415 if ((timing1_hsync == timing2_hsync) &&
416 (timing1_vsync == timing2_vsync)) {
423 static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
426 struct hdmi_cm cm = {-1};
427 DSSDBG("hdmi_get_code\n");
429 for (i = 0; i < ARRAY_SIZE(cea_timings); i++) {
430 if (hdmi_timings_compare(timing, &cea_timings[i].timings)) {
431 cm = cea_timings[i].cm;
435 for (i = 0; i < ARRAY_SIZE(vesa_timings); i++) {
436 if (hdmi_timings_compare(timing, &vesa_timings[i].timings)) {
437 cm = vesa_timings[i].cm;
446 unsigned long hdmi_get_pixel_clock(void)
448 /* HDMI Pixel Clock in Mhz */
449 return hdmi.ip_data.cfg.timings.pixel_clock * 1000;
452 static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
453 struct hdmi_pll_info *pi)
455 unsigned long clkin, refclk;
458 clkin = clk_get_rate(hdmi.sys_clk) / 10000;
460 * Input clock is predivided by N + 1
461 * out put of which is reference clk
463 if (dssdev->clocks.hdmi.regn == 0)
464 pi->regn = HDMI_DEFAULT_REGN;
466 pi->regn = dssdev->clocks.hdmi.regn;
468 refclk = clkin / pi->regn;
470 if (dssdev->clocks.hdmi.regm2 == 0)
471 pi->regm2 = HDMI_DEFAULT_REGM2;
473 pi->regm2 = dssdev->clocks.hdmi.regm2;
476 * multiplier is pixel_clk/ref_clk
477 * Multiplying by 100 to avoid fractional part removal
479 pi->regm = phy * pi->regm2 / refclk;
482 * fractional multiplier is remainder of the difference between
483 * multiplier and actual phy(required pixel clock thus should be
484 * multiplied by 2^18(262144) divided by the reference clock
486 mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
487 pi->regmf = pi->regm2 * mf / refclk;
490 * Dcofreq should be set to 1 if required pixel clock
491 * is greater than 1000MHz
493 pi->dcofreq = phy > 1000 * 100;
494 pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
496 /* Set the reference clock to sysclk reference */
497 pi->refsel = HDMI_REFSEL_SYSCLK;
499 DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
500 DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
503 static int hdmi_power_on(struct omap_dss_device *dssdev)
506 struct omap_video_timings *p;
507 struct omap_overlay_manager *mgr = dssdev->output->manager;
510 gpio_set_value(hdmi.ct_cp_hpd_gpio, 1);
511 gpio_set_value(hdmi.ls_oe_gpio, 1);
513 /* wait 300us after CT_CP_HPD for the 5V power output to reach 90% */
516 r = regulator_enable(hdmi.vdda_hdmi_dac_reg);
518 goto err_vdac_enable;
520 r = hdmi_runtime_get();
522 goto err_runtime_get;
524 dss_mgr_disable(mgr);
526 p = &hdmi.ip_data.cfg.timings;
528 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
530 phy = p->pixel_clock;
532 hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
534 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
536 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
537 r = hdmi.ip_data.ops->pll_enable(&hdmi.ip_data);
539 DSSDBG("Failed to lock PLL\n");
543 r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);
545 DSSDBG("Failed to start PHY\n");
549 hdmi.ip_data.ops->video_configure(&hdmi.ip_data);
551 /* Make selection of HDMI in DSS */
552 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
554 /* Select the dispc clock source as PRCM clock, to ensure that it is not
555 * DSI PLL source as the clock selected by DSI PLL might not be
556 * sufficient for the resolution selected / that can be changed
557 * dynamically by user. This can be moved to single location , say
560 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
562 /* bypass TV gamma table */
563 dispc_enable_gamma_table(0);
566 dss_mgr_set_timings(mgr, p);
568 r = hdmi.ip_data.ops->video_enable(&hdmi.ip_data);
572 r = dss_mgr_enable(mgr);
579 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
581 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
583 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
587 regulator_disable(hdmi.vdda_hdmi_dac_reg);
589 gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
590 gpio_set_value(hdmi.ls_oe_gpio, 0);
594 static void hdmi_power_off(struct omap_dss_device *dssdev)
596 struct omap_overlay_manager *mgr = dssdev->output->manager;
598 dss_mgr_disable(mgr);
600 hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
601 hdmi.ip_data.ops->phy_disable(&hdmi.ip_data);
602 hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
605 regulator_disable(hdmi.vdda_hdmi_dac_reg);
607 gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
608 gpio_set_value(hdmi.ls_oe_gpio, 0);
611 int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
612 struct omap_video_timings *timings)
616 cm = hdmi_get_code(timings);
625 void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev,
626 struct omap_video_timings *timings)
629 const struct hdmi_config *t;
631 mutex_lock(&hdmi.lock);
633 cm = hdmi_get_code(timings);
634 hdmi.ip_data.cfg.cm = cm;
636 t = hdmi_get_timings();
638 hdmi.ip_data.cfg = *t;
640 mutex_unlock(&hdmi.lock);
643 static void hdmi_dump_regs(struct seq_file *s)
645 mutex_lock(&hdmi.lock);
647 if (hdmi_runtime_get())
650 hdmi.ip_data.ops->dump_wrapper(&hdmi.ip_data, s);
651 hdmi.ip_data.ops->dump_pll(&hdmi.ip_data, s);
652 hdmi.ip_data.ops->dump_phy(&hdmi.ip_data, s);
653 hdmi.ip_data.ops->dump_core(&hdmi.ip_data, s);
656 mutex_unlock(&hdmi.lock);
659 int omapdss_hdmi_read_edid(u8 *buf, int len)
663 mutex_lock(&hdmi.lock);
665 r = hdmi_runtime_get();
668 r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len);
671 mutex_unlock(&hdmi.lock);
676 bool omapdss_hdmi_detect(void)
680 mutex_lock(&hdmi.lock);
682 r = hdmi_runtime_get();
685 r = hdmi.ip_data.ops->detect(&hdmi.ip_data);
688 mutex_unlock(&hdmi.lock);
693 int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
695 struct omap_dss_output *out = dssdev->output;
698 DSSDBG("ENTER hdmi_display_enable\n");
700 mutex_lock(&hdmi.lock);
702 if (out == NULL || out->manager == NULL) {
703 DSSERR("failed to enable display: no output/manager\n");
708 hdmi.ip_data.hpd_gpio = hdmi.hpd_gpio;
710 r = omap_dss_start_device(dssdev);
712 DSSERR("failed to start device\n");
716 r = hdmi_power_on(dssdev);
718 DSSERR("failed to power on device\n");
722 mutex_unlock(&hdmi.lock);
726 omap_dss_stop_device(dssdev);
728 mutex_unlock(&hdmi.lock);
732 void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
734 DSSDBG("Enter hdmi_display_disable\n");
736 mutex_lock(&hdmi.lock);
738 hdmi_power_off(dssdev);
740 omap_dss_stop_device(dssdev);
742 mutex_unlock(&hdmi.lock);
745 static int hdmi_get_clocks(struct platform_device *pdev)
749 clk = clk_get(&pdev->dev, "sys_clk");
751 DSSERR("can't get sys_clk\n");
760 static void hdmi_put_clocks(void)
763 clk_put(hdmi.sys_clk);
766 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
767 int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts)
770 bool deep_color_correct = false;
771 u32 pclk = hdmi.ip_data.cfg.timings.pixel_clock;
773 if (n == NULL || cts == NULL)
776 /* TODO: When implemented, query deep color mode here. */
780 * When using deep color, the default N value (as in the HDMI
781 * specification) yields to an non-integer CTS. Hence, we
782 * modify it while keeping the restrictions described in
783 * section 7.2.1 of the HDMI 1.4a specification.
785 switch (sample_freq) {
790 if (deep_color == 125)
791 if (pclk == 27027 || pclk == 74250)
792 deep_color_correct = true;
793 if (deep_color == 150)
795 deep_color_correct = true;
800 if (deep_color == 125)
802 deep_color_correct = true;
808 if (deep_color_correct) {
809 switch (sample_freq) {
835 switch (sample_freq) {
861 /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
862 *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);
867 int hdmi_audio_enable(void)
869 DSSDBG("audio_enable\n");
871 return hdmi.ip_data.ops->audio_enable(&hdmi.ip_data);
874 void hdmi_audio_disable(void)
876 DSSDBG("audio_disable\n");
878 hdmi.ip_data.ops->audio_disable(&hdmi.ip_data);
881 int hdmi_audio_start(void)
883 DSSDBG("audio_start\n");
885 return hdmi.ip_data.ops->audio_start(&hdmi.ip_data);
888 void hdmi_audio_stop(void)
890 DSSDBG("audio_stop\n");
892 hdmi.ip_data.ops->audio_stop(&hdmi.ip_data);
895 bool hdmi_mode_has_audio(void)
897 if (hdmi.ip_data.cfg.cm.mode == HDMI_HDMI)
903 int hdmi_audio_config(struct omap_dss_audio *audio)
905 return hdmi.ip_data.ops->audio_config(&hdmi.ip_data, audio);
910 static struct omap_dss_device * __init hdmi_find_dssdev(struct platform_device *pdev)
912 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
913 const char *def_disp_name = dss_get_default_display_name();
914 struct omap_dss_device *def_dssdev;
919 for (i = 0; i < pdata->num_devices; ++i) {
920 struct omap_dss_device *dssdev = pdata->devices[i];
922 if (dssdev->type != OMAP_DISPLAY_TYPE_HDMI)
925 if (def_dssdev == NULL)
928 if (def_disp_name != NULL &&
929 strcmp(dssdev->name, def_disp_name) == 0) {
938 static void __init hdmi_probe_pdata(struct platform_device *pdev)
940 struct omap_dss_device *plat_dssdev;
941 struct omap_dss_device *dssdev;
942 struct omap_dss_hdmi_data *priv;
945 plat_dssdev = hdmi_find_dssdev(pdev);
950 dssdev = dss_alloc_and_init_device(&pdev->dev);
954 dss_copy_device_pdata(dssdev, plat_dssdev);
958 hdmi.ct_cp_hpd_gpio = priv->ct_cp_hpd_gpio;
959 hdmi.ls_oe_gpio = priv->ls_oe_gpio;
960 hdmi.hpd_gpio = priv->hpd_gpio;
962 dssdev->channel = OMAP_DSS_CHANNEL_DIGIT;
964 r = hdmi_init_display(dssdev);
966 DSSERR("device %s init failed: %d\n", dssdev->name, r);
967 dss_put_device(dssdev);
971 r = dss_add_device(dssdev);
973 DSSERR("device %s register failed: %d\n", dssdev->name, r);
974 dss_put_device(dssdev);
979 static void __init hdmi_init_output(struct platform_device *pdev)
981 struct omap_dss_output *out = &hdmi.output;
984 out->id = OMAP_DSS_OUTPUT_HDMI;
985 out->type = OMAP_DISPLAY_TYPE_HDMI;
987 dss_register_output(out);
990 static void __exit hdmi_uninit_output(struct platform_device *pdev)
992 struct omap_dss_output *out = &hdmi.output;
994 dss_unregister_output(out);
997 /* HDMI HW IP initialisation */
998 static int __init omapdss_hdmihw_probe(struct platform_device *pdev)
1000 struct resource *hdmi_mem;
1005 mutex_init(&hdmi.lock);
1007 hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
1009 DSSERR("can't get IORESOURCE_MEM HDMI\n");
1013 /* Base address taken from platform */
1014 hdmi.ip_data.base_wp = ioremap(hdmi_mem->start,
1015 resource_size(hdmi_mem));
1016 if (!hdmi.ip_data.base_wp) {
1017 DSSERR("can't ioremap WP\n");
1021 r = hdmi_get_clocks(pdev);
1023 iounmap(hdmi.ip_data.base_wp);
1027 pm_runtime_enable(&pdev->dev);
1029 hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
1030 hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
1031 hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
1032 hdmi.ip_data.phy_offset = HDMI_PHY;
1034 mutex_init(&hdmi.ip_data.lock);
1038 dss_debugfs_create_file("hdmi", hdmi_dump_regs);
1040 hdmi_init_output(pdev);
1042 hdmi_probe_pdata(pdev);
1047 static int __exit hdmi_remove_child(struct device *dev, void *data)
1049 struct omap_dss_device *dssdev = to_dss_device(dev);
1050 hdmi_uninit_display(dssdev);
1054 static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
1056 device_for_each_child(&pdev->dev, NULL, hdmi_remove_child);
1058 dss_unregister_child_devices(&pdev->dev);
1062 hdmi_uninit_output(pdev);
1064 pm_runtime_disable(&pdev->dev);
1068 iounmap(hdmi.ip_data.base_wp);
1073 static int hdmi_runtime_suspend(struct device *dev)
1075 clk_disable_unprepare(hdmi.sys_clk);
1077 dispc_runtime_put();
1082 static int hdmi_runtime_resume(struct device *dev)
1086 r = dispc_runtime_get();
1090 clk_prepare_enable(hdmi.sys_clk);
1095 static const struct dev_pm_ops hdmi_pm_ops = {
1096 .runtime_suspend = hdmi_runtime_suspend,
1097 .runtime_resume = hdmi_runtime_resume,
1100 static struct platform_driver omapdss_hdmihw_driver = {
1101 .remove = __exit_p(omapdss_hdmihw_remove),
1103 .name = "omapdss_hdmi",
1104 .owner = THIS_MODULE,
1109 int __init hdmi_init_platform_driver(void)
1111 return platform_driver_probe(&omapdss_hdmihw_driver, omapdss_hdmihw_probe);
1114 void __exit hdmi_uninit_platform_driver(void)
1116 platform_driver_unregister(&omapdss_hdmihw_driver);