2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device
4 * Copyright (C) 1995 Jay Estabrook
5 * Copyright (C) 1997 Geert Uytterhoeven
6 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
7 * Copyright (C) 2002 Richard Henderson
8 * Copyright (C) 2006, 2007 Maciej W. Rozycki
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive for
15 #include <linux/aperture.h>
16 #include <linux/bitrev.h>
17 #include <linux/compiler.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/errno.h>
22 #include <linux/init.h>
23 #include <linux/ioport.h>
24 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/selection.h>
29 #include <linux/string.h>
34 #include <video/tgafb.h>
37 #define TGA_BUS_TC(dev) (dev->bus == &tc_bus_type)
39 #define TGA_BUS_TC(dev) 0
46 static int tgafb_check_var(struct fb_var_screeninfo *, struct fb_info *);
47 static int tgafb_set_par(struct fb_info *);
48 static void tgafb_set_pll(struct tga_par *, int);
49 static int tgafb_setcolreg(unsigned, unsigned, unsigned, unsigned,
50 unsigned, struct fb_info *);
51 static int tgafb_blank(int, struct fb_info *);
52 static void tgafb_init_fix(struct fb_info *);
54 static void tgafb_imageblit(struct fb_info *, const struct fb_image *);
55 static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *);
56 static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *);
57 static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
59 static int tgafb_register(struct device *dev);
60 static void tgafb_unregister(struct device *dev);
62 static const char *mode_option;
63 static const char *mode_option_pci = "640x480@60";
64 static const char *mode_option_tc = "1280x1024@72";
67 static struct pci_driver tgafb_pci_driver;
68 static struct tc_driver tgafb_tc_driver;
71 * Frame buffer operations
74 static const struct fb_ops tgafb_ops = {
76 .fb_check_var = tgafb_check_var,
77 .fb_set_par = tgafb_set_par,
78 .fb_setcolreg = tgafb_setcolreg,
79 .fb_blank = tgafb_blank,
80 .fb_pan_display = tgafb_pan_display,
81 .fb_fillrect = tgafb_fillrect,
82 .fb_copyarea = tgafb_copyarea,
83 .fb_imageblit = tgafb_imageblit,
89 * PCI registration operations
91 static int tgafb_pci_register(struct pci_dev *, const struct pci_device_id *);
92 static void tgafb_pci_unregister(struct pci_dev *);
94 static struct pci_device_id const tgafb_pci_table[] = {
95 { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA) },
98 MODULE_DEVICE_TABLE(pci, tgafb_pci_table);
100 static struct pci_driver tgafb_pci_driver = {
102 .id_table = tgafb_pci_table,
103 .probe = tgafb_pci_register,
104 .remove = tgafb_pci_unregister,
107 static int tgafb_pci_register(struct pci_dev *pdev,
108 const struct pci_device_id *ent)
112 ret = aperture_remove_conflicting_pci_devices(pdev, "tgafb");
116 return tgafb_register(&pdev->dev);
119 static void tgafb_pci_unregister(struct pci_dev *pdev)
121 tgafb_unregister(&pdev->dev);
123 #endif /* CONFIG_PCI */
127 * TC registration operations
129 static int tgafb_tc_register(struct device *);
130 static int tgafb_tc_unregister(struct device *);
132 static struct tc_device_id const tgafb_tc_table[] = {
133 { "DEC ", "PMAGD-AA" },
134 { "DEC ", "PMAGD " },
137 MODULE_DEVICE_TABLE(tc, tgafb_tc_table);
139 static struct tc_driver tgafb_tc_driver = {
140 .id_table = tgafb_tc_table,
144 .probe = tgafb_tc_register,
145 .remove = tgafb_tc_unregister,
149 static int tgafb_tc_register(struct device *dev)
151 int status = tgafb_register(dev);
157 static int tgafb_tc_unregister(struct device *dev)
160 tgafb_unregister(dev);
163 #endif /* CONFIG_TC */
167 * tgafb_check_var - Optional function. Validates a var passed in.
168 * @var: frame buffer variable screen structure
169 * @info: frame buffer structure that represents a single frame buffer
172 tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
174 struct tga_par *par = (struct tga_par *)info->par;
179 if (par->tga_type == TGA_TYPE_8PLANE) {
180 if (var->bits_per_pixel != 8)
183 if (var->bits_per_pixel != 32)
186 var->red.length = var->green.length = var->blue.length = 8;
187 if (var->bits_per_pixel == 32) {
188 var->red.offset = 16;
189 var->green.offset = 8;
190 var->blue.offset = 0;
193 if (var->xres_virtual != var->xres || var->yres_virtual != var->yres)
195 if (var->xres * var->yres * (var->bits_per_pixel >> 3) > info->fix.smem_len)
199 if (1000000000 / var->pixclock > TGA_PLL_MAX_FREQ)
201 if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
204 /* Some of the acceleration routines assume the line width is
205 a multiple of 8 bytes. */
206 if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 8)
213 * tgafb_set_par - Optional function. Alters the hardware state.
214 * @info: frame buffer structure that represents a single frame buffer
217 tgafb_set_par(struct fb_info *info)
219 static unsigned int const deep_presets[4] = {
225 static unsigned int const rasterop_presets[4] = {
231 static unsigned int const mode_presets[4] = {
237 static unsigned int const base_addr_presets[4] = {
244 struct tga_par *par = (struct tga_par *) info->par;
245 int tga_bus_pci = dev_is_pci(par->dev);
246 int tga_bus_tc = TGA_BUS_TC(par->dev);
247 u32 htimings, vtimings, pll_freq;
251 /* Encode video timings. */
252 htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
253 | (((info->var.xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB));
254 vtimings = (info->var.yres & TGA_VERT_ACTIVE);
255 htimings |= ((info->var.right_margin/4) << 9) & TGA_HORIZ_FP;
256 vtimings |= (info->var.lower_margin << 11) & TGA_VERT_FP;
257 htimings |= ((info->var.hsync_len/4) << 14) & TGA_HORIZ_SYNC;
258 vtimings |= (info->var.vsync_len << 16) & TGA_VERT_SYNC;
259 htimings |= ((info->var.left_margin/4) << 21) & TGA_HORIZ_BP;
260 vtimings |= (info->var.upper_margin << 22) & TGA_VERT_BP;
262 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
263 htimings |= TGA_HORIZ_POLARITY;
264 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
265 vtimings |= TGA_VERT_POLARITY;
267 par->htimings = htimings;
268 par->vtimings = vtimings;
270 par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN);
272 /* Store other useful values in par. */
273 par->xres = info->var.xres;
274 par->yres = info->var.yres;
275 par->pll_freq = pll_freq = 1000000000 / info->var.pixclock;
276 par->bits_per_pixel = info->var.bits_per_pixel;
277 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3);
279 tga_type = par->tga_type;
281 /* First, disable video. */
282 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
284 /* Write the DEEP register. */
285 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
288 TGA_WRITE_REG(par, deep_presets[tga_type] |
289 (par->sync_on_green ? 0x0 : 0x00010000),
291 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
295 /* Write some more registers. */
296 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
297 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
298 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
300 /* Calculate & write the PLL. */
301 tgafb_set_pll(par, pll_freq);
303 /* Write some more registers. */
304 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
305 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
307 /* Init video timing regs. */
308 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
309 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
311 /* Initialise RAMDAC. */
312 if (tga_type == TGA_TYPE_8PLANE && tga_bus_pci) {
314 /* Init BT485 RAMDAC registers. */
315 BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0),
317 BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE);
318 BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */
319 BT485_WRITE(par, 0x40, BT485_CMD_1);
320 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
321 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
323 /* Fill palette registers. */
324 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
325 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
327 for (i = 0; i < 256 * 3; i += 4) {
328 TGA_WRITE_REG(par, 0x55 | (BT485_DATA_PAL << 8),
330 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
332 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
334 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
338 } else if (tga_type == TGA_TYPE_8PLANE && tga_bus_tc) {
340 /* Init BT459 RAMDAC registers. */
341 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_0, 0x40);
342 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_1, 0x00);
343 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_2,
344 (par->sync_on_green ? 0xc0 : 0x40));
346 BT459_WRITE(par, BT459_REG_ACC, BT459_CUR_CMD_REG, 0x00);
348 /* Fill the palette. */
349 BT459_LOAD_ADDR(par, 0x0000);
350 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
352 for (i = 0; i < 256 * 3; i += 4) {
353 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
354 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
355 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
356 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
359 } else { /* 24-plane or 24plusZ */
361 /* Init BT463 RAMDAC registers. */
362 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
363 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
364 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
365 (par->sync_on_green ? 0xc0 : 0x40));
367 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
368 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
369 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff);
370 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f);
372 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00);
373 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00);
374 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
375 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
377 /* Fill the palette. */
378 BT463_LOAD_ADDR(par, 0x0000);
379 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
381 #ifdef CONFIG_HW_CONSOLE
382 for (i = 0; i < 16; i++) {
383 int j = color_table[i];
385 TGA_WRITE_REG(par, default_red[j], TGA_RAMDAC_REG);
386 TGA_WRITE_REG(par, default_grn[j], TGA_RAMDAC_REG);
387 TGA_WRITE_REG(par, default_blu[j], TGA_RAMDAC_REG);
389 for (i = 0; i < 512 * 3; i += 4) {
391 for (i = 0; i < 528 * 3; i += 4) {
393 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
394 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
395 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
396 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
399 /* Fill window type table after start of vertical retrace. */
400 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
402 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
404 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
406 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
408 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE);
409 TGA_WRITE_REG(par, BT463_REG_ACC << 2, TGA_RAMDAC_SETUP_REG);
411 for (i = 0; i < 16; i++) {
412 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
413 TGA_WRITE_REG(par, 0x01, TGA_RAMDAC_REG);
414 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
419 /* Finally, enable video scan (and pray for the monitor... :-) */
420 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
425 #define DIFFCHECK(X) \
428 int delta = f - (TGA_PLL_BASE_FREQ * (X)) / (r << shift); \
431 if (delta < min_diff) \
432 min_diff = delta, vm = m, va = a, vr = r; \
437 tgafb_set_pll(struct tga_par *par, int f)
439 int n, shift, base, min_diff, target;
440 int r,a,m,vm = 34, va = 1, vr = 30;
442 for (r = 0 ; r < 12 ; r++)
443 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
445 if (f > TGA_PLL_MAX_FREQ)
446 f = TGA_PLL_MAX_FREQ;
448 if (f >= TGA_PLL_MAX_FREQ / 2)
450 else if (f >= TGA_PLL_MAX_FREQ / 4)
455 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
456 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
458 for (r = 0 ; r < 10 ; r++)
459 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
462 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
463 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
465 else if (f <= 200000) {
466 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
467 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
470 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
471 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
474 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
475 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
476 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
477 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
478 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
479 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
481 target = (f << shift) / TGA_PLL_BASE_FREQ;
482 min_diff = TGA_PLL_MAX_FREQ;
489 for (n = base < 7 ? 7 : base; n < base + target && n < 449; n++) {
490 m = ((n + 3) / 7) - 1;
492 DIFFCHECK((m + 1) * 7);
494 DIFFCHECK((m + 1) * 7);
505 for (r = 0; r < 8; r++)
506 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
507 for (r = 0; r < 8 ; r++)
508 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
509 for (r = 0; r < 7 ; r++)
510 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
511 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
516 * tgafb_setcolreg - Optional function. Sets a color register.
517 * @regno: boolean, 0 copy local, 1 get_user() function
518 * @red: frame buffer colormap structure
519 * @green: The green value which can be up to 16 bits wide
520 * @blue: The blue value which can be up to 16 bits wide.
521 * @transp: If supported the alpha value which can be up to 16 bits wide.
522 * @info: frame buffer info structure
525 tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
526 unsigned transp, struct fb_info *info)
528 struct tga_par *par = (struct tga_par *) info->par;
529 int tga_bus_pci = dev_is_pci(par->dev);
530 int tga_bus_tc = TGA_BUS_TC(par->dev);
538 if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_pci) {
539 BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE);
540 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
541 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
542 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
543 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
544 } else if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_tc) {
545 BT459_LOAD_ADDR(par, regno);
546 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
547 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
548 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
549 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
552 u32 value = (regno << 16) | (regno << 8) | regno;
553 ((u32 *)info->pseudo_palette)[regno] = value;
555 BT463_LOAD_ADDR(par, regno);
556 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
557 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
558 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
559 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
567 * tgafb_blank - Optional function. Blanks the display.
568 * @blank: the blank mode we want.
569 * @info: frame buffer structure that represents a single frame buffer
572 tgafb_blank(int blank, struct fb_info *info)
574 struct tga_par *par = (struct tga_par *) info->par;
575 u32 vhcr, vvcr, vvvr;
578 local_irq_save(flags);
580 vhcr = TGA_READ_REG(par, TGA_HORIZ_REG);
581 vvcr = TGA_READ_REG(par, TGA_VERT_REG);
582 vvvr = TGA_READ_REG(par, TGA_VALID_REG);
583 vvvr &= ~(TGA_VALID_VIDEO | TGA_VALID_BLANK);
586 case FB_BLANK_UNBLANK: /* Unblanking */
587 if (par->vesa_blanked) {
588 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
589 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
590 par->vesa_blanked = 0;
592 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
595 case FB_BLANK_NORMAL: /* Normal blanking */
596 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
600 case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
601 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
602 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
603 par->vesa_blanked = 1;
606 case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
607 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
608 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
609 par->vesa_blanked = 1;
612 case FB_BLANK_POWERDOWN: /* Poweroff */
613 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
614 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
615 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
616 par->vesa_blanked = 1;
620 local_irq_restore(flags);
630 tgafb_mono_imageblit(struct fb_info *info, const struct fb_image *image)
632 struct tga_par *par = (struct tga_par *) info->par;
633 u32 fgcolor, bgcolor, dx, dy, width, height, vxres, vyres, pixelmask;
634 unsigned long rincr, line_length, shift, pos, is8bpp;
636 const unsigned char *data;
637 void __iomem *regs_base;
638 void __iomem *fb_base;
640 is8bpp = info->var.bits_per_pixel == 8;
644 width = image->width;
645 height = image->height;
646 vxres = info->var.xres_virtual;
647 vyres = info->var.yres_virtual;
648 line_length = info->fix.line_length;
649 rincr = (width + 7) / 8;
651 /* A shift below cannot cope with. */
652 if (unlikely(width == 0))
654 /* Crop the image to the screen. */
655 if (dx > vxres || dy > vyres)
657 if (dx + width > vxres)
659 if (dy + height > vyres)
662 regs_base = par->tga_regs_base;
663 fb_base = par->tga_fb_base;
665 /* Expand the color values to fill 32-bits. */
666 /* ??? Would be nice to notice colour changes elsewhere, so
667 that we can do this only when necessary. */
668 fgcolor = image->fg_color;
669 bgcolor = image->bg_color;
671 fgcolor |= fgcolor << 8;
672 fgcolor |= fgcolor << 16;
673 bgcolor |= bgcolor << 8;
674 bgcolor |= bgcolor << 16;
677 fgcolor = ((u32 *)info->pseudo_palette)[fgcolor];
679 bgcolor = ((u32 *)info->pseudo_palette)[bgcolor];
681 __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG);
682 __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG);
684 /* Acquire proper alignment; set up the PIXELMASK register
685 so that we only write the proper character cell. */
686 pos = dy * line_length;
693 shift = (pos & 7) >> 2;
697 data = (const unsigned char *) image->data;
699 /* Enable opaque stipple mode. */
701 ? TGA_MODE_SBM_8BPP | TGA_MODE_OPAQUE_STIPPLE
702 : TGA_MODE_SBM_24BPP | TGA_MODE_OPAQUE_STIPPLE),
703 regs_base + TGA_MODE_REG);
705 if (width + shift <= 32) {
706 unsigned long bwidth;
708 /* Handle common case of imaging a single character, in
709 a font less than or 32 pixels wide. */
711 /* Avoid a shift by 32; width > 0 implied. */
712 pixelmask = (2ul << (width - 1)) - 1;
714 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
717 bwidth = (width + 7) / 8;
719 for (i = 0; i < height; ++i) {
722 /* The image data is bit big endian; we need
724 for (j = 0; j < bwidth; ++j)
725 mask |= bitrev8(data[j]) << (j * 8);
727 __raw_writel(mask << shift, fb_base + pos);
733 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
734 } else if (shift == 0) {
735 unsigned long pos0 = pos;
736 const unsigned char *data0 = data;
737 unsigned long bincr = (is8bpp ? 8 : 8*4);
738 unsigned long bwidth;
740 /* Handle another common case in which accel_putcs
741 generates a large bitmap, which happens to be aligned.
742 Allow the tail to be misaligned. This case is
743 interesting because we've not got to hold partial
744 bytes across the words being written. */
748 bwidth = (width / 8) & -4;
749 for (i = 0; i < height; ++i) {
750 for (j = 0; j < bwidth; j += 4) {
752 mask |= bitrev8(data[j+0]) << (0 * 8);
753 mask |= bitrev8(data[j+1]) << (1 * 8);
754 mask |= bitrev8(data[j+2]) << (2 * 8);
755 mask |= bitrev8(data[j+3]) << (3 * 8);
756 __raw_writel(mask, fb_base + pos + j*bincr);
763 pixelmask = (1ul << (width & 31)) - 1;
765 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
768 pos = pos0 + bwidth*bincr;
769 data = data0 + bwidth;
770 bwidth = ((width & 31) + 7) / 8;
772 for (i = 0; i < height; ++i) {
774 for (j = 0; j < bwidth; ++j)
775 mask |= bitrev8(data[j]) << (j * 8);
776 __raw_writel(mask, fb_base + pos);
781 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
784 unsigned long pos0 = pos;
785 const unsigned char *data0 = data;
786 unsigned long bincr = (is8bpp ? 8 : 8*4);
787 unsigned long bwidth;
789 /* Finally, handle the generic case of misaligned start.
790 Here we split the write into 16-bit spans. This allows
791 us to use only one pixel mask, instead of four as would
792 be required by writing 24-bit spans. */
794 pixelmask = 0xffff << shift;
795 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
798 bwidth = (width / 8) & -2;
799 for (i = 0; i < height; ++i) {
800 for (j = 0; j < bwidth; j += 2) {
802 mask |= bitrev8(data[j+0]) << (0 * 8);
803 mask |= bitrev8(data[j+1]) << (1 * 8);
805 __raw_writel(mask, fb_base + pos + j*bincr);
812 pixelmask = ((1ul << (width & 15)) - 1) << shift;
814 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
817 pos = pos0 + bwidth*bincr;
818 data = data0 + bwidth;
819 bwidth = (width & 15) > 8;
821 for (i = 0; i < height; ++i) {
822 u32 mask = bitrev8(data[0]);
824 mask |= bitrev8(data[1]) << 8;
826 __raw_writel(mask, fb_base + pos);
832 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
835 /* Disable opaque stipple mode. */
837 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
838 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
839 regs_base + TGA_MODE_REG);
843 tgafb_clut_imageblit(struct fb_info *info, const struct fb_image *image)
845 struct tga_par *par = (struct tga_par *) info->par;
846 u32 color, dx, dy, width, height, vxres, vyres;
847 u32 *palette = ((u32 *)info->pseudo_palette);
848 unsigned long pos, line_length, i, j;
849 const unsigned char *data;
850 void __iomem *fb_base;
854 width = image->width;
855 height = image->height;
856 vxres = info->var.xres_virtual;
857 vyres = info->var.yres_virtual;
858 line_length = info->fix.line_length;
860 /* Crop the image to the screen. */
861 if (dx > vxres || dy > vyres)
863 if (dx + width > vxres)
865 if (dy + height > vyres)
868 fb_base = par->tga_fb_base;
870 pos = dy * line_length + (dx * 4);
873 /* Now copy the image, color_expanding via the palette. */
874 for (i = 0; i < height; i++) {
875 for (j = 0; j < width; j++) {
876 color = palette[*data++];
877 __raw_writel(color, fb_base + pos + j*4);
884 * tgafb_imageblit - REQUIRED function. Can use generic routines if
885 * non acclerated hardware and packed pixel based.
886 * Copies a image from system memory to the screen.
888 * @info: frame buffer structure that represents a single frame buffer
889 * @image: structure defining the image.
892 tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
894 unsigned int is8bpp = info->var.bits_per_pixel == 8;
896 /* If a mono image, regardless of FB depth, go do it. */
897 if (image->depth == 1) {
898 tgafb_mono_imageblit(info, image);
902 /* For copies that aren't pixel expansion, there's little we
903 can do better than the generic code. */
904 /* ??? There is a DMA write mode; I wonder if that could be
905 made to pull the data from the image buffer... */
906 if (image->depth == info->var.bits_per_pixel) {
907 cfb_imageblit(info, image);
911 /* If 24-plane FB and the image is 8-plane with CLUT, we can do it. */
912 if (!is8bpp && image->depth == 8) {
913 tgafb_clut_imageblit(info, image);
917 /* Silently return... */
921 * tgafb_fillrect - REQUIRED function. Can use generic routines if
922 * non acclerated hardware and packed pixel based.
923 * Draws a rectangle on the screen.
925 * @info: frame buffer structure that represents a single frame buffer
926 * @rect: structure defining the rectagle and operation.
929 tgafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
931 struct tga_par *par = (struct tga_par *) info->par;
932 int is8bpp = info->var.bits_per_pixel == 8;
933 u32 dx, dy, width, height, vxres, vyres, color;
934 unsigned long pos, align, line_length, i, j;
935 void __iomem *regs_base;
936 void __iomem *fb_base;
941 height = rect->height;
942 vxres = info->var.xres_virtual;
943 vyres = info->var.yres_virtual;
944 line_length = info->fix.line_length;
945 regs_base = par->tga_regs_base;
946 fb_base = par->tga_fb_base;
948 /* Crop the rectangle to the screen. */
949 if (dx > vxres || dy > vyres || !width || !height)
951 if (dx + width > vxres)
953 if (dy + height > vyres)
956 pos = dy * line_length + dx * (is8bpp ? 1 : 4);
958 /* ??? We could implement ROP_XOR with opaque fill mode
959 and a RasterOp setting of GXxor, but as far as I can
960 tell, this mode is not actually used in the kernel.
961 Thus I am ignoring it for now. */
962 if (rect->rop != ROP_COPY) {
963 cfb_fillrect(info, rect);
967 /* Expand the color value to fill 8 pixels. */
971 color |= color << 16;
972 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
973 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
976 color = ((u32 *)info->pseudo_palette)[color];
977 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
978 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
979 __raw_writel(color, regs_base + TGA_BLOCK_COLOR2_REG);
980 __raw_writel(color, regs_base + TGA_BLOCK_COLOR3_REG);
981 __raw_writel(color, regs_base + TGA_BLOCK_COLOR4_REG);
982 __raw_writel(color, regs_base + TGA_BLOCK_COLOR5_REG);
983 __raw_writel(color, regs_base + TGA_BLOCK_COLOR6_REG);
984 __raw_writel(color, regs_base + TGA_BLOCK_COLOR7_REG);
987 /* The DATA register holds the fill mask for block fill mode.
988 Since we're not stippling, this is all ones. */
989 __raw_writel(0xffffffff, regs_base + TGA_DATA_REG);
991 /* Enable block fill mode. */
993 ? TGA_MODE_SBM_8BPP | TGA_MODE_BLOCK_FILL
994 : TGA_MODE_SBM_24BPP | TGA_MODE_BLOCK_FILL),
995 regs_base + TGA_MODE_REG);
998 /* We can fill 2k pixels per operation. Notice blocks that fit
999 the width of the screen so that we can take advantage of this
1000 and fill more than one line per write. */
1001 if (width == line_length) {
1006 /* The write into the frame buffer must be aligned to 4 bytes,
1007 but we are allowed to encode the offset within the word in
1008 the data word written. */
1009 align = (pos & 3) << 16;
1012 if (width <= 2048) {
1015 data = (width - 1) | align;
1017 for (i = 0; i < height; ++i) {
1018 __raw_writel(data, fb_base + pos);
1022 unsigned long Bpp = (is8bpp ? 1 : 4);
1023 unsigned long nwidth = width & -2048;
1026 fdata = (2048 - 1) | align;
1027 ldata = ((width & 2047) - 1) | align;
1029 for (i = 0; i < height; ++i) {
1030 for (j = 0; j < nwidth; j += 2048)
1031 __raw_writel(fdata, fb_base + pos + j*Bpp);
1033 __raw_writel(ldata, fb_base + pos + j*Bpp);
1039 /* Disable block fill mode. */
1040 __raw_writel((is8bpp
1041 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
1042 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
1043 regs_base + TGA_MODE_REG);
1047 * tgafb_copyarea - REQUIRED function. Can use generic routines if
1048 * non acclerated hardware and packed pixel based.
1049 * Copies on area of the screen to another area.
1051 * @info: frame buffer structure that represents a single frame buffer
1052 * @area: structure defining the source and destination.
1055 /* Handle the special case of copying entire lines, e.g. during scrolling.
1056 We can avoid a lot of needless computation in this case. In the 8bpp
1057 case we need to use the COPY64 registers instead of mask writes into
1058 the frame buffer to achieve maximum performance. */
1061 copyarea_line_8bpp(struct fb_info *info, u32 dy, u32 sy,
1062 u32 height, u32 width)
1064 struct tga_par *par = (struct tga_par *) info->par;
1065 void __iomem *tga_regs = par->tga_regs_base;
1066 unsigned long dpos, spos, i, n64;
1068 /* Set up the MODE and PIXELSHIFT registers. */
1069 __raw_writel(TGA_MODE_SBM_8BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1070 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1073 n64 = (height * width) / 64;
1076 spos = (sy + height) * width;
1077 dpos = (dy + height) * width;
1079 for (i = 0; i < n64; ++i) {
1082 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
1084 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
1091 for (i = 0; i < n64; ++i) {
1092 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
1094 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
1101 /* Reset the MODE register to normal. */
1102 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1106 copyarea_line_32bpp(struct fb_info *info, u32 dy, u32 sy,
1107 u32 height, u32 width)
1109 struct tga_par *par = (struct tga_par *) info->par;
1110 void __iomem *tga_regs = par->tga_regs_base;
1111 void __iomem *tga_fb = par->tga_fb_base;
1114 unsigned long i, n16;
1116 /* Set up the MODE and PIXELSHIFT registers. */
1117 __raw_writel(TGA_MODE_SBM_24BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1118 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1121 n16 = (height * width) / 16;
1124 src = tga_fb + (sy + height) * width * 4;
1125 dst = tga_fb + (dy + height) * width * 4;
1127 for (i = 0; i < n16; ++i) {
1130 __raw_writel(0xffff, src);
1132 __raw_writel(0xffff, dst);
1136 src = tga_fb + sy * width * 4;
1137 dst = tga_fb + dy * width * 4;
1139 for (i = 0; i < n16; ++i) {
1140 __raw_writel(0xffff, src);
1142 __raw_writel(0xffff, dst);
1149 /* Reset the MODE register to normal. */
1150 __raw_writel(TGA_MODE_SBM_24BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1153 /* The (almost) general case of backward copy in 8bpp mode. */
1155 copyarea_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1156 u32 height, u32 width, u32 line_length,
1157 const struct fb_copyarea *area)
1159 struct tga_par *par = (struct tga_par *) info->par;
1161 int depos, sepos, backward, last_step, step;
1164 void __iomem *tga_regs;
1165 void __iomem *tga_fb;
1167 /* Do acceleration only if we are aligned on 8 pixels */
1168 if ((dx | sx | width) & 7) {
1169 cfb_copyarea(info, area);
1173 yincr = line_length;
1179 backward = dy == sy && dx > sx && dx < sx + width;
1181 /* Compute the offsets and alignments in the frame buffer.
1182 More than anything else, these control how we do copies. */
1183 depos = dy * line_length + dx;
1184 sepos = sy * line_length + sx;
1190 /* Next copy full words at a time. */
1192 last_step = width % 32;
1194 /* Finally copy the unaligned head of the span. */
1195 mask_last = (1ul << last_step) - 1;
1202 last_step = -last_step;
1207 tga_regs = par->tga_regs_base;
1208 tga_fb = par->tga_fb_base;
1210 /* Set up the MODE and PIXELSHIFT registers. */
1211 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1212 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1215 for (i = 0; i < height; ++i) {
1220 sfb = tga_fb + sepos;
1221 dfb = tga_fb + depos;
1223 for (j = 0; j < n32; j++) {
1224 if (j < 2 && j + 1 < n32 && !backward &&
1225 !(((unsigned long)sfb | (unsigned long)dfb) & 63)) {
1227 __raw_writel(sfb - tga_fb, tga_regs+TGA_COPY64_SRC);
1229 __raw_writel(dfb - tga_fb, tga_regs+TGA_COPY64_DST);
1234 } while (j + 1 < n32);
1238 __raw_writel(0xffffffff, sfb);
1240 __raw_writel(0xffffffff, dfb);
1247 sfb += last_step - step;
1248 dfb += last_step - step;
1249 __raw_writel(mask_last, sfb);
1251 __raw_writel(mask_last, dfb);
1259 /* Reset the MODE register to normal. */
1260 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1264 tgafb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1266 unsigned long dx, dy, width, height, sx, sy, vxres, vyres;
1267 unsigned long line_length, bpp;
1271 width = area->width;
1272 height = area->height;
1275 vxres = info->var.xres_virtual;
1276 vyres = info->var.yres_virtual;
1277 line_length = info->fix.line_length;
1279 /* The top left corners must be in the virtual screen. */
1280 if (dx > vxres || sx > vxres || dy > vyres || sy > vyres)
1283 /* Clip the destination. */
1284 if (dx + width > vxres)
1286 if (dy + height > vyres)
1287 height = vyres - dy;
1289 /* The source must be completely inside the virtual screen. */
1290 if (sx + width > vxres || sy + height > vyres)
1293 bpp = info->var.bits_per_pixel;
1295 /* Detect copies of the entire line. */
1296 if (!(line_length & 63) && width * (bpp >> 3) == line_length) {
1298 copyarea_line_8bpp(info, dy, sy, height, width);
1300 copyarea_line_32bpp(info, dy, sy, height, width);
1303 /* ??? The documentation is unclear to me exactly how the pixelshift
1304 register works in 32bpp mode. Since I don't have hardware to test,
1305 give up for now and fall back on the generic routines. */
1307 cfb_copyarea(info, area);
1310 copyarea_8bpp(info, dx, dy, sx, sy, height,
1311 width, line_length, area);
1320 tgafb_init_fix(struct fb_info *info)
1322 struct tga_par *par = (struct tga_par *)info->par;
1323 int tga_bus_pci = dev_is_pci(par->dev);
1324 int tga_bus_tc = TGA_BUS_TC(par->dev);
1325 u8 tga_type = par->tga_type;
1326 const char *tga_type_name = NULL;
1327 unsigned memory_size;
1330 case TGA_TYPE_8PLANE:
1332 tga_type_name = "Digital ZLXp-E1";
1334 tga_type_name = "Digital ZLX-E1";
1335 memory_size = 2097152;
1337 case TGA_TYPE_24PLANE:
1339 tga_type_name = "Digital ZLXp-E2";
1341 tga_type_name = "Digital ZLX-E2";
1342 memory_size = 8388608;
1344 case TGA_TYPE_24PLUSZ:
1346 tga_type_name = "Digital ZLXp-E3";
1348 tga_type_name = "Digital ZLX-E3";
1349 memory_size = 16777216;
1352 if (!tga_type_name) {
1353 tga_type_name = "Unknown";
1354 memory_size = 16777216;
1357 strscpy(info->fix.id, tga_type_name, sizeof(info->fix.id));
1359 info->fix.type = FB_TYPE_PACKED_PIXELS;
1360 info->fix.type_aux = 0;
1361 info->fix.visual = (tga_type == TGA_TYPE_8PLANE
1362 ? FB_VISUAL_PSEUDOCOLOR
1363 : FB_VISUAL_DIRECTCOLOR);
1365 info->fix.smem_start = (size_t) par->tga_fb_base;
1366 info->fix.smem_len = memory_size;
1367 info->fix.mmio_start = (size_t) par->tga_regs_base;
1368 info->fix.mmio_len = 512;
1370 info->fix.xpanstep = 0;
1371 info->fix.ypanstep = 0;
1372 info->fix.ywrapstep = 0;
1374 info->fix.accel = FB_ACCEL_DEC_TGA;
1377 * These are needed by fb_set_logo_truepalette(), so we
1378 * set them here for 24-plane cards.
1380 if (tga_type != TGA_TYPE_8PLANE) {
1381 info->var.red.length = 8;
1382 info->var.green.length = 8;
1383 info->var.blue.length = 8;
1384 info->var.red.offset = 16;
1385 info->var.green.offset = 8;
1386 info->var.blue.offset = 0;
1390 static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1392 /* We just use this to catch switches out of graphics mode. */
1393 tgafb_set_par(info); /* A bit of overkill for BASE_ADDR reset. */
1397 static int tgafb_register(struct device *dev)
1399 static const struct fb_videomode modedb_tc = {
1400 /* 1280x1024 @ 72 Hz, 76.8 kHz hsync */
1401 "1280x1024@72", 0, 1280, 1024, 7645, 224, 28, 33, 3, 160, 3,
1402 FB_SYNC_ON_GREEN, FB_VMODE_NONINTERLACED
1405 static unsigned int const fb_offset_presets[4] = {
1406 TGA_8PLANE_FB_OFFSET,
1407 TGA_24PLANE_FB_OFFSET,
1409 TGA_24PLUSZ_FB_OFFSET
1412 const struct fb_videomode *modedb_tga = NULL;
1413 resource_size_t bar0_start = 0, bar0_len = 0;
1414 const char *mode_option_tga = NULL;
1415 int tga_bus_pci = dev_is_pci(dev);
1416 int tga_bus_tc = TGA_BUS_TC(dev);
1417 unsigned int modedbsize_tga = 0;
1418 void __iomem *mem_base;
1419 struct fb_info *info;
1420 struct tga_par *par;
1424 /* Enable device in PCI config. */
1425 if (tga_bus_pci && pci_enable_device(to_pci_dev(dev))) {
1426 printk(KERN_ERR "tgafb: Cannot enable PCI device\n");
1430 /* Allocate the fb and par structures. */
1431 info = framebuffer_alloc(sizeof(struct tga_par), dev);
1436 dev_set_drvdata(dev, info);
1438 /* Request the mem regions. */
1441 bar0_start = pci_resource_start(to_pci_dev(dev), 0);
1442 bar0_len = pci_resource_len(to_pci_dev(dev), 0);
1445 bar0_start = to_tc_dev(dev)->resource.start;
1446 bar0_len = to_tc_dev(dev)->resource.end - bar0_start + 1;
1448 if (!request_mem_region (bar0_start, bar0_len, "tgafb")) {
1449 printk(KERN_ERR "tgafb: cannot reserve FB region\n");
1453 /* Map the framebuffer. */
1454 mem_base = ioremap(bar0_start, bar0_len);
1456 printk(KERN_ERR "tgafb: Cannot map MMIO\n");
1460 /* Grab info about the card. */
1461 tga_type = (readl(mem_base) >> 12) & 0x0f;
1463 par->tga_mem_base = mem_base;
1464 par->tga_fb_base = mem_base + fb_offset_presets[tga_type];
1465 par->tga_regs_base = mem_base + TGA_REGS_OFFSET;
1466 par->tga_type = tga_type;
1468 par->tga_chip_rev = (to_pci_dev(dev))->revision;
1470 par->tga_chip_rev = TGA_READ_REG(par, TGA_START_REG) & 0xff;
1472 /* Setup framebuffer. */
1473 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
1474 FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT;
1475 info->fbops = &tgafb_ops;
1476 info->screen_base = par->tga_fb_base;
1477 info->pseudo_palette = par->palette;
1479 /* This should give a reasonable default video mode. */
1481 mode_option_tga = mode_option_pci;
1484 mode_option_tga = mode_option_tc;
1485 modedb_tga = &modedb_tc;
1489 tgafb_init_fix(info);
1491 ret = fb_find_mode(&info->var, info,
1492 mode_option ? mode_option : mode_option_tga,
1493 modedb_tga, modedbsize_tga, NULL,
1494 tga_type == TGA_TYPE_8PLANE ? 8 : 32);
1495 if (ret == 0 || ret == 4) {
1496 printk(KERN_ERR "tgafb: Could not find valid video mode\n");
1501 if (fb_alloc_cmap(&info->cmap, 256, 0)) {
1502 printk(KERN_ERR "tgafb: Could not allocate color map\n");
1507 tgafb_set_par(info);
1509 if (register_framebuffer(info) < 0) {
1510 printk(KERN_ERR "tgafb: Could not register framebuffer\n");
1516 pr_info("tgafb: DC21030 [TGA] detected, rev=0x%02x\n",
1518 pr_info("tgafb: at PCI bus %d, device %d, function %d\n",
1519 to_pci_dev(dev)->bus->number,
1520 PCI_SLOT(to_pci_dev(dev)->devfn),
1521 PCI_FUNC(to_pci_dev(dev)->devfn));
1524 pr_info("tgafb: SFB+ detected, rev=0x%02x\n",
1526 fb_info(info, "%s frame buffer device at 0x%lx\n",
1527 info->fix.id, (long)bar0_start);
1532 fb_dealloc_cmap(&info->cmap);
1536 release_mem_region(bar0_start, bar0_len);
1538 framebuffer_release(info);
1542 static void tgafb_unregister(struct device *dev)
1544 resource_size_t bar0_start = 0, bar0_len = 0;
1545 int tga_bus_pci = dev_is_pci(dev);
1546 int tga_bus_tc = TGA_BUS_TC(dev);
1547 struct fb_info *info = NULL;
1548 struct tga_par *par;
1550 info = dev_get_drvdata(dev);
1555 unregister_framebuffer(info);
1556 fb_dealloc_cmap(&info->cmap);
1557 iounmap(par->tga_mem_base);
1559 bar0_start = pci_resource_start(to_pci_dev(dev), 0);
1560 bar0_len = pci_resource_len(to_pci_dev(dev), 0);
1563 bar0_start = to_tc_dev(dev)->resource.start;
1564 bar0_len = to_tc_dev(dev)->resource.end - bar0_start + 1;
1566 release_mem_region(bar0_start, bar0_len);
1567 framebuffer_release(info);
1570 static void tgafb_exit(void)
1572 tc_unregister_driver(&tgafb_tc_driver);
1573 pci_unregister_driver(&tgafb_pci_driver);
1577 static int tgafb_setup(char *arg)
1582 while ((this_opt = strsep(&arg, ","))) {
1585 if (!strncmp(this_opt, "mode:", 5))
1586 mode_option = this_opt+5;
1589 "tgafb: unknown parameter %s\n",
1596 #endif /* !MODULE */
1598 static int tgafb_init(void)
1602 char *option = NULL;
1605 if (fb_modesetting_disabled("tgafb"))
1609 if (fb_get_options("tgafb", &option))
1611 tgafb_setup(option);
1613 status = pci_register_driver(&tgafb_pci_driver);
1615 status = tc_register_driver(&tgafb_tc_driver);
1623 module_init(tgafb_init);
1624 module_exit(tgafb_exit);
1626 MODULE_DESCRIPTION("Framebuffer driver for TGA/SFB+ chipset");
1627 MODULE_LICENSE("GPL");