drivers/video/fbdev/s3c2410fb.c

   1 /* linux/drivers/video/s3c2410fb.c
   2  *      Copyright (c) 2004,2005 Arnaud Patard
   3  *      Copyright (c) 2004-2008 Ben Dooks
   4  *
   5  * S3C2410 LCD Framebuffer Driver
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file COPYING in the main directory of this archive for
   9  * more details.
  10  *
  11  * Driver based on skeletonfb.c, sa1100fb.c and others.
  12 */
  13
  14 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  15
  16 #include <linux/module.h>
  17 #include <linux/kernel.h>
  18 #include <linux/err.h>
  19 #include <linux/errno.h>
  20 #include <linux/string.h>
  21 #include <linux/mm.h>
  22 #include <linux/slab.h>
  23 #include <linux/delay.h>
  24 #include <linux/fb.h>
  25 #include <linux/init.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/clk.h>
  30 #include <linux/cpufreq.h>
  31 #include <linux/io.h>
  32
  33 #include <asm/div64.h>
  34
  35 #include <asm/mach/map.h>
  36 #include <mach/regs-lcd.h>
  37 #include <mach/regs-gpio.h>
  38 #include <mach/fb.h>
  39
  40 #ifdef CONFIG_PM
  41 #include <linux/pm.h>
  42 #endif
  43
  44 #include "s3c2410fb.h"
  45
  46 /* Debugging stuff */
  47 static int debug = IS_BUILTIN(CONFIG_FB_S3C2410_DEBUG);
  48
  49 #define dprintk(msg...) \
  50 do { \
  51         if (debug) \
  52                 pr_debug(msg); \
  53 } while (0)
  54
  55 /* useful functions */
  56
  57 static int is_s3c2412(struct s3c2410fb_info *fbi)
  58 {
  59         return (fbi->drv_type == DRV_S3C2412);
  60 }
  61
  62 /* s3c2410fb_set_lcdaddr
  63  *
  64  * initialise lcd controller address pointers
  65  */
  66 static void s3c2410fb_set_lcdaddr(struct fb_info *info)
  67 {
  68         unsigned long saddr1, saddr2, saddr3;
  69         struct s3c2410fb_info *fbi = info->par;
  70         void __iomem *regs = fbi->io;
  71
  72         saddr1  = info->fix.smem_start >> 1;
  73         saddr2  = info->fix.smem_start;
  74         saddr2 += info->fix.line_length * info->var.yres;
  75         saddr2 >>= 1;
  76
  77         saddr3 = S3C2410_OFFSIZE(0) |
  78                  S3C2410_PAGEWIDTH((info->fix.line_length / 2) & 0x3ff);
  79
  80         dprintk("LCDSADDR1 = 0x%08lx\n", saddr1);
  81         dprintk("LCDSADDR2 = 0x%08lx\n", saddr2);
  82         dprintk("LCDSADDR3 = 0x%08lx\n", saddr3);
  83
  84         writel(saddr1, regs + S3C2410_LCDSADDR1);
  85         writel(saddr2, regs + S3C2410_LCDSADDR2);
  86         writel(saddr3, regs + S3C2410_LCDSADDR3);
  87 }
  88
  89 /* s3c2410fb_calc_pixclk()
  90  *
  91  * calculate divisor for clk->pixclk
  92  */
  93 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
  94                                           unsigned long pixclk)
  95 {
  96         unsigned long clk = fbi->clk_rate;
  97         unsigned long long div;
  98
  99         /* pixclk is in picoseconds, our clock is in Hz
 100          *
 101          * Hz -> picoseconds is / 10^-12
 102          */
 103
 104         div = (unsigned long long)clk * pixclk;
 105         div >>= 12;                     /* div / 2^12 */
 106         do_div(div, 625 * 625UL * 625); /* div / 5^12 */
 107
 108         dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);
 109         return div;
 110 }
 111
 112 /*
 113  *      s3c2410fb_check_var():
 114  *      Get the video params out of 'var'. If a value doesn't fit, round it up,
 115  *      if it's too big, return -EINVAL.
 116  *
 117  */
 118 static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
 119                                struct fb_info *info)
 120 {
 121         struct s3c2410fb_info *fbi = info->par;
 122         struct s3c2410fb_mach_info *mach_info = dev_get_platdata(fbi->dev);
 123         struct s3c2410fb_display *display = NULL;
 124         struct s3c2410fb_display *default_display = mach_info->displays +
 125                                                     mach_info->default_display;
 126         int type = default_display->type;
 127         unsigned i;
 128
 129         dprintk("check_var(var=%p, info=%p)\n", var, info);
 130
 131         /* validate x/y resolution */
 132         /* choose default mode if possible */
 133         if (var->yres == default_display->yres &&
 134             var->xres == default_display->xres &&
 135             var->bits_per_pixel == default_display->bpp)
 136                 display = default_display;
 137         else
 138                 for (i = 0; i < mach_info->num_displays; i++)
 139                         if (type == mach_info->displays[i].type &&
 140                             var->yres == mach_info->displays[i].yres &&
 141                             var->xres == mach_info->displays[i].xres &&
 142                             var->bits_per_pixel == mach_info->displays[i].bpp) {
 143                                 display = mach_info->displays + i;
 144                                 break;
 145                         }
 146
 147         if (!display) {
 148                 dprintk("wrong resolution or depth %dx%d at %d bpp\n",
 149                         var->xres, var->yres, var->bits_per_pixel);
 150                 return -EINVAL;
 151         }
 152
 153         /* it is always the size as the display */
 154         var->xres_virtual = display->xres;
 155         var->yres_virtual = display->yres;
 156         var->height = display->height;
 157         var->width = display->width;
 158
 159         /* copy lcd settings */
 160         var->pixclock = display->pixclock;
 161         var->left_margin = display->left_margin;
 162         var->right_margin = display->right_margin;
 163         var->upper_margin = display->upper_margin;
 164         var->lower_margin = display->lower_margin;
 165         var->vsync_len = display->vsync_len;
 166         var->hsync_len = display->hsync_len;
 167
 168         fbi->regs.lcdcon5 = display->lcdcon5;
 169         /* set display type */
 170         fbi->regs.lcdcon1 = display->type;
 171
 172         var->transp.offset = 0;
 173         var->transp.length = 0;
 174         /* set r/g/b positions */
 175         switch (var->bits_per_pixel) {
 176         case 1:
 177         case 2:
 178         case 4:
 179                 var->red.offset = 0;
 180                 var->red.length = var->bits_per_pixel;
 181                 var->green      = var->red;
 182                 var->blue       = var->red;
 183                 break;
 184         case 8:
 185                 if (display->type != S3C2410_LCDCON1_TFT) {
 186                         /* 8 bpp 332 */
 187                         var->red.length         = 3;
 188                         var->red.offset         = 5;
 189                         var->green.length       = 3;
 190                         var->green.offset       = 2;
 191                         var->blue.length        = 2;
 192                         var->blue.offset        = 0;
 193                 } else {
 194                         var->red.offset         = 0;
 195                         var->red.length         = 8;
 196                         var->green              = var->red;
 197                         var->blue               = var->red;
 198                 }
 199                 break;
 200         case 12:
 201                 /* 12 bpp 444 */
 202                 var->red.length         = 4;
 203                 var->red.offset         = 8;
 204                 var->green.length       = 4;
 205                 var->green.offset       = 4;
 206                 var->blue.length        = 4;
 207                 var->blue.offset        = 0;
 208                 break;
 209
 210         default:
 211         case 16:
 212                 if (display->lcdcon5 & S3C2410_LCDCON5_FRM565) {
 213                         /* 16 bpp, 565 format */
 214                         var->red.offset         = 11;
 215                         var->green.offset       = 5;
 216                         var->blue.offset        = 0;
 217                         var->red.length         = 5;
 218                         var->green.length       = 6;
 219                         var->blue.length        = 5;
 220                 } else {
 221                         /* 16 bpp, 5551 format */
 222                         var->red.offset         = 11;
 223                         var->green.offset       = 6;
 224                         var->blue.offset        = 1;
 225                         var->red.length         = 5;
 226                         var->green.length       = 5;
 227                         var->blue.length        = 5;
 228                 }
 229                 break;
 230         case 32:
 231                 /* 24 bpp 888 and 8 dummy */
 232                 var->red.length         = 8;
 233                 var->red.offset         = 16;
 234                 var->green.length       = 8;
 235                 var->green.offset       = 8;
 236                 var->blue.length        = 8;
 237                 var->blue.offset        = 0;
 238                 break;
 239         }
 240         return 0;
 241 }
 242
 243 /* s3c2410fb_calculate_stn_lcd_regs
 244  *
 245  * calculate register values from var settings
 246  */
 247 static void s3c2410fb_calculate_stn_lcd_regs(const struct fb_info *info,
 248                                              struct s3c2410fb_hw *regs)
 249 {
 250         const struct s3c2410fb_info *fbi = info->par;
 251         const struct fb_var_screeninfo *var = &info->var;
 252         int type = regs->lcdcon1 & ~S3C2410_LCDCON1_TFT;
 253         int hs = var->xres >> 2;
 254         unsigned wdly = (var->left_margin >> 4) - 1;
 255         unsigned wlh = (var->hsync_len >> 4) - 1;
 256
 257         if (type != S3C2410_LCDCON1_STN4)
 258                 hs >>= 1;
 259
 260         switch (var->bits_per_pixel) {
 261         case 1:
 262                 regs->lcdcon1 |= S3C2410_LCDCON1_STN1BPP;
 263                 break;
 264         case 2:
 265                 regs->lcdcon1 |= S3C2410_LCDCON1_STN2GREY;
 266                 break;
 267         case 4:
 268                 regs->lcdcon1 |= S3C2410_LCDCON1_STN4GREY;
 269                 break;
 270         case 8:
 271                 regs->lcdcon1 |= S3C2410_LCDCON1_STN8BPP;
 272                 hs *= 3;
 273                 break;
 274         case 12:
 275                 regs->lcdcon1 |= S3C2410_LCDCON1_STN12BPP;
 276                 hs *= 3;
 277                 break;
 278
 279         default:
 280                 /* invalid pixel depth */
 281                 dev_err(fbi->dev, "invalid bpp %d\n",
 282                         var->bits_per_pixel);
 283         }
 284         /* update X/Y info */
 285         dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 286                 var->left_margin, var->right_margin, var->hsync_len);
 287
 288         regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1);
 289
 290         if (wdly > 3)
 291                 wdly = 3;
 292
 293         if (wlh > 3)
 294                 wlh = 3;
 295
 296         regs->lcdcon3 = S3C2410_LCDCON3_WDLY(wdly) |
 297                         S3C2410_LCDCON3_LINEBLANK(var->right_margin / 8) |
 298                         S3C2410_LCDCON3_HOZVAL(hs - 1);
 299
 300         regs->lcdcon4 = S3C2410_LCDCON4_WLH(wlh);
 301 }
 302
 303 /* s3c2410fb_calculate_tft_lcd_regs
 304  *
 305  * calculate register values from var settings
 306  */
 307 static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info *info,
 308                                              struct s3c2410fb_hw *regs)
 309 {
 310         const struct s3c2410fb_info *fbi = info->par;
 311         const struct fb_var_screeninfo *var = &info->var;
 312
 313         switch (var->bits_per_pixel) {
 314         case 1:
 315                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
 316                 break;
 317         case 2:
 318                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT2BPP;
 319                 break;
 320         case 4:
 321                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT4BPP;
 322                 break;
 323         case 8:
 324                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
 325                 regs->lcdcon5 |= S3C2410_LCDCON5_BSWP |
 326                                  S3C2410_LCDCON5_FRM565;
 327                 regs->lcdcon5 &= ~S3C2410_LCDCON5_HWSWP;
 328                 break;
 329         case 16:
 330                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
 331                 regs->lcdcon5 &= ~S3C2410_LCDCON5_BSWP;
 332                 regs->lcdcon5 |= S3C2410_LCDCON5_HWSWP;
 333                 break;
 334         case 32:
 335                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT24BPP;
 336                 regs->lcdcon5 &= ~(S3C2410_LCDCON5_BSWP |
 337                                    S3C2410_LCDCON5_HWSWP |
 338                                    S3C2410_LCDCON5_BPP24BL);
 339                 break;
 340         default:
 341                 /* invalid pixel depth */
 342                 dev_err(fbi->dev, "invalid bpp %d\n",
 343                         var->bits_per_pixel);
 344         }
 345         /* update X/Y info */
 346         dprintk("setting vert: up=%d, low=%d, sync=%d\n",
 347                 var->upper_margin, var->lower_margin, var->vsync_len);
 348
 349         dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 350                 var->left_margin, var->right_margin, var->hsync_len);
 351
 352         regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1) |
 353                         S3C2410_LCDCON2_VBPD(var->upper_margin - 1) |
 354                         S3C2410_LCDCON2_VFPD(var->lower_margin - 1) |
 355                         S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
 356
 357         regs->lcdcon3 = S3C2410_LCDCON3_HBPD(var->right_margin - 1) |
 358                         S3C2410_LCDCON3_HFPD(var->left_margin - 1) |
 359                         S3C2410_LCDCON3_HOZVAL(var->xres - 1);
 360
 361         regs->lcdcon4 = S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
 362 }
 363
 364 /* s3c2410fb_activate_var
 365  *
 366  * activate (set) the controller from the given framebuffer
 367  * information
 368  */
 369 static void s3c2410fb_activate_var(struct fb_info *info)
 370 {
 371         struct s3c2410fb_info *fbi = info->par;
 372         void __iomem *regs = fbi->io;
 373         int type = fbi->regs.lcdcon1 & S3C2410_LCDCON1_TFT;
 374         struct fb_var_screeninfo *var = &info->var;
 375         int clkdiv;
 376
 377         clkdiv = DIV_ROUND_UP(s3c2410fb_calc_pixclk(fbi, var->pixclock), 2);
 378
 379         dprintk("%s: var->xres  = %d\n", __func__, var->xres);
 380         dprintk("%s: var->yres  = %d\n", __func__, var->yres);
 381         dprintk("%s: var->bpp   = %d\n", __func__, var->bits_per_pixel);
 382
 383         if (type == S3C2410_LCDCON1_TFT) {
 384                 s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs);
 385                 --clkdiv;
 386                 if (clkdiv < 0)
 387                         clkdiv = 0;
 388         } else {
 389                 s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs);
 390                 if (clkdiv < 2)
 391                         clkdiv = 2;
 392         }
 393
 394         fbi->regs.lcdcon1 |=  S3C2410_LCDCON1_CLKVAL(clkdiv);
 395
 396         /* write new registers */
 397
 398         dprintk("new register set:\n");
 399         dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
 400         dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
 401         dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
 402         dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
 403         dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
 404
 405         writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID,
 406                 regs + S3C2410_LCDCON1);
 407         writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2);
 408         writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3);
 409         writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4);
 410         writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5);
 411
 412         /* set lcd address pointers */
 413         s3c2410fb_set_lcdaddr(info);
 414
 415         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID,
 416         writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
 417 }
 418
 419 /*
 420  *      s3c2410fb_set_par - Alters the hardware state.
 421  *      @info: frame buffer structure that represents a single frame buffer
 422  *
 423  */
 424 static int s3c2410fb_set_par(struct fb_info *info)
 425 {
 426         struct fb_var_screeninfo *var = &info->var;
 427
 428         switch (var->bits_per_pixel) {
 429         case 32:
 430         case 16:
 431         case 12:
 432                 info->fix.visual = FB_VISUAL_TRUECOLOR;
 433                 break;
 434         case 1:
 435                 info->fix.visual = FB_VISUAL_MONO01;
 436                 break;
 437         default:
 438                 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 439                 break;
 440         }
 441
 442         info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
 443
 444         /* activate this new configuration */
 445
 446         s3c2410fb_activate_var(info);
 447         return 0;
 448 }
 449
 450 static void schedule_palette_update(struct s3c2410fb_info *fbi,
 451                                     unsigned int regno, unsigned int val)
 452 {
 453         unsigned long flags;
 454         unsigned long irqen;
 455         void __iomem *irq_base = fbi->irq_base;
 456
 457         local_irq_save(flags);
 458
 459         fbi->palette_buffer[regno] = val;
 460
 461         if (!fbi->palette_ready) {
 462                 fbi->palette_ready = 1;
 463
 464                 /* enable IRQ */
 465                 irqen = readl(irq_base + S3C24XX_LCDINTMSK);
 466                 irqen &= ~S3C2410_LCDINT_FRSYNC;
 467                 writel(irqen, irq_base + S3C24XX_LCDINTMSK);
 468         }
 469
 470         local_irq_restore(flags);
 471 }
 472
 473 /* from pxafb.c */
 474 static inline unsigned int chan_to_field(unsigned int chan,
 475                                          struct fb_bitfield *bf)
 476 {
 477         chan &= 0xffff;
 478         chan >>= 16 - bf->length;
 479         return chan << bf->offset;
 480 }
 481
 482 static int s3c2410fb_setcolreg(unsigned regno,
 483                                unsigned red, unsigned green, unsigned blue,
 484                                unsigned transp, struct fb_info *info)
 485 {
 486         struct s3c2410fb_info *fbi = info->par;
 487         void __iomem *regs = fbi->io;
 488         unsigned int val;
 489
 490         /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n",
 491                    regno, red, green, blue); */
 492
 493         switch (info->fix.visual) {
 494         case FB_VISUAL_TRUECOLOR:
 495                 /* true-colour, use pseudo-palette */
 496
 497                 if (regno < 16) {
 498                         u32 *pal = info->pseudo_palette;
 499
 500                         val  = chan_to_field(red,   &info->var.red);
 501                         val |= chan_to_field(green, &info->var.green);
 502                         val |= chan_to_field(blue,  &info->var.blue);
 503
 504                         pal[regno] = val;
 505                 }
 506                 break;
 507
 508         case FB_VISUAL_PSEUDOCOLOR:
 509                 if (regno < 256) {
 510                         /* currently assume RGB 5-6-5 mode */
 511
 512                         val  = (red   >>  0) & 0xf800;
 513                         val |= (green >>  5) & 0x07e0;
 514                         val |= (blue  >> 11) & 0x001f;
 515
 516                         writel(val, regs + S3C2410_TFTPAL(regno));
 517                         schedule_palette_update(fbi, regno, val);
 518                 }
 519
 520                 break;
 521
 522         default:
 523                 return 1;       /* unknown type */
 524         }
 525
 526         return 0;
 527 }
 528
 529 /* s3c2410fb_lcd_enable
 530  *
 531  * shutdown the lcd controller
 532  */
 533 static void s3c2410fb_lcd_enable(struct s3c2410fb_info *fbi, int enable)
 534 {
 535         unsigned long flags;
 536
 537         local_irq_save(flags);
 538
 539         if (enable)
 540                 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID;
 541         else
 542                 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
 543
 544         writel(fbi->regs.lcdcon1, fbi->io + S3C2410_LCDCON1);
 545
 546         local_irq_restore(flags);
 547 }
 548
 549
 550 /*
 551  *      s3c2410fb_blank
 552  *      @blank_mode: the blank mode we want.
 553  *      @info: frame buffer structure that represents a single frame buffer
 554  *
 555  *      Blank the screen if blank_mode != 0, else unblank. Return 0 if
 556  *      blanking succeeded, != 0 if un-/blanking failed due to e.g. a
 557  *      video mode which doesn't support it. Implements VESA suspend
 558  *      and powerdown modes on hardware that supports disabling hsync/vsync:
 559  *
 560  *      Returns negative errno on error, or zero on success.
 561  *
 562  */
 563 static int s3c2410fb_blank(int blank_mode, struct fb_info *info)
 564 {
 565         struct s3c2410fb_info *fbi = info->par;
 566         void __iomem *tpal_reg = fbi->io;
 567
 568         dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
 569
 570         tpal_reg += is_s3c2412(fbi) ? S3C2412_TPAL : S3C2410_TPAL;
 571
 572         if (blank_mode == FB_BLANK_POWERDOWN)
 573                 s3c2410fb_lcd_enable(fbi, 0);
 574         else
 575                 s3c2410fb_lcd_enable(fbi, 1);
 576
 577         if (blank_mode == FB_BLANK_UNBLANK)
 578                 writel(0x0, tpal_reg);
 579         else {
 580                 dprintk("setting TPAL to output 0x000000\n");
 581                 writel(S3C2410_TPAL_EN, tpal_reg);
 582         }
 583
 584         return 0;
 585 }
 586
 587 static int s3c2410fb_debug_show(struct device *dev,
 588                                 struct device_attribute *attr, char *buf)
 589 {
 590         return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off");
 591 }
 592
 593 static int s3c2410fb_debug_store(struct device *dev,
 594                                  struct device_attribute *attr,
 595                                  const char *buf, size_t len)
 596 {
 597         if (len < 1)
 598                 return -EINVAL;
 599
 600         if (strncasecmp(buf, "on", 2) == 0 ||
 601             strncasecmp(buf, "1", 1) == 0) {
 602                 debug = 1;
 603                 dev_dbg(dev, "s3c2410fb: Debug On");
 604         } else if (strncasecmp(buf, "off", 3) == 0 ||
 605                    strncasecmp(buf, "0", 1) == 0) {
 606                 debug = 0;
 607                 dev_dbg(dev, "s3c2410fb: Debug Off");
 608         } else {
 609                 return -EINVAL;
 610         }
 611
 612         return len;
 613 }
 614
 615 static DEVICE_ATTR(debug, 0664, s3c2410fb_debug_show, s3c2410fb_debug_store);
 616
 617 static const struct fb_ops s3c2410fb_ops = {
 618         .owner          = THIS_MODULE,
 619         .fb_check_var   = s3c2410fb_check_var,
 620         .fb_set_par     = s3c2410fb_set_par,
 621         .fb_blank       = s3c2410fb_blank,
 622         .fb_setcolreg   = s3c2410fb_setcolreg,
 623         .fb_fillrect    = cfb_fillrect,
 624         .fb_copyarea    = cfb_copyarea,
 625         .fb_imageblit   = cfb_imageblit,
 626 };
 627
 628 /*
 629  * s3c2410fb_map_video_memory():
 630  *      Allocates the DRAM memory for the frame buffer.  This buffer is
 631  *      remapped into a non-cached, non-buffered, memory region to
 632  *      allow palette and pixel writes to occur without flushing the
 633  *      cache.  Once this area is remapped, all virtual memory
 634  *      access to the video memory should occur at the new region.
 635  */
 636 static int s3c2410fb_map_video_memory(struct fb_info *info)
 637 {
 638         struct s3c2410fb_info *fbi = info->par;
 639         dma_addr_t map_dma;
 640         unsigned map_size = PAGE_ALIGN(info->fix.smem_len);
 641
 642         dprintk("map_video_memory(fbi=%p) map_size %u\n", fbi, map_size);
 643
 644         info->screen_base = dma_alloc_wc(fbi->dev, map_size, &map_dma,
 645                                          GFP_KERNEL);
 646
 647         if (info->screen_base) {
 648                 /* prevent initial garbage on screen */
 649                 dprintk("map_video_memory: clear %p:%08x\n",
 650                         info->screen_base, map_size);
 651                 memset(info->screen_base, 0x00, map_size);
 652
 653                 info->fix.smem_start = map_dma;
 654
 655                 dprintk("map_video_memory: dma=%08lx cpu=%p size=%08x\n",
 656                         info->fix.smem_start, info->screen_base, map_size);
 657         }
 658
 659         return info->screen_base ? 0 : -ENOMEM;
 660 }
 661
 662 static inline void s3c2410fb_unmap_video_memory(struct fb_info *info)
 663 {
 664         struct s3c2410fb_info *fbi = info->par;
 665
 666         dma_free_wc(fbi->dev, PAGE_ALIGN(info->fix.smem_len),
 667                     info->screen_base, info->fix.smem_start);
 668 }
 669
 670 static inline void modify_gpio(void __iomem *reg,
 671                                unsigned long set, unsigned long mask)
 672 {
 673         unsigned long tmp;
 674
 675         tmp = readl(reg) & ~mask;
 676         writel(tmp | set, reg);
 677 }
 678
 679 /*
 680  * s3c2410fb_init_registers - Initialise all LCD-related registers
 681  */
 682 static int s3c2410fb_init_registers(struct fb_info *info)
 683 {
 684         struct s3c2410fb_info *fbi = info->par;
 685         struct s3c2410fb_mach_info *mach_info = dev_get_platdata(fbi->dev);
 686         unsigned long flags;
 687         void __iomem *regs = fbi->io;
 688         void __iomem *tpal;
 689         void __iomem *lpcsel;
 690
 691         if (is_s3c2412(fbi)) {
 692                 tpal = regs + S3C2412_TPAL;
 693                 lpcsel = regs + S3C2412_TCONSEL;
 694         } else {
 695                 tpal = regs + S3C2410_TPAL;
 696                 lpcsel = regs + S3C2410_LPCSEL;
 697         }
 698
 699         /* Initialise LCD with values from haret */
 700
 701         local_irq_save(flags);
 702
 703         /* modify the gpio(s) with interrupts set (bjd) */
 704
 705         modify_gpio(S3C2410_GPCUP,  mach_info->gpcup,  mach_info->gpcup_mask);
 706         modify_gpio(S3C2410_GPCCON, mach_info->gpccon, mach_info->gpccon_mask);
 707         modify_gpio(S3C2410_GPDUP,  mach_info->gpdup,  mach_info->gpdup_mask);
 708         modify_gpio(S3C2410_GPDCON, mach_info->gpdcon, mach_info->gpdcon_mask);
 709
 710         local_irq_restore(flags);
 711
 712         dprintk("LPCSEL    = 0x%08lx\n", mach_info->lpcsel);
 713         writel(mach_info->lpcsel, lpcsel);
 714
 715         dprintk("replacing TPAL %08x\n", readl(tpal));
 716
 717         /* ensure temporary palette disabled */
 718         writel(0x00, tpal);
 719
 720         return 0;
 721 }
 722
 723 static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi)
 724 {
 725         unsigned int i;
 726         void __iomem *regs = fbi->io;
 727
 728         fbi->palette_ready = 0;
 729
 730         for (i = 0; i < 256; i++) {
 731                 unsigned long ent = fbi->palette_buffer[i];
 732                 if (ent == PALETTE_BUFF_CLEAR)
 733                         continue;
 734
 735                 writel(ent, regs + S3C2410_TFTPAL(i));
 736
 737                 /* it seems the only way to know exactly
 738                  * if the palette wrote ok, is to check
 739                  * to see if the value verifies ok
 740                  */
 741
 742                 if (readw(regs + S3C2410_TFTPAL(i)) == ent)
 743                         fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 744                 else
 745                         fbi->palette_ready = 1;   /* retry */
 746         }
 747 }
 748
 749 static irqreturn_t s3c2410fb_irq(int irq, void *dev_id)
 750 {
 751         struct s3c2410fb_info *fbi = dev_id;
 752         void __iomem *irq_base = fbi->irq_base;
 753         unsigned long lcdirq = readl(irq_base + S3C24XX_LCDINTPND);
 754
 755         if (lcdirq & S3C2410_LCDINT_FRSYNC) {
 756                 if (fbi->palette_ready)
 757                         s3c2410fb_write_palette(fbi);
 758
 759                 writel(S3C2410_LCDINT_FRSYNC, irq_base + S3C24XX_LCDINTPND);
 760                 writel(S3C2410_LCDINT_FRSYNC, irq_base + S3C24XX_LCDSRCPND);
 761         }
 762
 763         return IRQ_HANDLED;
 764 }
 765
 766 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
 767
 768 static int s3c2410fb_cpufreq_transition(struct notifier_block *nb,
 769                                         unsigned long val, void *data)
 770 {
 771         struct s3c2410fb_info *info;
 772         struct fb_info *fbinfo;
 773         long delta_f;
 774
 775         info = container_of(nb, struct s3c2410fb_info, freq_transition);
 776         fbinfo = dev_get_drvdata(info->dev);
 777
 778         /* work out change, <0 for speed-up */
 779         delta_f = info->clk_rate - clk_get_rate(info->clk);
 780
 781         if ((val == CPUFREQ_POSTCHANGE && delta_f > 0) ||
 782             (val == CPUFREQ_PRECHANGE && delta_f < 0)) {
 783                 info->clk_rate = clk_get_rate(info->clk);
 784                 s3c2410fb_activate_var(fbinfo);
 785         }
 786
 787         return 0;
 788 }
 789
 790 static inline int s3c2410fb_cpufreq_register(struct s3c2410fb_info *info)
 791 {
 792         info->freq_transition.notifier_call = s3c2410fb_cpufreq_transition;
 793
 794         return cpufreq_register_notifier(&info->freq_transition,
 795                                          CPUFREQ_TRANSITION_NOTIFIER);
 796 }
 797
 798 static inline void s3c2410fb_cpufreq_deregister(struct s3c2410fb_info *info)
 799 {
 800         cpufreq_unregister_notifier(&info->freq_transition,
 801                                     CPUFREQ_TRANSITION_NOTIFIER);
 802 }
 803
 804 #else
 805 static inline int s3c2410fb_cpufreq_register(struct s3c2410fb_info *info)
 806 {
 807         return 0;
 808 }
 809
 810 static inline void s3c2410fb_cpufreq_deregister(struct s3c2410fb_info *info)
 811 {
 812 }
 813 #endif
 814
 815
 816 static const char driver_name[] = "s3c2410fb";
 817
 818 static int s3c24xxfb_probe(struct platform_device *pdev,
 819                            enum s3c_drv_type drv_type)
 820 {
 821         struct s3c2410fb_info *info;
 822         struct s3c2410fb_display *display;
 823         struct fb_info *fbinfo;
 824         struct s3c2410fb_mach_info *mach_info;
 825         struct resource *res;
 826         int ret;
 827         int irq;
 828         int i;
 829         int size;
 830         u32 lcdcon1;
 831
 832         mach_info = dev_get_platdata(&pdev->dev);
 833         if (mach_info == NULL) {
 834                 dev_err(&pdev->dev,
 835                         "no platform data for lcd, cannot attach\n");
 836                 return -EINVAL;
 837         }
 838
 839         if (mach_info->default_display >= mach_info->num_displays) {
 840                 dev_err(&pdev->dev, "default is %d but only %d displays\n",
 841                         mach_info->default_display, mach_info->num_displays);
 842                 return -EINVAL;
 843         }
 844
 845         display = mach_info->displays + mach_info->default_display;
 846
 847         irq = platform_get_irq(pdev, 0);
 848         if (irq < 0) {
 849                 dev_err(&pdev->dev, "no irq for device\n");
 850                 return -ENOENT;
 851         }
 852
 853         fbinfo = framebuffer_alloc(sizeof(struct s3c2410fb_info), &pdev->dev);
 854         if (!fbinfo)
 855                 return -ENOMEM;
 856
 857         platform_set_drvdata(pdev, fbinfo);
 858
 859         info = fbinfo->par;
 860         info->dev = &pdev->dev;
 861         info->drv_type = drv_type;
 862
 863         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 864         if (res == NULL) {
 865                 dev_err(&pdev->dev, "failed to get memory registers\n");
 866                 ret = -ENXIO;
 867                 goto dealloc_fb;
 868         }
 869
 870         size = resource_size(res);
 871         info->mem = request_mem_region(res->start, size, pdev->name);
 872         if (info->mem == NULL) {
 873                 dev_err(&pdev->dev, "failed to get memory region\n");
 874                 ret = -ENOENT;
 875                 goto dealloc_fb;
 876         }
 877
 878         info->io = ioremap(res->start, size);
 879         if (info->io == NULL) {
 880                 dev_err(&pdev->dev, "ioremap() of registers failed\n");
 881                 ret = -ENXIO;
 882                 goto release_mem;
 883         }
 884
 885         if (drv_type == DRV_S3C2412)
 886                 info->irq_base = info->io + S3C2412_LCDINTBASE;
 887         else
 888                 info->irq_base = info->io + S3C2410_LCDINTBASE;
 889
 890         dprintk("devinit\n");
 891
 892         strcpy(fbinfo->fix.id, driver_name);
 893
 894         /* Stop the video */
 895         lcdcon1 = readl(info->io + S3C2410_LCDCON1);
 896         writel(lcdcon1 & ~S3C2410_LCDCON1_ENVID, info->io + S3C2410_LCDCON1);
 897
 898         fbinfo->fix.type            = FB_TYPE_PACKED_PIXELS;
 899         fbinfo->fix.type_aux        = 0;
 900         fbinfo->fix.xpanstep        = 0;
 901         fbinfo->fix.ypanstep        = 0;
 902         fbinfo->fix.ywrapstep       = 0;
 903         fbinfo->fix.accel           = FB_ACCEL_NONE;
 904
 905         fbinfo->var.nonstd          = 0;
 906         fbinfo->var.activate        = FB_ACTIVATE_NOW;
 907         fbinfo->var.accel_flags     = 0;
 908         fbinfo->var.vmode           = FB_VMODE_NONINTERLACED;
 909
 910         fbinfo->fbops               = &s3c2410fb_ops;
 911         fbinfo->flags               = FBINFO_FLAG_DEFAULT;
 912         fbinfo->pseudo_palette      = &info->pseudo_pal;
 913
 914         for (i = 0; i < 256; i++)
 915                 info->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 916
 917         ret = request_irq(irq, s3c2410fb_irq, 0, pdev->name, info);
 918         if (ret) {
 919                 dev_err(&pdev->dev, "cannot get irq %d - err %d\n", irq, ret);
 920                 ret = -EBUSY;
 921                 goto release_regs;
 922         }
 923
 924         info->clk = clk_get(NULL, "lcd");
 925         if (IS_ERR(info->clk)) {
 926                 dev_err(&pdev->dev, "failed to get lcd clock source\n");
 927                 ret = PTR_ERR(info->clk);
 928                 goto release_irq;
 929         }
 930
 931         clk_prepare_enable(info->clk);
 932         dprintk("got and enabled clock\n");
 933
 934         usleep_range(1000, 1100);
 935
 936         info->clk_rate = clk_get_rate(info->clk);
 937
 938         /* find maximum required memory size for display */
 939         for (i = 0; i < mach_info->num_displays; i++) {
 940                 unsigned long smem_len = mach_info->displays[i].xres;
 941
 942                 smem_len *= mach_info->displays[i].yres;
 943                 smem_len *= mach_info->displays[i].bpp;
 944                 smem_len >>= 3;
 945                 if (fbinfo->fix.smem_len < smem_len)
 946                         fbinfo->fix.smem_len = smem_len;
 947         }
 948
 949         /* Initialize video memory */
 950         ret = s3c2410fb_map_video_memory(fbinfo);
 951         if (ret) {
 952                 dev_err(&pdev->dev, "Failed to allocate video RAM: %d\n", ret);
 953                 ret = -ENOMEM;
 954                 goto release_clock;
 955         }
 956
 957         dprintk("got video memory\n");
 958
 959         fbinfo->var.xres = display->xres;
 960         fbinfo->var.yres = display->yres;
 961         fbinfo->var.bits_per_pixel = display->bpp;
 962
 963         s3c2410fb_init_registers(fbinfo);
 964
 965         s3c2410fb_check_var(&fbinfo->var, fbinfo);
 966
 967         ret = s3c2410fb_cpufreq_register(info);
 968         if (ret < 0) {
 969                 dev_err(&pdev->dev, "Failed to register cpufreq\n");
 970                 goto free_video_memory;
 971         }
 972
 973         ret = register_framebuffer(fbinfo);
 974         if (ret < 0) {
 975                 dev_err(&pdev->dev, "Failed to register framebuffer device: %d\n",
 976                         ret);
 977                 goto free_cpufreq;
 978         }
 979
 980         /* create device files */
 981         ret = device_create_file(&pdev->dev, &dev_attr_debug);
 982         if (ret)
 983                 dev_err(&pdev->dev, "failed to add debug attribute\n");
 984
 985         dev_info(&pdev->dev, "fb%d: %s frame buffer device\n",
 986                 fbinfo->node, fbinfo->fix.id);
 987
 988         return 0;
 989
 990  free_cpufreq:
 991         s3c2410fb_cpufreq_deregister(info);
 992 free_video_memory:
 993         s3c2410fb_unmap_video_memory(fbinfo);
 994 release_clock:
 995         clk_disable_unprepare(info->clk);
 996         clk_put(info->clk);
 997 release_irq:
 998         free_irq(irq, info);
 999 release_regs:
1000         iounmap(info->io);
1001 release_mem:
1002         release_mem_region(res->start, size);
1003 dealloc_fb:
1004         framebuffer_release(fbinfo);
1005         return ret;
1006 }
1007
1008 static int s3c2410fb_probe(struct platform_device *pdev)
1009 {
1010         return s3c24xxfb_probe(pdev, DRV_S3C2410);
1011 }
1012
1013 static int s3c2412fb_probe(struct platform_device *pdev)
1014 {
1015         return s3c24xxfb_probe(pdev, DRV_S3C2412);
1016 }
1017
1018
1019 /*
1020  *  Cleanup
1021  */
1022 static int s3c2410fb_remove(struct platform_device *pdev)
1023 {
1024         struct fb_info *fbinfo = platform_get_drvdata(pdev);
1025         struct s3c2410fb_info *info = fbinfo->par;
1026         int irq;
1027
1028         unregister_framebuffer(fbinfo);
1029         s3c2410fb_cpufreq_deregister(info);
1030
1031         s3c2410fb_lcd_enable(info, 0);
1032         usleep_range(1000, 1100);
1033
1034         s3c2410fb_unmap_video_memory(fbinfo);
1035
1036         if (info->clk) {
1037                 clk_disable_unprepare(info->clk);
1038                 clk_put(info->clk);
1039                 info->clk = NULL;
1040         }
1041
1042         irq = platform_get_irq(pdev, 0);
1043         free_irq(irq, info);
1044
1045         iounmap(info->io);
1046
1047         release_mem_region(info->mem->start, resource_size(info->mem));
1048
1049         framebuffer_release(fbinfo);
1050
1051         return 0;
1052 }
1053
1054 #ifdef CONFIG_PM
1055
1056 /* suspend and resume support for the lcd controller */
1057 static int s3c2410fb_suspend(struct platform_device *dev, pm_message_t state)
1058 {
1059         struct fb_info     *fbinfo = platform_get_drvdata(dev);
1060         struct s3c2410fb_info *info = fbinfo->par;
1061
1062         s3c2410fb_lcd_enable(info, 0);
1063
1064         /* sleep before disabling the clock, we need to ensure
1065          * the LCD DMA engine is not going to get back on the bus
1066          * before the clock goes off again (bjd) */
1067
1068         usleep_range(1000, 1100);
1069         clk_disable_unprepare(info->clk);
1070
1071         return 0;
1072 }
1073
1074 static int s3c2410fb_resume(struct platform_device *dev)
1075 {
1076         struct fb_info     *fbinfo = platform_get_drvdata(dev);
1077         struct s3c2410fb_info *info = fbinfo->par;
1078
1079         clk_prepare_enable(info->clk);
1080         usleep_range(1000, 1100);
1081
1082         s3c2410fb_init_registers(fbinfo);
1083
1084         /* re-activate our display after resume */
1085         s3c2410fb_activate_var(fbinfo);
1086         s3c2410fb_blank(FB_BLANK_UNBLANK, fbinfo);
1087
1088         return 0;
1089 }
1090
1091 #else
1092 #define s3c2410fb_suspend NULL
1093 #define s3c2410fb_resume  NULL
1094 #endif
1095
1096 static struct platform_driver s3c2410fb_driver = {
1097         .probe          = s3c2410fb_probe,
1098         .remove         = s3c2410fb_remove,
1099         .suspend        = s3c2410fb_suspend,
1100         .resume         = s3c2410fb_resume,
1101         .driver         = {
1102                 .name   = "s3c2410-lcd",
1103         },
1104 };
1105
1106 static struct platform_driver s3c2412fb_driver = {
1107         .probe          = s3c2412fb_probe,
1108         .remove         = s3c2410fb_remove,
1109         .suspend        = s3c2410fb_suspend,
1110         .resume         = s3c2410fb_resume,
1111         .driver         = {
1112                 .name   = "s3c2412-lcd",
1113         },
1114 };
1115
1116 int __init s3c2410fb_init(void)
1117 {
1118         int ret = platform_driver_register(&s3c2410fb_driver);
1119
1120         if (ret == 0)
1121                 ret = platform_driver_register(&s3c2412fb_driver);
1122
1123         return ret;
1124 }
1125
1126 static void __exit s3c2410fb_cleanup(void)
1127 {
1128         platform_driver_unregister(&s3c2410fb_driver);
1129         platform_driver_unregister(&s3c2412fb_driver);
1130 }
1131
1132 module_init(s3c2410fb_init);
1133 module_exit(s3c2410fb_cleanup);
1134
1135 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
1136 MODULE_AUTHOR("Ben Dooks <ben-linux@fluff.org>");
1137 MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
1138 MODULE_LICENSE("GPL");
1139 MODULE_ALIAS("platform:s3c2410-lcd");
1140 MODULE_ALIAS("platform:s3c2412-lcd");