drivers/video/fbdev/pxa3xx-gcu.c

   1 /*
   2  *  pxa3xx-gcu.c - Linux kernel module for PXA3xx graphics controllers
   3  *
   4  *  This driver needs a DirectFB counterpart in user space, communication
   5  *  is handled via mmap()ed memory areas and an ioctl.
   6  *
   7  *  Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
   8  *  Copyright (c) 2009 Janine Kropp <nin@directfb.org>
   9  *  Copyright (c) 2009 Denis Oliver Kropp <dok@directfb.org>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify
  12  *  it under the terms of the GNU General Public License as published by
  13  *  the Free Software Foundation; either version 2 of the License, or
  14  *  (at your option) any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful,
  17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *  GNU General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License
  22  *  along with this program; if not, write to the Free Software
  23  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 /*
  27  * WARNING: This controller is attached to System Bus 2 of the PXA which
  28  * needs its arbiter to be enabled explicitly (CKENB & 1<<9).
  29  * There is currently no way to do this from Linux, so you need to teach
  30  * your bootloader for now.
  31  */
  32
  33 #include <linux/module.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/miscdevice.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/spinlock.h>
  39 #include <linux/uaccess.h>
  40 #include <linux/ioctl.h>
  41 #include <linux/delay.h>
  42 #include <linux/sched.h>
  43 #include <linux/slab.h>
  44 #include <linux/clk.h>
  45 #include <linux/fs.h>
  46 #include <linux/io.h>
  47 #include <linux/of.h>
  48
  49 #include "pxa3xx-gcu.h"
  50
  51 #define DRV_NAME        "pxa3xx-gcu"
  52 #define MISCDEV_MINOR   197
  53
  54 #define REG_GCCR        0x00
  55 #define GCCR_SYNC_CLR   (1 << 9)
  56 #define GCCR_BP_RST     (1 << 8)
  57 #define GCCR_ABORT      (1 << 6)
  58 #define GCCR_STOP       (1 << 4)
  59
  60 #define REG_GCISCR      0x04
  61 #define REG_GCIECR      0x08
  62 #define REG_GCRBBR      0x20
  63 #define REG_GCRBLR      0x24
  64 #define REG_GCRBHR      0x28
  65 #define REG_GCRBTR      0x2C
  66 #define REG_GCRBEXHR    0x30
  67
  68 #define IE_EOB          (1 << 0)
  69 #define IE_EEOB         (1 << 5)
  70 #define IE_ALL          0xff
  71
  72 #define SHARED_SIZE     PAGE_ALIGN(sizeof(struct pxa3xx_gcu_shared))
  73
  74 /* #define PXA3XX_GCU_DEBUG */
  75 /* #define PXA3XX_GCU_DEBUG_TIMER */
  76
  77 #ifdef PXA3XX_GCU_DEBUG
  78 #define QDUMP(msg)                                      \
  79         do {                                            \
  80                 QPRINT(priv, KERN_DEBUG, msg);          \
  81         } while (0)
  82 #else
  83 #define QDUMP(msg)      do {} while (0)
  84 #endif
  85
  86 #define QERROR(msg)                                     \
  87         do {                                            \
  88                 QPRINT(priv, KERN_ERR, msg);            \
  89         } while (0)
  90
  91 struct pxa3xx_gcu_batch {
  92         struct pxa3xx_gcu_batch *next;
  93         u32                     *ptr;
  94         dma_addr_t               phys;
  95         unsigned long            length;
  96 };
  97
  98 struct pxa3xx_gcu_priv {
  99         struct device            *dev;
 100         void __iomem             *mmio_base;
 101         struct clk               *clk;
 102         struct pxa3xx_gcu_shared *shared;
 103         dma_addr_t                shared_phys;
 104         struct resource          *resource_mem;
 105         struct miscdevice         misc_dev;
 106         wait_queue_head_t         wait_idle;
 107         wait_queue_head_t         wait_free;
 108         spinlock_t                spinlock;
 109         struct timespec64         base_time;
 110
 111         struct pxa3xx_gcu_batch *free;
 112         struct pxa3xx_gcu_batch *ready;
 113         struct pxa3xx_gcu_batch *ready_last;
 114         struct pxa3xx_gcu_batch *running;
 115 };
 116
 117 static inline unsigned long
 118 gc_readl(struct pxa3xx_gcu_priv *priv, unsigned int off)
 119 {
 120         return __raw_readl(priv->mmio_base + off);
 121 }
 122
 123 static inline void
 124 gc_writel(struct pxa3xx_gcu_priv *priv, unsigned int off, unsigned long val)
 125 {
 126         __raw_writel(val, priv->mmio_base + off);
 127 }
 128
 129 #define QPRINT(priv, level, msg)                                        \
 130         do {                                                            \
 131                 struct timespec64 ts;                                   \
 132                 struct pxa3xx_gcu_shared *shared = priv->shared;        \
 133                 u32 base = gc_readl(priv, REG_GCRBBR);                  \
 134                                                                         \
 135                 ktime_get_ts64(&ts);                                    \
 136                 ts = timespec64_sub(ts, priv->base_time);               \
 137                                                                         \
 138                 printk(level "%lld.%03ld.%03ld - %-17s: %-21s (%s, "    \
 139                         "STATUS "                                       \
 140                         "0x%02lx, B 0x%08lx [%ld], E %5ld, H %5ld, "    \
 141                         "T %5ld)\n",                                    \
 142                         (s64)(ts.tv_sec),                               \
 143                         ts.tv_nsec / NSEC_PER_MSEC,                     \
 144                         (ts.tv_nsec % NSEC_PER_MSEC) / USEC_PER_MSEC,   \
 145                         __func__, msg,                                  \
 146                         shared->hw_running ? "running" : "   idle",     \
 147                         gc_readl(priv, REG_GCISCR),                     \
 148                         gc_readl(priv, REG_GCRBBR),                     \
 149                         gc_readl(priv, REG_GCRBLR),                     \
 150                         (gc_readl(priv, REG_GCRBEXHR) - base) / 4,      \
 151                         (gc_readl(priv, REG_GCRBHR) - base) / 4,        \
 152                         (gc_readl(priv, REG_GCRBTR) - base) / 4);       \
 153         } while (0)
 154
 155 static void
 156 pxa3xx_gcu_reset(struct pxa3xx_gcu_priv *priv)
 157 {
 158         QDUMP("RESET");
 159
 160         /* disable interrupts */
 161         gc_writel(priv, REG_GCIECR, 0);
 162
 163         /* reset hardware */
 164         gc_writel(priv, REG_GCCR, GCCR_ABORT);
 165         gc_writel(priv, REG_GCCR, 0);
 166
 167         memset(priv->shared, 0, SHARED_SIZE);
 168         priv->shared->buffer_phys = priv->shared_phys;
 169         priv->shared->magic = PXA3XX_GCU_SHARED_MAGIC;
 170
 171         ktime_get_ts64(&priv->base_time);
 172
 173         /* set up the ring buffer pointers */
 174         gc_writel(priv, REG_GCRBLR, 0);
 175         gc_writel(priv, REG_GCRBBR, priv->shared_phys);
 176         gc_writel(priv, REG_GCRBTR, priv->shared_phys);
 177
 178         /* enable all IRQs except EOB */
 179         gc_writel(priv, REG_GCIECR, IE_ALL & ~IE_EOB);
 180 }
 181
 182 static void
 183 dump_whole_state(struct pxa3xx_gcu_priv *priv)
 184 {
 185         struct pxa3xx_gcu_shared *sh = priv->shared;
 186         u32 base = gc_readl(priv, REG_GCRBBR);
 187
 188         QDUMP("DUMP");
 189
 190         printk(KERN_DEBUG "== PXA3XX-GCU DUMP ==\n"
 191                 "%s, STATUS 0x%02lx, B 0x%08lx [%ld], E %5ld, H %5ld, T %5ld\n",
 192                 sh->hw_running ? "running" : "idle   ",
 193                 gc_readl(priv, REG_GCISCR),
 194                 gc_readl(priv, REG_GCRBBR),
 195                 gc_readl(priv, REG_GCRBLR),
 196                 (gc_readl(priv, REG_GCRBEXHR) - base) / 4,
 197                 (gc_readl(priv, REG_GCRBHR) - base) / 4,
 198                 (gc_readl(priv, REG_GCRBTR) - base) / 4);
 199 }
 200
 201 static void
 202 flush_running(struct pxa3xx_gcu_priv *priv)
 203 {
 204         struct pxa3xx_gcu_batch *running = priv->running;
 205         struct pxa3xx_gcu_batch *next;
 206
 207         while (running) {
 208                 next = running->next;
 209                 running->next = priv->free;
 210                 priv->free = running;
 211                 running = next;
 212         }
 213
 214         priv->running = NULL;
 215 }
 216
 217 static void
 218 run_ready(struct pxa3xx_gcu_priv *priv)
 219 {
 220         unsigned int num = 0;
 221         struct pxa3xx_gcu_shared *shared = priv->shared;
 222         struct pxa3xx_gcu_batch *ready = priv->ready;
 223
 224         QDUMP("Start");
 225
 226         BUG_ON(!ready);
 227
 228         shared->buffer[num++] = 0x05000000;
 229
 230         while (ready) {
 231                 shared->buffer[num++] = 0x00000001;
 232                 shared->buffer[num++] = ready->phys;
 233                 ready = ready->next;
 234         }
 235
 236         shared->buffer[num++] = 0x05000000;
 237         priv->running = priv->ready;
 238         priv->ready = priv->ready_last = NULL;
 239         gc_writel(priv, REG_GCRBLR, 0);
 240         shared->hw_running = 1;
 241
 242         /* ring base address */
 243         gc_writel(priv, REG_GCRBBR, shared->buffer_phys);
 244
 245         /* ring tail address */
 246         gc_writel(priv, REG_GCRBTR, shared->buffer_phys + num * 4);
 247
 248         /* ring length */
 249         gc_writel(priv, REG_GCRBLR, ((num + 63) & ~63) * 4);
 250 }
 251
 252 static irqreturn_t
 253 pxa3xx_gcu_handle_irq(int irq, void *ctx)
 254 {
 255         struct pxa3xx_gcu_priv *priv = ctx;
 256         struct pxa3xx_gcu_shared *shared = priv->shared;
 257         u32 status = gc_readl(priv, REG_GCISCR) & IE_ALL;
 258
 259         QDUMP("-Interrupt");
 260
 261         if (!status)
 262                 return IRQ_NONE;
 263
 264         spin_lock(&priv->spinlock);
 265         shared->num_interrupts++;
 266
 267         if (status & IE_EEOB) {
 268                 QDUMP(" [EEOB]");
 269
 270                 flush_running(priv);
 271                 wake_up_all(&priv->wait_free);
 272
 273                 if (priv->ready) {
 274                         run_ready(priv);
 275                 } else {
 276                         /* There is no more data prepared by the userspace.
 277                          * Set hw_running = 0 and wait for the next userspace
 278                          * kick-off */
 279                         shared->num_idle++;
 280                         shared->hw_running = 0;
 281
 282                         QDUMP(" '-> Idle.");
 283
 284                         /* set ring buffer length to zero */
 285                         gc_writel(priv, REG_GCRBLR, 0);
 286
 287                         wake_up_all(&priv->wait_idle);
 288                 }
 289
 290                 shared->num_done++;
 291         } else {
 292                 QERROR(" [???]");
 293                 dump_whole_state(priv);
 294         }
 295
 296         /* Clear the interrupt */
 297         gc_writel(priv, REG_GCISCR, status);
 298         spin_unlock(&priv->spinlock);
 299
 300         return IRQ_HANDLED;
 301 }
 302
 303 static int
 304 pxa3xx_gcu_wait_idle(struct pxa3xx_gcu_priv *priv)
 305 {
 306         int ret = 0;
 307
 308         QDUMP("Waiting for idle...");
 309
 310         /* Does not need to be atomic. There's a lock in user space,
 311          * but anyhow, this is just for statistics. */
 312         priv->shared->num_wait_idle++;
 313
 314         while (priv->shared->hw_running) {
 315                 int num = priv->shared->num_interrupts;
 316                 u32 rbexhr = gc_readl(priv, REG_GCRBEXHR);
 317
 318                 ret = wait_event_interruptible_timeout(priv->wait_idle,
 319                                         !priv->shared->hw_running, HZ*4);
 320
 321                 if (ret != 0)
 322                         break;
 323
 324                 if (gc_readl(priv, REG_GCRBEXHR) == rbexhr &&
 325                     priv->shared->num_interrupts == num) {
 326                         QERROR("TIMEOUT");
 327                         ret = -ETIMEDOUT;
 328                         break;
 329                 }
 330         }
 331
 332         QDUMP("done");
 333
 334         return ret;
 335 }
 336
 337 static int
 338 pxa3xx_gcu_wait_free(struct pxa3xx_gcu_priv *priv)
 339 {
 340         int ret = 0;
 341
 342         QDUMP("Waiting for free...");
 343
 344         /* Does not need to be atomic. There's a lock in user space,
 345          * but anyhow, this is just for statistics. */
 346         priv->shared->num_wait_free++;
 347
 348         while (!priv->free) {
 349                 u32 rbexhr = gc_readl(priv, REG_GCRBEXHR);
 350
 351                 ret = wait_event_interruptible_timeout(priv->wait_free,
 352                                                        priv->free, HZ*4);
 353
 354                 if (ret < 0)
 355                         break;
 356
 357                 if (ret > 0)
 358                         continue;
 359
 360                 if (gc_readl(priv, REG_GCRBEXHR) == rbexhr) {
 361                         QERROR("TIMEOUT");
 362                         ret = -ETIMEDOUT;
 363                         break;
 364                 }
 365         }
 366
 367         QDUMP("done");
 368
 369         return ret;
 370 }
 371
 372 /* Misc device layer */
 373
 374 static inline struct pxa3xx_gcu_priv *to_pxa3xx_gcu_priv(struct file *file)
 375 {
 376         struct miscdevice *dev = file->private_data;
 377         return container_of(dev, struct pxa3xx_gcu_priv, misc_dev);
 378 }
 379
 380 /*
 381  * provide an empty .open callback, so the core sets file->private_data
 382  * for us.
 383  */
 384 static int pxa3xx_gcu_open(struct inode *inode, struct file *file)
 385 {
 386         return 0;
 387 }
 388
 389 static ssize_t
 390 pxa3xx_gcu_write(struct file *file, const char *buff,
 391                  size_t count, loff_t *offp)
 392 {
 393         int ret;
 394         unsigned long flags;
 395         struct pxa3xx_gcu_batch *buffer;
 396         struct pxa3xx_gcu_priv *priv = to_pxa3xx_gcu_priv(file);
 397
 398         int words = count / 4;
 399
 400         /* Does not need to be atomic. There's a lock in user space,
 401          * but anyhow, this is just for statistics. */
 402         priv->shared->num_writes++;
 403         priv->shared->num_words += words;
 404
 405         /* Last word reserved for batch buffer end command */
 406         if (words >= PXA3XX_GCU_BATCH_WORDS)
 407                 return -E2BIG;
 408
 409         /* Wait for a free buffer */
 410         if (!priv->free) {
 411                 ret = pxa3xx_gcu_wait_free(priv);
 412                 if (ret < 0)
 413                         return ret;
 414         }
 415
 416         /*
 417          * Get buffer from free list
 418          */
 419         spin_lock_irqsave(&priv->spinlock, flags);
 420         buffer = priv->free;
 421         priv->free = buffer->next;
 422         spin_unlock_irqrestore(&priv->spinlock, flags);
 423
 424
 425         /* Copy data from user into buffer */
 426         ret = copy_from_user(buffer->ptr, buff, words * 4);
 427         if (ret) {
 428                 spin_lock_irqsave(&priv->spinlock, flags);
 429                 buffer->next = priv->free;
 430                 priv->free = buffer;
 431                 spin_unlock_irqrestore(&priv->spinlock, flags);
 432                 return -EFAULT;
 433         }
 434
 435         buffer->length = words;
 436
 437         /* Append batch buffer end command */
 438         buffer->ptr[words] = 0x01000000;
 439
 440         /*
 441          * Add buffer to ready list
 442          */
 443         spin_lock_irqsave(&priv->spinlock, flags);
 444
 445         buffer->next = NULL;
 446
 447         if (priv->ready) {
 448                 BUG_ON(priv->ready_last == NULL);
 449
 450                 priv->ready_last->next = buffer;
 451         } else
 452                 priv->ready = buffer;
 453
 454         priv->ready_last = buffer;
 455
 456         if (!priv->shared->hw_running)
 457                 run_ready(priv);
 458
 459         spin_unlock_irqrestore(&priv->spinlock, flags);
 460
 461         return words * 4;
 462 }
 463
 464
 465 static long
 466 pxa3xx_gcu_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
 467 {
 468         unsigned long flags;
 469         struct pxa3xx_gcu_priv *priv = to_pxa3xx_gcu_priv(file);
 470
 471         switch (cmd) {
 472         case PXA3XX_GCU_IOCTL_RESET:
 473                 spin_lock_irqsave(&priv->spinlock, flags);
 474                 pxa3xx_gcu_reset(priv);
 475                 spin_unlock_irqrestore(&priv->spinlock, flags);
 476                 return 0;
 477
 478         case PXA3XX_GCU_IOCTL_WAIT_IDLE:
 479                 return pxa3xx_gcu_wait_idle(priv);
 480         }
 481
 482         return -ENOSYS;
 483 }
 484
 485 static int
 486 pxa3xx_gcu_mmap(struct file *file, struct vm_area_struct *vma)
 487 {
 488         unsigned int size = vma->vm_end - vma->vm_start;
 489         struct pxa3xx_gcu_priv *priv = to_pxa3xx_gcu_priv(file);
 490
 491         switch (vma->vm_pgoff) {
 492         case 0:
 493                 /* hand out the shared data area */
 494                 if (size != SHARED_SIZE)
 495                         return -EINVAL;
 496
 497                 return dma_mmap_coherent(priv->dev, vma,
 498                         priv->shared, priv->shared_phys, size);
 499
 500         case SHARED_SIZE >> PAGE_SHIFT:
 501                 /* hand out the MMIO base for direct register access
 502                  * from userspace */
 503                 if (size != resource_size(priv->resource_mem))
 504                         return -EINVAL;
 505
 506                 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 507
 508                 return io_remap_pfn_range(vma, vma->vm_start,
 509                                 priv->resource_mem->start >> PAGE_SHIFT,
 510                                 size, vma->vm_page_prot);
 511         }
 512
 513         return -EINVAL;
 514 }
 515
 516
 517 #ifdef PXA3XX_GCU_DEBUG_TIMER
 518 static struct timer_list pxa3xx_gcu_debug_timer;
 519 static struct pxa3xx_gcu_priv *debug_timer_priv;
 520
 521 static void pxa3xx_gcu_debug_timedout(struct timer_list *unused)
 522 {
 523         struct pxa3xx_gcu_priv *priv = debug_timer_priv;
 524
 525         QERROR("Timer DUMP");
 526
 527         mod_timer(&pxa3xx_gcu_debug_timer, jiffies + 5 * HZ);
 528 }
 529
 530 static void pxa3xx_gcu_init_debug_timer(struct pxa3xx_gcu_priv *priv)
 531 {
 532         /* init the timer structure */
 533         debug_timer_priv = priv;
 534         timer_setup(&pxa3xx_gcu_debug_timer, pxa3xx_gcu_debug_timedout, 0);
 535         pxa3xx_gcu_debug_timedout(NULL);
 536 }
 537 #else
 538 static inline void pxa3xx_gcu_init_debug_timer(struct pxa3xx_gcu_priv *priv) {}
 539 #endif
 540
 541 static int
 542 pxa3xx_gcu_add_buffer(struct device *dev,
 543                       struct pxa3xx_gcu_priv *priv)
 544 {
 545         struct pxa3xx_gcu_batch *buffer;
 546
 547         buffer = kzalloc(sizeof(struct pxa3xx_gcu_batch), GFP_KERNEL);
 548         if (!buffer)
 549                 return -ENOMEM;
 550
 551         buffer->ptr = dma_alloc_coherent(dev, PXA3XX_GCU_BATCH_WORDS * 4,
 552                                          &buffer->phys, GFP_KERNEL);
 553         if (!buffer->ptr) {
 554                 kfree(buffer);
 555                 return -ENOMEM;
 556         }
 557
 558         buffer->next = priv->free;
 559         priv->free = buffer;
 560
 561         return 0;
 562 }
 563
 564 static void
 565 pxa3xx_gcu_free_buffers(struct device *dev,
 566                         struct pxa3xx_gcu_priv *priv)
 567 {
 568         struct pxa3xx_gcu_batch *next, *buffer = priv->free;
 569
 570         while (buffer) {
 571                 next = buffer->next;
 572
 573                 dma_free_coherent(dev, PXA3XX_GCU_BATCH_WORDS * 4,
 574                                   buffer->ptr, buffer->phys);
 575
 576                 kfree(buffer);
 577                 buffer = next;
 578         }
 579
 580         priv->free = NULL;
 581 }
 582
 583 static const struct file_operations pxa3xx_gcu_miscdev_fops = {
 584         .owner =                THIS_MODULE,
 585         .open =                 pxa3xx_gcu_open,
 586         .write =                pxa3xx_gcu_write,
 587         .unlocked_ioctl =       pxa3xx_gcu_ioctl,
 588         .mmap =                 pxa3xx_gcu_mmap,
 589 };
 590
 591 static int pxa3xx_gcu_probe(struct platform_device *pdev)
 592 {
 593         int i, ret, irq;
 594         struct resource *r;
 595         struct pxa3xx_gcu_priv *priv;
 596         struct device *dev = &pdev->dev;
 597
 598         priv = devm_kzalloc(dev, sizeof(struct pxa3xx_gcu_priv), GFP_KERNEL);
 599         if (!priv)
 600                 return -ENOMEM;
 601
 602         init_waitqueue_head(&priv->wait_idle);
 603         init_waitqueue_head(&priv->wait_free);
 604         spin_lock_init(&priv->spinlock);
 605
 606         /* we allocate the misc device structure as part of our own allocation,
 607          * so we can get a pointer to our priv structure later on with
 608          * container_of(). This isn't really necessary as we have a fixed minor
 609          * number anyway, but this is to avoid statics. */
 610
 611         priv->misc_dev.minor    = MISCDEV_MINOR,
 612         priv->misc_dev.name     = DRV_NAME,
 613         priv->misc_dev.fops     = &pxa3xx_gcu_miscdev_fops;
 614
 615         /* handle IO resources */
 616         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 617         priv->mmio_base = devm_ioremap_resource(dev, r);
 618         if (IS_ERR(priv->mmio_base))
 619                 return PTR_ERR(priv->mmio_base);
 620
 621         /* enable the clock */
 622         priv->clk = devm_clk_get(dev, NULL);
 623         if (IS_ERR(priv->clk)) {
 624                 dev_err(dev, "failed to get clock\n");
 625                 return PTR_ERR(priv->clk);
 626         }
 627
 628         /* request the IRQ */
 629         irq = platform_get_irq(pdev, 0);
 630         if (irq < 0) {
 631                 dev_err(dev, "no IRQ defined: %d\n", irq);
 632                 return irq;
 633         }
 634
 635         ret = devm_request_irq(dev, irq, pxa3xx_gcu_handle_irq,
 636                                0, DRV_NAME, priv);
 637         if (ret < 0) {
 638                 dev_err(dev, "request_irq failed\n");
 639                 return ret;
 640         }
 641
 642         /* allocate dma memory */
 643         priv->shared = dma_alloc_coherent(dev, SHARED_SIZE,
 644                                           &priv->shared_phys, GFP_KERNEL);
 645         if (!priv->shared) {
 646                 dev_err(dev, "failed to allocate DMA memory\n");
 647                 return -ENOMEM;
 648         }
 649
 650         /* register misc device */
 651         ret = misc_register(&priv->misc_dev);
 652         if (ret < 0) {
 653                 dev_err(dev, "misc_register() for minor %d failed\n",
 654                         MISCDEV_MINOR);
 655                 goto err_free_dma;
 656         }
 657
 658         ret = clk_prepare_enable(priv->clk);
 659         if (ret < 0) {
 660                 dev_err(dev, "failed to enable clock\n");
 661                 goto err_misc_deregister;
 662         }
 663
 664         for (i = 0; i < 8; i++) {
 665                 ret = pxa3xx_gcu_add_buffer(dev, priv);
 666                 if (ret) {
 667                         dev_err(dev, "failed to allocate DMA memory\n");
 668                         goto err_disable_clk;
 669                 }
 670         }
 671
 672         platform_set_drvdata(pdev, priv);
 673         priv->resource_mem = r;
 674         priv->dev = dev;
 675         pxa3xx_gcu_reset(priv);
 676         pxa3xx_gcu_init_debug_timer(priv);
 677
 678         dev_info(dev, "registered @0x%p, DMA 0x%p (%d bytes), IRQ %d\n",
 679                         (void *) r->start, (void *) priv->shared_phys,
 680                         SHARED_SIZE, irq);
 681         return 0;
 682
 683 err_free_dma:
 684         dma_free_coherent(dev, SHARED_SIZE,
 685                         priv->shared, priv->shared_phys);
 686
 687 err_misc_deregister:
 688         misc_deregister(&priv->misc_dev);
 689
 690 err_disable_clk:
 691         clk_disable_unprepare(priv->clk);
 692
 693         return ret;
 694 }
 695
 696 static int pxa3xx_gcu_remove(struct platform_device *pdev)
 697 {
 698         struct pxa3xx_gcu_priv *priv = platform_get_drvdata(pdev);
 699         struct device *dev = &pdev->dev;
 700
 701         pxa3xx_gcu_wait_idle(priv);
 702         misc_deregister(&priv->misc_dev);
 703         dma_free_coherent(dev, SHARED_SIZE, priv->shared, priv->shared_phys);
 704         pxa3xx_gcu_free_buffers(dev, priv);
 705
 706         return 0;
 707 }
 708
 709 #ifdef CONFIG_OF
 710 static const struct of_device_id pxa3xx_gcu_of_match[] = {
 711         { .compatible = "marvell,pxa300-gcu", },
 712         { }
 713 };
 714 MODULE_DEVICE_TABLE(of, pxa3xx_gcu_of_match);
 715 #endif
 716
 717 static struct platform_driver pxa3xx_gcu_driver = {
 718         .probe    = pxa3xx_gcu_probe,
 719         .remove  = pxa3xx_gcu_remove,
 720         .driver  = {
 721                 .name   = DRV_NAME,
 722                 .of_match_table = of_match_ptr(pxa3xx_gcu_of_match),
 723         },
 724 };
 725
 726 module_platform_driver(pxa3xx_gcu_driver);
 727
 728 MODULE_DESCRIPTION("PXA3xx graphics controller unit driver");
 729 MODULE_LICENSE("GPL");
 730 MODULE_ALIAS_MISCDEV(MISCDEV_MINOR);
 731 MODULE_AUTHOR("Janine Kropp <nin@directfb.org>, "
 732                 "Denis Oliver Kropp <dok@directfb.org>, "
 733                 "Daniel Mack <daniel@caiaq.de>");