1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013 Texas Instruments Incorporated
8 #include <linux/kernel.h>
11 #include <linux/platform_device.h>
12 #include <linux/slab.h>
13 #include <linux/seq_file.h>
15 #include <video/omapfb_dss.h>
20 struct hdmi_phy_features {
23 unsigned long max_phy;
26 static const struct hdmi_phy_features *phy_feat;
28 void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s)
30 #define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\
31 hdmi_read_reg(phy->base, r))
33 DUMPPHY(HDMI_TXPHY_TX_CTRL);
34 DUMPPHY(HDMI_TXPHY_DIGITAL_CTRL);
35 DUMPPHY(HDMI_TXPHY_POWER_CTRL);
36 DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL);
37 if (phy_feat->bist_ctrl)
38 DUMPPHY(HDMI_TXPHY_BIST_CONTROL);
41 int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes)
45 for (i = 0; i < 8; i += 2) {
52 if (dx < 0 || dx >= 8)
55 if (dy < 0 || dy >= 8)
70 phy->lane_function[lane] = i / 2;
71 phy->lane_polarity[lane] = pol;
77 static void hdmi_phy_configure_lanes(struct hdmi_phy_data *phy)
79 static const u16 pad_cfg_list[] = {
108 unsigned lane_cfg_val;
111 for (i = 0; i < 4; ++i)
112 lane_cfg |= phy->lane_function[i] << ((3 - i) * 4);
114 pol_val |= phy->lane_polarity[0] << 0;
115 pol_val |= phy->lane_polarity[1] << 3;
116 pol_val |= phy->lane_polarity[2] << 2;
117 pol_val |= phy->lane_polarity[3] << 1;
119 for (i = 0; i < ARRAY_SIZE(pad_cfg_list); ++i)
120 if (pad_cfg_list[i] == lane_cfg)
123 if (WARN_ON(i == ARRAY_SIZE(pad_cfg_list)))
128 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, lane_cfg_val, 26, 22);
129 REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, pol_val, 30, 27);
132 int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk,
133 unsigned long lfbitclk)
138 * Read address 0 in order to get the SCP reset done completed
139 * Dummy access performed to make sure reset is done
141 hdmi_read_reg(phy->base, HDMI_TXPHY_TX_CTRL);
144 * In OMAP5+, the HFBITCLK must be divided by 2 before issuing the
145 * HDMI_PHYPWRCMD_LDOON command.
147 if (phy_feat->bist_ctrl)
148 REG_FLD_MOD(phy->base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11);
151 * If the hfbitclk != lfbitclk, it means the lfbitclk was configured
152 * to be used for TMDS.
154 if (hfbitclk != lfbitclk)
156 else if (hfbitclk / 10 < phy_feat->max_phy)
162 * Write to phy address 0 to configure the clock
163 * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
165 REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, freqout, 31, 30);
167 /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
168 hdmi_write_reg(phy->base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
170 /* Setup max LDO voltage */
171 if (phy_feat->ldo_voltage)
172 REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
174 hdmi_phy_configure_lanes(phy);
179 static const struct hdmi_phy_features omap44xx_phy_feats = {
182 .max_phy = 185675000,
185 static const struct hdmi_phy_features omap54xx_phy_feats = {
187 .ldo_voltage = false,
188 .max_phy = 186000000,
191 static const struct hdmi_phy_features *hdmi_phy_get_features(void)
193 switch (omapdss_get_version()) {
194 case OMAPDSS_VER_OMAP4430_ES1:
195 case OMAPDSS_VER_OMAP4430_ES2:
196 case OMAPDSS_VER_OMAP4:
197 return &omap44xx_phy_feats;
199 case OMAPDSS_VER_OMAP5:
200 case OMAPDSS_VER_DRA7xx:
201 return &omap54xx_phy_feats;
208 int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy)
210 phy_feat = hdmi_phy_get_features();
214 phy->base = devm_platform_ioremap_resource_byname(pdev, "phy");
215 if (IS_ERR(phy->base)) {
216 DSSERR("can't ioremap TX PHY\n");
217 return PTR_ERR(phy->base);