drivers/usb/phy/phy-tegra-usb.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2010 Google, Inc.
   4  * Copyright (C) 2013 NVIDIA Corporation
   5  *
   6  * Author:
   7  *      Erik Gilling <konkers@google.com>
   8  *      Benoit Goby <benoit@android.com>
   9  *      Venu Byravarasu <vbyravarasu@nvidia.com>
  10  */
  11
  12 #include <linux/delay.h>
  13 #include <linux/err.h>
  14 #include <linux/export.h>
  15 #include <linux/gpio/consumer.h>
  16 #include <linux/iopoll.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/of_device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/resource.h>
  22 #include <linux/slab.h>
  23 #include <linux/spinlock.h>
  24
  25 #include <linux/regulator/consumer.h>
  26
  27 #include <linux/usb/ehci_def.h>
  28 #include <linux/usb/of.h>
  29 #include <linux/usb/tegra_usb_phy.h>
  30 #include <linux/usb/ulpi.h>
  31
  32 #define ULPI_VIEWPORT                           0x170
  33
  34 /* PORTSC PTS/PHCD bits, Tegra20 only */
  35 #define TEGRA_USB_PORTSC1                       0x184
  36 #define TEGRA_USB_PORTSC1_PTS(x)                (((x) & 0x3) << 30)
  37 #define TEGRA_USB_PORTSC1_PHCD                  BIT(23)
  38
  39 /* HOSTPC1 PTS/PHCD bits, Tegra30 and above */
  40 #define TEGRA_USB_HOSTPC1_DEVLC                 0x1b4
  41 #define TEGRA_USB_HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
  42 #define TEGRA_USB_HOSTPC1_DEVLC_PHCD            BIT(22)
  43
  44 /* Bits of PORTSC1, which will get cleared by writing 1 into them */
  45 #define TEGRA_PORTSC1_RWC_BITS  (PORT_CSC | PORT_PEC | PORT_OCC)
  46
  47 #define USB_SUSP_CTRL                           0x400
  48 #define   USB_WAKE_ON_CNNT_EN_DEV               BIT(3)
  49 #define   USB_WAKE_ON_DISCON_EN_DEV             BIT(4)
  50 #define   USB_SUSP_CLR                          BIT(5)
  51 #define   USB_PHY_CLK_VALID                     BIT(7)
  52 #define   UTMIP_RESET                           BIT(11)
  53 #define   UHSIC_RESET                           BIT(11)
  54 #define   UTMIP_PHY_ENABLE                      BIT(12)
  55 #define   ULPI_PHY_ENABLE                       BIT(13)
  56 #define   USB_SUSP_SET                          BIT(14)
  57 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)          (((x) & 0x7) << 16)
  58
  59 #define USB1_LEGACY_CTRL                        0x410
  60 #define   USB1_NO_LEGACY_MODE                   BIT(0)
  61 #define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
  62 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
  63 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
  64                                                 (1 << 1)
  65 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
  66 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
  67
  68 #define ULPI_TIMING_CTRL_0                      0x424
  69 #define   ULPI_OUTPUT_PINMUX_BYP                BIT(10)
  70 #define   ULPI_CLKOUT_PINMUX_BYP                BIT(11)
  71
  72 #define ULPI_TIMING_CTRL_1                      0x428
  73 #define   ULPI_DATA_TRIMMER_LOAD                BIT(0)
  74 #define   ULPI_DATA_TRIMMER_SEL(x)              (((x) & 0x7) << 1)
  75 #define   ULPI_STPDIRNXT_TRIMMER_LOAD           BIT(16)
  76 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x)         (((x) & 0x7) << 17)
  77 #define   ULPI_DIR_TRIMMER_LOAD                 BIT(24)
  78 #define   ULPI_DIR_TRIMMER_SEL(x)               (((x) & 0x7) << 25)
  79
  80 #define UTMIP_PLL_CFG1                          0x804
  81 #define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
  82 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
  83
  84 #define UTMIP_XCVR_CFG0                         0x808
  85 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
  86 #define   UTMIP_XCVR_SETUP_MSB(x)               ((((x) & 0x70) >> 4) << 22)
  87 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
  88 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
  89 #define   UTMIP_FORCE_PD_POWERDOWN              BIT(14)
  90 #define   UTMIP_FORCE_PD2_POWERDOWN             BIT(16)
  91 #define   UTMIP_FORCE_PDZI_POWERDOWN            BIT(18)
  92 #define   UTMIP_XCVR_LSBIAS_SEL                 BIT(21)
  93 #define   UTMIP_XCVR_HSSLEW(x)                  (((x) & 0x3) << 4)
  94 #define   UTMIP_XCVR_HSSLEW_MSB(x)              ((((x) & 0x1fc) >> 2) << 25)
  95
  96 #define UTMIP_BIAS_CFG0                         0x80c
  97 #define   UTMIP_OTGPD                           BIT(11)
  98 #define   UTMIP_BIASPD                          BIT(10)
  99 #define   UTMIP_HSSQUELCH_LEVEL(x)              (((x) & 0x3) << 0)
 100 #define   UTMIP_HSDISCON_LEVEL(x)               (((x) & 0x3) << 2)
 101 #define   UTMIP_HSDISCON_LEVEL_MSB(x)           ((((x) & 0x4) >> 2) << 24)
 102
 103 #define UTMIP_HSRX_CFG0                         0x810
 104 #define   UTMIP_ELASTIC_LIMIT(x)                (((x) & 0x1f) << 10)
 105 #define   UTMIP_IDLE_WAIT(x)                    (((x) & 0x1f) << 15)
 106
 107 #define UTMIP_HSRX_CFG1                         0x814
 108 #define   UTMIP_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
 109
 110 #define UTMIP_TX_CFG0                           0x820
 111 #define   UTMIP_FS_PREABMLE_J                   BIT(19)
 112 #define   UTMIP_HS_DISCON_DISABLE               BIT(8)
 113
 114 #define UTMIP_MISC_CFG0                         0x824
 115 #define   UTMIP_DPDM_OBSERVE                    BIT(26)
 116 #define   UTMIP_DPDM_OBSERVE_SEL(x)             (((x) & 0xf) << 27)
 117 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J           UTMIP_DPDM_OBSERVE_SEL(0xf)
 118 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K           UTMIP_DPDM_OBSERVE_SEL(0xe)
 119 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1         UTMIP_DPDM_OBSERVE_SEL(0xd)
 120 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0         UTMIP_DPDM_OBSERVE_SEL(0xc)
 121 #define   UTMIP_SUSPEND_EXIT_ON_EDGE            BIT(22)
 122
 123 #define UTMIP_MISC_CFG1                         0x828
 124 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x)         (((x) & 0x1f) << 18)
 125 #define   UTMIP_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 6)
 126
 127 #define UTMIP_DEBOUNCE_CFG0                     0x82c
 128 #define   UTMIP_BIAS_DEBOUNCE_A(x)              (((x) & 0xffff) << 0)
 129
 130 #define UTMIP_BAT_CHRG_CFG0                     0x830
 131 #define   UTMIP_PD_CHRG                         BIT(0)
 132
 133 #define UTMIP_SPARE_CFG0                        0x834
 134 #define   FUSE_SETUP_SEL                        BIT(3)
 135
 136 #define UTMIP_XCVR_CFG1                         0x838
 137 #define   UTMIP_FORCE_PDDISC_POWERDOWN          BIT(0)
 138 #define   UTMIP_FORCE_PDCHRP_POWERDOWN          BIT(2)
 139 #define   UTMIP_FORCE_PDDR_POWERDOWN            BIT(4)
 140 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)          (((x) & 0xf) << 18)
 141
 142 #define UTMIP_BIAS_CFG1                         0x83c
 143 #define   UTMIP_BIAS_PDTRK_COUNT(x)             (((x) & 0x1f) << 3)
 144
 145 /* For Tegra30 and above only, the address is different in Tegra20 */
 146 #define USB_USBMODE                             0x1f8
 147 #define   USB_USBMODE_MASK                      (3 << 0)
 148 #define   USB_USBMODE_HOST                      (3 << 0)
 149 #define   USB_USBMODE_DEVICE                    (2 << 0)
 150
 151 static DEFINE_SPINLOCK(utmip_pad_lock);
 152 static unsigned int utmip_pad_count;
 153
 154 struct tegra_xtal_freq {
 155         unsigned int freq;
 156         u8 enable_delay;
 157         u8 stable_count;
 158         u8 active_delay;
 159         u8 xtal_freq_count;
 160         u16 debounce;
 161 };
 162
 163 static const struct tegra_xtal_freq tegra_freq_table[] = {
 164         {
 165                 .freq = 12000000,
 166                 .enable_delay = 0x02,
 167                 .stable_count = 0x2F,
 168                 .active_delay = 0x04,
 169                 .xtal_freq_count = 0x76,
 170                 .debounce = 0x7530,
 171         },
 172         {
 173                 .freq = 13000000,
 174                 .enable_delay = 0x02,
 175                 .stable_count = 0x33,
 176                 .active_delay = 0x05,
 177                 .xtal_freq_count = 0x7F,
 178                 .debounce = 0x7EF4,
 179         },
 180         {
 181                 .freq = 19200000,
 182                 .enable_delay = 0x03,
 183                 .stable_count = 0x4B,
 184                 .active_delay = 0x06,
 185                 .xtal_freq_count = 0xBB,
 186                 .debounce = 0xBB80,
 187         },
 188         {
 189                 .freq = 26000000,
 190                 .enable_delay = 0x04,
 191                 .stable_count = 0x66,
 192                 .active_delay = 0x09,
 193                 .xtal_freq_count = 0xFE,
 194                 .debounce = 0xFDE8,
 195         },
 196 };
 197
 198 static inline struct tegra_usb_phy *to_tegra_usb_phy(struct usb_phy *u_phy)
 199 {
 200         return container_of(u_phy, struct tegra_usb_phy, u_phy);
 201 }
 202
 203 static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)
 204 {
 205         void __iomem *base = phy->regs;
 206         u32 val;
 207
 208         if (phy->soc_config->has_hostpc) {
 209                 val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
 210                 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0);
 211                 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val);
 212                 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
 213         } else {
 214                 val = readl_relaxed(base + TEGRA_USB_PORTSC1);
 215                 val &= ~TEGRA_PORTSC1_RWC_BITS;
 216                 val &= ~TEGRA_USB_PORTSC1_PTS(~0);
 217                 val |= TEGRA_USB_PORTSC1_PTS(pts_val);
 218                 writel_relaxed(val, base + TEGRA_USB_PORTSC1);
 219         }
 220 }
 221
 222 static void set_phcd(struct tegra_usb_phy *phy, bool enable)
 223 {
 224         void __iomem *base = phy->regs;
 225         u32 val;
 226
 227         if (phy->soc_config->has_hostpc) {
 228                 val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
 229                 if (enable)
 230                         val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD;
 231                 else
 232                         val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD;
 233                 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
 234         } else {
 235                 val = readl_relaxed(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;
 236                 if (enable)
 237                         val |= TEGRA_USB_PORTSC1_PHCD;
 238                 else
 239                         val &= ~TEGRA_USB_PORTSC1_PHCD;
 240                 writel_relaxed(val, base + TEGRA_USB_PORTSC1);
 241         }
 242 }
 243
 244 static int utmip_pad_open(struct tegra_usb_phy *phy)
 245 {
 246         int ret;
 247
 248         ret = clk_prepare_enable(phy->pad_clk);
 249         if (ret) {
 250                 dev_err(phy->u_phy.dev,
 251                         "Failed to enable UTMI-pads clock: %d\n", ret);
 252                 return ret;
 253         }
 254
 255         spin_lock(&utmip_pad_lock);
 256
 257         ret = reset_control_deassert(phy->pad_rst);
 258         if (ret) {
 259                 dev_err(phy->u_phy.dev,
 260                         "Failed to initialize UTMI-pads reset: %d\n", ret);
 261                 goto unlock;
 262         }
 263
 264         ret = reset_control_assert(phy->pad_rst);
 265         if (ret) {
 266                 dev_err(phy->u_phy.dev,
 267                         "Failed to assert UTMI-pads reset: %d\n", ret);
 268                 goto unlock;
 269         }
 270
 271         udelay(1);
 272
 273         ret = reset_control_deassert(phy->pad_rst);
 274         if (ret)
 275                 dev_err(phy->u_phy.dev,
 276                         "Failed to deassert UTMI-pads reset: %d\n", ret);
 277 unlock:
 278         spin_unlock(&utmip_pad_lock);
 279
 280         clk_disable_unprepare(phy->pad_clk);
 281
 282         return ret;
 283 }
 284
 285 static int utmip_pad_close(struct tegra_usb_phy *phy)
 286 {
 287         int ret;
 288
 289         ret = clk_prepare_enable(phy->pad_clk);
 290         if (ret) {
 291                 dev_err(phy->u_phy.dev,
 292                         "Failed to enable UTMI-pads clock: %d\n", ret);
 293                 return ret;
 294         }
 295
 296         ret = reset_control_assert(phy->pad_rst);
 297         if (ret)
 298                 dev_err(phy->u_phy.dev,
 299                         "Failed to assert UTMI-pads reset: %d\n", ret);
 300
 301         udelay(1);
 302
 303         clk_disable_unprepare(phy->pad_clk);
 304
 305         return ret;
 306 }
 307
 308 static int utmip_pad_power_on(struct tegra_usb_phy *phy)
 309 {
 310         struct tegra_utmip_config *config = phy->config;
 311         void __iomem *base = phy->pad_regs;
 312         u32 val;
 313         int err;
 314
 315         err = clk_prepare_enable(phy->pad_clk);
 316         if (err)
 317                 return err;
 318
 319         spin_lock(&utmip_pad_lock);
 320
 321         if (utmip_pad_count++ == 0) {
 322                 val = readl_relaxed(base + UTMIP_BIAS_CFG0);
 323                 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
 324
 325                 if (phy->soc_config->requires_extra_tuning_parameters) {
 326                         val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) |
 327                                 UTMIP_HSDISCON_LEVEL(~0) |
 328                                 UTMIP_HSDISCON_LEVEL_MSB(~0));
 329
 330                         val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level);
 331                         val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level);
 332                         val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level);
 333                 }
 334                 writel_relaxed(val, base + UTMIP_BIAS_CFG0);
 335         }
 336
 337         spin_unlock(&utmip_pad_lock);
 338
 339         clk_disable_unprepare(phy->pad_clk);
 340
 341         return 0;
 342 }
 343
 344 static int utmip_pad_power_off(struct tegra_usb_phy *phy)
 345 {
 346         void __iomem *base = phy->pad_regs;
 347         u32 val;
 348         int ret;
 349
 350         ret = clk_prepare_enable(phy->pad_clk);
 351         if (ret)
 352                 return ret;
 353
 354         spin_lock(&utmip_pad_lock);
 355
 356         if (!utmip_pad_count) {
 357                 dev_err(phy->u_phy.dev, "UTMIP pad already powered off\n");
 358                 ret = -EINVAL;
 359                 goto ulock;
 360         }
 361
 362         if (--utmip_pad_count == 0) {
 363                 val = readl_relaxed(base + UTMIP_BIAS_CFG0);
 364                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
 365                 writel_relaxed(val, base + UTMIP_BIAS_CFG0);
 366         }
 367 ulock:
 368         spin_unlock(&utmip_pad_lock);
 369
 370         clk_disable_unprepare(phy->pad_clk);
 371
 372         return ret;
 373 }
 374
 375 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
 376 {
 377         u32 tmp;
 378
 379         return readl_relaxed_poll_timeout(reg, tmp, (tmp & mask) == result,
 380                                           2000, 6000);
 381 }
 382
 383 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
 384 {
 385         void __iomem *base = phy->regs;
 386         u32 val;
 387
 388         /*
 389          * The USB driver may have already initiated the phy clock
 390          * disable so wait to see if the clock turns off and if not
 391          * then proceed with gating the clock.
 392          */
 393         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) == 0)
 394                 return;
 395
 396         if (phy->is_legacy_phy) {
 397                 val = readl_relaxed(base + USB_SUSP_CTRL);
 398                 val |= USB_SUSP_SET;
 399                 writel_relaxed(val, base + USB_SUSP_CTRL);
 400
 401                 usleep_range(10, 100);
 402
 403                 val = readl_relaxed(base + USB_SUSP_CTRL);
 404                 val &= ~USB_SUSP_SET;
 405                 writel_relaxed(val, base + USB_SUSP_CTRL);
 406         } else {
 407                 set_phcd(phy, true);
 408         }
 409
 410         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0))
 411                 dev_err(phy->u_phy.dev,
 412                         "Timeout waiting for PHY to stabilize on disable\n");
 413 }
 414
 415 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
 416 {
 417         void __iomem *base = phy->regs;
 418         u32 val;
 419
 420         /*
 421          * The USB driver may have already initiated the phy clock
 422          * enable so wait to see if the clock turns on and if not
 423          * then proceed with ungating the clock.
 424          */
 425         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
 426                                USB_PHY_CLK_VALID) == 0)
 427                 return;
 428
 429         if (phy->is_legacy_phy) {
 430                 val = readl_relaxed(base + USB_SUSP_CTRL);
 431                 val |= USB_SUSP_CLR;
 432                 writel_relaxed(val, base + USB_SUSP_CTRL);
 433
 434                 usleep_range(10, 100);
 435
 436                 val = readl_relaxed(base + USB_SUSP_CTRL);
 437                 val &= ~USB_SUSP_CLR;
 438                 writel_relaxed(val, base + USB_SUSP_CTRL);
 439         } else {
 440                 set_phcd(phy, false);
 441         }
 442
 443         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
 444                                USB_PHY_CLK_VALID))
 445                 dev_err(phy->u_phy.dev,
 446                         "Timeout waiting for PHY to stabilize on enable\n");
 447 }
 448
 449 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
 450 {
 451         struct tegra_utmip_config *config = phy->config;
 452         void __iomem *base = phy->regs;
 453         u32 val;
 454         int err;
 455
 456         val = readl_relaxed(base + USB_SUSP_CTRL);
 457         val |= UTMIP_RESET;
 458         writel_relaxed(val, base + USB_SUSP_CTRL);
 459
 460         if (phy->is_legacy_phy) {
 461                 val = readl_relaxed(base + USB1_LEGACY_CTRL);
 462                 val |= USB1_NO_LEGACY_MODE;
 463                 writel_relaxed(val, base + USB1_LEGACY_CTRL);
 464         }
 465
 466         val = readl_relaxed(base + UTMIP_TX_CFG0);
 467         val |= UTMIP_FS_PREABMLE_J;
 468         writel_relaxed(val, base + UTMIP_TX_CFG0);
 469
 470         val = readl_relaxed(base + UTMIP_HSRX_CFG0);
 471         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
 472         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
 473         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
 474         writel_relaxed(val, base + UTMIP_HSRX_CFG0);
 475
 476         val = readl_relaxed(base + UTMIP_HSRX_CFG1);
 477         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
 478         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
 479         writel_relaxed(val, base + UTMIP_HSRX_CFG1);
 480
 481         val = readl_relaxed(base + UTMIP_DEBOUNCE_CFG0);
 482         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
 483         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
 484         writel_relaxed(val, base + UTMIP_DEBOUNCE_CFG0);
 485
 486         val = readl_relaxed(base + UTMIP_MISC_CFG0);
 487         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
 488         writel_relaxed(val, base + UTMIP_MISC_CFG0);
 489
 490         if (!phy->soc_config->utmi_pll_config_in_car_module) {
 491                 val = readl_relaxed(base + UTMIP_MISC_CFG1);
 492                 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) |
 493                         UTMIP_PLLU_STABLE_COUNT(~0));
 494                 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
 495                         UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
 496                 writel_relaxed(val, base + UTMIP_MISC_CFG1);
 497
 498                 val = readl_relaxed(base + UTMIP_PLL_CFG1);
 499                 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) |
 500                         UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
 501                 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
 502                         UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
 503                 writel_relaxed(val, base + UTMIP_PLL_CFG1);
 504         }
 505
 506         if (phy->mode == USB_DR_MODE_PERIPHERAL) {
 507                 val = readl_relaxed(base + USB_SUSP_CTRL);
 508                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
 509                 writel_relaxed(val, base + USB_SUSP_CTRL);
 510
 511                 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
 512                 val &= ~UTMIP_PD_CHRG;
 513                 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
 514         } else {
 515                 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
 516                 val |= UTMIP_PD_CHRG;
 517                 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
 518         }
 519
 520         err = utmip_pad_power_on(phy);
 521         if (err)
 522                 return err;
 523
 524         val = readl_relaxed(base + UTMIP_XCVR_CFG0);
 525         val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
 526                  UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL |
 527                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) |
 528                  UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0));
 529
 530         if (!config->xcvr_setup_use_fuses) {
 531                 val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
 532                 val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup);
 533         }
 534         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
 535         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
 536
 537         if (phy->soc_config->requires_extra_tuning_parameters) {
 538                 val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
 539                 val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew);
 540                 val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew);
 541         }
 542         writel_relaxed(val, base + UTMIP_XCVR_CFG0);
 543
 544         val = readl_relaxed(base + UTMIP_XCVR_CFG1);
 545         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
 546                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
 547         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
 548         writel_relaxed(val, base + UTMIP_XCVR_CFG1);
 549
 550         val = readl_relaxed(base + UTMIP_BIAS_CFG1);
 551         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
 552         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
 553         writel_relaxed(val, base + UTMIP_BIAS_CFG1);
 554
 555         val = readl_relaxed(base + UTMIP_SPARE_CFG0);
 556         if (config->xcvr_setup_use_fuses)
 557                 val |= FUSE_SETUP_SEL;
 558         else
 559                 val &= ~FUSE_SETUP_SEL;
 560         writel_relaxed(val, base + UTMIP_SPARE_CFG0);
 561
 562         if (!phy->is_legacy_phy) {
 563                 val = readl_relaxed(base + USB_SUSP_CTRL);
 564                 val |= UTMIP_PHY_ENABLE;
 565                 writel_relaxed(val, base + USB_SUSP_CTRL);
 566         }
 567
 568         val = readl_relaxed(base + USB_SUSP_CTRL);
 569         val &= ~UTMIP_RESET;
 570         writel_relaxed(val, base + USB_SUSP_CTRL);
 571
 572         if (phy->is_legacy_phy) {
 573                 val = readl_relaxed(base + USB1_LEGACY_CTRL);
 574                 val &= ~USB1_VBUS_SENSE_CTL_MASK;
 575                 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
 576                 writel_relaxed(val, base + USB1_LEGACY_CTRL);
 577
 578                 val = readl_relaxed(base + USB_SUSP_CTRL);
 579                 val &= ~USB_SUSP_SET;
 580                 writel_relaxed(val, base + USB_SUSP_CTRL);
 581         }
 582
 583         utmi_phy_clk_enable(phy);
 584
 585         if (phy->soc_config->requires_usbmode_setup) {
 586                 val = readl_relaxed(base + USB_USBMODE);
 587                 val &= ~USB_USBMODE_MASK;
 588                 if (phy->mode == USB_DR_MODE_HOST)
 589                         val |= USB_USBMODE_HOST;
 590                 else
 591                         val |= USB_USBMODE_DEVICE;
 592                 writel_relaxed(val, base + USB_USBMODE);
 593         }
 594
 595         if (!phy->is_legacy_phy)
 596                 set_pts(phy, 0);
 597
 598         return 0;
 599 }
 600
 601 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
 602 {
 603         void __iomem *base = phy->regs;
 604         u32 val;
 605
 606         utmi_phy_clk_disable(phy);
 607
 608         if (phy->mode == USB_DR_MODE_PERIPHERAL) {
 609                 val = readl_relaxed(base + USB_SUSP_CTRL);
 610                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
 611                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
 612                 writel_relaxed(val, base + USB_SUSP_CTRL);
 613         }
 614
 615         val = readl_relaxed(base + USB_SUSP_CTRL);
 616         val |= UTMIP_RESET;
 617         writel_relaxed(val, base + USB_SUSP_CTRL);
 618
 619         val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
 620         val |= UTMIP_PD_CHRG;
 621         writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
 622
 623         val = readl_relaxed(base + UTMIP_XCVR_CFG0);
 624         val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
 625                UTMIP_FORCE_PDZI_POWERDOWN;
 626         writel_relaxed(val, base + UTMIP_XCVR_CFG0);
 627
 628         val = readl_relaxed(base + UTMIP_XCVR_CFG1);
 629         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
 630                UTMIP_FORCE_PDDR_POWERDOWN;
 631         writel_relaxed(val, base + UTMIP_XCVR_CFG1);
 632
 633         return utmip_pad_power_off(phy);
 634 }
 635
 636 static void utmi_phy_preresume(struct tegra_usb_phy *phy)
 637 {
 638         void __iomem *base = phy->regs;
 639         u32 val;
 640
 641         val = readl_relaxed(base + UTMIP_TX_CFG0);
 642         val |= UTMIP_HS_DISCON_DISABLE;
 643         writel_relaxed(val, base + UTMIP_TX_CFG0);
 644 }
 645
 646 static void utmi_phy_postresume(struct tegra_usb_phy *phy)
 647 {
 648         void __iomem *base = phy->regs;
 649         u32 val;
 650
 651         val = readl_relaxed(base + UTMIP_TX_CFG0);
 652         val &= ~UTMIP_HS_DISCON_DISABLE;
 653         writel_relaxed(val, base + UTMIP_TX_CFG0);
 654 }
 655
 656 static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
 657                                    enum tegra_usb_phy_port_speed port_speed)
 658 {
 659         void __iomem *base = phy->regs;
 660         u32 val;
 661
 662         val = readl_relaxed(base + UTMIP_MISC_CFG0);
 663         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
 664         if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
 665                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
 666         else
 667                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
 668         writel_relaxed(val, base + UTMIP_MISC_CFG0);
 669         usleep_range(1, 10);
 670
 671         val = readl_relaxed(base + UTMIP_MISC_CFG0);
 672         val |= UTMIP_DPDM_OBSERVE;
 673         writel_relaxed(val, base + UTMIP_MISC_CFG0);
 674         usleep_range(10, 100);
 675 }
 676
 677 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
 678 {
 679         void __iomem *base = phy->regs;
 680         u32 val;
 681
 682         val = readl_relaxed(base + UTMIP_MISC_CFG0);
 683         val &= ~UTMIP_DPDM_OBSERVE;
 684         writel_relaxed(val, base + UTMIP_MISC_CFG0);
 685         usleep_range(10, 100);
 686 }
 687
 688 static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
 689 {
 690         void __iomem *base = phy->regs;
 691         u32 val;
 692         int err;
 693
 694         gpiod_set_value_cansleep(phy->reset_gpio, 1);
 695
 696         err = clk_prepare_enable(phy->clk);
 697         if (err)
 698                 return err;
 699
 700         usleep_range(5000, 6000);
 701
 702         gpiod_set_value_cansleep(phy->reset_gpio, 0);
 703
 704         usleep_range(1000, 2000);
 705
 706         val = readl_relaxed(base + USB_SUSP_CTRL);
 707         val |= UHSIC_RESET;
 708         writel_relaxed(val, base + USB_SUSP_CTRL);
 709
 710         val = readl_relaxed(base + ULPI_TIMING_CTRL_0);
 711         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
 712         writel_relaxed(val, base + ULPI_TIMING_CTRL_0);
 713
 714         val = readl_relaxed(base + USB_SUSP_CTRL);
 715         val |= ULPI_PHY_ENABLE;
 716         writel_relaxed(val, base + USB_SUSP_CTRL);
 717
 718         val = 0;
 719         writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
 720
 721         val |= ULPI_DATA_TRIMMER_SEL(4);
 722         val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
 723         val |= ULPI_DIR_TRIMMER_SEL(4);
 724         writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
 725         usleep_range(10, 100);
 726
 727         val |= ULPI_DATA_TRIMMER_LOAD;
 728         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
 729         val |= ULPI_DIR_TRIMMER_LOAD;
 730         writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
 731
 732         /* Fix VbusInvalid due to floating VBUS */
 733         err = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
 734         if (err) {
 735                 dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", err);
 736                 goto disable_clk;
 737         }
 738
 739         err = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
 740         if (err) {
 741                 dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", err);
 742                 goto disable_clk;
 743         }
 744
 745         val = readl_relaxed(base + USB_SUSP_CTRL);
 746         val |= USB_SUSP_CLR;
 747         writel_relaxed(val, base + USB_SUSP_CTRL);
 748         usleep_range(100, 1000);
 749
 750         val = readl_relaxed(base + USB_SUSP_CTRL);
 751         val &= ~USB_SUSP_CLR;
 752         writel_relaxed(val, base + USB_SUSP_CTRL);
 753
 754         return 0;
 755
 756 disable_clk:
 757         clk_disable_unprepare(phy->clk);
 758
 759         return err;
 760 }
 761
 762 static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
 763 {
 764         gpiod_set_value_cansleep(phy->reset_gpio, 1);
 765         usleep_range(5000, 6000);
 766         clk_disable_unprepare(phy->clk);
 767
 768         return 0;
 769 }
 770
 771 static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
 772 {
 773         int err;
 774
 775         if (phy->powered_on)
 776                 return 0;
 777
 778         if (phy->is_ulpi_phy)
 779                 err = ulpi_phy_power_on(phy);
 780         else
 781                 err = utmi_phy_power_on(phy);
 782         if (err)
 783                 return err;
 784
 785         phy->powered_on = true;
 786
 787         return 0;
 788 }
 789
 790 static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
 791 {
 792         int err;
 793
 794         if (!phy->powered_on)
 795                 return 0;
 796
 797         if (phy->is_ulpi_phy)
 798                 err = ulpi_phy_power_off(phy);
 799         else
 800                 err = utmi_phy_power_off(phy);
 801         if (err)
 802                 return err;
 803
 804         phy->powered_on = false;
 805
 806         return 0;
 807 }
 808
 809 static void tegra_usb_phy_shutdown(struct usb_phy *u_phy)
 810 {
 811         struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
 812
 813         if (WARN_ON(!phy->freq))
 814                 return;
 815
 816         tegra_usb_phy_power_off(phy);
 817
 818         if (!phy->is_ulpi_phy)
 819                 utmip_pad_close(phy);
 820
 821         regulator_disable(phy->vbus);
 822         clk_disable_unprepare(phy->pll_u);
 823
 824         phy->freq = NULL;
 825 }
 826
 827 static int tegra_usb_phy_set_suspend(struct usb_phy *u_phy, int suspend)
 828 {
 829         struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
 830
 831         if (WARN_ON(!phy->freq))
 832                 return -EINVAL;
 833
 834         if (suspend)
 835                 return tegra_usb_phy_power_off(phy);
 836         else
 837                 return tegra_usb_phy_power_on(phy);
 838 }
 839
 840 static int tegra_usb_phy_init(struct usb_phy *u_phy)
 841 {
 842         struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
 843         unsigned long parent_rate;
 844         unsigned int i;
 845         int err;
 846
 847         if (WARN_ON(phy->freq))
 848                 return 0;
 849
 850         err = clk_prepare_enable(phy->pll_u);
 851         if (err)
 852                 return err;
 853
 854         parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
 855         for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
 856                 if (tegra_freq_table[i].freq == parent_rate) {
 857                         phy->freq = &tegra_freq_table[i];
 858                         break;
 859                 }
 860         }
 861         if (!phy->freq) {
 862                 dev_err(phy->u_phy.dev, "Invalid pll_u parent rate %ld\n",
 863                         parent_rate);
 864                 err = -EINVAL;
 865                 goto disable_clk;
 866         }
 867
 868         err = regulator_enable(phy->vbus);
 869         if (err) {
 870                 dev_err(phy->u_phy.dev,
 871                         "Failed to enable USB VBUS regulator: %d\n", err);
 872                 goto disable_clk;
 873         }
 874
 875         if (!phy->is_ulpi_phy) {
 876                 err = utmip_pad_open(phy);
 877                 if (err)
 878                         goto disable_vbus;
 879         }
 880
 881         err = tegra_usb_phy_power_on(phy);
 882         if (err)
 883                 goto close_phy;
 884
 885         return 0;
 886
 887 close_phy:
 888         if (!phy->is_ulpi_phy)
 889                 utmip_pad_close(phy);
 890
 891 disable_vbus:
 892         regulator_disable(phy->vbus);
 893
 894 disable_clk:
 895         clk_disable_unprepare(phy->pll_u);
 896
 897         phy->freq = NULL;
 898
 899         return err;
 900 }
 901
 902 void tegra_usb_phy_preresume(struct usb_phy *u_phy)
 903 {
 904         struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
 905
 906         if (!phy->is_ulpi_phy)
 907                 utmi_phy_preresume(phy);
 908 }
 909 EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
 910
 911 void tegra_usb_phy_postresume(struct usb_phy *u_phy)
 912 {
 913         struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
 914
 915         if (!phy->is_ulpi_phy)
 916                 utmi_phy_postresume(phy);
 917 }
 918 EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
 919
 920 void tegra_ehci_phy_restore_start(struct usb_phy *u_phy,
 921                                   enum tegra_usb_phy_port_speed port_speed)
 922 {
 923         struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
 924
 925         if (!phy->is_ulpi_phy)
 926                 utmi_phy_restore_start(phy, port_speed);
 927 }
 928 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
 929
 930 void tegra_ehci_phy_restore_end(struct usb_phy *u_phy)
 931 {
 932         struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
 933
 934         if (!phy->is_ulpi_phy)
 935                 utmi_phy_restore_end(phy);
 936 }
 937 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
 938
 939 static int read_utmi_param(struct platform_device *pdev, const char *param,
 940                            u8 *dest)
 941 {
 942         u32 value;
 943         int err;
 944
 945         err = of_property_read_u32(pdev->dev.of_node, param, &value);
 946         if (err)
 947                 dev_err(&pdev->dev,
 948                         "Failed to read USB UTMI parameter %s: %d\n",
 949                         param, err);
 950         else
 951                 *dest = value;
 952
 953         return err;
 954 }
 955
 956 static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy,
 957                           struct platform_device *pdev)
 958 {
 959         struct tegra_utmip_config *config;
 960         struct resource *res;
 961         int err;
 962
 963         tegra_phy->is_ulpi_phy = false;
 964
 965         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 966         if (!res) {
 967                 dev_err(&pdev->dev, "Failed to get UTMI pad regs\n");
 968                 return  -ENXIO;
 969         }
 970
 971         /*
 972          * Note that UTMI pad registers are shared by all PHYs, therefore
 973          * devm_platform_ioremap_resource() can't be used here.
 974          */
 975         tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start,
 976                                            resource_size(res));
 977         if (!tegra_phy->pad_regs) {
 978                 dev_err(&pdev->dev, "Failed to remap UTMI pad regs\n");
 979                 return -ENOMEM;
 980         }
 981
 982         tegra_phy->config = devm_kzalloc(&pdev->dev, sizeof(*config),
 983                                          GFP_KERNEL);
 984         if (!tegra_phy->config)
 985                 return -ENOMEM;
 986
 987         config = tegra_phy->config;
 988
 989         err = read_utmi_param(pdev, "nvidia,hssync-start-delay",
 990                               &config->hssync_start_delay);
 991         if (err)
 992                 return err;
 993
 994         err = read_utmi_param(pdev, "nvidia,elastic-limit",
 995                               &config->elastic_limit);
 996         if (err)
 997                 return err;
 998
 999         err = read_utmi_param(pdev, "nvidia,idle-wait-delay",
1000                               &config->idle_wait_delay);
1001         if (err)
1002                 return err;
1003
1004         err = read_utmi_param(pdev, "nvidia,term-range-adj",
1005                               &config->term_range_adj);
1006         if (err)
1007                 return err;
1008
1009         err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew",
1010                               &config->xcvr_lsfslew);
1011         if (err)
1012                 return err;
1013
1014         err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew",
1015                               &config->xcvr_lsrslew);
1016         if (err)
1017                 return err;
1018
1019         if (tegra_phy->soc_config->requires_extra_tuning_parameters) {
1020                 err = read_utmi_param(pdev, "nvidia,xcvr-hsslew",
1021                                       &config->xcvr_hsslew);
1022                 if (err)
1023                         return err;
1024
1025                 err = read_utmi_param(pdev, "nvidia,hssquelch-level",
1026                                       &config->hssquelch_level);
1027                 if (err)
1028                         return err;
1029
1030                 err = read_utmi_param(pdev, "nvidia,hsdiscon-level",
1031                                       &config->hsdiscon_level);
1032                 if (err)
1033                         return err;
1034         }
1035
1036         config->xcvr_setup_use_fuses = of_property_read_bool(
1037                 pdev->dev.of_node, "nvidia,xcvr-setup-use-fuses");
1038
1039         if (!config->xcvr_setup_use_fuses) {
1040                 err = read_utmi_param(pdev, "nvidia,xcvr-setup",
1041                                       &config->xcvr_setup);
1042                 if (err)
1043                         return err;
1044         }
1045
1046         return 0;
1047 }
1048
1049 static const struct tegra_phy_soc_config tegra20_soc_config = {
1050         .utmi_pll_config_in_car_module = false,
1051         .has_hostpc = false,
1052         .requires_usbmode_setup = false,
1053         .requires_extra_tuning_parameters = false,
1054 };
1055
1056 static const struct tegra_phy_soc_config tegra30_soc_config = {
1057         .utmi_pll_config_in_car_module = true,
1058         .has_hostpc = true,
1059         .requires_usbmode_setup = true,
1060         .requires_extra_tuning_parameters = true,
1061 };
1062
1063 static const struct of_device_id tegra_usb_phy_id_table[] = {
1064         { .compatible = "nvidia,tegra30-usb-phy", .data = &tegra30_soc_config },
1065         { .compatible = "nvidia,tegra20-usb-phy", .data = &tegra20_soc_config },
1066         { },
1067 };
1068 MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table);
1069
1070 static int tegra_usb_phy_probe(struct platform_device *pdev)
1071 {
1072         struct device_node *np = pdev->dev.of_node;
1073         struct tegra_usb_phy *tegra_phy;
1074         enum usb_phy_interface phy_type;
1075         struct reset_control *reset;
1076         struct gpio_desc *gpiod;
1077         struct resource *res;
1078         struct usb_phy *phy;
1079         int err;
1080
1081         tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL);
1082         if (!tegra_phy)
1083                 return -ENOMEM;
1084
1085         tegra_phy->soc_config = of_device_get_match_data(&pdev->dev);
1086
1087         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1088         if (!res) {
1089                 dev_err(&pdev->dev, "Failed to get I/O memory\n");
1090                 return  -ENXIO;
1091         }
1092
1093         /*
1094          * Note that PHY and USB controller are using shared registers,
1095          * therefore devm_platform_ioremap_resource() can't be used here.
1096          */
1097         tegra_phy->regs = devm_ioremap(&pdev->dev, res->start,
1098                                        resource_size(res));
1099         if (!tegra_phy->regs) {
1100                 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
1101                 return -ENOMEM;
1102         }
1103
1104         tegra_phy->is_legacy_phy =
1105                 of_property_read_bool(np, "nvidia,has-legacy-mode");
1106
1107         if (of_find_property(np, "dr_mode", NULL))
1108                 tegra_phy->mode = usb_get_dr_mode(&pdev->dev);
1109         else
1110                 tegra_phy->mode = USB_DR_MODE_HOST;
1111
1112         if (tegra_phy->mode == USB_DR_MODE_UNKNOWN) {
1113                 dev_err(&pdev->dev, "dr_mode is invalid\n");
1114                 return -EINVAL;
1115         }
1116
1117         /* On some boards, the VBUS regulator doesn't need to be controlled */
1118         tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
1119         if (IS_ERR(tegra_phy->vbus))
1120                 return PTR_ERR(tegra_phy->vbus);
1121
1122         tegra_phy->pll_u = devm_clk_get(&pdev->dev, "pll_u");
1123         err = PTR_ERR_OR_ZERO(tegra_phy->pll_u);
1124         if (err) {
1125                 dev_err(&pdev->dev, "Failed to get pll_u clock: %d\n", err);
1126                 return err;
1127         }
1128
1129         phy_type = of_usb_get_phy_mode(np);
1130         switch (phy_type) {
1131         case USBPHY_INTERFACE_MODE_UTMI:
1132                 err = utmi_phy_probe(tegra_phy, pdev);
1133                 if (err)
1134                         return err;
1135
1136                 tegra_phy->pad_clk = devm_clk_get(&pdev->dev, "utmi-pads");
1137                 err = PTR_ERR_OR_ZERO(tegra_phy->pad_clk);
1138                 if (err) {
1139                         dev_err(&pdev->dev,
1140                                 "Failed to get UTMIP pad clock: %d\n", err);
1141                         return err;
1142                 }
1143
1144                 reset = devm_reset_control_get_optional_shared(&pdev->dev,
1145                                                                "utmi-pads");
1146                 err = PTR_ERR_OR_ZERO(reset);
1147                 if (err) {
1148                         dev_err(&pdev->dev,
1149                                 "Failed to get UTMI-pads reset: %d\n", err);
1150                         return err;
1151                 }
1152                 tegra_phy->pad_rst = reset;
1153                 break;
1154
1155         case USBPHY_INTERFACE_MODE_ULPI:
1156                 tegra_phy->is_ulpi_phy = true;
1157
1158                 tegra_phy->clk = devm_clk_get(&pdev->dev, "ulpi-link");
1159                 err = PTR_ERR_OR_ZERO(tegra_phy->clk);
1160                 if (err) {
1161                         dev_err(&pdev->dev,
1162                                 "Failed to get ULPI clock: %d\n", err);
1163                         return err;
1164                 }
1165
1166                 gpiod = devm_gpiod_get_from_of_node(&pdev->dev, np,
1167                                                     "nvidia,phy-reset-gpio",
1168                                                     0, GPIOD_OUT_HIGH,
1169                                                     "ulpi_phy_reset_b");
1170                 err = PTR_ERR_OR_ZERO(gpiod);
1171                 if (err) {
1172                         dev_err(&pdev->dev,
1173                                 "Request failed for reset GPIO: %d\n", err);
1174                         return err;
1175                 }
1176                 tegra_phy->reset_gpio = gpiod;
1177
1178                 phy = devm_otg_ulpi_create(&pdev->dev,
1179                                            &ulpi_viewport_access_ops, 0);
1180                 if (!phy) {
1181                         dev_err(&pdev->dev, "Failed to create ULPI OTG\n");
1182                         return -ENOMEM;
1183                 }
1184
1185                 tegra_phy->ulpi = phy;
1186                 tegra_phy->ulpi->io_priv = tegra_phy->regs + ULPI_VIEWPORT;
1187                 break;
1188
1189         default:
1190                 dev_err(&pdev->dev, "phy_type %u is invalid or unsupported\n",
1191                         phy_type);
1192                 return -EINVAL;
1193         }
1194
1195         tegra_phy->u_phy.dev = &pdev->dev;
1196         tegra_phy->u_phy.init = tegra_usb_phy_init;
1197         tegra_phy->u_phy.shutdown = tegra_usb_phy_shutdown;
1198         tegra_phy->u_phy.set_suspend = tegra_usb_phy_set_suspend;
1199
1200         platform_set_drvdata(pdev, tegra_phy);
1201
1202         return usb_add_phy_dev(&tegra_phy->u_phy);
1203 }
1204
1205 static int tegra_usb_phy_remove(struct platform_device *pdev)
1206 {
1207         struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev);
1208
1209         usb_remove_phy(&tegra_phy->u_phy);
1210
1211         return 0;
1212 }
1213
1214 static struct platform_driver tegra_usb_phy_driver = {
1215         .probe          = tegra_usb_phy_probe,
1216         .remove         = tegra_usb_phy_remove,
1217         .driver         = {
1218                 .name   = "tegra-phy",
1219                 .of_match_table = tegra_usb_phy_id_table,
1220         },
1221 };
1222 module_platform_driver(tegra_usb_phy_driver);
1223
1224 MODULE_DESCRIPTION("Tegra USB PHY driver");
1225 MODULE_LICENSE("GPL v2");