1 /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/extcon.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/platform_device.h>
24 #include <linux/clk.h>
25 #include <linux/slab.h>
26 #include <linux/interrupt.h>
27 #include <linux/err.h>
28 #include <linux/delay.h>
30 #include <linux/ioport.h>
31 #include <linux/uaccess.h>
32 #include <linux/debugfs.h>
33 #include <linux/seq_file.h>
34 #include <linux/pm_runtime.h>
36 #include <linux/of_device.h>
37 #include <linux/reboot.h>
38 #include <linux/reset.h>
39 #include <linux/types.h>
40 #include <linux/usb/otg.h>
42 #include <linux/usb.h>
43 #include <linux/usb/otg.h>
44 #include <linux/usb/of.h>
45 #include <linux/usb/ulpi.h>
46 #include <linux/usb/gadget.h>
47 #include <linux/usb/hcd.h>
48 #include <linux/usb/msm_hsusb_hw.h>
49 #include <linux/regulator/consumer.h>
54 * OTG_NO_CONTROL Id/VBUS notifications not required. Useful in host
56 * OTG_PHY_CONTROL Id/VBUS notifications comes form USB PHY.
57 * OTG_PMIC_CONTROL Id/VBUS notifications comes from PMIC hardware.
58 * OTG_USER_CONTROL Id/VBUS notifcations comes from User via sysfs.
61 enum otg_control_type {
71 * INVALID_PHY Unsupported PHY
72 * CI_45NM_INTEGRATED_PHY Chipidea 45nm integrated PHY
73 * SNPS_28NM_INTEGRATED_PHY Synopsis 28nm integrated PHY
76 enum msm_usb_phy_type {
78 CI_45NM_INTEGRATED_PHY,
79 SNPS_28NM_INTEGRATED_PHY,
82 #define IDEV_CHG_MAX 1500
86 * Different states involved in USB charger detection.
88 * USB_CHG_STATE_UNDEFINED USB charger is not connected or detection
89 * process is not yet started.
90 * USB_CHG_STATE_WAIT_FOR_DCD Waiting for Data pins contact.
91 * USB_CHG_STATE_DCD_DONE Data pin contact is detected.
92 * USB_CHG_STATE_PRIMARY_DONE Primary detection is completed (Detects
93 * between SDP and DCP/CDP).
94 * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
95 * between DCP and CDP).
96 * USB_CHG_STATE_DETECTED USB charger type is determined.
100 USB_CHG_STATE_UNDEFINED = 0,
101 USB_CHG_STATE_WAIT_FOR_DCD,
102 USB_CHG_STATE_DCD_DONE,
103 USB_CHG_STATE_PRIMARY_DONE,
104 USB_CHG_STATE_SECONDARY_DONE,
105 USB_CHG_STATE_DETECTED,
111 * USB_INVALID_CHARGER Invalid USB charger.
112 * USB_SDP_CHARGER Standard downstream port. Refers to a downstream port
113 * on USB2.0 compliant host/hub.
114 * USB_DCP_CHARGER Dedicated charger port (AC charger/ Wall charger).
115 * USB_CDP_CHARGER Charging downstream port. Enumeration can happen and
116 * IDEV_CHG_MAX can be drawn irrespective of USB state.
120 USB_INVALID_CHARGER = 0,
127 * struct msm_otg_platform_data - platform device data
128 * for msm_otg driver.
129 * @phy_init_seq: PHY configuration sequence values. Value of -1 is reserved as
130 * "do not overwrite default vaule at this address".
131 * @phy_init_sz: PHY configuration sequence size.
132 * @vbus_power: VBUS power on/off routine.
133 * @power_budget: VBUS power budget in mA (0 will be treated as 500mA).
134 * @mode: Supported mode (OTG/peripheral/host).
135 * @otg_control: OTG switch controlled by user/Id pin
137 struct msm_otg_platform_data {
140 void (*vbus_power)(bool on);
141 unsigned power_budget;
142 enum usb_dr_mode mode;
143 enum otg_control_type otg_control;
144 enum msm_usb_phy_type phy_type;
145 void (*setup_gpio)(enum usb_otg_state state);
149 * struct msm_otg: OTG driver data. Shared by HCD and DCD.
150 * @otg: USB OTG Transceiver structure.
151 * @pdata: otg device platform data.
152 * @irq: IRQ number assigned for HSUSB controller.
153 * @clk: clock struct of usb_hs_clk.
154 * @pclk: clock struct of usb_hs_pclk.
155 * @core_clk: clock struct of usb_hs_core_clk.
156 * @regs: ioremapped register base address.
157 * @inputs: OTG state machine inputs(Id, SessValid etc).
158 * @sm_work: OTG state machine work.
159 * @in_lpm: indicates low power mode (LPM) state.
160 * @async_int: Async interrupt arrived.
161 * @cur_power: The amount of mA available from downstream port.
162 * @chg_work: Charger detection work.
163 * @chg_state: The state of charger detection process.
164 * @chg_type: The type of charger attached.
165 * @dcd_retires: The retry count used to track Data contact
167 * @manual_pullup: true if VBUS is not routed to USB controller/phy
168 * and controller driver therefore enables pull-up explicitly before
169 * starting controller using usbcmd run/stop bit.
170 * @vbus: VBUS signal state trakining, using extcon framework
171 * @id: ID signal state trakining, using extcon framework
172 * @switch_gpio: Descriptor for GPIO used to control external Dual
174 * @reboot: Used to inform the driver to route USB D+/D- line to Device
179 struct msm_otg_platform_data *pdata;
183 struct clk *core_clk;
187 unsigned long inputs;
188 struct work_struct sm_work;
193 struct delayed_work chg_work;
194 enum usb_chg_state chg_state;
195 enum usb_chg_type chg_type;
197 struct regulator *v3p3;
198 struct regulator *v1p8;
199 struct regulator *vddcx;
201 struct reset_control *phy_rst;
202 struct reset_control *link_rst;
207 struct gpio_desc *switch_gpio;
208 struct notifier_block reboot;
211 #define MSM_USB_BASE (motg->regs)
212 #define DRIVER_NAME "msm_otg"
214 #define ULPI_IO_TIMEOUT_USEC (10 * 1000)
215 #define LINK_RESET_TIMEOUT_USEC (250 * 1000)
217 #define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
218 #define USB_PHY_3P3_VOL_MAX 3300000 /* uV */
219 #define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
220 #define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
222 #define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
223 #define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
224 #define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
225 #define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
227 #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
228 #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
229 #define USB_PHY_SUSP_DIG_VOL 500000 /* uV */
237 static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
242 ret = regulator_set_voltage(motg->vddcx,
243 motg->vdd_levels[VDD_LEVEL_MIN],
244 motg->vdd_levels[VDD_LEVEL_MAX]);
246 dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
250 ret = regulator_enable(motg->vddcx);
252 dev_err(motg->phy.dev, "unable to enable hsusb vddcx\n");
254 ret = regulator_set_voltage(motg->vddcx, 0,
255 motg->vdd_levels[VDD_LEVEL_MAX]);
257 dev_err(motg->phy.dev, "Cannot set vddcx voltage\n");
258 ret = regulator_disable(motg->vddcx);
260 dev_err(motg->phy.dev, "unable to disable hsusb vddcx\n");
266 static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
271 rc = regulator_set_voltage(motg->v3p3, USB_PHY_3P3_VOL_MIN,
272 USB_PHY_3P3_VOL_MAX);
274 dev_err(motg->phy.dev, "Cannot set v3p3 voltage\n");
277 rc = regulator_enable(motg->v3p3);
279 dev_err(motg->phy.dev, "unable to enable the hsusb 3p3\n");
282 rc = regulator_set_voltage(motg->v1p8, USB_PHY_1P8_VOL_MIN,
283 USB_PHY_1P8_VOL_MAX);
285 dev_err(motg->phy.dev, "Cannot set v1p8 voltage\n");
288 rc = regulator_enable(motg->v1p8);
290 dev_err(motg->phy.dev, "unable to enable the hsusb 1p8\n");
297 regulator_disable(motg->v1p8);
299 regulator_disable(motg->v3p3);
304 static int msm_hsusb_ldo_set_mode(struct msm_otg *motg, int on)
309 ret = regulator_set_load(motg->v1p8, USB_PHY_1P8_HPM_LOAD);
311 pr_err("Could not set HPM for v1p8\n");
314 ret = regulator_set_load(motg->v3p3, USB_PHY_3P3_HPM_LOAD);
316 pr_err("Could not set HPM for v3p3\n");
317 regulator_set_load(motg->v1p8, USB_PHY_1P8_LPM_LOAD);
321 ret = regulator_set_load(motg->v1p8, USB_PHY_1P8_LPM_LOAD);
323 pr_err("Could not set LPM for v1p8\n");
324 ret = regulator_set_load(motg->v3p3, USB_PHY_3P3_LPM_LOAD);
326 pr_err("Could not set LPM for v3p3\n");
329 pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
330 return ret < 0 ? ret : 0;
333 static int ulpi_read(struct usb_phy *phy, u32 reg)
335 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
338 /* initiate read operation */
339 writel(ULPI_RUN | ULPI_READ | ULPI_ADDR(reg),
342 /* wait for completion */
343 while (cnt < ULPI_IO_TIMEOUT_USEC) {
344 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
350 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
351 dev_err(phy->dev, "ulpi_read: timeout %08x\n",
352 readl(USB_ULPI_VIEWPORT));
355 return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT));
358 static int ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
360 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
363 /* initiate write operation */
364 writel(ULPI_RUN | ULPI_WRITE |
365 ULPI_ADDR(reg) | ULPI_DATA(val),
368 /* wait for completion */
369 while (cnt < ULPI_IO_TIMEOUT_USEC) {
370 if (!(readl(USB_ULPI_VIEWPORT) & ULPI_RUN))
376 if (cnt >= ULPI_IO_TIMEOUT_USEC) {
377 dev_err(phy->dev, "ulpi_write: timeout\n");
383 static struct usb_phy_io_ops msm_otg_io_ops = {
388 static void ulpi_init(struct msm_otg *motg)
390 struct msm_otg_platform_data *pdata = motg->pdata;
391 int *seq = pdata->phy_init_seq, idx;
392 u32 addr = ULPI_EXT_VENDOR_SPECIFIC;
394 for (idx = 0; idx < pdata->phy_init_sz; idx++) {
398 dev_vdbg(motg->phy.dev, "ulpi: write 0x%02x to 0x%02x\n",
399 seq[idx], addr + idx);
400 ulpi_write(&motg->phy, seq[idx], addr + idx);
404 static int msm_phy_notify_disconnect(struct usb_phy *phy,
405 enum usb_device_speed speed)
407 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
410 if (motg->manual_pullup) {
411 val = ULPI_MISC_A_VBUSVLDEXT | ULPI_MISC_A_VBUSVLDEXTSEL;
412 usb_phy_io_write(phy, val, ULPI_CLR(ULPI_MISC_A));
416 * Put the transceiver in non-driving mode. Otherwise host
417 * may not detect soft-disconnection.
419 val = ulpi_read(phy, ULPI_FUNC_CTRL);
420 val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
421 val |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
422 ulpi_write(phy, val, ULPI_FUNC_CTRL);
427 static int msm_otg_link_clk_reset(struct msm_otg *motg, bool assert)
432 ret = reset_control_assert(motg->link_rst);
434 ret = reset_control_deassert(motg->link_rst);
437 dev_err(motg->phy.dev, "usb link clk reset %s failed\n",
438 assert ? "assert" : "deassert");
443 static int msm_otg_phy_clk_reset(struct msm_otg *motg)
448 ret = reset_control_reset(motg->phy_rst);
451 dev_err(motg->phy.dev, "usb phy clk reset failed\n");
456 static int msm_link_reset(struct msm_otg *motg)
461 ret = msm_otg_link_clk_reset(motg, 1);
465 /* wait for 1ms delay as suggested in HPG. */
466 usleep_range(1000, 1200);
468 ret = msm_otg_link_clk_reset(motg, 0);
472 if (motg->phy_number)
473 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
475 /* put transceiver in serial mode as part of reset */
476 val = readl(USB_PORTSC) & ~PORTSC_PTS_MASK;
477 writel(val | PORTSC_PTS_SERIAL, USB_PORTSC);
482 static int msm_otg_reset(struct usb_phy *phy)
484 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
487 writel(USBCMD_RESET, USB_USBCMD);
488 while (cnt < LINK_RESET_TIMEOUT_USEC) {
489 if (!(readl(USB_USBCMD) & USBCMD_RESET))
494 if (cnt >= LINK_RESET_TIMEOUT_USEC)
497 /* select ULPI phy and clear other status/control bits in PORTSC */
498 writel(PORTSC_PTS_ULPI, USB_PORTSC);
500 writel(0x0, USB_AHBBURST);
501 writel(0x08, USB_AHBMODE);
503 if (motg->phy_number)
504 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
508 static void msm_phy_reset(struct msm_otg *motg)
512 if (motg->pdata->phy_type != SNPS_28NM_INTEGRATED_PHY) {
513 msm_otg_phy_clk_reset(motg);
518 if (motg->phy_number)
519 addr = USB_PHY_CTRL2;
521 /* Assert USB PHY_POR */
522 writel(readl(addr) | PHY_POR_ASSERT, addr);
525 * wait for minimum 10 microseconds as suggested in HPG.
526 * Use a slightly larger value since the exact value didn't
527 * work 100% of the time.
531 /* Deassert USB PHY_POR */
532 writel(readl(addr) & ~PHY_POR_ASSERT, addr);
535 static int msm_usb_reset(struct usb_phy *phy)
537 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
540 if (!IS_ERR(motg->core_clk))
541 clk_prepare_enable(motg->core_clk);
543 ret = msm_link_reset(motg);
545 dev_err(phy->dev, "phy_reset failed\n");
549 ret = msm_otg_reset(&motg->phy);
551 dev_err(phy->dev, "link reset failed\n");
557 /* Reset USB PHY after performing USB Link RESET */
560 if (!IS_ERR(motg->core_clk))
561 clk_disable_unprepare(motg->core_clk);
566 static int msm_phy_init(struct usb_phy *phy)
568 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
569 struct msm_otg_platform_data *pdata = motg->pdata;
570 u32 val, ulpi_val = 0;
572 /* Program USB PHY Override registers. */
576 * It is recommended in HPG to reset USB PHY after programming
577 * USB PHY Override registers.
581 if (pdata->otg_control == OTG_PHY_CONTROL) {
582 val = readl(USB_OTGSC);
583 if (pdata->mode == USB_DR_MODE_OTG) {
584 ulpi_val = ULPI_INT_IDGRD | ULPI_INT_SESS_VALID;
585 val |= OTGSC_IDIE | OTGSC_BSVIE;
586 } else if (pdata->mode == USB_DR_MODE_PERIPHERAL) {
587 ulpi_val = ULPI_INT_SESS_VALID;
590 writel(val, USB_OTGSC);
591 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_RISE);
592 ulpi_write(phy, ulpi_val, ULPI_USB_INT_EN_FALL);
595 if (motg->manual_pullup) {
596 val = ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT;
597 ulpi_write(phy, val, ULPI_SET(ULPI_MISC_A));
599 val = readl(USB_GENCONFIG_2);
600 val |= GENCONFIG_2_SESS_VLD_CTRL_EN;
601 writel(val, USB_GENCONFIG_2);
603 val = readl(USB_USBCMD);
604 val |= USBCMD_SESS_VLD_CTRL;
605 writel(val, USB_USBCMD);
607 val = ulpi_read(phy, ULPI_FUNC_CTRL);
608 val &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
609 val |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
610 ulpi_write(phy, val, ULPI_FUNC_CTRL);
613 if (motg->phy_number)
614 writel(readl(USB_PHY_CTRL2) | BIT(16), USB_PHY_CTRL2);
619 #define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
620 #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
624 static int msm_hsusb_config_vddcx(struct msm_otg *motg, int high)
626 int max_vol = motg->vdd_levels[VDD_LEVEL_MAX];
631 min_vol = motg->vdd_levels[VDD_LEVEL_MIN];
633 min_vol = motg->vdd_levels[VDD_LEVEL_NONE];
635 ret = regulator_set_voltage(motg->vddcx, min_vol, max_vol);
637 pr_err("Cannot set vddcx voltage\n");
641 pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
646 static int msm_otg_suspend(struct msm_otg *motg)
648 struct usb_phy *phy = &motg->phy;
649 struct usb_bus *bus = phy->otg->host;
650 struct msm_otg_platform_data *pdata = motg->pdata;
654 if (atomic_read(&motg->in_lpm))
657 disable_irq(motg->irq);
659 * Chipidea 45-nm PHY suspend sequence:
661 * Interrupt Latch Register auto-clear feature is not present
662 * in all PHY versions. Latch register is clear on read type.
663 * Clear latch register to avoid spurious wakeup from
664 * low power mode (LPM).
666 * PHY comparators are disabled when PHY enters into low power
667 * mode (LPM). Keep PHY comparators ON in LPM only when we expect
668 * VBUS/Id notifications from USB PHY. Otherwise turn off USB
669 * PHY comparators. This save significant amount of power.
671 * PLL is not turned off when PHY enters into low power mode (LPM).
672 * Disable PLL for maximum power savings.
675 if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
676 ulpi_read(phy, 0x14);
677 if (pdata->otg_control == OTG_PHY_CONTROL)
678 ulpi_write(phy, 0x01, 0x30);
679 ulpi_write(phy, 0x08, 0x09);
683 * PHY may take some time or even fail to enter into low power
684 * mode (LPM). Hence poll for 500 msec and reset the PHY and link
687 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
688 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
689 if (readl(USB_PORTSC) & PORTSC_PHCD)
695 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC) {
696 dev_err(phy->dev, "Unable to suspend PHY\n");
698 enable_irq(motg->irq);
703 * PHY has capability to generate interrupt asynchronously in low
704 * power mode (LPM). This interrupt is level triggered. So USB IRQ
705 * line must be disabled till async interrupt enable bit is cleared
706 * in USBCMD register. Assert STP (ULPI interface STOP signal) to
707 * block data communication from PHY.
709 writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
712 if (motg->phy_number)
713 addr = USB_PHY_CTRL2;
715 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
716 motg->pdata->otg_control == OTG_PMIC_CONTROL)
717 writel(readl(addr) | PHY_RETEN, addr);
719 clk_disable_unprepare(motg->pclk);
720 clk_disable_unprepare(motg->clk);
721 if (!IS_ERR(motg->core_clk))
722 clk_disable_unprepare(motg->core_clk);
724 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
725 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
726 msm_hsusb_ldo_set_mode(motg, 0);
727 msm_hsusb_config_vddcx(motg, 0);
730 if (device_may_wakeup(phy->dev))
731 enable_irq_wake(motg->irq);
733 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
735 atomic_set(&motg->in_lpm, 1);
736 enable_irq(motg->irq);
738 dev_info(phy->dev, "USB in low power mode\n");
743 static int msm_otg_resume(struct msm_otg *motg)
745 struct usb_phy *phy = &motg->phy;
746 struct usb_bus *bus = phy->otg->host;
751 if (!atomic_read(&motg->in_lpm))
754 clk_prepare_enable(motg->pclk);
755 clk_prepare_enable(motg->clk);
756 if (!IS_ERR(motg->core_clk))
757 clk_prepare_enable(motg->core_clk);
759 if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
760 motg->pdata->otg_control == OTG_PMIC_CONTROL) {
763 if (motg->phy_number)
764 addr = USB_PHY_CTRL2;
766 msm_hsusb_ldo_set_mode(motg, 1);
767 msm_hsusb_config_vddcx(motg, 1);
768 writel(readl(addr) & ~PHY_RETEN, addr);
771 temp = readl(USB_USBCMD);
772 temp &= ~ASYNC_INTR_CTRL;
773 temp &= ~ULPI_STP_CTRL;
774 writel(temp, USB_USBCMD);
777 * PHY comes out of low power mode (LPM) in case of wakeup
778 * from asynchronous interrupt.
780 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
781 goto skip_phy_resume;
783 writel(readl(USB_PORTSC) & ~PORTSC_PHCD, USB_PORTSC);
784 while (cnt < PHY_RESUME_TIMEOUT_USEC) {
785 if (!(readl(USB_PORTSC) & PORTSC_PHCD))
791 if (cnt >= PHY_RESUME_TIMEOUT_USEC) {
793 * This is a fatal error. Reset the link and
794 * PHY. USB state can not be restored. Re-insertion
795 * of USB cable is the only way to get USB working.
797 dev_err(phy->dev, "Unable to resume USB. Re-plugin the cable\n");
802 if (device_may_wakeup(phy->dev))
803 disable_irq_wake(motg->irq);
805 set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
807 atomic_set(&motg->in_lpm, 0);
809 if (motg->async_int) {
811 pm_runtime_put(phy->dev);
812 enable_irq(motg->irq);
815 dev_info(phy->dev, "USB exited from low power mode\n");
821 static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA)
823 if (motg->cur_power == mA)
826 /* TODO: Notify PMIC about available current */
827 dev_info(motg->phy.dev, "Avail curr from USB = %u\n", mA);
828 motg->cur_power = mA;
831 static void msm_otg_start_host(struct usb_phy *phy, int on)
833 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
834 struct msm_otg_platform_data *pdata = motg->pdata;
840 hcd = bus_to_hcd(phy->otg->host);
843 dev_dbg(phy->dev, "host on\n");
845 if (pdata->vbus_power)
846 pdata->vbus_power(1);
848 * Some boards have a switch cotrolled by gpio
849 * to enable/disable internal HUB. Enable internal
850 * HUB before kicking the host.
852 if (pdata->setup_gpio)
853 pdata->setup_gpio(OTG_STATE_A_HOST);
855 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
856 device_wakeup_enable(hcd->self.controller);
859 dev_dbg(phy->dev, "host off\n");
864 if (pdata->setup_gpio)
865 pdata->setup_gpio(OTG_STATE_UNDEFINED);
866 if (pdata->vbus_power)
867 pdata->vbus_power(0);
871 static int msm_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
873 struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
877 * Fail host registration if this board can support
878 * only peripheral configuration.
880 if (motg->pdata->mode == USB_DR_MODE_PERIPHERAL) {
881 dev_info(otg->usb_phy->dev, "Host mode is not supported\n");
886 if (otg->state == OTG_STATE_A_HOST) {
887 pm_runtime_get_sync(otg->usb_phy->dev);
888 msm_otg_start_host(otg->usb_phy, 0);
890 otg->state = OTG_STATE_UNDEFINED;
891 schedule_work(&motg->sm_work);
899 hcd = bus_to_hcd(host);
900 hcd->power_budget = motg->pdata->power_budget;
903 dev_dbg(otg->usb_phy->dev, "host driver registered w/ tranceiver\n");
905 pm_runtime_get_sync(otg->usb_phy->dev);
906 schedule_work(&motg->sm_work);
911 static void msm_otg_start_peripheral(struct usb_phy *phy, int on)
913 struct msm_otg *motg = container_of(phy, struct msm_otg, phy);
914 struct msm_otg_platform_data *pdata = motg->pdata;
916 if (!phy->otg->gadget)
920 dev_dbg(phy->dev, "gadget on\n");
922 * Some boards have a switch cotrolled by gpio
923 * to enable/disable internal HUB. Disable internal
924 * HUB before kicking the gadget.
926 if (pdata->setup_gpio)
927 pdata->setup_gpio(OTG_STATE_B_PERIPHERAL);
928 usb_gadget_vbus_connect(phy->otg->gadget);
930 dev_dbg(phy->dev, "gadget off\n");
931 usb_gadget_vbus_disconnect(phy->otg->gadget);
932 if (pdata->setup_gpio)
933 pdata->setup_gpio(OTG_STATE_UNDEFINED);
938 static int msm_otg_set_peripheral(struct usb_otg *otg,
939 struct usb_gadget *gadget)
941 struct msm_otg *motg = container_of(otg->usb_phy, struct msm_otg, phy);
944 * Fail peripheral registration if this board can support
945 * only host configuration.
947 if (motg->pdata->mode == USB_DR_MODE_HOST) {
948 dev_info(otg->usb_phy->dev, "Peripheral mode is not supported\n");
953 if (otg->state == OTG_STATE_B_PERIPHERAL) {
954 pm_runtime_get_sync(otg->usb_phy->dev);
955 msm_otg_start_peripheral(otg->usb_phy, 0);
957 otg->state = OTG_STATE_UNDEFINED;
958 schedule_work(&motg->sm_work);
965 otg->gadget = gadget;
966 dev_dbg(otg->usb_phy->dev,
967 "peripheral driver registered w/ tranceiver\n");
969 pm_runtime_get_sync(otg->usb_phy->dev);
970 schedule_work(&motg->sm_work);
975 static bool msm_chg_check_secondary_det(struct msm_otg *motg)
977 struct usb_phy *phy = &motg->phy;
981 switch (motg->pdata->phy_type) {
982 case CI_45NM_INTEGRATED_PHY:
983 chg_det = ulpi_read(phy, 0x34);
984 ret = chg_det & (1 << 4);
986 case SNPS_28NM_INTEGRATED_PHY:
987 chg_det = ulpi_read(phy, 0x87);
996 static void msm_chg_enable_secondary_det(struct msm_otg *motg)
998 struct usb_phy *phy = &motg->phy;
1001 switch (motg->pdata->phy_type) {
1002 case CI_45NM_INTEGRATED_PHY:
1003 chg_det = ulpi_read(phy, 0x34);
1004 /* Turn off charger block */
1005 chg_det |= ~(1 << 1);
1006 ulpi_write(phy, chg_det, 0x34);
1008 /* control chg block via ULPI */
1009 chg_det &= ~(1 << 3);
1010 ulpi_write(phy, chg_det, 0x34);
1011 /* put it in host mode for enabling D- source */
1012 chg_det &= ~(1 << 2);
1013 ulpi_write(phy, chg_det, 0x34);
1014 /* Turn on chg detect block */
1015 chg_det &= ~(1 << 1);
1016 ulpi_write(phy, chg_det, 0x34);
1018 /* enable chg detection */
1019 chg_det &= ~(1 << 0);
1020 ulpi_write(phy, chg_det, 0x34);
1022 case SNPS_28NM_INTEGRATED_PHY:
1024 * Configure DM as current source, DP as current sink
1025 * and enable battery charging comparators.
1027 ulpi_write(phy, 0x8, 0x85);
1028 ulpi_write(phy, 0x2, 0x85);
1029 ulpi_write(phy, 0x1, 0x85);
1036 static bool msm_chg_check_primary_det(struct msm_otg *motg)
1038 struct usb_phy *phy = &motg->phy;
1042 switch (motg->pdata->phy_type) {
1043 case CI_45NM_INTEGRATED_PHY:
1044 chg_det = ulpi_read(phy, 0x34);
1045 ret = chg_det & (1 << 4);
1047 case SNPS_28NM_INTEGRATED_PHY:
1048 chg_det = ulpi_read(phy, 0x87);
1057 static void msm_chg_enable_primary_det(struct msm_otg *motg)
1059 struct usb_phy *phy = &motg->phy;
1062 switch (motg->pdata->phy_type) {
1063 case CI_45NM_INTEGRATED_PHY:
1064 chg_det = ulpi_read(phy, 0x34);
1065 /* enable chg detection */
1066 chg_det &= ~(1 << 0);
1067 ulpi_write(phy, chg_det, 0x34);
1069 case SNPS_28NM_INTEGRATED_PHY:
1071 * Configure DP as current source, DM as current sink
1072 * and enable battery charging comparators.
1074 ulpi_write(phy, 0x2, 0x85);
1075 ulpi_write(phy, 0x1, 0x85);
1082 static bool msm_chg_check_dcd(struct msm_otg *motg)
1084 struct usb_phy *phy = &motg->phy;
1088 switch (motg->pdata->phy_type) {
1089 case CI_45NM_INTEGRATED_PHY:
1090 line_state = ulpi_read(phy, 0x15);
1091 ret = !(line_state & 1);
1093 case SNPS_28NM_INTEGRATED_PHY:
1094 line_state = ulpi_read(phy, 0x87);
1095 ret = line_state & 2;
1103 static void msm_chg_disable_dcd(struct msm_otg *motg)
1105 struct usb_phy *phy = &motg->phy;
1108 switch (motg->pdata->phy_type) {
1109 case CI_45NM_INTEGRATED_PHY:
1110 chg_det = ulpi_read(phy, 0x34);
1111 chg_det &= ~(1 << 5);
1112 ulpi_write(phy, chg_det, 0x34);
1114 case SNPS_28NM_INTEGRATED_PHY:
1115 ulpi_write(phy, 0x10, 0x86);
1122 static void msm_chg_enable_dcd(struct msm_otg *motg)
1124 struct usb_phy *phy = &motg->phy;
1127 switch (motg->pdata->phy_type) {
1128 case CI_45NM_INTEGRATED_PHY:
1129 chg_det = ulpi_read(phy, 0x34);
1130 /* Turn on D+ current source */
1131 chg_det |= (1 << 5);
1132 ulpi_write(phy, chg_det, 0x34);
1134 case SNPS_28NM_INTEGRATED_PHY:
1135 /* Data contact detection enable */
1136 ulpi_write(phy, 0x10, 0x85);
1143 static void msm_chg_block_on(struct msm_otg *motg)
1145 struct usb_phy *phy = &motg->phy;
1146 u32 func_ctrl, chg_det;
1148 /* put the controller in non-driving mode */
1149 func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1150 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1151 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
1152 ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1154 switch (motg->pdata->phy_type) {
1155 case CI_45NM_INTEGRATED_PHY:
1156 chg_det = ulpi_read(phy, 0x34);
1157 /* control chg block via ULPI */
1158 chg_det &= ~(1 << 3);
1159 ulpi_write(phy, chg_det, 0x34);
1160 /* Turn on chg detect block */
1161 chg_det &= ~(1 << 1);
1162 ulpi_write(phy, chg_det, 0x34);
1165 case SNPS_28NM_INTEGRATED_PHY:
1166 /* Clear charger detecting control bits */
1167 ulpi_write(phy, 0x3F, 0x86);
1168 /* Clear alt interrupt latch and enable bits */
1169 ulpi_write(phy, 0x1F, 0x92);
1170 ulpi_write(phy, 0x1F, 0x95);
1178 static void msm_chg_block_off(struct msm_otg *motg)
1180 struct usb_phy *phy = &motg->phy;
1181 u32 func_ctrl, chg_det;
1183 switch (motg->pdata->phy_type) {
1184 case CI_45NM_INTEGRATED_PHY:
1185 chg_det = ulpi_read(phy, 0x34);
1186 /* Turn off charger block */
1187 chg_det |= ~(1 << 1);
1188 ulpi_write(phy, chg_det, 0x34);
1190 case SNPS_28NM_INTEGRATED_PHY:
1191 /* Clear charger detecting control bits */
1192 ulpi_write(phy, 0x3F, 0x86);
1193 /* Clear alt interrupt latch and enable bits */
1194 ulpi_write(phy, 0x1F, 0x92);
1195 ulpi_write(phy, 0x1F, 0x95);
1201 /* put the controller in normal mode */
1202 func_ctrl = ulpi_read(phy, ULPI_FUNC_CTRL);
1203 func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
1204 func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
1205 ulpi_write(phy, func_ctrl, ULPI_FUNC_CTRL);
1208 #define MSM_CHG_DCD_POLL_TIME (100 * HZ/1000) /* 100 msec */
1209 #define MSM_CHG_DCD_MAX_RETRIES 6 /* Tdcd_tmout = 6 * 100 msec */
1210 #define MSM_CHG_PRIMARY_DET_TIME (40 * HZ/1000) /* TVDPSRC_ON */
1211 #define MSM_CHG_SECONDARY_DET_TIME (40 * HZ/1000) /* TVDMSRC_ON */
1212 static void msm_chg_detect_work(struct work_struct *w)
1214 struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work);
1215 struct usb_phy *phy = &motg->phy;
1216 bool is_dcd, tmout, vout;
1217 unsigned long delay;
1219 dev_dbg(phy->dev, "chg detection work\n");
1220 switch (motg->chg_state) {
1221 case USB_CHG_STATE_UNDEFINED:
1222 pm_runtime_get_sync(phy->dev);
1223 msm_chg_block_on(motg);
1224 msm_chg_enable_dcd(motg);
1225 motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
1226 motg->dcd_retries = 0;
1227 delay = MSM_CHG_DCD_POLL_TIME;
1229 case USB_CHG_STATE_WAIT_FOR_DCD:
1230 is_dcd = msm_chg_check_dcd(motg);
1231 tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES;
1232 if (is_dcd || tmout) {
1233 msm_chg_disable_dcd(motg);
1234 msm_chg_enable_primary_det(motg);
1235 delay = MSM_CHG_PRIMARY_DET_TIME;
1236 motg->chg_state = USB_CHG_STATE_DCD_DONE;
1238 delay = MSM_CHG_DCD_POLL_TIME;
1241 case USB_CHG_STATE_DCD_DONE:
1242 vout = msm_chg_check_primary_det(motg);
1244 msm_chg_enable_secondary_det(motg);
1245 delay = MSM_CHG_SECONDARY_DET_TIME;
1246 motg->chg_state = USB_CHG_STATE_PRIMARY_DONE;
1248 motg->chg_type = USB_SDP_CHARGER;
1249 motg->chg_state = USB_CHG_STATE_DETECTED;
1253 case USB_CHG_STATE_PRIMARY_DONE:
1254 vout = msm_chg_check_secondary_det(motg);
1256 motg->chg_type = USB_DCP_CHARGER;
1258 motg->chg_type = USB_CDP_CHARGER;
1259 motg->chg_state = USB_CHG_STATE_SECONDARY_DONE;
1261 case USB_CHG_STATE_SECONDARY_DONE:
1262 motg->chg_state = USB_CHG_STATE_DETECTED;
1263 case USB_CHG_STATE_DETECTED:
1264 msm_chg_block_off(motg);
1265 dev_dbg(phy->dev, "charger = %d\n", motg->chg_type);
1266 schedule_work(&motg->sm_work);
1272 schedule_delayed_work(&motg->chg_work, delay);
1276 * We support OTG, Peripheral only and Host only configurations. In case
1277 * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1278 * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1279 * enabled when switch is controlled by user and default mode is supplied
1280 * by board file, which can be changed by userspace later.
1282 static void msm_otg_init_sm(struct msm_otg *motg)
1284 struct msm_otg_platform_data *pdata = motg->pdata;
1285 u32 otgsc = readl(USB_OTGSC);
1287 switch (pdata->mode) {
1288 case USB_DR_MODE_OTG:
1289 if (pdata->otg_control == OTG_PHY_CONTROL) {
1290 if (otgsc & OTGSC_ID)
1291 set_bit(ID, &motg->inputs);
1293 clear_bit(ID, &motg->inputs);
1295 if (otgsc & OTGSC_BSV)
1296 set_bit(B_SESS_VLD, &motg->inputs);
1298 clear_bit(B_SESS_VLD, &motg->inputs);
1299 } else if (pdata->otg_control == OTG_USER_CONTROL) {
1300 set_bit(ID, &motg->inputs);
1301 clear_bit(B_SESS_VLD, &motg->inputs);
1304 case USB_DR_MODE_HOST:
1305 clear_bit(ID, &motg->inputs);
1307 case USB_DR_MODE_PERIPHERAL:
1308 set_bit(ID, &motg->inputs);
1309 if (otgsc & OTGSC_BSV)
1310 set_bit(B_SESS_VLD, &motg->inputs);
1312 clear_bit(B_SESS_VLD, &motg->inputs);
1319 static void msm_otg_sm_work(struct work_struct *w)
1321 struct msm_otg *motg = container_of(w, struct msm_otg, sm_work);
1322 struct usb_otg *otg = motg->phy.otg;
1324 switch (otg->state) {
1325 case OTG_STATE_UNDEFINED:
1326 dev_dbg(otg->usb_phy->dev, "OTG_STATE_UNDEFINED state\n");
1327 msm_otg_reset(otg->usb_phy);
1328 msm_otg_init_sm(motg);
1329 otg->state = OTG_STATE_B_IDLE;
1331 case OTG_STATE_B_IDLE:
1332 dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_IDLE state\n");
1333 if (!test_bit(ID, &motg->inputs) && otg->host) {
1334 /* disable BSV bit */
1335 writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
1336 msm_otg_start_host(otg->usb_phy, 1);
1337 otg->state = OTG_STATE_A_HOST;
1338 } else if (test_bit(B_SESS_VLD, &motg->inputs)) {
1339 switch (motg->chg_state) {
1340 case USB_CHG_STATE_UNDEFINED:
1341 msm_chg_detect_work(&motg->chg_work.work);
1343 case USB_CHG_STATE_DETECTED:
1344 switch (motg->chg_type) {
1345 case USB_DCP_CHARGER:
1346 msm_otg_notify_charger(motg,
1349 case USB_CDP_CHARGER:
1350 msm_otg_notify_charger(motg,
1352 msm_otg_start_peripheral(otg->usb_phy,
1355 = OTG_STATE_B_PERIPHERAL;
1357 case USB_SDP_CHARGER:
1358 msm_otg_notify_charger(motg, IUNIT);
1359 msm_otg_start_peripheral(otg->usb_phy,
1362 = OTG_STATE_B_PERIPHERAL;
1373 * If charger detection work is pending, decrement
1374 * the pm usage counter to balance with the one that
1375 * is incremented in charger detection work.
1377 if (cancel_delayed_work_sync(&motg->chg_work)) {
1378 pm_runtime_put_sync(otg->usb_phy->dev);
1379 msm_otg_reset(otg->usb_phy);
1381 msm_otg_notify_charger(motg, 0);
1382 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1383 motg->chg_type = USB_INVALID_CHARGER;
1386 if (otg->state == OTG_STATE_B_IDLE)
1387 pm_runtime_put_sync(otg->usb_phy->dev);
1389 case OTG_STATE_B_PERIPHERAL:
1390 dev_dbg(otg->usb_phy->dev, "OTG_STATE_B_PERIPHERAL state\n");
1391 if (!test_bit(B_SESS_VLD, &motg->inputs) ||
1392 !test_bit(ID, &motg->inputs)) {
1393 msm_otg_notify_charger(motg, 0);
1394 msm_otg_start_peripheral(otg->usb_phy, 0);
1395 motg->chg_state = USB_CHG_STATE_UNDEFINED;
1396 motg->chg_type = USB_INVALID_CHARGER;
1397 otg->state = OTG_STATE_B_IDLE;
1398 msm_otg_reset(otg->usb_phy);
1402 case OTG_STATE_A_HOST:
1403 dev_dbg(otg->usb_phy->dev, "OTG_STATE_A_HOST state\n");
1404 if (test_bit(ID, &motg->inputs)) {
1405 msm_otg_start_host(otg->usb_phy, 0);
1406 otg->state = OTG_STATE_B_IDLE;
1407 msm_otg_reset(otg->usb_phy);
1416 static irqreturn_t msm_otg_irq(int irq, void *data)
1418 struct msm_otg *motg = data;
1419 struct usb_phy *phy = &motg->phy;
1422 if (atomic_read(&motg->in_lpm)) {
1423 disable_irq_nosync(irq);
1424 motg->async_int = 1;
1425 pm_runtime_get(phy->dev);
1429 otgsc = readl(USB_OTGSC);
1430 if (!(otgsc & (OTGSC_IDIS | OTGSC_BSVIS)))
1433 if ((otgsc & OTGSC_IDIS) && (otgsc & OTGSC_IDIE)) {
1434 if (otgsc & OTGSC_ID)
1435 set_bit(ID, &motg->inputs);
1437 clear_bit(ID, &motg->inputs);
1438 dev_dbg(phy->dev, "ID set/clear\n");
1439 pm_runtime_get_noresume(phy->dev);
1440 } else if ((otgsc & OTGSC_BSVIS) && (otgsc & OTGSC_BSVIE)) {
1441 if (otgsc & OTGSC_BSV)
1442 set_bit(B_SESS_VLD, &motg->inputs);
1444 clear_bit(B_SESS_VLD, &motg->inputs);
1445 dev_dbg(phy->dev, "BSV set/clear\n");
1446 pm_runtime_get_noresume(phy->dev);
1449 writel(otgsc, USB_OTGSC);
1450 schedule_work(&motg->sm_work);
1454 static int msm_otg_mode_show(struct seq_file *s, void *unused)
1456 struct msm_otg *motg = s->private;
1457 struct usb_otg *otg = motg->phy.otg;
1459 switch (otg->state) {
1460 case OTG_STATE_A_HOST:
1461 seq_puts(s, "host\n");
1463 case OTG_STATE_B_PERIPHERAL:
1464 seq_puts(s, "peripheral\n");
1467 seq_puts(s, "none\n");
1474 static int msm_otg_mode_open(struct inode *inode, struct file *file)
1476 return single_open(file, msm_otg_mode_show, inode->i_private);
1479 static ssize_t msm_otg_mode_write(struct file *file, const char __user *ubuf,
1480 size_t count, loff_t *ppos)
1482 struct seq_file *s = file->private_data;
1483 struct msm_otg *motg = s->private;
1485 struct usb_otg *otg = motg->phy.otg;
1487 enum usb_dr_mode req_mode;
1489 memset(buf, 0x00, sizeof(buf));
1491 if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count))) {
1496 if (!strncmp(buf, "host", 4)) {
1497 req_mode = USB_DR_MODE_HOST;
1498 } else if (!strncmp(buf, "peripheral", 10)) {
1499 req_mode = USB_DR_MODE_PERIPHERAL;
1500 } else if (!strncmp(buf, "none", 4)) {
1501 req_mode = USB_DR_MODE_UNKNOWN;
1508 case USB_DR_MODE_UNKNOWN:
1509 switch (otg->state) {
1510 case OTG_STATE_A_HOST:
1511 case OTG_STATE_B_PERIPHERAL:
1512 set_bit(ID, &motg->inputs);
1513 clear_bit(B_SESS_VLD, &motg->inputs);
1519 case USB_DR_MODE_PERIPHERAL:
1520 switch (otg->state) {
1521 case OTG_STATE_B_IDLE:
1522 case OTG_STATE_A_HOST:
1523 set_bit(ID, &motg->inputs);
1524 set_bit(B_SESS_VLD, &motg->inputs);
1530 case USB_DR_MODE_HOST:
1531 switch (otg->state) {
1532 case OTG_STATE_B_IDLE:
1533 case OTG_STATE_B_PERIPHERAL:
1534 clear_bit(ID, &motg->inputs);
1544 pm_runtime_get_sync(otg->usb_phy->dev);
1545 schedule_work(&motg->sm_work);
1550 static const struct file_operations msm_otg_mode_fops = {
1551 .open = msm_otg_mode_open,
1553 .write = msm_otg_mode_write,
1554 .llseek = seq_lseek,
1555 .release = single_release,
1558 static struct dentry *msm_otg_dbg_root;
1559 static struct dentry *msm_otg_dbg_mode;
1561 static int msm_otg_debugfs_init(struct msm_otg *motg)
1563 msm_otg_dbg_root = debugfs_create_dir("msm_otg", NULL);
1565 if (!msm_otg_dbg_root || IS_ERR(msm_otg_dbg_root))
1568 msm_otg_dbg_mode = debugfs_create_file("mode", S_IRUGO | S_IWUSR,
1569 msm_otg_dbg_root, motg, &msm_otg_mode_fops);
1570 if (!msm_otg_dbg_mode) {
1571 debugfs_remove(msm_otg_dbg_root);
1572 msm_otg_dbg_root = NULL;
1579 static void msm_otg_debugfs_cleanup(void)
1581 debugfs_remove(msm_otg_dbg_mode);
1582 debugfs_remove(msm_otg_dbg_root);
1585 static const struct of_device_id msm_otg_dt_match[] = {
1587 .compatible = "qcom,usb-otg-ci",
1588 .data = (void *) CI_45NM_INTEGRATED_PHY
1591 .compatible = "qcom,usb-otg-snps",
1592 .data = (void *) SNPS_28NM_INTEGRATED_PHY
1596 MODULE_DEVICE_TABLE(of, msm_otg_dt_match);
1598 static int msm_otg_vbus_notifier(struct notifier_block *nb, unsigned long event,
1601 struct usb_phy *usb_phy = container_of(nb, struct usb_phy, vbus_nb);
1602 struct msm_otg *motg = container_of(usb_phy, struct msm_otg, phy);
1605 set_bit(B_SESS_VLD, &motg->inputs);
1607 clear_bit(B_SESS_VLD, &motg->inputs);
1609 if (test_bit(B_SESS_VLD, &motg->inputs)) {
1610 /* Switch D+/D- lines to Device connector */
1611 gpiod_set_value_cansleep(motg->switch_gpio, 0);
1613 /* Switch D+/D- lines to Hub */
1614 gpiod_set_value_cansleep(motg->switch_gpio, 1);
1617 schedule_work(&motg->sm_work);
1622 static int msm_otg_id_notifier(struct notifier_block *nb, unsigned long event,
1625 struct usb_phy *usb_phy = container_of(nb, struct usb_phy, id_nb);
1626 struct msm_otg *motg = container_of(usb_phy, struct msm_otg, phy);
1629 clear_bit(ID, &motg->inputs);
1631 set_bit(ID, &motg->inputs);
1633 schedule_work(&motg->sm_work);
1638 static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg)
1640 struct msm_otg_platform_data *pdata;
1641 struct device_node *node = pdev->dev.of_node;
1642 struct property *prop;
1643 int len, ret, words;
1646 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1650 motg->pdata = pdata;
1652 pdata->phy_type = (enum msm_usb_phy_type)of_device_get_match_data(&pdev->dev);
1653 if (!pdata->phy_type)
1656 motg->link_rst = devm_reset_control_get(&pdev->dev, "link");
1657 if (IS_ERR(motg->link_rst))
1658 return PTR_ERR(motg->link_rst);
1660 motg->phy_rst = devm_reset_control_get(&pdev->dev, "phy");
1661 if (IS_ERR(motg->phy_rst))
1662 motg->phy_rst = NULL;
1664 pdata->mode = usb_get_dr_mode(&pdev->dev);
1665 if (pdata->mode == USB_DR_MODE_UNKNOWN)
1666 pdata->mode = USB_DR_MODE_OTG;
1668 pdata->otg_control = OTG_PHY_CONTROL;
1669 if (!of_property_read_u32(node, "qcom,otg-control", &val))
1670 if (val == OTG_PMIC_CONTROL)
1671 pdata->otg_control = val;
1673 if (!of_property_read_u32(node, "qcom,phy-num", &val) && val < 2)
1674 motg->phy_number = val;
1676 motg->vdd_levels[VDD_LEVEL_NONE] = USB_PHY_SUSP_DIG_VOL;
1677 motg->vdd_levels[VDD_LEVEL_MIN] = USB_PHY_VDD_DIG_VOL_MIN;
1678 motg->vdd_levels[VDD_LEVEL_MAX] = USB_PHY_VDD_DIG_VOL_MAX;
1680 if (of_get_property(node, "qcom,vdd-levels", &len) &&
1681 len == sizeof(tmp)) {
1682 of_property_read_u32_array(node, "qcom,vdd-levels",
1683 tmp, len / sizeof(*tmp));
1684 motg->vdd_levels[VDD_LEVEL_NONE] = tmp[VDD_LEVEL_NONE];
1685 motg->vdd_levels[VDD_LEVEL_MIN] = tmp[VDD_LEVEL_MIN];
1686 motg->vdd_levels[VDD_LEVEL_MAX] = tmp[VDD_LEVEL_MAX];
1689 motg->manual_pullup = of_property_read_bool(node, "qcom,manual-pullup");
1691 motg->switch_gpio = devm_gpiod_get_optional(&pdev->dev, "switch",
1693 if (IS_ERR(motg->switch_gpio))
1694 return PTR_ERR(motg->switch_gpio);
1696 prop = of_find_property(node, "qcom,phy-init-sequence", &len);
1700 words = len / sizeof(u32);
1702 if (words >= ULPI_EXT_VENDOR_SPECIFIC) {
1703 dev_warn(&pdev->dev, "Too big PHY init sequence %d\n", words);
1707 pdata->phy_init_seq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1708 if (!pdata->phy_init_seq)
1711 ret = of_property_read_u32_array(node, "qcom,phy-init-sequence",
1712 pdata->phy_init_seq, words);
1714 pdata->phy_init_sz = words;
1719 static int msm_otg_reboot_notify(struct notifier_block *this,
1720 unsigned long code, void *unused)
1722 struct msm_otg *motg = container_of(this, struct msm_otg, reboot);
1725 * Ensure that D+/D- lines are routed to uB connector, so
1726 * we could load bootloader/kernel at next reboot
1728 gpiod_set_value_cansleep(motg->switch_gpio, 0);
1732 static int msm_otg_probe(struct platform_device *pdev)
1734 struct regulator_bulk_data regs[3];
1736 struct device_node *np = pdev->dev.of_node;
1737 struct msm_otg_platform_data *pdata;
1738 struct resource *res;
1739 struct msm_otg *motg;
1740 struct usb_phy *phy;
1741 void __iomem *phy_select;
1743 motg = devm_kzalloc(&pdev->dev, sizeof(struct msm_otg), GFP_KERNEL);
1747 motg->phy.otg = devm_kzalloc(&pdev->dev, sizeof(struct usb_otg),
1753 phy->dev = &pdev->dev;
1755 motg->clk = devm_clk_get(&pdev->dev, np ? "core" : "usb_hs_clk");
1756 if (IS_ERR(motg->clk)) {
1757 dev_err(&pdev->dev, "failed to get usb_hs_clk\n");
1758 return PTR_ERR(motg->clk);
1762 * If USB Core is running its protocol engine based on CORE CLK,
1763 * CORE CLK must be running at >55Mhz for correct HSUSB
1764 * operation and USB core cannot tolerate frequency changes on
1767 motg->pclk = devm_clk_get(&pdev->dev, np ? "iface" : "usb_hs_pclk");
1768 if (IS_ERR(motg->pclk)) {
1769 dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
1770 return PTR_ERR(motg->pclk);
1774 * USB core clock is not present on all MSM chips. This
1775 * clock is introduced to remove the dependency on AXI
1778 motg->core_clk = devm_clk_get(&pdev->dev,
1779 np ? "alt_core" : "usb_hs_core_clk");
1781 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1784 motg->regs = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1788 pdata = dev_get_platdata(&pdev->dev);
1792 ret = msm_otg_read_dt(pdev, motg);
1798 * NOTE: The PHYs can be multiplexed between the chipidea controller
1799 * and the dwc3 controller, using a single bit. It is important that
1800 * the dwc3 driver does not set this bit in an incompatible way.
1802 if (motg->phy_number) {
1803 phy_select = devm_ioremap_nocache(&pdev->dev, USB2_PHY_SEL, 4);
1807 /* Enable second PHY with the OTG port */
1808 writel(0x1, phy_select);
1811 dev_info(&pdev->dev, "OTG regs = %p\n", motg->regs);
1813 motg->irq = platform_get_irq(pdev, 0);
1814 if (motg->irq < 0) {
1815 dev_err(&pdev->dev, "platform_get_irq failed\n");
1820 regs[0].supply = "vddcx";
1821 regs[1].supply = "v3p3";
1822 regs[2].supply = "v1p8";
1824 ret = devm_regulator_bulk_get(motg->phy.dev, ARRAY_SIZE(regs), regs);
1828 motg->vddcx = regs[0].consumer;
1829 motg->v3p3 = regs[1].consumer;
1830 motg->v1p8 = regs[2].consumer;
1832 clk_set_rate(motg->clk, 60000000);
1834 clk_prepare_enable(motg->clk);
1835 clk_prepare_enable(motg->pclk);
1837 if (!IS_ERR(motg->core_clk))
1838 clk_prepare_enable(motg->core_clk);
1840 ret = msm_hsusb_init_vddcx(motg, 1);
1842 dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
1846 ret = msm_hsusb_ldo_init(motg, 1);
1848 dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
1851 ret = msm_hsusb_ldo_set_mode(motg, 1);
1853 dev_err(&pdev->dev, "hsusb vreg enable failed\n");
1857 writel(0, USB_USBINTR);
1858 writel(0, USB_OTGSC);
1860 INIT_WORK(&motg->sm_work, msm_otg_sm_work);
1861 INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work);
1862 ret = devm_request_irq(&pdev->dev, motg->irq, msm_otg_irq, IRQF_SHARED,
1865 dev_err(&pdev->dev, "request irq failed\n");
1869 phy->init = msm_phy_init;
1870 phy->notify_disconnect = msm_phy_notify_disconnect;
1871 phy->type = USB_PHY_TYPE_USB2;
1872 phy->vbus_nb.notifier_call = msm_otg_vbus_notifier;
1873 phy->id_nb.notifier_call = msm_otg_id_notifier;
1875 phy->io_ops = &msm_otg_io_ops;
1877 phy->otg->usb_phy = &motg->phy;
1878 phy->otg->set_host = msm_otg_set_host;
1879 phy->otg->set_peripheral = msm_otg_set_peripheral;
1883 ret = usb_add_phy_dev(&motg->phy);
1885 dev_err(&pdev->dev, "usb_add_phy failed\n");
1889 ret = extcon_get_state(phy->edev, EXTCON_USB);
1891 set_bit(B_SESS_VLD, &motg->inputs);
1893 clear_bit(B_SESS_VLD, &motg->inputs);
1895 ret = extcon_get_state(phy->id_edev, EXTCON_USB_HOST);
1897 clear_bit(ID, &motg->inputs);
1899 set_bit(ID, &motg->inputs);
1901 platform_set_drvdata(pdev, motg);
1902 device_init_wakeup(&pdev->dev, 1);
1904 if (motg->pdata->mode == USB_DR_MODE_OTG &&
1905 motg->pdata->otg_control == OTG_USER_CONTROL) {
1906 ret = msm_otg_debugfs_init(motg);
1908 dev_dbg(&pdev->dev, "Can not create mode change file\n");
1911 if (test_bit(B_SESS_VLD, &motg->inputs)) {
1912 /* Switch D+/D- lines to Device connector */
1913 gpiod_set_value_cansleep(motg->switch_gpio, 0);
1915 /* Switch D+/D- lines to Hub */
1916 gpiod_set_value_cansleep(motg->switch_gpio, 1);
1919 motg->reboot.notifier_call = msm_otg_reboot_notify;
1920 register_reboot_notifier(&motg->reboot);
1922 pm_runtime_set_active(&pdev->dev);
1923 pm_runtime_enable(&pdev->dev);
1928 msm_hsusb_ldo_init(motg, 0);
1930 msm_hsusb_init_vddcx(motg, 0);
1932 clk_disable_unprepare(motg->pclk);
1933 clk_disable_unprepare(motg->clk);
1934 if (!IS_ERR(motg->core_clk))
1935 clk_disable_unprepare(motg->core_clk);
1940 static int msm_otg_remove(struct platform_device *pdev)
1942 struct msm_otg *motg = platform_get_drvdata(pdev);
1943 struct usb_phy *phy = &motg->phy;
1946 if (phy->otg->host || phy->otg->gadget)
1949 unregister_reboot_notifier(&motg->reboot);
1952 * Ensure that D+/D- lines are routed to uB connector, so
1953 * we could load bootloader/kernel at next reboot
1955 gpiod_set_value_cansleep(motg->switch_gpio, 0);
1957 msm_otg_debugfs_cleanup();
1958 cancel_delayed_work_sync(&motg->chg_work);
1959 cancel_work_sync(&motg->sm_work);
1961 pm_runtime_resume(&pdev->dev);
1963 device_init_wakeup(&pdev->dev, 0);
1964 pm_runtime_disable(&pdev->dev);
1966 usb_remove_phy(phy);
1967 disable_irq(motg->irq);
1970 * Put PHY in low power mode.
1972 ulpi_read(phy, 0x14);
1973 ulpi_write(phy, 0x08, 0x09);
1975 writel(readl(USB_PORTSC) | PORTSC_PHCD, USB_PORTSC);
1976 while (cnt < PHY_SUSPEND_TIMEOUT_USEC) {
1977 if (readl(USB_PORTSC) & PORTSC_PHCD)
1982 if (cnt >= PHY_SUSPEND_TIMEOUT_USEC)
1983 dev_err(phy->dev, "Unable to suspend PHY\n");
1985 clk_disable_unprepare(motg->pclk);
1986 clk_disable_unprepare(motg->clk);
1987 if (!IS_ERR(motg->core_clk))
1988 clk_disable_unprepare(motg->core_clk);
1989 msm_hsusb_ldo_init(motg, 0);
1991 pm_runtime_set_suspended(&pdev->dev);
1997 static int msm_otg_runtime_idle(struct device *dev)
1999 struct msm_otg *motg = dev_get_drvdata(dev);
2000 struct usb_otg *otg = motg->phy.otg;
2002 dev_dbg(dev, "OTG runtime idle\n");
2005 * It is observed some times that a spurious interrupt
2006 * comes when PHY is put into LPM immediately after PHY reset.
2007 * This 1 sec delay also prevents entering into LPM immediately
2008 * after asynchronous interrupt.
2010 if (otg->state != OTG_STATE_UNDEFINED)
2011 pm_schedule_suspend(dev, 1000);
2016 static int msm_otg_runtime_suspend(struct device *dev)
2018 struct msm_otg *motg = dev_get_drvdata(dev);
2020 dev_dbg(dev, "OTG runtime suspend\n");
2021 return msm_otg_suspend(motg);
2024 static int msm_otg_runtime_resume(struct device *dev)
2026 struct msm_otg *motg = dev_get_drvdata(dev);
2028 dev_dbg(dev, "OTG runtime resume\n");
2029 return msm_otg_resume(motg);
2033 #ifdef CONFIG_PM_SLEEP
2034 static int msm_otg_pm_suspend(struct device *dev)
2036 struct msm_otg *motg = dev_get_drvdata(dev);
2038 dev_dbg(dev, "OTG PM suspend\n");
2039 return msm_otg_suspend(motg);
2042 static int msm_otg_pm_resume(struct device *dev)
2044 struct msm_otg *motg = dev_get_drvdata(dev);
2047 dev_dbg(dev, "OTG PM resume\n");
2049 ret = msm_otg_resume(motg);
2054 * Runtime PM Documentation recommends bringing the
2055 * device to full powered state upon resume.
2057 pm_runtime_disable(dev);
2058 pm_runtime_set_active(dev);
2059 pm_runtime_enable(dev);
2065 static const struct dev_pm_ops msm_otg_dev_pm_ops = {
2066 SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend, msm_otg_pm_resume)
2067 SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend, msm_otg_runtime_resume,
2068 msm_otg_runtime_idle)
2071 static struct platform_driver msm_otg_driver = {
2072 .probe = msm_otg_probe,
2073 .remove = msm_otg_remove,
2075 .name = DRIVER_NAME,
2076 .pm = &msm_otg_dev_pm_ops,
2077 .of_match_table = msm_otg_dt_match,
2081 module_platform_driver(msm_otg_driver);
2083 MODULE_LICENSE("GPL v2");
2084 MODULE_DESCRIPTION("MSM USB transceiver driver");