1 // SPDX-License-Identifier: GPL-2.0
3 * Texas Instruments DSPS platforms "glue layer"
5 * Copyright (C) 2012, by Texas Instruments
7 * Based on the am35x "glue layer" code.
9 * This file is part of the Inventra Controller Driver for Linux.
11 * musb_dsps.c will be a common file for all the TI DSPS platforms
12 * such as dm64x, dm36x, dm35x, da8x, am35x and ti81x.
13 * For now only ti81x is using this and in future davinci.c, am35x.c
14 * da8xx.c would be merged to this file after testing.
18 #include <linux/err.h>
19 #include <linux/platform_device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/module.h>
23 #include <linux/usb/usb_phy_generic.h>
24 #include <linux/platform_data/usb-omap.h>
25 #include <linux/sizes.h>
28 #include <linux/of_device.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/usb/of.h>
33 #include <linux/debugfs.h>
35 #include "musb_core.h"
37 static const struct of_device_id musb_dsps_of_match[];
40 * DSPS musb wrapper register offset.
41 * FIXME: This should be expanded to have all the wrapper registers from TI DSPS
44 struct dsps_musb_wrapper {
59 /* bit positions for control */
62 /* bit positions for interrupt */
68 unsigned txep_shift:5;
72 unsigned rxep_shift:5;
76 /* bit positions for phy_utmi */
77 unsigned otg_disable:5;
79 /* bit positions for mode */
82 /* miscellaneous stuff */
83 unsigned poll_timeout;
87 * register shadow for suspend
100 * DSPS glue structure.
104 struct platform_device *musb; /* child musb pdev */
105 const struct dsps_musb_wrapper *wrp; /* wrapper register offsets */
106 int vbus_irq; /* optional vbus irq */
107 unsigned long last_timer; /* last timer data for each instance */
108 bool sw_babble_enabled;
109 void __iomem *usbss_base;
111 struct dsps_context context;
112 struct debugfs_regset32 regset;
113 struct dentry *dbgfs_root;
116 static const struct debugfs_reg32 dsps_musb_regs[] = {
117 { "revision", 0x00 },
121 { "intr0_stat", 0x30 },
122 { "intr1_stat", 0x34 },
123 { "intr0_set", 0x38 },
124 { "intr1_set", 0x3c },
128 { "srpfixtime", 0xd4 },
130 { "phy_utmi", 0xe0 },
134 static void dsps_mod_timer(struct dsps_glue *glue, int wait_ms)
136 struct musb *musb = platform_get_drvdata(glue->musb);
140 wait = msecs_to_jiffies(glue->wrp->poll_timeout);
142 wait = msecs_to_jiffies(wait_ms);
144 mod_timer(&musb->dev_timer, jiffies + wait);
148 * If no vbus irq from the PMIC is configured, we need to poll VBUS status.
150 static void dsps_mod_timer_optional(struct dsps_glue *glue)
155 dsps_mod_timer(glue, -1);
158 /* USBSS / USB AM335x */
159 #define USBSS_IRQ_STATUS 0x28
160 #define USBSS_IRQ_ENABLER 0x2c
161 #define USBSS_IRQ_CLEARR 0x30
163 #define USBSS_IRQ_PD_COMP (1 << 2)
166 * dsps_musb_enable - enable interrupts
168 static void dsps_musb_enable(struct musb *musb)
170 struct device *dev = musb->controller;
171 struct platform_device *pdev = to_platform_device(dev->parent);
172 struct dsps_glue *glue = platform_get_drvdata(pdev);
173 const struct dsps_musb_wrapper *wrp = glue->wrp;
174 void __iomem *reg_base = musb->ctrl_base;
175 u32 epmask, coremask;
177 /* Workaround: setup IRQs through both register sets. */
178 epmask = ((musb->epmask & wrp->txep_mask) << wrp->txep_shift) |
179 ((musb->epmask & wrp->rxep_mask) << wrp->rxep_shift);
180 coremask = (wrp->usb_bitmap & ~MUSB_INTR_SOF);
182 musb_writel(reg_base, wrp->epintr_set, epmask);
183 musb_writel(reg_base, wrp->coreintr_set, coremask);
184 /* start polling for ID change in dual-role idle mode */
185 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE &&
186 musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE)
187 dsps_mod_timer(glue, -1);
191 * dsps_musb_disable - disable HDRC and flush interrupts
193 static void dsps_musb_disable(struct musb *musb)
195 struct device *dev = musb->controller;
196 struct platform_device *pdev = to_platform_device(dev->parent);
197 struct dsps_glue *glue = platform_get_drvdata(pdev);
198 const struct dsps_musb_wrapper *wrp = glue->wrp;
199 void __iomem *reg_base = musb->ctrl_base;
201 musb_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap);
202 musb_writel(reg_base, wrp->epintr_clear,
203 wrp->txep_bitmap | wrp->rxep_bitmap);
204 del_timer_sync(&musb->dev_timer);
207 /* Caller must take musb->lock */
208 static int dsps_check_status(struct musb *musb, void *unused)
210 void __iomem *mregs = musb->mregs;
211 struct device *dev = musb->controller;
212 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
213 const struct dsps_musb_wrapper *wrp = glue->wrp;
215 int skip_session = 0;
218 del_timer(&musb->dev_timer);
221 * We poll because DSPS IP's won't expose several OTG-critical
222 * status change events (from the transceiver) otherwise.
224 devctl = musb_readb(mregs, MUSB_DEVCTL);
225 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
226 usb_otg_state_string(musb->xceiv->otg->state));
228 switch (musb->xceiv->otg->state) {
229 case OTG_STATE_A_WAIT_VRISE:
230 dsps_mod_timer_optional(glue);
232 case OTG_STATE_A_WAIT_BCON:
233 /* keep VBUS on for host-only mode */
234 if (musb->port_mode == MUSB_PORT_MODE_HOST) {
235 dsps_mod_timer_optional(glue);
238 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
242 case OTG_STATE_A_IDLE:
243 case OTG_STATE_B_IDLE:
244 if (!glue->vbus_irq) {
245 if (devctl & MUSB_DEVCTL_BDEVICE) {
246 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
249 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
252 if (!(devctl & MUSB_DEVCTL_SESSION) && !skip_session)
253 musb_writeb(mregs, MUSB_DEVCTL,
254 MUSB_DEVCTL_SESSION);
256 dsps_mod_timer_optional(glue);
258 case OTG_STATE_A_WAIT_VFALL:
259 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
260 musb_writel(musb->ctrl_base, wrp->coreintr_set,
261 MUSB_INTR_VBUSERROR << wrp->usb_shift);
270 static void otg_timer(struct timer_list *t)
272 struct musb *musb = from_timer(musb, t, dev_timer);
273 struct device *dev = musb->controller;
277 err = pm_runtime_get(dev);
278 if ((err != -EINPROGRESS) && err < 0) {
279 dev_err(dev, "Poll could not pm_runtime_get: %i\n", err);
280 pm_runtime_put_noidle(dev);
285 spin_lock_irqsave(&musb->lock, flags);
286 err = musb_queue_resume_work(musb, dsps_check_status, NULL);
288 dev_err(dev, "%s resume work: %i\n", __func__, err);
289 spin_unlock_irqrestore(&musb->lock, flags);
290 pm_runtime_mark_last_busy(dev);
291 pm_runtime_put_autosuspend(dev);
294 static void dsps_musb_clear_ep_rxintr(struct musb *musb, int epnum)
297 struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent);
298 const struct dsps_musb_wrapper *wrp = glue->wrp;
300 /* musb->lock might already been held */
301 epintr = (1 << epnum) << wrp->rxep_shift;
302 musb_writel(musb->ctrl_base, wrp->epintr_status, epintr);
305 static irqreturn_t dsps_interrupt(int irq, void *hci)
307 struct musb *musb = hci;
308 void __iomem *reg_base = musb->ctrl_base;
309 struct device *dev = musb->controller;
310 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
311 const struct dsps_musb_wrapper *wrp = glue->wrp;
313 irqreturn_t ret = IRQ_NONE;
316 spin_lock_irqsave(&musb->lock, flags);
318 /* Get endpoint interrupts */
319 epintr = musb_readl(reg_base, wrp->epintr_status);
320 musb->int_rx = (epintr & wrp->rxep_bitmap) >> wrp->rxep_shift;
321 musb->int_tx = (epintr & wrp->txep_bitmap) >> wrp->txep_shift;
324 musb_writel(reg_base, wrp->epintr_status, epintr);
326 /* Get usb core interrupts */
327 usbintr = musb_readl(reg_base, wrp->coreintr_status);
328 if (!usbintr && !epintr)
331 musb->int_usb = (usbintr & wrp->usb_bitmap) >> wrp->usb_shift;
333 musb_writel(reg_base, wrp->coreintr_status, usbintr);
335 dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n",
338 if (usbintr & ((1 << wrp->drvvbus) << wrp->usb_shift)) {
339 int drvvbus = musb_readl(reg_base, wrp->status);
340 void __iomem *mregs = musb->mregs;
341 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
344 err = musb->int_usb & MUSB_INTR_VBUSERROR;
347 * The Mentor core doesn't debounce VBUS as needed
348 * to cope with device connect current spikes. This
349 * means it's not uncommon for bus-powered devices
350 * to get VBUS errors during enumeration.
352 * This is a workaround, but newer RTL from Mentor
353 * seems to allow a better one: "re"-starting sessions
354 * without waiting for VBUS to stop registering in
357 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
358 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
359 dsps_mod_timer_optional(glue);
360 WARNING("VBUS error workaround (delay coming)\n");
361 } else if (drvvbus) {
363 musb->xceiv->otg->default_a = 1;
364 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
365 dsps_mod_timer_optional(glue);
369 musb->xceiv->otg->default_a = 0;
370 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
373 /* NOTE: this must complete power-on within 100 ms. */
374 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
375 drvvbus ? "on" : "off",
376 usb_otg_state_string(musb->xceiv->otg->state),
382 if (musb->int_tx || musb->int_rx || musb->int_usb)
383 ret |= musb_interrupt(musb);
385 /* Poll for ID change and connect */
386 switch (musb->xceiv->otg->state) {
387 case OTG_STATE_B_IDLE:
388 case OTG_STATE_A_WAIT_BCON:
389 dsps_mod_timer_optional(glue);
396 spin_unlock_irqrestore(&musb->lock, flags);
401 static int dsps_musb_dbg_init(struct musb *musb, struct dsps_glue *glue)
407 sprintf(buf, "%s.dsps", dev_name(musb->controller));
408 root = debugfs_create_dir(buf, NULL);
411 glue->dbgfs_root = root;
413 glue->regset.regs = dsps_musb_regs;
414 glue->regset.nregs = ARRAY_SIZE(dsps_musb_regs);
415 glue->regset.base = musb->ctrl_base;
417 file = debugfs_create_regset32("regdump", S_IRUGO, root, &glue->regset);
419 debugfs_remove_recursive(root);
425 static int dsps_musb_init(struct musb *musb)
427 struct device *dev = musb->controller;
428 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
429 struct platform_device *parent = to_platform_device(dev->parent);
430 const struct dsps_musb_wrapper *wrp = glue->wrp;
431 void __iomem *reg_base;
436 r = platform_get_resource_byname(parent, IORESOURCE_MEM, "control");
437 reg_base = devm_ioremap_resource(dev, r);
438 if (IS_ERR(reg_base))
439 return PTR_ERR(reg_base);
440 musb->ctrl_base = reg_base;
442 /* NOP driver needs change if supporting dual instance */
443 musb->xceiv = devm_usb_get_phy_by_phandle(dev->parent, "phys", 0);
444 if (IS_ERR(musb->xceiv))
445 return PTR_ERR(musb->xceiv);
447 musb->phy = devm_phy_get(dev->parent, "usb2-phy");
449 /* Returns zero if e.g. not clocked */
450 rev = musb_readl(reg_base, wrp->revision);
454 usb_phy_init(musb->xceiv);
455 if (IS_ERR(musb->phy)) {
458 ret = phy_init(musb->phy);
461 ret = phy_power_on(musb->phy);
468 timer_setup(&musb->dev_timer, otg_timer, 0);
471 musb_writel(reg_base, wrp->control, (1 << wrp->reset));
473 musb->isr = dsps_interrupt;
475 /* reset the otgdisable bit, needed for host mode to work */
476 val = musb_readl(reg_base, wrp->phy_utmi);
477 val &= ~(1 << wrp->otg_disable);
478 musb_writel(musb->ctrl_base, wrp->phy_utmi, val);
481 * Check whether the dsps version has babble control enabled.
482 * In latest silicon revision the babble control logic is enabled.
483 * If MUSB_BABBLE_CTL returns 0x4 then we have the babble control
486 val = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
487 if (val & MUSB_BABBLE_RCV_DISABLE) {
488 glue->sw_babble_enabled = true;
489 val |= MUSB_BABBLE_SW_SESSION_CTRL;
490 musb_writeb(musb->mregs, MUSB_BABBLE_CTL, val);
493 dsps_mod_timer(glue, -1);
495 return dsps_musb_dbg_init(musb, glue);
498 static int dsps_musb_exit(struct musb *musb)
500 struct device *dev = musb->controller;
501 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
503 del_timer_sync(&musb->dev_timer);
504 usb_phy_shutdown(musb->xceiv);
505 phy_power_off(musb->phy);
507 debugfs_remove_recursive(glue->dbgfs_root);
512 static int dsps_musb_set_mode(struct musb *musb, u8 mode)
514 struct device *dev = musb->controller;
515 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
516 const struct dsps_musb_wrapper *wrp = glue->wrp;
517 void __iomem *ctrl_base = musb->ctrl_base;
520 reg = musb_readl(ctrl_base, wrp->mode);
524 reg &= ~(1 << wrp->iddig);
527 * if we're setting mode to host-only or device-only, we're
528 * going to ignore whatever the PHY sends us and just force
529 * ID pin status by SW
531 reg |= (1 << wrp->iddig_mux);
533 musb_writel(ctrl_base, wrp->mode, reg);
534 musb_writel(ctrl_base, wrp->phy_utmi, 0x02);
536 case MUSB_PERIPHERAL:
537 reg |= (1 << wrp->iddig);
540 * if we're setting mode to host-only or device-only, we're
541 * going to ignore whatever the PHY sends us and just force
542 * ID pin status by SW
544 reg |= (1 << wrp->iddig_mux);
546 musb_writel(ctrl_base, wrp->mode, reg);
549 musb_writel(ctrl_base, wrp->phy_utmi, 0x02);
552 dev_err(glue->dev, "unsupported mode %d\n", mode);
559 static bool dsps_sw_babble_control(struct musb *musb)
562 bool session_restart = false;
564 babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
565 dev_dbg(musb->controller, "babble: MUSB_BABBLE_CTL value %x\n",
568 * check line monitor flag to check whether babble is
571 dev_dbg(musb->controller, "STUCK_J is %s\n",
572 babble_ctl & MUSB_BABBLE_STUCK_J ? "set" : "reset");
574 if (babble_ctl & MUSB_BABBLE_STUCK_J) {
578 * babble is due to noise, then set transmit idle (d7 bit)
579 * to resume normal operation
581 babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
582 babble_ctl |= MUSB_BABBLE_FORCE_TXIDLE;
583 musb_writeb(musb->mregs, MUSB_BABBLE_CTL, babble_ctl);
585 /* wait till line monitor flag cleared */
586 dev_dbg(musb->controller, "Set TXIDLE, wait J to clear\n");
588 babble_ctl = musb_readb(musb->mregs, MUSB_BABBLE_CTL);
590 } while ((babble_ctl & MUSB_BABBLE_STUCK_J) && timeout--);
592 /* check whether stuck_at_j bit cleared */
593 if (babble_ctl & MUSB_BABBLE_STUCK_J) {
595 * real babble condition has occurred
596 * restart the controller to start the
599 dev_dbg(musb->controller, "J not cleared, misc (%x)\n",
601 session_restart = true;
604 session_restart = true;
607 return session_restart;
610 static int dsps_musb_recover(struct musb *musb)
612 struct device *dev = musb->controller;
613 struct dsps_glue *glue = dev_get_drvdata(dev->parent);
614 int session_restart = 0;
616 if (glue->sw_babble_enabled)
617 session_restart = dsps_sw_babble_control(musb);
621 return session_restart ? 0 : -EPIPE;
624 /* Similar to am35x, dm81xx support only 32-bit read operation */
625 static void dsps_read_fifo32(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
627 void __iomem *fifo = hw_ep->fifo;
630 ioread32_rep(fifo, dst, len >> 2);
635 /* Read any remaining 1 to 3 bytes */
637 u32 val = musb_readl(fifo, 0);
638 memcpy(dst, &val, len);
642 #ifdef CONFIG_USB_TI_CPPI41_DMA
643 static void dsps_dma_controller_callback(struct dma_controller *c)
645 struct musb *musb = c->musb;
646 struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent);
647 void __iomem *usbss_base = glue->usbss_base;
650 status = musb_readl(usbss_base, USBSS_IRQ_STATUS);
651 if (status & USBSS_IRQ_PD_COMP)
652 musb_writel(usbss_base, USBSS_IRQ_STATUS, USBSS_IRQ_PD_COMP);
655 static struct dma_controller *
656 dsps_dma_controller_create(struct musb *musb, void __iomem *base)
658 struct dma_controller *controller;
659 struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent);
660 void __iomem *usbss_base = glue->usbss_base;
662 controller = cppi41_dma_controller_create(musb, base);
663 if (IS_ERR_OR_NULL(controller))
666 musb_writel(usbss_base, USBSS_IRQ_ENABLER, USBSS_IRQ_PD_COMP);
667 controller->dma_callback = dsps_dma_controller_callback;
672 static void dsps_dma_controller_destroy(struct dma_controller *c)
674 struct musb *musb = c->musb;
675 struct dsps_glue *glue = dev_get_drvdata(musb->controller->parent);
676 void __iomem *usbss_base = glue->usbss_base;
678 musb_writel(usbss_base, USBSS_IRQ_CLEARR, USBSS_IRQ_PD_COMP);
679 cppi41_dma_controller_destroy(c);
682 #ifdef CONFIG_PM_SLEEP
683 static void dsps_dma_controller_suspend(struct dsps_glue *glue)
685 void __iomem *usbss_base = glue->usbss_base;
687 musb_writel(usbss_base, USBSS_IRQ_CLEARR, USBSS_IRQ_PD_COMP);
690 static void dsps_dma_controller_resume(struct dsps_glue *glue)
692 void __iomem *usbss_base = glue->usbss_base;
694 musb_writel(usbss_base, USBSS_IRQ_ENABLER, USBSS_IRQ_PD_COMP);
697 #else /* CONFIG_USB_TI_CPPI41_DMA */
698 #ifdef CONFIG_PM_SLEEP
699 static void dsps_dma_controller_suspend(struct dsps_glue *glue) {}
700 static void dsps_dma_controller_resume(struct dsps_glue *glue) {}
702 #endif /* CONFIG_USB_TI_CPPI41_DMA */
704 static struct musb_platform_ops dsps_ops = {
705 .quirks = MUSB_DMA_CPPI41 | MUSB_INDEXED_EP,
706 .init = dsps_musb_init,
707 .exit = dsps_musb_exit,
709 #ifdef CONFIG_USB_TI_CPPI41_DMA
710 .dma_init = dsps_dma_controller_create,
711 .dma_exit = dsps_dma_controller_destroy,
713 .enable = dsps_musb_enable,
714 .disable = dsps_musb_disable,
716 .set_mode = dsps_musb_set_mode,
717 .recover = dsps_musb_recover,
718 .clear_ep_rxintr = dsps_musb_clear_ep_rxintr,
721 static u64 musb_dmamask = DMA_BIT_MASK(32);
723 static int get_int_prop(struct device_node *dn, const char *s)
728 ret = of_property_read_u32(dn, s, &val);
734 static int get_musb_port_mode(struct device *dev)
736 enum usb_dr_mode mode;
738 mode = usb_get_dr_mode(dev);
740 case USB_DR_MODE_HOST:
741 return MUSB_PORT_MODE_HOST;
743 case USB_DR_MODE_PERIPHERAL:
744 return MUSB_PORT_MODE_GADGET;
746 case USB_DR_MODE_UNKNOWN:
747 case USB_DR_MODE_OTG:
749 return MUSB_PORT_MODE_DUAL_ROLE;
753 static int dsps_create_musb_pdev(struct dsps_glue *glue,
754 struct platform_device *parent)
756 struct musb_hdrc_platform_data pdata;
757 struct resource resources[2];
758 struct resource *res;
759 struct device *dev = &parent->dev;
760 struct musb_hdrc_config *config;
761 struct platform_device *musb;
762 struct device_node *dn = parent->dev.of_node;
765 memset(resources, 0, sizeof(resources));
766 res = platform_get_resource_byname(parent, IORESOURCE_MEM, "mc");
768 dev_err(dev, "failed to get memory.\n");
773 res = platform_get_resource_byname(parent, IORESOURCE_IRQ, "mc");
775 dev_err(dev, "failed to get irq.\n");
780 /* allocate the child platform device */
781 musb = platform_device_alloc("musb-hdrc",
782 (resources[0].start & 0xFFF) == 0x400 ? 0 : 1);
784 dev_err(dev, "failed to allocate musb device\n");
788 musb->dev.parent = dev;
789 musb->dev.dma_mask = &musb_dmamask;
790 musb->dev.coherent_dma_mask = musb_dmamask;
794 ret = platform_device_add_resources(musb, resources,
795 ARRAY_SIZE(resources));
797 dev_err(dev, "failed to add resources\n");
801 config = devm_kzalloc(&parent->dev, sizeof(*config), GFP_KERNEL);
806 pdata.config = config;
807 pdata.platform_ops = &dsps_ops;
809 config->num_eps = get_int_prop(dn, "mentor,num-eps");
810 config->ram_bits = get_int_prop(dn, "mentor,ram-bits");
811 config->host_port_deassert_reset_at_resume = 1;
812 pdata.mode = get_musb_port_mode(dev);
813 /* DT keeps this entry in mA, musb expects it as per USB spec */
814 pdata.power = get_int_prop(dn, "mentor,power") / 2;
816 ret = of_property_read_u32(dn, "mentor,multipoint", &val);
818 config->multipoint = true;
820 config->maximum_speed = usb_get_maximum_speed(&parent->dev);
821 switch (config->maximum_speed) {
825 case USB_SPEED_SUPER:
826 dev_warn(dev, "ignore incorrect maximum_speed "
827 "(super-speed) setting in dts");
830 config->maximum_speed = USB_SPEED_HIGH;
833 ret = platform_device_add_data(musb, &pdata, sizeof(pdata));
835 dev_err(dev, "failed to add platform_data\n");
839 ret = platform_device_add(musb);
841 dev_err(dev, "failed to register musb device\n");
847 platform_device_put(musb);
851 static irqreturn_t dsps_vbus_threaded_irq(int irq, void *priv)
853 struct dsps_glue *glue = priv;
854 struct musb *musb = platform_get_drvdata(glue->musb);
859 dev_dbg(glue->dev, "VBUS interrupt\n");
860 dsps_mod_timer(glue, 0);
865 static int dsps_setup_optional_vbus_irq(struct platform_device *pdev,
866 struct dsps_glue *glue)
870 glue->vbus_irq = platform_get_irq_byname(pdev, "vbus");
871 if (glue->vbus_irq == -EPROBE_DEFER)
872 return -EPROBE_DEFER;
874 if (glue->vbus_irq <= 0) {
879 error = devm_request_threaded_irq(glue->dev, glue->vbus_irq,
880 NULL, dsps_vbus_threaded_irq,
887 dev_dbg(glue->dev, "VBUS irq %i configured\n", glue->vbus_irq);
892 static int dsps_probe(struct platform_device *pdev)
894 const struct of_device_id *match;
895 const struct dsps_musb_wrapper *wrp;
896 struct dsps_glue *glue;
899 if (!strcmp(pdev->name, "musb-hdrc"))
902 match = of_match_node(musb_dsps_of_match, pdev->dev.of_node);
904 dev_err(&pdev->dev, "fail to get matching of_match struct\n");
909 if (of_device_is_compatible(pdev->dev.of_node, "ti,musb-dm816"))
910 dsps_ops.read_fifo = dsps_read_fifo32;
913 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
917 glue->dev = &pdev->dev;
919 glue->usbss_base = of_iomap(pdev->dev.parent->of_node, 0);
920 if (!glue->usbss_base)
923 if (usb_get_dr_mode(&pdev->dev) == USB_DR_MODE_PERIPHERAL) {
924 ret = dsps_setup_optional_vbus_irq(pdev, glue);
929 platform_set_drvdata(pdev, glue);
930 pm_runtime_enable(&pdev->dev);
931 ret = dsps_create_musb_pdev(glue, pdev);
938 pm_runtime_disable(&pdev->dev);
940 iounmap(glue->usbss_base);
944 static int dsps_remove(struct platform_device *pdev)
946 struct dsps_glue *glue = platform_get_drvdata(pdev);
948 platform_device_unregister(glue->musb);
950 pm_runtime_disable(&pdev->dev);
951 iounmap(glue->usbss_base);
956 static const struct dsps_musb_wrapper am33xx_driver_data = {
961 .epintr_clear = 0x40,
962 .epintr_status = 0x30,
963 .coreintr_set = 0x3c,
964 .coreintr_clear = 0x44,
965 .coreintr_status = 0x34,
976 .usb_bitmap = (0x1ff << 0),
980 .txep_bitmap = (0xffff << 0),
983 .rxep_bitmap = (0xfffe << 16),
984 .poll_timeout = 2000, /* ms */
987 static const struct of_device_id musb_dsps_of_match[] = {
988 { .compatible = "ti,musb-am33xx",
989 .data = &am33xx_driver_data, },
990 { .compatible = "ti,musb-dm816",
991 .data = &am33xx_driver_data, },
994 MODULE_DEVICE_TABLE(of, musb_dsps_of_match);
996 #ifdef CONFIG_PM_SLEEP
997 static int dsps_suspend(struct device *dev)
999 struct dsps_glue *glue = dev_get_drvdata(dev);
1000 const struct dsps_musb_wrapper *wrp = glue->wrp;
1001 struct musb *musb = platform_get_drvdata(glue->musb);
1002 void __iomem *mbase;
1006 /* This can happen if the musb device is in -EPROBE_DEFER */
1009 ret = pm_runtime_get_sync(dev);
1011 pm_runtime_put_noidle(dev);
1015 del_timer_sync(&musb->dev_timer);
1017 mbase = musb->ctrl_base;
1018 glue->context.control = musb_readl(mbase, wrp->control);
1019 glue->context.epintr = musb_readl(mbase, wrp->epintr_set);
1020 glue->context.coreintr = musb_readl(mbase, wrp->coreintr_set);
1021 glue->context.phy_utmi = musb_readl(mbase, wrp->phy_utmi);
1022 glue->context.mode = musb_readl(mbase, wrp->mode);
1023 glue->context.tx_mode = musb_readl(mbase, wrp->tx_mode);
1024 glue->context.rx_mode = musb_readl(mbase, wrp->rx_mode);
1026 dsps_dma_controller_suspend(glue);
1031 static int dsps_resume(struct device *dev)
1033 struct dsps_glue *glue = dev_get_drvdata(dev);
1034 const struct dsps_musb_wrapper *wrp = glue->wrp;
1035 struct musb *musb = platform_get_drvdata(glue->musb);
1036 void __iomem *mbase;
1041 dsps_dma_controller_resume(glue);
1043 mbase = musb->ctrl_base;
1044 musb_writel(mbase, wrp->control, glue->context.control);
1045 musb_writel(mbase, wrp->epintr_set, glue->context.epintr);
1046 musb_writel(mbase, wrp->coreintr_set, glue->context.coreintr);
1047 musb_writel(mbase, wrp->phy_utmi, glue->context.phy_utmi);
1048 musb_writel(mbase, wrp->mode, glue->context.mode);
1049 musb_writel(mbase, wrp->tx_mode, glue->context.tx_mode);
1050 musb_writel(mbase, wrp->rx_mode, glue->context.rx_mode);
1051 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE &&
1052 musb->port_mode == MUSB_PORT_MODE_DUAL_ROLE)
1053 dsps_mod_timer(glue, -1);
1055 pm_runtime_put(dev);
1061 static SIMPLE_DEV_PM_OPS(dsps_pm_ops, dsps_suspend, dsps_resume);
1063 static struct platform_driver dsps_usbss_driver = {
1064 .probe = dsps_probe,
1065 .remove = dsps_remove,
1067 .name = "musb-dsps",
1069 .of_match_table = musb_dsps_of_match,
1073 MODULE_DESCRIPTION("TI DSPS MUSB Glue Layer");
1074 MODULE_AUTHOR("Ravi B <ravibabu@ti.com>");
1075 MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
1076 MODULE_LICENSE("GPL v2");
1078 module_platform_driver(dsps_usbss_driver);