1 // SPDX-License-Identifier: GPL-2.0
3 * mtu3_hw_regs.h - MediaTek USB3 DRD register and field definitions
5 * Copyright (C) 2016 MediaTek Inc.
7 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
10 #ifndef _SSUSB_HW_REGS_H_
11 #define _SSUSB_HW_REGS_H_
13 /* segment offset of MAC register */
14 #define SSUSB_DEV_BASE 0x0000
15 #define SSUSB_EPCTL_CSR_BASE 0x0800
16 #define SSUSB_USB3_MAC_CSR_BASE 0x1400
17 #define SSUSB_USB3_SYS_CSR_BASE 0x1400
18 #define SSUSB_USB2_CSR_BASE 0x2400
20 /* IPPC register in Infra */
21 #define SSUSB_SIFSLV_IPPC_BASE 0x0000
23 /* --------------- SSUSB_DEV REGISTER DEFINITION --------------- */
25 #define U3D_LV1ISR (SSUSB_DEV_BASE + 0x0000)
26 #define U3D_LV1IER (SSUSB_DEV_BASE + 0x0004)
27 #define U3D_LV1IESR (SSUSB_DEV_BASE + 0x0008)
28 #define U3D_LV1IECR (SSUSB_DEV_BASE + 0x000C)
30 #define U3D_EPISR (SSUSB_DEV_BASE + 0x0080)
31 #define U3D_EPIER (SSUSB_DEV_BASE + 0x0084)
32 #define U3D_EPIESR (SSUSB_DEV_BASE + 0x0088)
33 #define U3D_EPIECR (SSUSB_DEV_BASE + 0x008C)
35 #define U3D_EP0CSR (SSUSB_DEV_BASE + 0x0100)
36 #define U3D_RXCOUNT0 (SSUSB_DEV_BASE + 0x0108)
37 #define U3D_RESERVED (SSUSB_DEV_BASE + 0x010C)
38 #define U3D_TX1CSR0 (SSUSB_DEV_BASE + 0x0110)
39 #define U3D_TX1CSR1 (SSUSB_DEV_BASE + 0x0114)
40 #define U3D_TX1CSR2 (SSUSB_DEV_BASE + 0x0118)
42 #define U3D_RX1CSR0 (SSUSB_DEV_BASE + 0x0210)
43 #define U3D_RX1CSR1 (SSUSB_DEV_BASE + 0x0214)
44 #define U3D_RX1CSR2 (SSUSB_DEV_BASE + 0x0218)
46 #define U3D_FIFO0 (SSUSB_DEV_BASE + 0x0300)
48 #define U3D_QCR0 (SSUSB_DEV_BASE + 0x0400)
49 #define U3D_QCR1 (SSUSB_DEV_BASE + 0x0404)
50 #define U3D_QCR2 (SSUSB_DEV_BASE + 0x0408)
51 #define U3D_QCR3 (SSUSB_DEV_BASE + 0x040C)
52 #define U3D_TXQHIAR1 (SSUSB_DEV_BASE + 0x0484)
53 #define U3D_RXQHIAR1 (SSUSB_DEV_BASE + 0x04C4)
55 #define U3D_TXQCSR1 (SSUSB_DEV_BASE + 0x0510)
56 #define U3D_TXQSAR1 (SSUSB_DEV_BASE + 0x0514)
57 #define U3D_TXQCPR1 (SSUSB_DEV_BASE + 0x0518)
59 #define U3D_RXQCSR1 (SSUSB_DEV_BASE + 0x0610)
60 #define U3D_RXQSAR1 (SSUSB_DEV_BASE + 0x0614)
61 #define U3D_RXQCPR1 (SSUSB_DEV_BASE + 0x0618)
62 #define U3D_RXQLDPR1 (SSUSB_DEV_BASE + 0x061C)
64 #define U3D_QISAR0 (SSUSB_DEV_BASE + 0x0700)
65 #define U3D_QIER0 (SSUSB_DEV_BASE + 0x0704)
66 #define U3D_QIESR0 (SSUSB_DEV_BASE + 0x0708)
67 #define U3D_QIECR0 (SSUSB_DEV_BASE + 0x070C)
68 #define U3D_QISAR1 (SSUSB_DEV_BASE + 0x0710)
69 #define U3D_QIER1 (SSUSB_DEV_BASE + 0x0714)
70 #define U3D_QIESR1 (SSUSB_DEV_BASE + 0x0718)
71 #define U3D_QIECR1 (SSUSB_DEV_BASE + 0x071C)
73 #define U3D_TQERRIR0 (SSUSB_DEV_BASE + 0x0780)
74 #define U3D_TQERRIER0 (SSUSB_DEV_BASE + 0x0784)
75 #define U3D_TQERRIESR0 (SSUSB_DEV_BASE + 0x0788)
76 #define U3D_TQERRIECR0 (SSUSB_DEV_BASE + 0x078C)
77 #define U3D_RQERRIR0 (SSUSB_DEV_BASE + 0x07C0)
78 #define U3D_RQERRIER0 (SSUSB_DEV_BASE + 0x07C4)
79 #define U3D_RQERRIESR0 (SSUSB_DEV_BASE + 0x07C8)
80 #define U3D_RQERRIECR0 (SSUSB_DEV_BASE + 0x07CC)
81 #define U3D_RQERRIR1 (SSUSB_DEV_BASE + 0x07D0)
82 #define U3D_RQERRIER1 (SSUSB_DEV_BASE + 0x07D4)
83 #define U3D_RQERRIESR1 (SSUSB_DEV_BASE + 0x07D8)
84 #define U3D_RQERRIECR1 (SSUSB_DEV_BASE + 0x07DC)
86 #define U3D_CAP_EP0FFSZ (SSUSB_DEV_BASE + 0x0C04)
87 #define U3D_CAP_EPNTXFFSZ (SSUSB_DEV_BASE + 0x0C08)
88 #define U3D_CAP_EPNRXFFSZ (SSUSB_DEV_BASE + 0x0C0C)
89 #define U3D_CAP_EPINFO (SSUSB_DEV_BASE + 0x0C10)
90 #define U3D_MISC_CTRL (SSUSB_DEV_BASE + 0x0C84)
92 /*---------------- SSUSB_DEV FIELD DEFINITION ---------------*/
95 #define EP_CTRL_INTR BIT(5)
96 #define MAC2_INTR BIT(4)
97 #define DMA_INTR BIT(3)
98 #define MAC3_INTR BIT(2)
99 #define QMU_INTR BIT(1)
100 #define BMU_INTR BIT(0)
103 #define LV1IECR_MSK GENMASK(31, 0)
106 #define EPRISR(x) (BIT(16) << (x))
107 #define SETUPENDISR BIT(16)
108 #define EPTISR(x) (BIT(0) << (x))
109 #define EP0ISR BIT(0)
112 #define EP0_SENDSTALL BIT(25)
113 #define EP0_FIFOFULL BIT(23)
114 #define EP0_SENTSTALL BIT(22)
115 #define EP0_DPHTX BIT(20)
116 #define EP0_DATAEND BIT(19)
117 #define EP0_TXPKTRDY BIT(18)
118 #define EP0_SETUPPKTRDY BIT(17)
119 #define EP0_RXPKTRDY BIT(16)
120 #define EP0_MAXPKTSZ_MSK GENMASK(9, 0)
121 #define EP0_MAXPKTSZ(x) ((x) & EP0_MAXPKTSZ_MSK)
122 #define EP0_W1C_BITS (~(EP0_RXPKTRDY | EP0_SETUPPKTRDY | EP0_SENTSTALL))
125 #define TX_DMAREQEN BIT(29)
126 #define TX_FIFOFULL BIT(25)
127 #define TX_FIFOEMPTY BIT(24)
128 #define TX_SENTSTALL BIT(22)
129 #define TX_SENDSTALL BIT(21)
130 #define TX_TXPKTRDY BIT(16)
131 #define TX_TXMAXPKTSZ_MSK GENMASK(10, 0)
132 #define TX_TXMAXPKTSZ(x) ((x) & TX_TXMAXPKTSZ_MSK)
133 #define TX_W1C_BITS (~(TX_SENTSTALL))
136 #define TX_MULT(x) (((x) & 0x3) << 22)
137 #define TX_MAX_PKT(x) (((x) & 0x3f) << 16)
138 #define TX_SLOT(x) (((x) & 0x3f) << 8)
139 #define TX_TYPE(x) (((x) & 0x3) << 4)
140 #define TX_SS_BURST(x) (((x) & 0xf) << 0)
142 /* for TX_TYPE & RX_TYPE */
143 #define TYPE_BULK (0x0)
144 #define TYPE_INT (0x1)
145 #define TYPE_ISO (0x2)
146 #define TYPE_MASK (0x3)
149 #define TX_BINTERVAL(x) (((x) & 0xff) << 24)
150 #define TX_FIFOSEGSIZE(x) (((x) & 0xf) << 16)
151 #define TX_FIFOADDR(x) (((x) & 0x1fff) << 0)
154 #define RX_DMAREQEN BIT(29)
155 #define RX_SENTSTALL BIT(22)
156 #define RX_SENDSTALL BIT(21)
157 #define RX_RXPKTRDY BIT(16)
158 #define RX_RXMAXPKTSZ_MSK GENMASK(10, 0)
159 #define RX_RXMAXPKTSZ(x) ((x) & RX_RXMAXPKTSZ_MSK)
160 #define RX_W1C_BITS (~(RX_SENTSTALL | RX_RXPKTRDY))
163 #define RX_MULT(x) (((x) & 0x3) << 22)
164 #define RX_MAX_PKT(x) (((x) & 0x3f) << 16)
165 #define RX_SLOT(x) (((x) & 0x3f) << 8)
166 #define RX_TYPE(x) (((x) & 0x3) << 4)
167 #define RX_SS_BURST(x) (((x) & 0xf) << 0)
170 #define RX_BINTERVAL(x) (((x) & 0xff) << 24)
171 #define RX_FIFOSEGSIZE(x) (((x) & 0xf) << 16)
172 #define RX_FIFOADDR(x) (((x) & 0x1fff) << 0)
175 #define QMU_RX_CS_EN(x) (BIT(16) << (x))
176 #define QMU_TX_CS_EN(x) (BIT(0) << (x))
177 #define QMU_CS16B_EN BIT(0)
180 #define QMU_TX_ZLP(x) (BIT(0) << (x))
183 #define QMU_RX_COZ(x) (BIT(16) << (x))
184 #define QMU_RX_ZLP(x) (BIT(0) << (x))
188 #define QMU_LAST_DONE_PTR_HI(x) (((x) >> 16) & 0xf)
189 #define QMU_CUR_GPD_ADDR_HI(x) (((x) >> 8) & 0xf)
190 #define QMU_START_ADDR_HI_MSK GENMASK(3, 0)
191 #define QMU_START_ADDR_HI(x) (((x) & 0xf) << 0)
195 #define QMU_Q_ACTIVE BIT(15)
196 #define QMU_Q_STOP BIT(2)
197 #define QMU_Q_RESUME BIT(1)
198 #define QMU_Q_START BIT(0)
200 /* U3D_QISAR0, U3D_QIER0, U3D_QIESR0, U3D_QIECR0 */
201 #define QMU_RX_DONE_INT(x) (BIT(16) << (x))
202 #define QMU_TX_DONE_INT(x) (BIT(0) << (x))
204 /* U3D_QISAR1, U3D_QIER1, U3D_QIESR1, U3D_QIECR1 */
205 #define RXQ_ZLPERR_INT BIT(20)
206 #define RXQ_LENERR_INT BIT(18)
207 #define RXQ_CSERR_INT BIT(17)
208 #define RXQ_EMPTY_INT BIT(16)
209 #define TXQ_LENERR_INT BIT(2)
210 #define TXQ_CSERR_INT BIT(1)
211 #define TXQ_EMPTY_INT BIT(0)
213 /* U3D_TQERRIR0, U3D_TQERRIER0, U3D_TQERRIESR0, U3D_TQERRIECR0 */
214 #define QMU_TX_LEN_ERR(x) (BIT(16) << (x))
215 #define QMU_TX_CS_ERR(x) (BIT(0) << (x))
217 /* U3D_RQERRIR0, U3D_RQERRIER0, U3D_RQERRIESR0, U3D_RQERRIECR0 */
218 #define QMU_RX_LEN_ERR(x) (BIT(16) << (x))
219 #define QMU_RX_CS_ERR(x) (BIT(0) << (x))
221 /* U3D_RQERRIR1, U3D_RQERRIER1, U3D_RQERRIESR1, U3D_RQERRIECR1 */
222 #define QMU_RX_ZLP_ERR(n) (BIT(16) << (n))
225 #define CAP_RX_EP_NUM(x) (((x) >> 8) & 0x1f)
226 #define CAP_TX_EP_NUM(x) ((x) & 0x1f)
229 #define DMA_ADDR_36BIT BIT(31)
230 #define VBUS_ON BIT(1)
231 #define VBUS_FRC_EN BIT(0)
234 /*---------------- SSUSB_EPCTL_CSR REGISTER DEFINITION ----------------*/
236 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
237 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
239 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
240 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
242 /*---------------- SSUSB_EPCTL_CSR FIELD DEFINITION ----------------*/
244 /* U3D_DEVICE_CONF */
245 #define DEV_ADDR_MSK GENMASK(30, 24)
246 #define DEV_ADDR(x) ((0x7f & (x)) << 24)
247 #define HW_USB2_3_SEL BIT(18)
248 #define SW_USB2_3_SEL_EN BIT(17)
249 #define SW_USB2_3_SEL BIT(16)
250 #define SSUSB_DEV_SPEED(x) ((x) & 0x7)
253 #define EP1_IN_RST BIT(17)
254 #define EP1_OUT_RST BIT(1)
255 #define EP_RST(is_in, epnum) (((is_in) ? BIT(16) : BIT(0)) << (epnum))
256 #define EP0_RST BIT(0)
258 /* U3D_DEV_LINK_INTR_ENABLE */
259 /* U3D_DEV_LINK_INTR */
260 #define SSUSB_DEV_SPEED_CHG_INTR BIT(0)
263 /*---------------- SSUSB_USB3_MAC_CSR REGISTER DEFINITION ----------------*/
265 #define U3D_LTSSM_CTRL (SSUSB_USB3_MAC_CSR_BASE + 0x0010)
266 #define U3D_USB3_CONFIG (SSUSB_USB3_MAC_CSR_BASE + 0x001C)
268 #define U3D_LTSSM_INTR_ENABLE (SSUSB_USB3_MAC_CSR_BASE + 0x013C)
269 #define U3D_LTSSM_INTR (SSUSB_USB3_MAC_CSR_BASE + 0x0140)
271 #define U3D_U3U2_SWITCH_CTRL (SSUSB_USB3_MAC_CSR_BASE + 0x0170)
273 /*---------------- SSUSB_USB3_MAC_CSR FIELD DEFINITION ----------------*/
276 #define FORCE_POLLING_FAIL BIT(4)
277 #define FORCE_RXDETECT_FAIL BIT(3)
278 #define SOFT_U3_EXIT_EN BIT(2)
279 #define COMPLIANCE_EN BIT(1)
280 #define U1_GO_U2_EN BIT(0)
282 /* U3D_USB3_CONFIG */
283 #define USB3_EN BIT(0)
285 /* U3D_LTSSM_INTR_ENABLE */
287 #define U3_RESUME_INTR BIT(18)
288 #define U3_LFPS_TMOUT_INTR BIT(17)
289 #define VBUS_FALL_INTR BIT(16)
290 #define VBUS_RISE_INTR BIT(15)
291 #define RXDET_SUCCESS_INTR BIT(14)
292 #define EXIT_U3_INTR BIT(13)
293 #define EXIT_U2_INTR BIT(12)
294 #define EXIT_U1_INTR BIT(11)
295 #define ENTER_U3_INTR BIT(10)
296 #define ENTER_U2_INTR BIT(9)
297 #define ENTER_U1_INTR BIT(8)
298 #define ENTER_U0_INTR BIT(7)
299 #define RECOVERY_INTR BIT(6)
300 #define WARM_RST_INTR BIT(5)
301 #define HOT_RST_INTR BIT(4)
302 #define LOOPBACK_INTR BIT(3)
303 #define COMPLIANCE_INTR BIT(2)
304 #define SS_DISABLE_INTR BIT(1)
305 #define SS_INACTIVE_INTR BIT(0)
307 /* U3D_U3U2_SWITCH_CTRL */
308 #define SOFTCON_CLR_AUTO_EN BIT(0)
310 /*---------------- SSUSB_USB3_SYS_CSR REGISTER DEFINITION ----------------*/
312 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
313 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
314 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
316 /*---------------- SSUSB_USB3_SYS_CSR FIELD DEFINITION ----------------*/
318 /* U3D_LINK_UX_INACT_TIMER */
319 #define DEV_U2_INACT_TIMEOUT_MSK GENMASK(23, 16)
320 #define DEV_U2_INACT_TIMEOUT_VALUE(x) (((x) & 0xff) << 16)
321 #define U2_INACT_TIMEOUT_MSK GENMASK(15, 8)
322 #define U1_INACT_TIMEOUT_MSK GENMASK(7, 0)
323 #define U1_INACT_TIMEOUT_VALUE(x) ((x) & 0xff)
325 /* U3D_LINK_POWER_CONTROL */
326 #define SW_U2_ACCEPT_ENABLE BIT(9)
327 #define SW_U1_ACCEPT_ENABLE BIT(8)
328 #define UX_EXIT BIT(5)
329 #define LGO_U3 BIT(4)
330 #define LGO_U2 BIT(3)
331 #define LGO_U1 BIT(2)
332 #define SW_U2_REQUEST_ENABLE BIT(1)
333 #define SW_U1_REQUEST_ENABLE BIT(0)
335 /* U3D_LINK_ERR_COUNT */
336 #define CLR_LINK_ERR_CNT BIT(16)
337 #define LINK_ERROR_COUNT GENMASK(15, 0)
339 /*---------------- SSUSB_USB2_CSR REGISTER DEFINITION ----------------*/
341 #define U3D_POWER_MANAGEMENT (SSUSB_USB2_CSR_BASE + 0x0004)
342 #define U3D_DEVICE_CONTROL (SSUSB_USB2_CSR_BASE + 0x000C)
343 #define U3D_USB2_TEST_MODE (SSUSB_USB2_CSR_BASE + 0x0014)
344 #define U3D_COMMON_USB_INTR_ENABLE (SSUSB_USB2_CSR_BASE + 0x0018)
345 #define U3D_COMMON_USB_INTR (SSUSB_USB2_CSR_BASE + 0x001C)
346 #define U3D_LINK_RESET_INFO (SSUSB_USB2_CSR_BASE + 0x0024)
347 #define U3D_USB20_FRAME_NUM (SSUSB_USB2_CSR_BASE + 0x003C)
348 #define U3D_USB20_LPM_PARAMETER (SSUSB_USB2_CSR_BASE + 0x0044)
349 #define U3D_USB20_MISC_CONTROL (SSUSB_USB2_CSR_BASE + 0x004C)
351 /*---------------- SSUSB_USB2_CSR FIELD DEFINITION ----------------*/
353 /* U3D_POWER_MANAGEMENT */
354 #define LPM_BESL_STALL BIT(14)
355 #define LPM_BESLD_STALL BIT(13)
356 #define LPM_RWP BIT(11)
357 #define LPM_HRWE BIT(10)
358 #define LPM_MODE(x) (((x) & 0x3) << 8)
359 #define ISO_UPDATE BIT(7)
360 #define SOFT_CONN BIT(6)
361 #define HS_ENABLE BIT(5)
362 #define RESUME BIT(2)
363 #define SUSPENDM_ENABLE BIT(0)
365 /* U3D_DEVICE_CONTROL */
366 #define DC_HOSTREQ BIT(1)
367 #define DC_SESSION BIT(0)
369 /* U3D_USB2_TEST_MODE */
370 #define U2U3_AUTO_SWITCH BIT(10)
371 #define LPM_FORCE_STALL BIT(8)
372 #define FIFO_ACCESS BIT(6)
373 #define FORCE_FS BIT(5)
374 #define FORCE_HS BIT(4)
375 #define TEST_PACKET_MODE BIT(3)
376 #define TEST_K_MODE BIT(2)
377 #define TEST_J_MODE BIT(1)
378 #define TEST_SE0_NAK_MODE BIT(0)
380 /* U3D_COMMON_USB_INTR_ENABLE */
381 /* U3D_COMMON_USB_INTR */
382 #define LPM_RESUME_INTR BIT(9)
383 #define LPM_INTR BIT(8)
384 #define DISCONN_INTR BIT(5)
385 #define CONN_INTR BIT(4)
386 #define SOF_INTR BIT(3)
387 #define RESET_INTR BIT(2)
388 #define RESUME_INTR BIT(1)
389 #define SUSPEND_INTR BIT(0)
391 /* U3D_LINK_RESET_INFO */
392 #define WTCHRP_MSK GENMASK(19, 16)
394 /* U3D_USB20_LPM_PARAMETER */
395 #define LPM_BESLCK_U3(x) (((x) & 0xf) << 12)
396 #define LPM_BESLCK(x) (((x) & 0xf) << 8)
397 #define LPM_BESLDCK(x) (((x) & 0xf) << 4)
398 #define LPM_BESL GENMASK(3, 0)
400 /* U3D_USB20_MISC_CONTROL */
401 #define LPM_U3_ACK_EN BIT(0)
403 /*---------------- SSUSB_SIFSLV_IPPC REGISTER DEFINITION ----------------*/
405 #define U3D_SSUSB_IP_PW_CTRL0 (SSUSB_SIFSLV_IPPC_BASE + 0x0000)
406 #define U3D_SSUSB_IP_PW_CTRL1 (SSUSB_SIFSLV_IPPC_BASE + 0x0004)
407 #define U3D_SSUSB_IP_PW_CTRL2 (SSUSB_SIFSLV_IPPC_BASE + 0x0008)
408 #define U3D_SSUSB_IP_PW_CTRL3 (SSUSB_SIFSLV_IPPC_BASE + 0x000C)
409 #define U3D_SSUSB_IP_PW_STS1 (SSUSB_SIFSLV_IPPC_BASE + 0x0010)
410 #define U3D_SSUSB_IP_PW_STS2 (SSUSB_SIFSLV_IPPC_BASE + 0x0014)
411 #define U3D_SSUSB_OTG_STS (SSUSB_SIFSLV_IPPC_BASE + 0x0018)
412 #define U3D_SSUSB_OTG_STS_CLR (SSUSB_SIFSLV_IPPC_BASE + 0x001C)
413 #define U3D_SSUSB_IP_XHCI_CAP (SSUSB_SIFSLV_IPPC_BASE + 0x0024)
414 #define U3D_SSUSB_IP_DEV_CAP (SSUSB_SIFSLV_IPPC_BASE + 0x0028)
415 #define U3D_SSUSB_OTG_INT_EN (SSUSB_SIFSLV_IPPC_BASE + 0x002C)
416 #define U3D_SSUSB_U3_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0030)
417 #define U3D_SSUSB_U2_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0050)
418 #define U3D_SSUSB_REF_CK_CTRL (SSUSB_SIFSLV_IPPC_BASE + 0x008C)
419 #define U3D_SSUSB_DEV_RST_CTRL (SSUSB_SIFSLV_IPPC_BASE + 0x0098)
420 #define U3D_SSUSB_HW_ID (SSUSB_SIFSLV_IPPC_BASE + 0x00A0)
421 #define U3D_SSUSB_HW_SUB_ID (SSUSB_SIFSLV_IPPC_BASE + 0x00A4)
422 #define U3D_SSUSB_IP_SPARE0 (SSUSB_SIFSLV_IPPC_BASE + 0x00C8)
424 /*---------------- SSUSB_SIFSLV_IPPC FIELD DEFINITION ----------------*/
426 /* U3D_SSUSB_IP_PW_CTRL0 */
427 #define SSUSB_IP_SW_RST BIT(0)
429 /* U3D_SSUSB_IP_PW_CTRL1 */
430 #define SSUSB_IP_HOST_PDN BIT(0)
432 /* U3D_SSUSB_IP_PW_CTRL2 */
433 #define SSUSB_IP_DEV_PDN BIT(0)
435 /* U3D_SSUSB_IP_PW_CTRL3 */
436 #define SSUSB_IP_PCIE_PDN BIT(0)
438 /* U3D_SSUSB_IP_PW_STS1 */
439 #define SSUSB_IP_SLEEP_STS BIT(30)
440 #define SSUSB_U3_MAC_RST_B_STS BIT(16)
441 #define SSUSB_XHCI_RST_B_STS BIT(11)
442 #define SSUSB_SYS125_RST_B_STS BIT(10)
443 #define SSUSB_REF_RST_B_STS BIT(8)
444 #define SSUSB_SYSPLL_STABLE BIT(0)
446 /* U3D_SSUSB_IP_PW_STS2 */
447 #define SSUSB_U2_MAC_SYS_RST_B_STS BIT(0)
449 /* U3D_SSUSB_OTG_STS */
450 #define SSUSB_VBUS_VALID BIT(9)
452 /* U3D_SSUSB_OTG_STS_CLR */
453 #define SSUSB_VBUS_INTR_CLR BIT(6)
455 /* U3D_SSUSB_IP_XHCI_CAP */
456 #define SSUSB_IP_XHCI_U2_PORT_NUM(x) (((x) >> 8) & 0xff)
457 #define SSUSB_IP_XHCI_U3_PORT_NUM(x) ((x) & 0xff)
459 /* U3D_SSUSB_IP_DEV_CAP */
460 #define SSUSB_IP_DEV_U3_PORT_NUM(x) ((x) & 0xff)
462 /* U3D_SSUSB_OTG_INT_EN */
463 #define SSUSB_VBUS_CHG_INT_A_EN BIT(7)
464 #define SSUSB_VBUS_CHG_INT_B_EN BIT(6)
466 /* U3D_SSUSB_U3_CTRL_0P */
467 #define SSUSB_U3_PORT_SSP_SPEED BIT(9)
468 #define SSUSB_U3_PORT_DUAL_MODE BIT(7)
469 #define SSUSB_U3_PORT_HOST_SEL BIT(2)
470 #define SSUSB_U3_PORT_PDN BIT(1)
471 #define SSUSB_U3_PORT_DIS BIT(0)
473 /* U3D_SSUSB_U2_CTRL_0P */
474 #define SSUSB_U2_PORT_RG_IDDIG BIT(12)
475 #define SSUSB_U2_PORT_FORCE_IDDIG BIT(11)
476 #define SSUSB_U2_PORT_VBUSVALID BIT(9)
477 #define SSUSB_U2_PORT_OTG_SEL BIT(7)
478 #define SSUSB_U2_PORT_HOST BIT(2)
479 #define SSUSB_U2_PORT_PDN BIT(1)
480 #define SSUSB_U2_PORT_DIS BIT(0)
481 #define SSUSB_U2_PORT_HOST_SEL (SSUSB_U2_PORT_VBUSVALID | SSUSB_U2_PORT_HOST)
483 /* U3D_SSUSB_DEV_RST_CTRL */
484 #define SSUSB_DEV_SW_RST BIT(0)
486 #endif /* _SSUSB_HW_REGS_H_ */
projects / linux-2.6-microblaze.git / blob