1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/iopoll.h>
13 #include <linux/irq.h>
14 #include <linux/log2.h>
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/slab.h>
18 #include <linux/dmi.h>
19 #include <linux/dma-mapping.h>
22 #include "xhci-trace.h"
23 #include "xhci-debugfs.h"
24 #include "xhci-dbgcap.h"
26 #define DRIVER_AUTHOR "Sarah Sharp"
27 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
29 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
32 static int link_quirk;
33 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
34 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
36 static unsigned long long quirks;
37 module_param(quirks, ullong, S_IRUGO);
38 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
40 static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
42 struct xhci_segment *seg = ring->first_seg;
44 if (!td || !td->start_seg)
47 if (seg == td->start_seg)
50 } while (seg && seg != ring->first_seg);
56 * xhci_handshake - spin reading hc until handshake completes or fails
57 * @ptr: address of hc register to be read
58 * @mask: bits to look at in result of read
59 * @done: value of those bits when handshake succeeds
60 * @usec: timeout in microseconds
62 * Returns negative errno, or zero on success
64 * Success happens when the "mask" bits have the specified value (hardware
65 * handshake done). There are two failure modes: "usec" have passed (major
66 * hardware flakeout), or the register reads as all-ones (hardware removed).
68 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us)
73 ret = readl_poll_timeout_atomic(ptr, result,
74 (result & mask) == done ||
77 if (result == U32_MAX) /* card removed */
84 * Disable interrupts and begin the xHCI halting process.
86 void xhci_quiesce(struct xhci_hcd *xhci)
93 halted = readl(&xhci->op_regs->status) & STS_HALT;
97 cmd = readl(&xhci->op_regs->command);
99 writel(cmd, &xhci->op_regs->command);
103 * Force HC into halt state.
105 * Disable any IRQs and clear the run/stop bit.
106 * HC will complete any current and actively pipelined transactions, and
107 * should halt within 16 ms of the run/stop bit being cleared.
108 * Read HC Halted bit in the status register to see when the HC is finished.
110 int xhci_halt(struct xhci_hcd *xhci)
114 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
117 ret = xhci_handshake(&xhci->op_regs->status,
118 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
120 xhci_warn(xhci, "Host halt failed, %d\n", ret);
124 xhci->xhc_state |= XHCI_STATE_HALTED;
125 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
131 * Set the run bit and wait for the host to be running.
133 int xhci_start(struct xhci_hcd *xhci)
138 temp = readl(&xhci->op_regs->command);
140 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
142 writel(temp, &xhci->op_regs->command);
145 * Wait for the HCHalted Status bit to be 0 to indicate the host is
148 ret = xhci_handshake(&xhci->op_regs->status,
149 STS_HALT, 0, XHCI_MAX_HALT_USEC);
150 if (ret == -ETIMEDOUT)
151 xhci_err(xhci, "Host took too long to start, "
152 "waited %u microseconds.\n",
155 /* clear state flags. Including dying, halted or removing */
164 * This resets pipelines, timers, counters, state machines, etc.
165 * Transactions will be terminated immediately, and operational registers
166 * will be set to their defaults.
168 int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us)
174 state = readl(&xhci->op_regs->status);
176 if (state == ~(u32)0) {
177 xhci_warn(xhci, "Host not accessible, reset failed.\n");
181 if ((state & STS_HALT) == 0) {
182 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
186 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
187 command = readl(&xhci->op_regs->command);
188 command |= CMD_RESET;
189 writel(command, &xhci->op_regs->command);
191 /* Existing Intel xHCI controllers require a delay of 1 mS,
192 * after setting the CMD_RESET bit, and before accessing any
193 * HC registers. This allows the HC to complete the
194 * reset operation and be ready for HC register access.
195 * Without this delay, the subsequent HC register access,
196 * may result in a system hang very rarely.
198 if (xhci->quirks & XHCI_INTEL_HOST)
201 ret = xhci_handshake(&xhci->op_regs->command, CMD_RESET, 0, timeout_us);
205 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
206 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
208 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
209 "Wait for controller to be ready for doorbell rings");
211 * xHCI cannot write to any doorbells or operational registers other
212 * than status until the "Controller Not Ready" flag is cleared.
214 ret = xhci_handshake(&xhci->op_regs->status, STS_CNR, 0, timeout_us);
216 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
217 xhci->usb2_rhub.bus_state.suspended_ports = 0;
218 xhci->usb2_rhub.bus_state.resuming_ports = 0;
219 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
220 xhci->usb3_rhub.bus_state.suspended_ports = 0;
221 xhci->usb3_rhub.bus_state.resuming_ports = 0;
226 static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
228 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
234 * Some Renesas controllers get into a weird state if they are
235 * reset while programmed with 64bit addresses (they will preserve
236 * the top half of the address in internal, non visible
237 * registers). You end up with half the address coming from the
238 * kernel, and the other half coming from the firmware. Also,
239 * changing the programming leads to extra accesses even if the
240 * controller is supposed to be halted. The controller ends up with
241 * a fatal fault, and is then ripe for being properly reset.
243 * Special care is taken to only apply this if the device is behind
244 * an iommu. Doing anything when there is no iommu is definitely
247 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !device_iommu_mapped(dev))
250 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
252 /* Clear HSEIE so that faults do not get signaled */
253 val = readl(&xhci->op_regs->command);
255 writel(val, &xhci->op_regs->command);
257 /* Clear HSE (aka FATAL) */
258 val = readl(&xhci->op_regs->status);
260 writel(val, &xhci->op_regs->status);
262 /* Now zero the registers, and brace for impact */
263 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
264 if (upper_32_bits(val))
265 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
266 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
267 if (upper_32_bits(val))
268 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
270 intrs = min_t(u32, HCS_MAX_INTRS(xhci->hcs_params1),
271 ARRAY_SIZE(xhci->run_regs->ir_set));
273 for (i = 0; i < intrs; i++) {
274 struct xhci_intr_reg __iomem *ir;
276 ir = &xhci->run_regs->ir_set[i];
277 val = xhci_read_64(xhci, &ir->erst_base);
278 if (upper_32_bits(val))
279 xhci_write_64(xhci, 0, &ir->erst_base);
280 val= xhci_read_64(xhci, &ir->erst_dequeue);
281 if (upper_32_bits(val))
282 xhci_write_64(xhci, 0, &ir->erst_dequeue);
285 /* Wait for the fault to appear. It will be cleared on reset */
286 err = xhci_handshake(&xhci->op_regs->status,
287 STS_FATAL, STS_FATAL,
290 xhci_info(xhci, "Fault detected\n");
293 #ifdef CONFIG_USB_PCI
297 static int xhci_setup_msi(struct xhci_hcd *xhci)
301 * TODO:Check with MSI Soc for sysdev
303 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
305 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
307 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
308 "failed to allocate MSI entry");
312 ret = request_irq(pdev->irq, xhci_msi_irq,
313 0, "xhci_hcd", xhci_to_hcd(xhci));
315 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
316 "disable MSI interrupt");
317 pci_free_irq_vectors(pdev);
326 static int xhci_setup_msix(struct xhci_hcd *xhci)
329 struct usb_hcd *hcd = xhci_to_hcd(xhci);
330 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
333 * calculate number of msi-x vectors supported.
334 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
335 * with max number of interrupters based on the xhci HCSPARAMS1.
336 * - num_online_cpus: maximum msi-x vectors per CPUs core.
337 * Add additional 1 vector to ensure always available interrupt.
339 xhci->msix_count = min(num_online_cpus() + 1,
340 HCS_MAX_INTRS(xhci->hcs_params1));
342 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
345 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
346 "Failed to enable MSI-X");
350 for (i = 0; i < xhci->msix_count; i++) {
351 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
352 "xhci_hcd", xhci_to_hcd(xhci));
357 hcd->msix_enabled = 1;
361 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
363 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
364 pci_free_irq_vectors(pdev);
368 /* Free any IRQs and disable MSI-X */
369 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
371 struct usb_hcd *hcd = xhci_to_hcd(xhci);
372 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
374 if (xhci->quirks & XHCI_PLAT)
377 /* return if using legacy interrupt */
381 if (hcd->msix_enabled) {
384 for (i = 0; i < xhci->msix_count; i++)
385 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
387 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
390 pci_free_irq_vectors(pdev);
391 hcd->msix_enabled = 0;
394 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
396 struct usb_hcd *hcd = xhci_to_hcd(xhci);
398 if (hcd->msix_enabled) {
399 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
402 for (i = 0; i < xhci->msix_count; i++)
403 synchronize_irq(pci_irq_vector(pdev, i));
407 static int xhci_try_enable_msi(struct usb_hcd *hcd)
409 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
410 struct pci_dev *pdev;
413 /* The xhci platform device has set up IRQs through usb_add_hcd. */
414 if (xhci->quirks & XHCI_PLAT)
417 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
419 * Some Fresco Logic host controllers advertise MSI, but fail to
420 * generate interrupts. Don't even try to enable MSI.
422 if (xhci->quirks & XHCI_BROKEN_MSI)
425 /* unregister the legacy interrupt */
427 free_irq(hcd->irq, hcd);
430 ret = xhci_setup_msix(xhci);
432 /* fall back to msi*/
433 ret = xhci_setup_msi(xhci);
436 hcd->msi_enabled = 1;
441 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
446 if (!strlen(hcd->irq_descr))
447 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
448 hcd->driver->description, hcd->self.busnum);
450 /* fall back to legacy interrupt*/
451 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
452 hcd->irq_descr, hcd);
454 xhci_err(xhci, "request interrupt %d failed\n",
458 hcd->irq = pdev->irq;
464 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
469 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
473 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
479 static void compliance_mode_recovery(struct timer_list *t)
481 struct xhci_hcd *xhci;
483 struct xhci_hub *rhub;
487 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
488 rhub = &xhci->usb3_rhub;
494 for (i = 0; i < rhub->num_ports; i++) {
495 temp = readl(rhub->ports[i]->addr);
496 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
498 * Compliance Mode Detected. Letting USB Core
499 * handle the Warm Reset
501 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
502 "Compliance mode detected->port %d",
504 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
505 "Attempting compliance mode recovery");
507 if (hcd->state == HC_STATE_SUSPENDED)
508 usb_hcd_resume_root_hub(hcd);
510 usb_hcd_poll_rh_status(hcd);
514 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
515 mod_timer(&xhci->comp_mode_recovery_timer,
516 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
520 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
521 * that causes ports behind that hardware to enter compliance mode sometimes.
522 * The quirk creates a timer that polls every 2 seconds the link state of
523 * each host controller's port and recovers it by issuing a Warm reset
524 * if Compliance mode is detected, otherwise the port will become "dead" (no
525 * device connections or disconnections will be detected anymore). Becasue no
526 * status event is generated when entering compliance mode (per xhci spec),
527 * this quirk is needed on systems that have the failing hardware installed.
529 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
531 xhci->port_status_u0 = 0;
532 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
534 xhci->comp_mode_recovery_timer.expires = jiffies +
535 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
537 add_timer(&xhci->comp_mode_recovery_timer);
538 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
539 "Compliance mode recovery timer initialized");
543 * This function identifies the systems that have installed the SN65LVPE502CP
544 * USB3.0 re-driver and that need the Compliance Mode Quirk.
546 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
548 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
550 const char *dmi_product_name, *dmi_sys_vendor;
552 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
553 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
554 if (!dmi_product_name || !dmi_sys_vendor)
557 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
560 if (strstr(dmi_product_name, "Z420") ||
561 strstr(dmi_product_name, "Z620") ||
562 strstr(dmi_product_name, "Z820") ||
563 strstr(dmi_product_name, "Z1 Workstation"))
569 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
571 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
576 * Initialize memory for HCD and xHC (one-time init).
578 * Program the PAGESIZE register, initialize the device context array, create
579 * device contexts (?), set up a command ring segment (or two?), create event
580 * ring (one for now).
582 static int xhci_init(struct usb_hcd *hcd)
584 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
587 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
588 spin_lock_init(&xhci->lock);
589 if (xhci->hci_version == 0x95 && link_quirk) {
590 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
591 "QUIRK: Not clearing Link TRB chain bits.");
592 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
594 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
595 "xHCI doesn't need link TRB QUIRK");
597 retval = xhci_mem_init(xhci, GFP_KERNEL);
598 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
600 /* Initializing Compliance Mode Recovery Data If Needed */
601 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
602 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
603 compliance_mode_recovery_timer_init(xhci);
609 /*-------------------------------------------------------------------------*/
612 static int xhci_run_finished(struct xhci_hcd *xhci)
614 if (xhci_start(xhci)) {
618 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
620 if (xhci->quirks & XHCI_NEC_HOST)
621 xhci_ring_cmd_db(xhci);
627 * Start the HC after it was halted.
629 * This function is called by the USB core when the HC driver is added.
630 * Its opposite is xhci_stop().
632 * xhci_init() must be called once before this function can be called.
633 * Reset the HC, enable device slot contexts, program DCBAAP, and
634 * set command ring pointer and event ring pointer.
636 * Setup MSI-X vectors and enable interrupts.
638 int xhci_run(struct usb_hcd *hcd)
643 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
645 /* Start the xHCI host controller running only after the USB 2.0 roothub
649 hcd->uses_new_polling = 1;
650 if (!usb_hcd_is_primary_hcd(hcd))
651 return xhci_run_finished(xhci);
653 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
655 ret = xhci_try_enable_msi(hcd);
659 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
660 temp_64 &= ~ERST_PTR_MASK;
661 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
662 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
664 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
665 "// Set the interrupt modulation register");
666 temp = readl(&xhci->ir_set->irq_control);
667 temp &= ~ER_IRQ_INTERVAL_MASK;
668 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
669 writel(temp, &xhci->ir_set->irq_control);
671 /* Set the HCD state before we enable the irqs */
672 temp = readl(&xhci->op_regs->command);
674 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
675 "// Enable interrupts, cmd = 0x%x.", temp);
676 writel(temp, &xhci->op_regs->command);
678 temp = readl(&xhci->ir_set->irq_pending);
679 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
680 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
681 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
682 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
684 if (xhci->quirks & XHCI_NEC_HOST) {
685 struct xhci_command *command;
687 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
691 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
692 TRB_TYPE(TRB_NEC_GET_FW));
694 xhci_free_command(xhci, command);
696 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
697 "Finished %s for main hcd", __func__);
699 xhci_create_dbc_dev(xhci);
701 xhci_debugfs_init(xhci);
703 if (xhci_has_one_roothub(xhci))
704 return xhci_run_finished(xhci);
706 set_bit(HCD_FLAG_DEFER_RH_REGISTER, &hcd->flags);
710 EXPORT_SYMBOL_GPL(xhci_run);
715 * This function is called by the USB core when the HC driver is removed.
716 * Its opposite is xhci_run().
718 * Disable device contexts, disable IRQs, and quiesce the HC.
719 * Reset the HC, finish any completed transactions, and cleanup memory.
721 static void xhci_stop(struct usb_hcd *hcd)
724 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
726 mutex_lock(&xhci->mutex);
728 /* Only halt host and free memory after both hcds are removed */
729 if (!usb_hcd_is_primary_hcd(hcd)) {
730 mutex_unlock(&xhci->mutex);
734 xhci_remove_dbc_dev(xhci);
736 spin_lock_irq(&xhci->lock);
737 xhci->xhc_state |= XHCI_STATE_HALTED;
738 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
740 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
741 spin_unlock_irq(&xhci->lock);
743 xhci_cleanup_msix(xhci);
745 /* Deleting Compliance Mode Recovery Timer */
746 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
747 (!(xhci_all_ports_seen_u0(xhci)))) {
748 del_timer_sync(&xhci->comp_mode_recovery_timer);
749 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
750 "%s: compliance mode recovery timer deleted",
754 if (xhci->quirks & XHCI_AMD_PLL_FIX)
757 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
758 "// Disabling event ring interrupts");
759 temp = readl(&xhci->op_regs->status);
760 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
761 temp = readl(&xhci->ir_set->irq_pending);
762 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
764 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
765 xhci_mem_cleanup(xhci);
766 xhci_debugfs_exit(xhci);
767 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
768 "xhci_stop completed - status = %x",
769 readl(&xhci->op_regs->status));
770 mutex_unlock(&xhci->mutex);
774 * Shutdown HC (not bus-specific)
776 * This is called when the machine is rebooting or halting. We assume that the
777 * machine will be powered off, and the HC's internal state will be reset.
778 * Don't bother to free memory.
780 * This will only ever be called with the main usb_hcd (the USB3 roothub).
782 void xhci_shutdown(struct usb_hcd *hcd)
784 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
786 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
787 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
789 /* Don't poll the roothubs after shutdown. */
790 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
791 __func__, hcd->self.busnum);
792 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
793 del_timer_sync(&hcd->rh_timer);
795 if (xhci->shared_hcd) {
796 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
797 del_timer_sync(&xhci->shared_hcd->rh_timer);
800 spin_lock_irq(&xhci->lock);
802 /* Workaround for spurious wakeups at shutdown with HSW */
803 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
804 xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
805 spin_unlock_irq(&xhci->lock);
807 xhci_cleanup_msix(xhci);
809 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
810 "xhci_shutdown completed - status = %x",
811 readl(&xhci->op_regs->status));
813 EXPORT_SYMBOL_GPL(xhci_shutdown);
816 static void xhci_save_registers(struct xhci_hcd *xhci)
818 xhci->s3.command = readl(&xhci->op_regs->command);
819 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
820 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
821 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
822 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
823 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
824 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
825 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
826 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
829 static void xhci_restore_registers(struct xhci_hcd *xhci)
831 writel(xhci->s3.command, &xhci->op_regs->command);
832 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
833 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
834 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
835 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
836 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
837 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
838 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
839 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
842 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
846 /* step 2: initialize command ring buffer */
847 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
848 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
849 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
850 xhci->cmd_ring->dequeue) &
851 (u64) ~CMD_RING_RSVD_BITS) |
852 xhci->cmd_ring->cycle_state;
853 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
854 "// Setting command ring address to 0x%llx",
855 (long unsigned long) val_64);
856 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
860 * The whole command ring must be cleared to zero when we suspend the host.
862 * The host doesn't save the command ring pointer in the suspend well, so we
863 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
864 * aligned, because of the reserved bits in the command ring dequeue pointer
865 * register. Therefore, we can't just set the dequeue pointer back in the
866 * middle of the ring (TRBs are 16-byte aligned).
868 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
870 struct xhci_ring *ring;
871 struct xhci_segment *seg;
873 ring = xhci->cmd_ring;
877 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
878 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
879 cpu_to_le32(~TRB_CYCLE);
881 } while (seg != ring->deq_seg);
883 /* Reset the software enqueue and dequeue pointers */
884 ring->deq_seg = ring->first_seg;
885 ring->dequeue = ring->first_seg->trbs;
886 ring->enq_seg = ring->deq_seg;
887 ring->enqueue = ring->dequeue;
889 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
891 * Ring is now zeroed, so the HW should look for change of ownership
892 * when the cycle bit is set to 1.
894 ring->cycle_state = 1;
897 * Reset the hardware dequeue pointer.
898 * Yes, this will need to be re-written after resume, but we're paranoid
899 * and want to make sure the hardware doesn't access bogus memory
900 * because, say, the BIOS or an SMI started the host without changing
901 * the command ring pointers.
903 xhci_set_cmd_ring_deq(xhci);
907 * Disable port wake bits if do_wakeup is not set.
909 * Also clear a possible internal port wake state left hanging for ports that
910 * detected termination but never successfully enumerated (trained to 0U).
911 * Internal wake causes immediate xHCI wake after suspend. PORT_CSC write done
912 * at enumeration clears this wake, force one here as well for unconnected ports
915 static void xhci_disable_hub_port_wake(struct xhci_hcd *xhci,
916 struct xhci_hub *rhub,
923 spin_lock_irqsave(&xhci->lock, flags);
925 for (i = 0; i < rhub->num_ports; i++) {
926 portsc = readl(rhub->ports[i]->addr);
927 t1 = xhci_port_state_to_neutral(portsc);
930 /* clear wake bits if do_wake is not set */
932 t2 &= ~PORT_WAKE_BITS;
934 /* Don't touch csc bit if connected or connect change is set */
935 if (!(portsc & (PORT_CSC | PORT_CONNECT)))
939 writel(t2, rhub->ports[i]->addr);
940 xhci_dbg(xhci, "config port %d-%d wake bits, portsc: 0x%x, write: 0x%x\n",
941 rhub->hcd->self.busnum, i + 1, portsc, t2);
944 spin_unlock_irqrestore(&xhci->lock, flags);
947 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
949 struct xhci_port **ports;
954 status = readl(&xhci->op_regs->status);
955 if (status & STS_EINT)
958 * Checking STS_EINT is not enough as there is a lag between a change
959 * bit being set and the Port Status Change Event that it generated
960 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
963 port_index = xhci->usb2_rhub.num_ports;
964 ports = xhci->usb2_rhub.ports;
965 while (port_index--) {
966 portsc = readl(ports[port_index]->addr);
967 if (portsc & PORT_CHANGE_MASK ||
968 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
971 port_index = xhci->usb3_rhub.num_ports;
972 ports = xhci->usb3_rhub.ports;
973 while (port_index--) {
974 portsc = readl(ports[port_index]->addr);
975 if (portsc & PORT_CHANGE_MASK ||
976 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
983 * Stop HC (not bus-specific)
985 * This is called when the machine transition into S3/S4 mode.
988 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
991 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
992 struct usb_hcd *hcd = xhci_to_hcd(xhci);
999 if (hcd->state != HC_STATE_SUSPENDED ||
1000 (xhci->shared_hcd && xhci->shared_hcd->state != HC_STATE_SUSPENDED))
1003 /* Clear root port wake on bits if wakeup not allowed. */
1004 xhci_disable_hub_port_wake(xhci, &xhci->usb3_rhub, do_wakeup);
1005 xhci_disable_hub_port_wake(xhci, &xhci->usb2_rhub, do_wakeup);
1007 if (!HCD_HW_ACCESSIBLE(hcd))
1010 xhci_dbc_suspend(xhci);
1012 /* Don't poll the roothubs on bus suspend. */
1013 xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
1014 __func__, hcd->self.busnum);
1015 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1016 del_timer_sync(&hcd->rh_timer);
1017 if (xhci->shared_hcd) {
1018 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1019 del_timer_sync(&xhci->shared_hcd->rh_timer);
1022 if (xhci->quirks & XHCI_SUSPEND_DELAY)
1023 usleep_range(1000, 1500);
1025 spin_lock_irq(&xhci->lock);
1026 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1027 if (xhci->shared_hcd)
1028 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1029 /* step 1: stop endpoint */
1030 /* skipped assuming that port suspend has done */
1032 /* step 2: clear Run/Stop bit */
1033 command = readl(&xhci->op_regs->command);
1034 command &= ~CMD_RUN;
1035 writel(command, &xhci->op_regs->command);
1037 /* Some chips from Fresco Logic need an extraordinary delay */
1038 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
1040 if (xhci_handshake(&xhci->op_regs->status,
1041 STS_HALT, STS_HALT, delay)) {
1042 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
1043 spin_unlock_irq(&xhci->lock);
1046 xhci_clear_command_ring(xhci);
1048 /* step 3: save registers */
1049 xhci_save_registers(xhci);
1051 /* step 4: set CSS flag */
1052 command = readl(&xhci->op_regs->command);
1054 writel(command, &xhci->op_regs->command);
1055 xhci->broken_suspend = 0;
1056 if (xhci_handshake(&xhci->op_regs->status,
1057 STS_SAVE, 0, 20 * 1000)) {
1059 * AMD SNPS xHC 3.0 occasionally does not clear the
1060 * SSS bit of USBSTS and when driver tries to poll
1061 * to see if the xHC clears BIT(8) which never happens
1062 * and driver assumes that controller is not responding
1063 * and times out. To workaround this, its good to check
1064 * if SRE and HCE bits are not set (as per xhci
1065 * Section 5.4.2) and bypass the timeout.
1067 res = readl(&xhci->op_regs->status);
1068 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
1069 (((res & STS_SRE) == 0) &&
1070 ((res & STS_HCE) == 0))) {
1071 xhci->broken_suspend = 1;
1073 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1074 spin_unlock_irq(&xhci->lock);
1078 spin_unlock_irq(&xhci->lock);
1081 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1082 * is about to be suspended.
1084 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1085 (!(xhci_all_ports_seen_u0(xhci)))) {
1086 del_timer_sync(&xhci->comp_mode_recovery_timer);
1087 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1088 "%s: compliance mode recovery timer deleted",
1092 /* step 5: remove core well power */
1093 /* synchronize irq when using MSI-X */
1094 xhci_msix_sync_irqs(xhci);
1098 EXPORT_SYMBOL_GPL(xhci_suspend);
1101 * start xHC (not bus-specific)
1103 * This is called when the machine transition from S3/S4 mode.
1106 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1108 u32 command, temp = 0;
1109 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1111 bool comp_timer_running = false;
1112 bool pending_portevent = false;
1113 bool reinit_xhc = false;
1118 /* Wait a bit if either of the roothubs need to settle from the
1119 * transition into bus suspend.
1122 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1123 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1126 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1127 if (xhci->shared_hcd)
1128 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1130 spin_lock_irq(&xhci->lock);
1132 if (hibernated || xhci->quirks & XHCI_RESET_ON_RESUME || xhci->broken_suspend)
1137 * Some controllers might lose power during suspend, so wait
1138 * for controller not ready bit to clear, just as in xHC init.
1140 retval = xhci_handshake(&xhci->op_regs->status,
1141 STS_CNR, 0, 10 * 1000 * 1000);
1143 xhci_warn(xhci, "Controller not ready at resume %d\n",
1145 spin_unlock_irq(&xhci->lock);
1148 /* step 1: restore register */
1149 xhci_restore_registers(xhci);
1150 /* step 2: initialize command ring buffer */
1151 xhci_set_cmd_ring_deq(xhci);
1152 /* step 3: restore state and start state*/
1153 /* step 3: set CRS flag */
1154 command = readl(&xhci->op_regs->command);
1156 writel(command, &xhci->op_regs->command);
1158 * Some controllers take up to 55+ ms to complete the controller
1159 * restore so setting the timeout to 100ms. Xhci specification
1160 * doesn't mention any timeout value.
1162 if (xhci_handshake(&xhci->op_regs->status,
1163 STS_RESTORE, 0, 100 * 1000)) {
1164 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1165 spin_unlock_irq(&xhci->lock);
1170 temp = readl(&xhci->op_regs->status);
1172 /* re-initialize the HC on Restore Error, or Host Controller Error */
1173 if (temp & (STS_SRE | STS_HCE)) {
1175 xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
1179 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1180 !(xhci_all_ports_seen_u0(xhci))) {
1181 del_timer_sync(&xhci->comp_mode_recovery_timer);
1182 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1183 "Compliance Mode Recovery Timer deleted!");
1186 /* Let the USB core know _both_ roothubs lost power. */
1187 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1188 if (xhci->shared_hcd)
1189 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1191 xhci_dbg(xhci, "Stop HCD\n");
1193 xhci_zero_64b_regs(xhci);
1194 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
1195 spin_unlock_irq(&xhci->lock);
1198 xhci_cleanup_msix(xhci);
1200 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1201 temp = readl(&xhci->op_regs->status);
1202 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1203 temp = readl(&xhci->ir_set->irq_pending);
1204 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1206 xhci_dbg(xhci, "cleaning up memory\n");
1207 xhci_mem_cleanup(xhci);
1208 xhci_debugfs_exit(xhci);
1209 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1210 readl(&xhci->op_regs->status));
1212 /* USB core calls the PCI reinit and start functions twice:
1213 * first with the primary HCD, and then with the secondary HCD.
1214 * If we don't do the same, the host will never be started.
1216 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1217 retval = xhci_init(hcd);
1220 comp_timer_running = true;
1222 xhci_dbg(xhci, "Start the primary HCD\n");
1223 retval = xhci_run(hcd);
1224 if (!retval && xhci->shared_hcd) {
1225 xhci_dbg(xhci, "Start the secondary HCD\n");
1226 retval = xhci_run(xhci->shared_hcd);
1229 hcd->state = HC_STATE_SUSPENDED;
1230 if (xhci->shared_hcd)
1231 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1235 /* step 4: set Run/Stop bit */
1236 command = readl(&xhci->op_regs->command);
1238 writel(command, &xhci->op_regs->command);
1239 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1242 /* step 5: walk topology and initialize portsc,
1243 * portpmsc and portli
1245 /* this is done in bus_resume */
1247 /* step 6: restart each of the previously
1248 * Running endpoints by ringing their doorbells
1251 spin_unlock_irq(&xhci->lock);
1253 xhci_dbc_resume(xhci);
1258 * Resume roothubs only if there are pending events.
1259 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1260 * the first wake signalling failed, give it that chance.
1262 pending_portevent = xhci_pending_portevent(xhci);
1263 if (!pending_portevent) {
1265 pending_portevent = xhci_pending_portevent(xhci);
1268 if (pending_portevent) {
1269 if (xhci->shared_hcd)
1270 usb_hcd_resume_root_hub(xhci->shared_hcd);
1271 usb_hcd_resume_root_hub(hcd);
1275 * If system is subject to the Quirk, Compliance Mode Timer needs to
1276 * be re-initialized Always after a system resume. Ports are subject
1277 * to suffer the Compliance Mode issue again. It doesn't matter if
1278 * ports have entered previously to U0 before system's suspension.
1280 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1281 compliance_mode_recovery_timer_init(xhci);
1283 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1284 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1286 /* Re-enable port polling. */
1287 xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
1288 __func__, hcd->self.busnum);
1289 if (xhci->shared_hcd) {
1290 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1291 usb_hcd_poll_rh_status(xhci->shared_hcd);
1293 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1294 usb_hcd_poll_rh_status(hcd);
1298 EXPORT_SYMBOL_GPL(xhci_resume);
1299 #endif /* CONFIG_PM */
1301 /*-------------------------------------------------------------------------*/
1303 static int xhci_map_temp_buffer(struct usb_hcd *hcd, struct urb *urb)
1307 unsigned int buf_len;
1308 enum dma_data_direction dir;
1310 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1311 buf_len = urb->transfer_buffer_length;
1313 temp = kzalloc_node(buf_len, GFP_ATOMIC,
1314 dev_to_node(hcd->self.sysdev));
1316 if (usb_urb_dir_out(urb))
1317 sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
1320 urb->transfer_buffer = temp;
1321 urb->transfer_dma = dma_map_single(hcd->self.sysdev,
1322 urb->transfer_buffer,
1323 urb->transfer_buffer_length,
1326 if (dma_mapping_error(hcd->self.sysdev,
1327 urb->transfer_dma)) {
1331 urb->transfer_flags |= URB_DMA_MAP_SINGLE;
1337 static bool xhci_urb_temp_buffer_required(struct usb_hcd *hcd,
1342 unsigned int len = 0;
1343 unsigned int trb_size;
1344 unsigned int max_pkt;
1345 struct scatterlist *sg;
1346 struct scatterlist *tail_sg;
1349 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
1354 if (urb->dev->speed >= USB_SPEED_SUPER)
1355 trb_size = TRB_CACHE_SIZE_SS;
1357 trb_size = TRB_CACHE_SIZE_HS;
1359 if (urb->transfer_buffer_length != 0 &&
1360 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)) {
1361 for_each_sg(urb->sg, sg, urb->num_sgs, i) {
1362 len = len + sg->length;
1363 if (i > trb_size - 2) {
1364 len = len - tail_sg->length;
1365 if (len < max_pkt) {
1370 tail_sg = sg_next(tail_sg);
1377 static void xhci_unmap_temp_buf(struct usb_hcd *hcd, struct urb *urb)
1380 unsigned int buf_len;
1381 enum dma_data_direction dir;
1383 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1385 buf_len = urb->transfer_buffer_length;
1387 if (IS_ENABLED(CONFIG_HAS_DMA) &&
1388 (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1389 dma_unmap_single(hcd->self.sysdev,
1391 urb->transfer_buffer_length,
1394 if (usb_urb_dir_in(urb)) {
1395 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs,
1396 urb->transfer_buffer,
1399 if (len != buf_len) {
1400 xhci_dbg(hcd_to_xhci(hcd),
1401 "Copy from tmp buf to urb sg list failed\n");
1402 urb->actual_length = len;
1405 urb->transfer_flags &= ~URB_DMA_MAP_SINGLE;
1406 kfree(urb->transfer_buffer);
1407 urb->transfer_buffer = NULL;
1411 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1412 * we'll copy the actual data into the TRB address register. This is limited to
1413 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1414 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1416 static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1419 struct xhci_hcd *xhci;
1421 xhci = hcd_to_xhci(hcd);
1423 if (xhci_urb_suitable_for_idt(urb))
1426 if (xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) {
1427 if (xhci_urb_temp_buffer_required(hcd, urb))
1428 return xhci_map_temp_buffer(hcd, urb);
1430 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1433 static void xhci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
1435 struct xhci_hcd *xhci;
1436 bool unmap_temp_buf = false;
1438 xhci = hcd_to_xhci(hcd);
1440 if (urb->num_sgs && (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1441 unmap_temp_buf = true;
1443 if ((xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) && unmap_temp_buf)
1444 xhci_unmap_temp_buf(hcd, urb);
1446 usb_hcd_unmap_urb_for_dma(hcd, urb);
1450 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1451 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1452 * value to right shift 1 for the bitmask.
1454 * Index = (epnum * 2) + direction - 1,
1455 * where direction = 0 for OUT, 1 for IN.
1456 * For control endpoints, the IN index is used (OUT index is unused), so
1457 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1459 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1462 if (usb_endpoint_xfer_control(desc))
1463 index = (unsigned int) (usb_endpoint_num(desc)*2);
1465 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1466 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1469 EXPORT_SYMBOL_GPL(xhci_get_endpoint_index);
1471 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1472 * address from the XHCI endpoint index.
1474 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1476 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1477 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1478 return direction | number;
1481 /* Find the flag for this endpoint (for use in the control context). Use the
1482 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1485 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1487 return 1 << (xhci_get_endpoint_index(desc) + 1);
1490 /* Compute the last valid endpoint context index. Basically, this is the
1491 * endpoint index plus one. For slot contexts with more than valid endpoint,
1492 * we find the most significant bit set in the added contexts flags.
1493 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1494 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1496 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1498 return fls(added_ctxs) - 1;
1501 /* Returns 1 if the arguments are OK;
1502 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1504 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1505 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1507 struct xhci_hcd *xhci;
1508 struct xhci_virt_device *virt_dev;
1510 if (!hcd || (check_ep && !ep) || !udev) {
1511 pr_debug("xHCI %s called with invalid args\n", func);
1514 if (!udev->parent) {
1515 pr_debug("xHCI %s called for root hub\n", func);
1519 xhci = hcd_to_xhci(hcd);
1520 if (check_virt_dev) {
1521 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1522 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1527 virt_dev = xhci->devs[udev->slot_id];
1528 if (virt_dev->udev != udev) {
1529 xhci_dbg(xhci, "xHCI %s called with udev and "
1530 "virt_dev does not match\n", func);
1535 if (xhci->xhc_state & XHCI_STATE_HALTED)
1541 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1542 struct usb_device *udev, struct xhci_command *command,
1543 bool ctx_change, bool must_succeed);
1546 * Full speed devices may have a max packet size greater than 8 bytes, but the
1547 * USB core doesn't know that until it reads the first 8 bytes of the
1548 * descriptor. If the usb_device's max packet size changes after that point,
1549 * we need to issue an evaluate context command and wait on it.
1551 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1552 unsigned int ep_index, struct urb *urb, gfp_t mem_flags)
1554 struct xhci_container_ctx *out_ctx;
1555 struct xhci_input_control_ctx *ctrl_ctx;
1556 struct xhci_ep_ctx *ep_ctx;
1557 struct xhci_command *command;
1558 int max_packet_size;
1559 int hw_max_packet_size;
1562 out_ctx = xhci->devs[slot_id]->out_ctx;
1563 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1564 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1565 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1566 if (hw_max_packet_size != max_packet_size) {
1567 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1568 "Max Packet Size for ep 0 changed.");
1569 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1570 "Max packet size in usb_device = %d",
1572 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1573 "Max packet size in xHCI HW = %d",
1574 hw_max_packet_size);
1575 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1576 "Issuing evaluate context command.");
1578 /* Set up the input context flags for the command */
1579 /* FIXME: This won't work if a non-default control endpoint
1580 * changes max packet sizes.
1583 command = xhci_alloc_command(xhci, true, mem_flags);
1587 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1588 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1590 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1593 goto command_cleanup;
1595 /* Set up the modified control endpoint 0 */
1596 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1597 xhci->devs[slot_id]->out_ctx, ep_index);
1599 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1600 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1601 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1602 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1604 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1605 ctrl_ctx->drop_flags = 0;
1607 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1610 /* Clean up the input context for later use by bandwidth
1613 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1615 kfree(command->completion);
1622 * non-error returns are a promise to giveback() the urb later
1623 * we drop ownership so next owner (or urb unlink) can get it
1625 static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1627 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1628 unsigned long flags;
1630 unsigned int slot_id, ep_index;
1631 unsigned int *ep_state;
1632 struct urb_priv *urb_priv;
1637 ret = xhci_check_args(hcd, urb->dev, urb->ep,
1638 true, true, __func__);
1640 return ret ? ret : -EINVAL;
1642 slot_id = urb->dev->slot_id;
1643 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1644 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1646 if (!HCD_HW_ACCESSIBLE(hcd))
1649 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1650 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1654 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1655 num_tds = urb->number_of_packets;
1656 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1657 urb->transfer_buffer_length > 0 &&
1658 urb->transfer_flags & URB_ZERO_PACKET &&
1659 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1664 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1668 urb_priv->num_tds = num_tds;
1669 urb_priv->num_tds_done = 0;
1670 urb->hcpriv = urb_priv;
1672 trace_xhci_urb_enqueue(urb);
1674 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1675 /* Check to see if the max packet size for the default control
1676 * endpoint changed during FS device enumeration
1678 if (urb->dev->speed == USB_SPEED_FULL) {
1679 ret = xhci_check_maxpacket(xhci, slot_id,
1680 ep_index, urb, mem_flags);
1682 xhci_urb_free_priv(urb_priv);
1689 spin_lock_irqsave(&xhci->lock, flags);
1691 if (xhci->xhc_state & XHCI_STATE_DYING) {
1692 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1693 urb->ep->desc.bEndpointAddress, urb);
1697 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1698 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1703 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1704 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1709 switch (usb_endpoint_type(&urb->ep->desc)) {
1711 case USB_ENDPOINT_XFER_CONTROL:
1712 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1715 case USB_ENDPOINT_XFER_BULK:
1716 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1719 case USB_ENDPOINT_XFER_INT:
1720 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1723 case USB_ENDPOINT_XFER_ISOC:
1724 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1730 xhci_urb_free_priv(urb_priv);
1733 spin_unlock_irqrestore(&xhci->lock, flags);
1738 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1739 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1740 * should pick up where it left off in the TD, unless a Set Transfer Ring
1741 * Dequeue Pointer is issued.
1743 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1744 * the ring. Since the ring is a contiguous structure, they can't be physically
1745 * removed. Instead, there are two options:
1747 * 1) If the HC is in the middle of processing the URB to be canceled, we
1748 * simply move the ring's dequeue pointer past those TRBs using the Set
1749 * Transfer Ring Dequeue Pointer command. This will be the common case,
1750 * when drivers timeout on the last submitted URB and attempt to cancel.
1752 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1753 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1754 * HC will need to invalidate the any TRBs it has cached after the stop
1755 * endpoint command, as noted in the xHCI 0.95 errata.
1757 * 3) The TD may have completed by the time the Stop Endpoint Command
1758 * completes, so software needs to handle that case too.
1760 * This function should protect against the TD enqueueing code ringing the
1761 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1762 * It also needs to account for multiple cancellations on happening at the same
1763 * time for the same endpoint.
1765 * Note that this function can be called in any context, or so says
1766 * usb_hcd_unlink_urb()
1768 static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1770 unsigned long flags;
1773 struct xhci_hcd *xhci;
1774 struct urb_priv *urb_priv;
1776 unsigned int ep_index;
1777 struct xhci_ring *ep_ring;
1778 struct xhci_virt_ep *ep;
1779 struct xhci_command *command;
1780 struct xhci_virt_device *vdev;
1782 xhci = hcd_to_xhci(hcd);
1783 spin_lock_irqsave(&xhci->lock, flags);
1785 trace_xhci_urb_dequeue(urb);
1787 /* Make sure the URB hasn't completed or been unlinked already */
1788 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1792 /* give back URB now if we can't queue it for cancel */
1793 vdev = xhci->devs[urb->dev->slot_id];
1794 urb_priv = urb->hcpriv;
1795 if (!vdev || !urb_priv)
1798 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1799 ep = &vdev->eps[ep_index];
1800 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1801 if (!ep || !ep_ring)
1804 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1805 temp = readl(&xhci->op_regs->status);
1806 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1812 * check ring is not re-allocated since URB was enqueued. If it is, then
1813 * make sure none of the ring related pointers in this URB private data
1814 * are touched, such as td_list, otherwise we overwrite freed data
1816 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1817 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1818 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1819 td = &urb_priv->td[i];
1820 if (!list_empty(&td->cancelled_td_list))
1821 list_del_init(&td->cancelled_td_list);
1826 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1827 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1828 "HC halted, freeing TD manually.");
1829 for (i = urb_priv->num_tds_done;
1830 i < urb_priv->num_tds;
1832 td = &urb_priv->td[i];
1833 if (!list_empty(&td->td_list))
1834 list_del_init(&td->td_list);
1835 if (!list_empty(&td->cancelled_td_list))
1836 list_del_init(&td->cancelled_td_list);
1841 i = urb_priv->num_tds_done;
1842 if (i < urb_priv->num_tds)
1843 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1844 "Cancel URB %p, dev %s, ep 0x%x, "
1845 "starting at offset 0x%llx",
1846 urb, urb->dev->devpath,
1847 urb->ep->desc.bEndpointAddress,
1848 (unsigned long long) xhci_trb_virt_to_dma(
1849 urb_priv->td[i].start_seg,
1850 urb_priv->td[i].first_trb));
1852 for (; i < urb_priv->num_tds; i++) {
1853 td = &urb_priv->td[i];
1854 /* TD can already be on cancelled list if ep halted on it */
1855 if (list_empty(&td->cancelled_td_list)) {
1856 td->cancel_status = TD_DIRTY;
1857 list_add_tail(&td->cancelled_td_list,
1858 &ep->cancelled_td_list);
1862 /* Queue a stop endpoint command, but only if this is
1863 * the first cancellation to be handled.
1865 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1866 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1871 ep->ep_state |= EP_STOP_CMD_PENDING;
1872 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1874 xhci_ring_cmd_db(xhci);
1877 spin_unlock_irqrestore(&xhci->lock, flags);
1882 xhci_urb_free_priv(urb_priv);
1883 usb_hcd_unlink_urb_from_ep(hcd, urb);
1884 spin_unlock_irqrestore(&xhci->lock, flags);
1885 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1889 /* Drop an endpoint from a new bandwidth configuration for this device.
1890 * Only one call to this function is allowed per endpoint before
1891 * check_bandwidth() or reset_bandwidth() must be called.
1892 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1893 * add the endpoint to the schedule with possibly new parameters denoted by a
1894 * different endpoint descriptor in usb_host_endpoint.
1895 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1898 * The USB core will not allow URBs to be queued to an endpoint that is being
1899 * disabled, so there's no need for mutual exclusion to protect
1900 * the xhci->devs[slot_id] structure.
1902 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1903 struct usb_host_endpoint *ep)
1905 struct xhci_hcd *xhci;
1906 struct xhci_container_ctx *in_ctx, *out_ctx;
1907 struct xhci_input_control_ctx *ctrl_ctx;
1908 unsigned int ep_index;
1909 struct xhci_ep_ctx *ep_ctx;
1911 u32 new_add_flags, new_drop_flags;
1914 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1917 xhci = hcd_to_xhci(hcd);
1918 if (xhci->xhc_state & XHCI_STATE_DYING)
1921 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1922 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1923 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1924 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1925 __func__, drop_flag);
1929 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1930 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1931 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1933 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1938 ep_index = xhci_get_endpoint_index(&ep->desc);
1939 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1940 /* If the HC already knows the endpoint is disabled,
1941 * or the HCD has noted it is disabled, ignore this request
1943 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1944 le32_to_cpu(ctrl_ctx->drop_flags) &
1945 xhci_get_endpoint_flag(&ep->desc)) {
1946 /* Do not warn when called after a usb_device_reset */
1947 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1948 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1953 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1954 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1956 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1957 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1959 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1961 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1963 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1964 (unsigned int) ep->desc.bEndpointAddress,
1966 (unsigned int) new_drop_flags,
1967 (unsigned int) new_add_flags);
1970 EXPORT_SYMBOL_GPL(xhci_drop_endpoint);
1972 /* Add an endpoint to a new possible bandwidth configuration for this device.
1973 * Only one call to this function is allowed per endpoint before
1974 * check_bandwidth() or reset_bandwidth() must be called.
1975 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1976 * add the endpoint to the schedule with possibly new parameters denoted by a
1977 * different endpoint descriptor in usb_host_endpoint.
1978 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1981 * The USB core will not allow URBs to be queued to an endpoint until the
1982 * configuration or alt setting is installed in the device, so there's no need
1983 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1985 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1986 struct usb_host_endpoint *ep)
1988 struct xhci_hcd *xhci;
1989 struct xhci_container_ctx *in_ctx;
1990 unsigned int ep_index;
1991 struct xhci_input_control_ctx *ctrl_ctx;
1992 struct xhci_ep_ctx *ep_ctx;
1994 u32 new_add_flags, new_drop_flags;
1995 struct xhci_virt_device *virt_dev;
1998 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
2000 /* So we won't queue a reset ep command for a root hub */
2004 xhci = hcd_to_xhci(hcd);
2005 if (xhci->xhc_state & XHCI_STATE_DYING)
2008 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
2009 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
2010 /* FIXME when we have to issue an evaluate endpoint command to
2011 * deal with ep0 max packet size changing once we get the
2014 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
2015 __func__, added_ctxs);
2019 virt_dev = xhci->devs[udev->slot_id];
2020 in_ctx = virt_dev->in_ctx;
2021 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2023 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2028 ep_index = xhci_get_endpoint_index(&ep->desc);
2029 /* If this endpoint is already in use, and the upper layers are trying
2030 * to add it again without dropping it, reject the addition.
2032 if (virt_dev->eps[ep_index].ring &&
2033 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
2034 xhci_warn(xhci, "Trying to add endpoint 0x%x "
2035 "without dropping it.\n",
2036 (unsigned int) ep->desc.bEndpointAddress);
2040 /* If the HCD has already noted the endpoint is enabled,
2041 * ignore this request.
2043 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
2044 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
2050 * Configuration and alternate setting changes must be done in
2051 * process context, not interrupt context (or so documenation
2052 * for usb_set_interface() and usb_set_configuration() claim).
2054 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
2055 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
2056 __func__, ep->desc.bEndpointAddress);
2060 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
2061 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
2063 /* If xhci_endpoint_disable() was called for this endpoint, but the
2064 * xHC hasn't been notified yet through the check_bandwidth() call,
2065 * this re-adds a new state for the endpoint from the new endpoint
2066 * descriptors. We must drop and re-add this endpoint, so we leave the
2069 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
2071 /* Store the usb_device pointer for later use */
2074 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
2075 trace_xhci_add_endpoint(ep_ctx);
2077 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
2078 (unsigned int) ep->desc.bEndpointAddress,
2080 (unsigned int) new_drop_flags,
2081 (unsigned int) new_add_flags);
2084 EXPORT_SYMBOL_GPL(xhci_add_endpoint);
2086 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
2088 struct xhci_input_control_ctx *ctrl_ctx;
2089 struct xhci_ep_ctx *ep_ctx;
2090 struct xhci_slot_ctx *slot_ctx;
2093 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
2095 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2100 /* When a device's add flag and drop flag are zero, any subsequent
2101 * configure endpoint command will leave that endpoint's state
2102 * untouched. Make sure we don't leave any old state in the input
2103 * endpoint contexts.
2105 ctrl_ctx->drop_flags = 0;
2106 ctrl_ctx->add_flags = 0;
2107 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2108 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2109 /* Endpoint 0 is always valid */
2110 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
2111 for (i = 1; i < 31; i++) {
2112 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
2113 ep_ctx->ep_info = 0;
2114 ep_ctx->ep_info2 = 0;
2116 ep_ctx->tx_info = 0;
2120 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
2121 struct usb_device *udev, u32 *cmd_status)
2125 switch (*cmd_status) {
2126 case COMP_COMMAND_ABORTED:
2127 case COMP_COMMAND_RING_STOPPED:
2128 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
2131 case COMP_RESOURCE_ERROR:
2132 dev_warn(&udev->dev,
2133 "Not enough host controller resources for new device state.\n");
2135 /* FIXME: can we allocate more resources for the HC? */
2137 case COMP_BANDWIDTH_ERROR:
2138 case COMP_SECONDARY_BANDWIDTH_ERROR:
2139 dev_warn(&udev->dev,
2140 "Not enough bandwidth for new device state.\n");
2142 /* FIXME: can we go back to the old state? */
2144 case COMP_TRB_ERROR:
2145 /* the HCD set up something wrong */
2146 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
2148 "and endpoint is not disabled.\n");
2151 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2152 dev_warn(&udev->dev,
2153 "ERROR: Incompatible device for endpoint configure command.\n");
2157 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2158 "Successful Endpoint Configure command");
2162 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2170 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2171 struct usb_device *udev, u32 *cmd_status)
2175 switch (*cmd_status) {
2176 case COMP_COMMAND_ABORTED:
2177 case COMP_COMMAND_RING_STOPPED:
2178 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2181 case COMP_PARAMETER_ERROR:
2182 dev_warn(&udev->dev,
2183 "WARN: xHCI driver setup invalid evaluate context command.\n");
2186 case COMP_SLOT_NOT_ENABLED_ERROR:
2187 dev_warn(&udev->dev,
2188 "WARN: slot not enabled for evaluate context command.\n");
2191 case COMP_CONTEXT_STATE_ERROR:
2192 dev_warn(&udev->dev,
2193 "WARN: invalid context state for evaluate context command.\n");
2196 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2197 dev_warn(&udev->dev,
2198 "ERROR: Incompatible device for evaluate context command.\n");
2201 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2202 /* Max Exit Latency too large error */
2203 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2207 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2208 "Successful evaluate context command");
2212 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2220 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2221 struct xhci_input_control_ctx *ctrl_ctx)
2223 u32 valid_add_flags;
2224 u32 valid_drop_flags;
2226 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2227 * (bit 1). The default control endpoint is added during the Address
2228 * Device command and is never removed until the slot is disabled.
2230 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2231 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2233 /* Use hweight32 to count the number of ones in the add flags, or
2234 * number of endpoints added. Don't count endpoints that are changed
2235 * (both added and dropped).
2237 return hweight32(valid_add_flags) -
2238 hweight32(valid_add_flags & valid_drop_flags);
2241 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2242 struct xhci_input_control_ctx *ctrl_ctx)
2244 u32 valid_add_flags;
2245 u32 valid_drop_flags;
2247 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2248 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2250 return hweight32(valid_drop_flags) -
2251 hweight32(valid_add_flags & valid_drop_flags);
2255 * We need to reserve the new number of endpoints before the configure endpoint
2256 * command completes. We can't subtract the dropped endpoints from the number
2257 * of active endpoints until the command completes because we can oversubscribe
2258 * the host in this case:
2260 * - the first configure endpoint command drops more endpoints than it adds
2261 * - a second configure endpoint command that adds more endpoints is queued
2262 * - the first configure endpoint command fails, so the config is unchanged
2263 * - the second command may succeed, even though there isn't enough resources
2265 * Must be called with xhci->lock held.
2267 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2268 struct xhci_input_control_ctx *ctrl_ctx)
2272 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2273 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2274 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2275 "Not enough ep ctxs: "
2276 "%u active, need to add %u, limit is %u.",
2277 xhci->num_active_eps, added_eps,
2278 xhci->limit_active_eps);
2281 xhci->num_active_eps += added_eps;
2282 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2283 "Adding %u ep ctxs, %u now active.", added_eps,
2284 xhci->num_active_eps);
2289 * The configure endpoint was failed by the xHC for some other reason, so we
2290 * need to revert the resources that failed configuration would have used.
2292 * Must be called with xhci->lock held.
2294 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2295 struct xhci_input_control_ctx *ctrl_ctx)
2299 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2300 xhci->num_active_eps -= num_failed_eps;
2301 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2302 "Removing %u failed ep ctxs, %u now active.",
2304 xhci->num_active_eps);
2308 * Now that the command has completed, clean up the active endpoint count by
2309 * subtracting out the endpoints that were dropped (but not changed).
2311 * Must be called with xhci->lock held.
2313 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2314 struct xhci_input_control_ctx *ctrl_ctx)
2316 u32 num_dropped_eps;
2318 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2319 xhci->num_active_eps -= num_dropped_eps;
2320 if (num_dropped_eps)
2321 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2322 "Removing %u dropped ep ctxs, %u now active.",
2324 xhci->num_active_eps);
2327 static unsigned int xhci_get_block_size(struct usb_device *udev)
2329 switch (udev->speed) {
2331 case USB_SPEED_FULL:
2333 case USB_SPEED_HIGH:
2335 case USB_SPEED_SUPER:
2336 case USB_SPEED_SUPER_PLUS:
2338 case USB_SPEED_UNKNOWN:
2339 case USB_SPEED_WIRELESS:
2341 /* Should never happen */
2347 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2349 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2351 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2356 /* If we are changing a LS/FS device under a HS hub,
2357 * make sure (if we are activating a new TT) that the HS bus has enough
2358 * bandwidth for this new TT.
2360 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2361 struct xhci_virt_device *virt_dev,
2364 struct xhci_interval_bw_table *bw_table;
2365 struct xhci_tt_bw_info *tt_info;
2367 /* Find the bandwidth table for the root port this TT is attached to. */
2368 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2369 tt_info = virt_dev->tt_info;
2370 /* If this TT already had active endpoints, the bandwidth for this TT
2371 * has already been added. Removing all periodic endpoints (and thus
2372 * making the TT enactive) will only decrease the bandwidth used.
2376 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2377 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2381 /* Not sure why we would have no new active endpoints...
2383 * Maybe because of an Evaluate Context change for a hub update or a
2384 * control endpoint 0 max packet size change?
2385 * FIXME: skip the bandwidth calculation in that case.
2390 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2391 struct xhci_virt_device *virt_dev)
2393 unsigned int bw_reserved;
2395 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2396 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2399 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2400 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2407 * This algorithm is a very conservative estimate of the worst-case scheduling
2408 * scenario for any one interval. The hardware dynamically schedules the
2409 * packets, so we can't tell which microframe could be the limiting factor in
2410 * the bandwidth scheduling. This only takes into account periodic endpoints.
2412 * Obviously, we can't solve an NP complete problem to find the minimum worst
2413 * case scenario. Instead, we come up with an estimate that is no less than
2414 * the worst case bandwidth used for any one microframe, but may be an
2417 * We walk the requirements for each endpoint by interval, starting with the
2418 * smallest interval, and place packets in the schedule where there is only one
2419 * possible way to schedule packets for that interval. In order to simplify
2420 * this algorithm, we record the largest max packet size for each interval, and
2421 * assume all packets will be that size.
2423 * For interval 0, we obviously must schedule all packets for each interval.
2424 * The bandwidth for interval 0 is just the amount of data to be transmitted
2425 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2426 * the number of packets).
2428 * For interval 1, we have two possible microframes to schedule those packets
2429 * in. For this algorithm, if we can schedule the same number of packets for
2430 * each possible scheduling opportunity (each microframe), we will do so. The
2431 * remaining number of packets will be saved to be transmitted in the gaps in
2432 * the next interval's scheduling sequence.
2434 * As we move those remaining packets to be scheduled with interval 2 packets,
2435 * we have to double the number of remaining packets to transmit. This is
2436 * because the intervals are actually powers of 2, and we would be transmitting
2437 * the previous interval's packets twice in this interval. We also have to be
2438 * sure that when we look at the largest max packet size for this interval, we
2439 * also look at the largest max packet size for the remaining packets and take
2440 * the greater of the two.
2442 * The algorithm continues to evenly distribute packets in each scheduling
2443 * opportunity, and push the remaining packets out, until we get to the last
2444 * interval. Then those packets and their associated overhead are just added
2445 * to the bandwidth used.
2447 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2448 struct xhci_virt_device *virt_dev,
2451 unsigned int bw_reserved;
2452 unsigned int max_bandwidth;
2453 unsigned int bw_used;
2454 unsigned int block_size;
2455 struct xhci_interval_bw_table *bw_table;
2456 unsigned int packet_size = 0;
2457 unsigned int overhead = 0;
2458 unsigned int packets_transmitted = 0;
2459 unsigned int packets_remaining = 0;
2462 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2463 return xhci_check_ss_bw(xhci, virt_dev);
2465 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2466 max_bandwidth = HS_BW_LIMIT;
2467 /* Convert percent of bus BW reserved to blocks reserved */
2468 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2470 max_bandwidth = FS_BW_LIMIT;
2471 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2474 bw_table = virt_dev->bw_table;
2475 /* We need to translate the max packet size and max ESIT payloads into
2476 * the units the hardware uses.
2478 block_size = xhci_get_block_size(virt_dev->udev);
2480 /* If we are manipulating a LS/FS device under a HS hub, double check
2481 * that the HS bus has enough bandwidth if we are activing a new TT.
2483 if (virt_dev->tt_info) {
2484 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2485 "Recalculating BW for rootport %u",
2486 virt_dev->real_port);
2487 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2488 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2489 "newly activated TT.\n");
2492 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2493 "Recalculating BW for TT slot %u port %u",
2494 virt_dev->tt_info->slot_id,
2495 virt_dev->tt_info->ttport);
2497 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2498 "Recalculating BW for rootport %u",
2499 virt_dev->real_port);
2502 /* Add in how much bandwidth will be used for interval zero, or the
2503 * rounded max ESIT payload + number of packets * largest overhead.
2505 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2506 bw_table->interval_bw[0].num_packets *
2507 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2509 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2510 unsigned int bw_added;
2511 unsigned int largest_mps;
2512 unsigned int interval_overhead;
2515 * How many packets could we transmit in this interval?
2516 * If packets didn't fit in the previous interval, we will need
2517 * to transmit that many packets twice within this interval.
2519 packets_remaining = 2 * packets_remaining +
2520 bw_table->interval_bw[i].num_packets;
2522 /* Find the largest max packet size of this or the previous
2525 if (list_empty(&bw_table->interval_bw[i].endpoints))
2528 struct xhci_virt_ep *virt_ep;
2529 struct list_head *ep_entry;
2531 ep_entry = bw_table->interval_bw[i].endpoints.next;
2532 virt_ep = list_entry(ep_entry,
2533 struct xhci_virt_ep, bw_endpoint_list);
2534 /* Convert to blocks, rounding up */
2535 largest_mps = DIV_ROUND_UP(
2536 virt_ep->bw_info.max_packet_size,
2539 if (largest_mps > packet_size)
2540 packet_size = largest_mps;
2542 /* Use the larger overhead of this or the previous interval. */
2543 interval_overhead = xhci_get_largest_overhead(
2544 &bw_table->interval_bw[i]);
2545 if (interval_overhead > overhead)
2546 overhead = interval_overhead;
2548 /* How many packets can we evenly distribute across
2549 * (1 << (i + 1)) possible scheduling opportunities?
2551 packets_transmitted = packets_remaining >> (i + 1);
2553 /* Add in the bandwidth used for those scheduled packets */
2554 bw_added = packets_transmitted * (overhead + packet_size);
2556 /* How many packets do we have remaining to transmit? */
2557 packets_remaining = packets_remaining % (1 << (i + 1));
2559 /* What largest max packet size should those packets have? */
2560 /* If we've transmitted all packets, don't carry over the
2561 * largest packet size.
2563 if (packets_remaining == 0) {
2566 } else if (packets_transmitted > 0) {
2567 /* Otherwise if we do have remaining packets, and we've
2568 * scheduled some packets in this interval, take the
2569 * largest max packet size from endpoints with this
2572 packet_size = largest_mps;
2573 overhead = interval_overhead;
2575 /* Otherwise carry over packet_size and overhead from the last
2576 * time we had a remainder.
2578 bw_used += bw_added;
2579 if (bw_used > max_bandwidth) {
2580 xhci_warn(xhci, "Not enough bandwidth. "
2581 "Proposed: %u, Max: %u\n",
2582 bw_used, max_bandwidth);
2587 * Ok, we know we have some packets left over after even-handedly
2588 * scheduling interval 15. We don't know which microframes they will
2589 * fit into, so we over-schedule and say they will be scheduled every
2592 if (packets_remaining > 0)
2593 bw_used += overhead + packet_size;
2595 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2596 unsigned int port_index = virt_dev->real_port - 1;
2598 /* OK, we're manipulating a HS device attached to a
2599 * root port bandwidth domain. Include the number of active TTs
2600 * in the bandwidth used.
2602 bw_used += TT_HS_OVERHEAD *
2603 xhci->rh_bw[port_index].num_active_tts;
2606 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2607 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2608 "Available: %u " "percent",
2609 bw_used, max_bandwidth, bw_reserved,
2610 (max_bandwidth - bw_used - bw_reserved) * 100 /
2613 bw_used += bw_reserved;
2614 if (bw_used > max_bandwidth) {
2615 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2616 bw_used, max_bandwidth);
2620 bw_table->bw_used = bw_used;
2624 static bool xhci_is_async_ep(unsigned int ep_type)
2626 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2627 ep_type != ISOC_IN_EP &&
2628 ep_type != INT_IN_EP);
2631 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2633 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2636 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2638 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2640 if (ep_bw->ep_interval == 0)
2641 return SS_OVERHEAD_BURST +
2642 (ep_bw->mult * ep_bw->num_packets *
2643 (SS_OVERHEAD + mps));
2644 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2645 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2646 1 << ep_bw->ep_interval);
2650 static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2651 struct xhci_bw_info *ep_bw,
2652 struct xhci_interval_bw_table *bw_table,
2653 struct usb_device *udev,
2654 struct xhci_virt_ep *virt_ep,
2655 struct xhci_tt_bw_info *tt_info)
2657 struct xhci_interval_bw *interval_bw;
2658 int normalized_interval;
2660 if (xhci_is_async_ep(ep_bw->type))
2663 if (udev->speed >= USB_SPEED_SUPER) {
2664 if (xhci_is_sync_in_ep(ep_bw->type))
2665 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2666 xhci_get_ss_bw_consumed(ep_bw);
2668 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2669 xhci_get_ss_bw_consumed(ep_bw);
2673 /* SuperSpeed endpoints never get added to intervals in the table, so
2674 * this check is only valid for HS/FS/LS devices.
2676 if (list_empty(&virt_ep->bw_endpoint_list))
2678 /* For LS/FS devices, we need to translate the interval expressed in
2679 * microframes to frames.
2681 if (udev->speed == USB_SPEED_HIGH)
2682 normalized_interval = ep_bw->ep_interval;
2684 normalized_interval = ep_bw->ep_interval - 3;
2686 if (normalized_interval == 0)
2687 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2688 interval_bw = &bw_table->interval_bw[normalized_interval];
2689 interval_bw->num_packets -= ep_bw->num_packets;
2690 switch (udev->speed) {
2692 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2694 case USB_SPEED_FULL:
2695 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2697 case USB_SPEED_HIGH:
2698 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2700 case USB_SPEED_SUPER:
2701 case USB_SPEED_SUPER_PLUS:
2702 case USB_SPEED_UNKNOWN:
2703 case USB_SPEED_WIRELESS:
2704 /* Should never happen because only LS/FS/HS endpoints will get
2705 * added to the endpoint list.
2710 tt_info->active_eps -= 1;
2711 list_del_init(&virt_ep->bw_endpoint_list);
2714 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2715 struct xhci_bw_info *ep_bw,
2716 struct xhci_interval_bw_table *bw_table,
2717 struct usb_device *udev,
2718 struct xhci_virt_ep *virt_ep,
2719 struct xhci_tt_bw_info *tt_info)
2721 struct xhci_interval_bw *interval_bw;
2722 struct xhci_virt_ep *smaller_ep;
2723 int normalized_interval;
2725 if (xhci_is_async_ep(ep_bw->type))
2728 if (udev->speed == USB_SPEED_SUPER) {
2729 if (xhci_is_sync_in_ep(ep_bw->type))
2730 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2731 xhci_get_ss_bw_consumed(ep_bw);
2733 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2734 xhci_get_ss_bw_consumed(ep_bw);
2738 /* For LS/FS devices, we need to translate the interval expressed in
2739 * microframes to frames.
2741 if (udev->speed == USB_SPEED_HIGH)
2742 normalized_interval = ep_bw->ep_interval;
2744 normalized_interval = ep_bw->ep_interval - 3;
2746 if (normalized_interval == 0)
2747 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2748 interval_bw = &bw_table->interval_bw[normalized_interval];
2749 interval_bw->num_packets += ep_bw->num_packets;
2750 switch (udev->speed) {
2752 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2754 case USB_SPEED_FULL:
2755 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2757 case USB_SPEED_HIGH:
2758 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2760 case USB_SPEED_SUPER:
2761 case USB_SPEED_SUPER_PLUS:
2762 case USB_SPEED_UNKNOWN:
2763 case USB_SPEED_WIRELESS:
2764 /* Should never happen because only LS/FS/HS endpoints will get
2765 * added to the endpoint list.
2771 tt_info->active_eps += 1;
2772 /* Insert the endpoint into the list, largest max packet size first. */
2773 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2775 if (ep_bw->max_packet_size >=
2776 smaller_ep->bw_info.max_packet_size) {
2777 /* Add the new ep before the smaller endpoint */
2778 list_add_tail(&virt_ep->bw_endpoint_list,
2779 &smaller_ep->bw_endpoint_list);
2783 /* Add the new endpoint at the end of the list. */
2784 list_add_tail(&virt_ep->bw_endpoint_list,
2785 &interval_bw->endpoints);
2788 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2789 struct xhci_virt_device *virt_dev,
2792 struct xhci_root_port_bw_info *rh_bw_info;
2793 if (!virt_dev->tt_info)
2796 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2797 if (old_active_eps == 0 &&
2798 virt_dev->tt_info->active_eps != 0) {
2799 rh_bw_info->num_active_tts += 1;
2800 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2801 } else if (old_active_eps != 0 &&
2802 virt_dev->tt_info->active_eps == 0) {
2803 rh_bw_info->num_active_tts -= 1;
2804 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2808 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2809 struct xhci_virt_device *virt_dev,
2810 struct xhci_container_ctx *in_ctx)
2812 struct xhci_bw_info ep_bw_info[31];
2814 struct xhci_input_control_ctx *ctrl_ctx;
2815 int old_active_eps = 0;
2817 if (virt_dev->tt_info)
2818 old_active_eps = virt_dev->tt_info->active_eps;
2820 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2822 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2827 for (i = 0; i < 31; i++) {
2828 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2831 /* Make a copy of the BW info in case we need to revert this */
2832 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2833 sizeof(ep_bw_info[i]));
2834 /* Drop the endpoint from the interval table if the endpoint is
2835 * being dropped or changed.
2837 if (EP_IS_DROPPED(ctrl_ctx, i))
2838 xhci_drop_ep_from_interval_table(xhci,
2839 &virt_dev->eps[i].bw_info,
2845 /* Overwrite the information stored in the endpoints' bw_info */
2846 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2847 for (i = 0; i < 31; i++) {
2848 /* Add any changed or added endpoints to the interval table */
2849 if (EP_IS_ADDED(ctrl_ctx, i))
2850 xhci_add_ep_to_interval_table(xhci,
2851 &virt_dev->eps[i].bw_info,
2858 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2859 /* Ok, this fits in the bandwidth we have.
2860 * Update the number of active TTs.
2862 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2866 /* We don't have enough bandwidth for this, revert the stored info. */
2867 for (i = 0; i < 31; i++) {
2868 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2871 /* Drop the new copies of any added or changed endpoints from
2872 * the interval table.
2874 if (EP_IS_ADDED(ctrl_ctx, i)) {
2875 xhci_drop_ep_from_interval_table(xhci,
2876 &virt_dev->eps[i].bw_info,
2882 /* Revert the endpoint back to its old information */
2883 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2884 sizeof(ep_bw_info[i]));
2885 /* Add any changed or dropped endpoints back into the table */
2886 if (EP_IS_DROPPED(ctrl_ctx, i))
2887 xhci_add_ep_to_interval_table(xhci,
2888 &virt_dev->eps[i].bw_info,
2898 /* Issue a configure endpoint command or evaluate context command
2899 * and wait for it to finish.
2901 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2902 struct usb_device *udev,
2903 struct xhci_command *command,
2904 bool ctx_change, bool must_succeed)
2907 unsigned long flags;
2908 struct xhci_input_control_ctx *ctrl_ctx;
2909 struct xhci_virt_device *virt_dev;
2910 struct xhci_slot_ctx *slot_ctx;
2915 spin_lock_irqsave(&xhci->lock, flags);
2917 if (xhci->xhc_state & XHCI_STATE_DYING) {
2918 spin_unlock_irqrestore(&xhci->lock, flags);
2922 virt_dev = xhci->devs[udev->slot_id];
2924 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2926 spin_unlock_irqrestore(&xhci->lock, flags);
2927 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2932 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2933 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2934 spin_unlock_irqrestore(&xhci->lock, flags);
2935 xhci_warn(xhci, "Not enough host resources, "
2936 "active endpoint contexts = %u\n",
2937 xhci->num_active_eps);
2940 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2941 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2942 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2943 xhci_free_host_resources(xhci, ctrl_ctx);
2944 spin_unlock_irqrestore(&xhci->lock, flags);
2945 xhci_warn(xhci, "Not enough bandwidth\n");
2949 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2951 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
2952 trace_xhci_configure_endpoint(slot_ctx);
2955 ret = xhci_queue_configure_endpoint(xhci, command,
2956 command->in_ctx->dma,
2957 udev->slot_id, must_succeed);
2959 ret = xhci_queue_evaluate_context(xhci, command,
2960 command->in_ctx->dma,
2961 udev->slot_id, must_succeed);
2963 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2964 xhci_free_host_resources(xhci, ctrl_ctx);
2965 spin_unlock_irqrestore(&xhci->lock, flags);
2966 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2967 "FIXME allocate a new ring segment");
2970 xhci_ring_cmd_db(xhci);
2971 spin_unlock_irqrestore(&xhci->lock, flags);
2973 /* Wait for the configure endpoint command to complete */
2974 wait_for_completion(command->completion);
2977 ret = xhci_configure_endpoint_result(xhci, udev,
2980 ret = xhci_evaluate_context_result(xhci, udev,
2983 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2984 spin_lock_irqsave(&xhci->lock, flags);
2985 /* If the command failed, remove the reserved resources.
2986 * Otherwise, clean up the estimate to include dropped eps.
2989 xhci_free_host_resources(xhci, ctrl_ctx);
2991 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2992 spin_unlock_irqrestore(&xhci->lock, flags);
2997 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2998 struct xhci_virt_device *vdev, int i)
3000 struct xhci_virt_ep *ep = &vdev->eps[i];
3002 if (ep->ep_state & EP_HAS_STREAMS) {
3003 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
3004 xhci_get_endpoint_address(i));
3005 xhci_free_stream_info(xhci, ep->stream_info);
3006 ep->stream_info = NULL;
3007 ep->ep_state &= ~EP_HAS_STREAMS;
3011 /* Called after one or more calls to xhci_add_endpoint() or
3012 * xhci_drop_endpoint(). If this call fails, the USB core is expected
3013 * to call xhci_reset_bandwidth().
3015 * Since we are in the middle of changing either configuration or
3016 * installing a new alt setting, the USB core won't allow URBs to be
3017 * enqueued for any endpoint on the old config or interface. Nothing
3018 * else should be touching the xhci->devs[slot_id] structure, so we
3019 * don't need to take the xhci->lock for manipulating that.
3021 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3025 struct xhci_hcd *xhci;
3026 struct xhci_virt_device *virt_dev;
3027 struct xhci_input_control_ctx *ctrl_ctx;
3028 struct xhci_slot_ctx *slot_ctx;
3029 struct xhci_command *command;
3031 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3034 xhci = hcd_to_xhci(hcd);
3035 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3036 (xhci->xhc_state & XHCI_STATE_REMOVING))
3039 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3040 virt_dev = xhci->devs[udev->slot_id];
3042 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3046 command->in_ctx = virt_dev->in_ctx;
3048 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
3049 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3051 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3054 goto command_cleanup;
3056 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3057 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
3058 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
3060 /* Don't issue the command if there's no endpoints to update. */
3061 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
3062 ctrl_ctx->drop_flags == 0) {
3064 goto command_cleanup;
3066 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
3067 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3068 for (i = 31; i >= 1; i--) {
3069 __le32 le32 = cpu_to_le32(BIT(i));
3071 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
3072 || (ctrl_ctx->add_flags & le32) || i == 1) {
3073 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
3074 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
3079 ret = xhci_configure_endpoint(xhci, udev, command,
3082 /* Callee should call reset_bandwidth() */
3083 goto command_cleanup;
3085 /* Free any rings that were dropped, but not changed. */
3086 for (i = 1; i < 31; i++) {
3087 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
3088 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
3089 xhci_free_endpoint_ring(xhci, virt_dev, i);
3090 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3093 xhci_zero_in_ctx(xhci, virt_dev);
3095 * Install any rings for completely new endpoints or changed endpoints,
3096 * and free any old rings from changed endpoints.
3098 for (i = 1; i < 31; i++) {
3099 if (!virt_dev->eps[i].new_ring)
3101 /* Only free the old ring if it exists.
3102 * It may not if this is the first add of an endpoint.
3104 if (virt_dev->eps[i].ring) {
3105 xhci_free_endpoint_ring(xhci, virt_dev, i);
3107 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3108 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
3109 virt_dev->eps[i].new_ring = NULL;
3110 xhci_debugfs_create_endpoint(xhci, virt_dev, i);
3113 kfree(command->completion);
3118 EXPORT_SYMBOL_GPL(xhci_check_bandwidth);
3120 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3122 struct xhci_hcd *xhci;
3123 struct xhci_virt_device *virt_dev;
3126 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3129 xhci = hcd_to_xhci(hcd);
3131 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3132 virt_dev = xhci->devs[udev->slot_id];
3133 /* Free any rings allocated for added endpoints */
3134 for (i = 0; i < 31; i++) {
3135 if (virt_dev->eps[i].new_ring) {
3136 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3137 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
3138 virt_dev->eps[i].new_ring = NULL;
3141 xhci_zero_in_ctx(xhci, virt_dev);
3143 EXPORT_SYMBOL_GPL(xhci_reset_bandwidth);
3145 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
3146 struct xhci_container_ctx *in_ctx,
3147 struct xhci_container_ctx *out_ctx,
3148 struct xhci_input_control_ctx *ctrl_ctx,
3149 u32 add_flags, u32 drop_flags)
3151 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
3152 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
3153 xhci_slot_copy(xhci, in_ctx, out_ctx);
3154 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3157 static void xhci_endpoint_disable(struct usb_hcd *hcd,
3158 struct usb_host_endpoint *host_ep)
3160 struct xhci_hcd *xhci;
3161 struct xhci_virt_device *vdev;
3162 struct xhci_virt_ep *ep;
3163 struct usb_device *udev;
3164 unsigned long flags;
3165 unsigned int ep_index;
3167 xhci = hcd_to_xhci(hcd);
3169 spin_lock_irqsave(&xhci->lock, flags);
3171 udev = (struct usb_device *)host_ep->hcpriv;
3172 if (!udev || !udev->slot_id)
3175 vdev = xhci->devs[udev->slot_id];
3179 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3180 ep = &vdev->eps[ep_index];
3182 /* wait for hub_tt_work to finish clearing hub TT */
3183 if (ep->ep_state & EP_CLEARING_TT) {
3184 spin_unlock_irqrestore(&xhci->lock, flags);
3185 schedule_timeout_uninterruptible(1);
3190 xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3193 host_ep->hcpriv = NULL;
3194 spin_unlock_irqrestore(&xhci->lock, flags);
3198 * Called after usb core issues a clear halt control message.
3199 * The host side of the halt should already be cleared by a reset endpoint
3200 * command issued when the STALL event was received.
3202 * The reset endpoint command may only be issued to endpoints in the halted
3203 * state. For software that wishes to reset the data toggle or sequence number
3204 * of an endpoint that isn't in the halted state this function will issue a
3205 * configure endpoint command with the Drop and Add bits set for the target
3206 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3209 static void xhci_endpoint_reset(struct usb_hcd *hcd,
3210 struct usb_host_endpoint *host_ep)
3212 struct xhci_hcd *xhci;
3213 struct usb_device *udev;
3214 struct xhci_virt_device *vdev;
3215 struct xhci_virt_ep *ep;
3216 struct xhci_input_control_ctx *ctrl_ctx;
3217 struct xhci_command *stop_cmd, *cfg_cmd;
3218 unsigned int ep_index;
3219 unsigned long flags;
3223 xhci = hcd_to_xhci(hcd);
3224 if (!host_ep->hcpriv)
3226 udev = (struct usb_device *) host_ep->hcpriv;
3227 vdev = xhci->devs[udev->slot_id];
3230 * vdev may be lost due to xHC restore error and re-initialization
3231 * during S3/S4 resume. A new vdev will be allocated later by
3232 * xhci_discover_or_reset_device()
3234 if (!udev->slot_id || !vdev)
3236 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3237 ep = &vdev->eps[ep_index];
3239 /* Bail out if toggle is already being cleared by a endpoint reset */
3240 spin_lock_irqsave(&xhci->lock, flags);
3241 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3242 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3243 spin_unlock_irqrestore(&xhci->lock, flags);
3246 spin_unlock_irqrestore(&xhci->lock, flags);
3247 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3248 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3249 usb_endpoint_xfer_isoc(&host_ep->desc))
3252 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3254 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3257 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3261 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3265 spin_lock_irqsave(&xhci->lock, flags);
3267 /* block queuing new trbs and ringing ep doorbell */
3268 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3271 * Make sure endpoint ring is empty before resetting the toggle/seq.
3272 * Driver is required to synchronously cancel all transfer request.
3273 * Stop the endpoint to force xHC to update the output context
3276 if (!list_empty(&ep->ring->td_list)) {
3277 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3278 spin_unlock_irqrestore(&xhci->lock, flags);
3279 xhci_free_command(xhci, cfg_cmd);
3283 err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3286 spin_unlock_irqrestore(&xhci->lock, flags);
3287 xhci_free_command(xhci, cfg_cmd);
3288 xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3293 xhci_ring_cmd_db(xhci);
3294 spin_unlock_irqrestore(&xhci->lock, flags);
3296 wait_for_completion(stop_cmd->completion);
3298 spin_lock_irqsave(&xhci->lock, flags);
3300 /* config ep command clears toggle if add and drop ep flags are set */
3301 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3303 spin_unlock_irqrestore(&xhci->lock, flags);
3304 xhci_free_command(xhci, cfg_cmd);
3305 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3310 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3311 ctrl_ctx, ep_flag, ep_flag);
3312 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3314 err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3315 udev->slot_id, false);
3317 spin_unlock_irqrestore(&xhci->lock, flags);
3318 xhci_free_command(xhci, cfg_cmd);
3319 xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3324 xhci_ring_cmd_db(xhci);
3325 spin_unlock_irqrestore(&xhci->lock, flags);
3327 wait_for_completion(cfg_cmd->completion);
3329 xhci_free_command(xhci, cfg_cmd);
3331 xhci_free_command(xhci, stop_cmd);
3332 spin_lock_irqsave(&xhci->lock, flags);
3333 if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE)
3334 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3335 spin_unlock_irqrestore(&xhci->lock, flags);
3338 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3339 struct usb_device *udev, struct usb_host_endpoint *ep,
3340 unsigned int slot_id)
3343 unsigned int ep_index;
3344 unsigned int ep_state;
3348 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3350 return ret ? ret : -EINVAL;
3351 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3352 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3353 " descriptor for ep 0x%x does not support streams\n",
3354 ep->desc.bEndpointAddress);
3358 ep_index = xhci_get_endpoint_index(&ep->desc);
3359 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3360 if (ep_state & EP_HAS_STREAMS ||
3361 ep_state & EP_GETTING_STREAMS) {
3362 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3363 "already has streams set up.\n",
3364 ep->desc.bEndpointAddress);
3365 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3366 "dynamic stream context array reallocation.\n");
3369 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3370 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3371 "endpoint 0x%x; URBs are pending.\n",
3372 ep->desc.bEndpointAddress);
3378 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3379 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3381 unsigned int max_streams;
3383 /* The stream context array size must be a power of two */
3384 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3386 * Find out how many primary stream array entries the host controller
3387 * supports. Later we may use secondary stream arrays (similar to 2nd
3388 * level page entries), but that's an optional feature for xHCI host
3389 * controllers. xHCs must support at least 4 stream IDs.
3391 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3392 if (*num_stream_ctxs > max_streams) {
3393 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3395 *num_stream_ctxs = max_streams;
3396 *num_streams = max_streams;
3400 /* Returns an error code if one of the endpoint already has streams.
3401 * This does not change any data structures, it only checks and gathers
3404 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3405 struct usb_device *udev,
3406 struct usb_host_endpoint **eps, unsigned int num_eps,
3407 unsigned int *num_streams, u32 *changed_ep_bitmask)
3409 unsigned int max_streams;
3410 unsigned int endpoint_flag;
3414 for (i = 0; i < num_eps; i++) {
3415 ret = xhci_check_streams_endpoint(xhci, udev,
3416 eps[i], udev->slot_id);
3420 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3421 if (max_streams < (*num_streams - 1)) {
3422 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3423 eps[i]->desc.bEndpointAddress,
3425 *num_streams = max_streams+1;
3428 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3429 if (*changed_ep_bitmask & endpoint_flag)
3431 *changed_ep_bitmask |= endpoint_flag;
3436 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3437 struct usb_device *udev,
3438 struct usb_host_endpoint **eps, unsigned int num_eps)
3440 u32 changed_ep_bitmask = 0;
3441 unsigned int slot_id;
3442 unsigned int ep_index;
3443 unsigned int ep_state;
3446 slot_id = udev->slot_id;
3447 if (!xhci->devs[slot_id])
3450 for (i = 0; i < num_eps; i++) {
3451 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3452 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3453 /* Are streams already being freed for the endpoint? */
3454 if (ep_state & EP_GETTING_NO_STREAMS) {
3455 xhci_warn(xhci, "WARN Can't disable streams for "
3457 "streams are being disabled already\n",
3458 eps[i]->desc.bEndpointAddress);
3461 /* Are there actually any streams to free? */
3462 if (!(ep_state & EP_HAS_STREAMS) &&
3463 !(ep_state & EP_GETTING_STREAMS)) {
3464 xhci_warn(xhci, "WARN Can't disable streams for "
3466 "streams are already disabled!\n",
3467 eps[i]->desc.bEndpointAddress);
3468 xhci_warn(xhci, "WARN xhci_free_streams() called "
3469 "with non-streams endpoint\n");
3472 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3474 return changed_ep_bitmask;
3478 * The USB device drivers use this function (through the HCD interface in USB
3479 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3480 * coordinate mass storage command queueing across multiple endpoints (basically
3481 * a stream ID == a task ID).
3483 * Setting up streams involves allocating the same size stream context array
3484 * for each endpoint and issuing a configure endpoint command for all endpoints.
3486 * Don't allow the call to succeed if one endpoint only supports one stream
3487 * (which means it doesn't support streams at all).
3489 * Drivers may get less stream IDs than they asked for, if the host controller
3490 * hardware or endpoints claim they can't support the number of requested
3493 static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3494 struct usb_host_endpoint **eps, unsigned int num_eps,
3495 unsigned int num_streams, gfp_t mem_flags)
3498 struct xhci_hcd *xhci;
3499 struct xhci_virt_device *vdev;
3500 struct xhci_command *config_cmd;
3501 struct xhci_input_control_ctx *ctrl_ctx;
3502 unsigned int ep_index;
3503 unsigned int num_stream_ctxs;
3504 unsigned int max_packet;
3505 unsigned long flags;
3506 u32 changed_ep_bitmask = 0;
3511 /* Add one to the number of streams requested to account for
3512 * stream 0 that is reserved for xHCI usage.
3515 xhci = hcd_to_xhci(hcd);
3516 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3519 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3520 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3521 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3522 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3526 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3530 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3532 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3534 xhci_free_command(xhci, config_cmd);
3538 /* Check to make sure all endpoints are not already configured for
3539 * streams. While we're at it, find the maximum number of streams that
3540 * all the endpoints will support and check for duplicate endpoints.
3542 spin_lock_irqsave(&xhci->lock, flags);
3543 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3544 num_eps, &num_streams, &changed_ep_bitmask);
3546 xhci_free_command(xhci, config_cmd);
3547 spin_unlock_irqrestore(&xhci->lock, flags);
3550 if (num_streams <= 1) {
3551 xhci_warn(xhci, "WARN: endpoints can't handle "
3552 "more than one stream.\n");
3553 xhci_free_command(xhci, config_cmd);
3554 spin_unlock_irqrestore(&xhci->lock, flags);
3557 vdev = xhci->devs[udev->slot_id];
3558 /* Mark each endpoint as being in transition, so
3559 * xhci_urb_enqueue() will reject all URBs.
3561 for (i = 0; i < num_eps; i++) {
3562 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3563 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3565 spin_unlock_irqrestore(&xhci->lock, flags);
3567 /* Setup internal data structures and allocate HW data structures for
3568 * streams (but don't install the HW structures in the input context
3569 * until we're sure all memory allocation succeeded).
3571 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3572 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3573 num_stream_ctxs, num_streams);
3575 for (i = 0; i < num_eps; i++) {
3576 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3577 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3578 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3581 max_packet, mem_flags);
3582 if (!vdev->eps[ep_index].stream_info)
3584 /* Set maxPstreams in endpoint context and update deq ptr to
3585 * point to stream context array. FIXME
3589 /* Set up the input context for a configure endpoint command. */
3590 for (i = 0; i < num_eps; i++) {
3591 struct xhci_ep_ctx *ep_ctx;
3593 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3594 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3596 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3597 vdev->out_ctx, ep_index);
3598 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3599 vdev->eps[ep_index].stream_info);
3601 /* Tell the HW to drop its old copy of the endpoint context info
3602 * and add the updated copy from the input context.
3604 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3605 vdev->out_ctx, ctrl_ctx,
3606 changed_ep_bitmask, changed_ep_bitmask);
3608 /* Issue and wait for the configure endpoint command */
3609 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3612 /* xHC rejected the configure endpoint command for some reason, so we
3613 * leave the old ring intact and free our internal streams data
3619 spin_lock_irqsave(&xhci->lock, flags);
3620 for (i = 0; i < num_eps; i++) {
3621 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3622 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3623 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3624 udev->slot_id, ep_index);
3625 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3627 xhci_free_command(xhci, config_cmd);
3628 spin_unlock_irqrestore(&xhci->lock, flags);
3630 for (i = 0; i < num_eps; i++) {
3631 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3632 xhci_debugfs_create_stream_files(xhci, vdev, ep_index);
3634 /* Subtract 1 for stream 0, which drivers can't use */
3635 return num_streams - 1;
3638 /* If it didn't work, free the streams! */
3639 for (i = 0; i < num_eps; i++) {
3640 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3641 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3642 vdev->eps[ep_index].stream_info = NULL;
3643 /* FIXME Unset maxPstreams in endpoint context and
3644 * update deq ptr to point to normal string ring.
3646 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3647 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3648 xhci_endpoint_zero(xhci, vdev, eps[i]);
3650 xhci_free_command(xhci, config_cmd);
3654 /* Transition the endpoint from using streams to being a "normal" endpoint
3657 * Modify the endpoint context state, submit a configure endpoint command,
3658 * and free all endpoint rings for streams if that completes successfully.
3660 static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3661 struct usb_host_endpoint **eps, unsigned int num_eps,
3665 struct xhci_hcd *xhci;
3666 struct xhci_virt_device *vdev;
3667 struct xhci_command *command;
3668 struct xhci_input_control_ctx *ctrl_ctx;
3669 unsigned int ep_index;
3670 unsigned long flags;
3671 u32 changed_ep_bitmask;
3673 xhci = hcd_to_xhci(hcd);
3674 vdev = xhci->devs[udev->slot_id];
3676 /* Set up a configure endpoint command to remove the streams rings */
3677 spin_lock_irqsave(&xhci->lock, flags);
3678 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3679 udev, eps, num_eps);
3680 if (changed_ep_bitmask == 0) {
3681 spin_unlock_irqrestore(&xhci->lock, flags);
3685 /* Use the xhci_command structure from the first endpoint. We may have
3686 * allocated too many, but the driver may call xhci_free_streams() for
3687 * each endpoint it grouped into one call to xhci_alloc_streams().
3689 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3690 command = vdev->eps[ep_index].stream_info->free_streams_command;
3691 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3693 spin_unlock_irqrestore(&xhci->lock, flags);
3694 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3699 for (i = 0; i < num_eps; i++) {
3700 struct xhci_ep_ctx *ep_ctx;
3702 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3703 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3704 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3705 EP_GETTING_NO_STREAMS;
3707 xhci_endpoint_copy(xhci, command->in_ctx,
3708 vdev->out_ctx, ep_index);
3709 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3710 &vdev->eps[ep_index]);
3712 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3713 vdev->out_ctx, ctrl_ctx,
3714 changed_ep_bitmask, changed_ep_bitmask);
3715 spin_unlock_irqrestore(&xhci->lock, flags);
3717 /* Issue and wait for the configure endpoint command,
3718 * which must succeed.
3720 ret = xhci_configure_endpoint(xhci, udev, command,
3723 /* xHC rejected the configure endpoint command for some reason, so we
3724 * leave the streams rings intact.
3729 spin_lock_irqsave(&xhci->lock, flags);
3730 for (i = 0; i < num_eps; i++) {
3731 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3732 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3733 vdev->eps[ep_index].stream_info = NULL;
3734 /* FIXME Unset maxPstreams in endpoint context and
3735 * update deq ptr to point to normal string ring.
3737 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3738 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3740 spin_unlock_irqrestore(&xhci->lock, flags);
3746 * Deletes endpoint resources for endpoints that were active before a Reset
3747 * Device command, or a Disable Slot command. The Reset Device command leaves
3748 * the control endpoint intact, whereas the Disable Slot command deletes it.
3750 * Must be called with xhci->lock held.
3752 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3753 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3756 unsigned int num_dropped_eps = 0;
3757 unsigned int drop_flags = 0;
3759 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3760 if (virt_dev->eps[i].ring) {
3761 drop_flags |= 1 << i;
3765 xhci->num_active_eps -= num_dropped_eps;
3766 if (num_dropped_eps)
3767 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3768 "Dropped %u ep ctxs, flags = 0x%x, "
3770 num_dropped_eps, drop_flags,
3771 xhci->num_active_eps);
3775 * This submits a Reset Device Command, which will set the device state to 0,
3776 * set the device address to 0, and disable all the endpoints except the default
3777 * control endpoint. The USB core should come back and call
3778 * xhci_address_device(), and then re-set up the configuration. If this is
3779 * called because of a usb_reset_and_verify_device(), then the old alternate
3780 * settings will be re-installed through the normal bandwidth allocation
3783 * Wait for the Reset Device command to finish. Remove all structures
3784 * associated with the endpoints that were disabled. Clear the input device
3785 * structure? Reset the control endpoint 0 max packet size?
3787 * If the virt_dev to be reset does not exist or does not match the udev,
3788 * it means the device is lost, possibly due to the xHC restore error and
3789 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3790 * re-allocate the device.
3792 static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3793 struct usb_device *udev)
3796 unsigned long flags;
3797 struct xhci_hcd *xhci;
3798 unsigned int slot_id;
3799 struct xhci_virt_device *virt_dev;
3800 struct xhci_command *reset_device_cmd;
3801 struct xhci_slot_ctx *slot_ctx;
3802 int old_active_eps = 0;
3804 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3807 xhci = hcd_to_xhci(hcd);
3808 slot_id = udev->slot_id;
3809 virt_dev = xhci->devs[slot_id];
3811 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3812 "not exist. Re-allocate the device\n", slot_id);
3813 ret = xhci_alloc_dev(hcd, udev);
3820 if (virt_dev->tt_info)
3821 old_active_eps = virt_dev->tt_info->active_eps;
3823 if (virt_dev->udev != udev) {
3824 /* If the virt_dev and the udev does not match, this virt_dev
3825 * may belong to another udev.
3826 * Re-allocate the device.
3828 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3829 "not match the udev. Re-allocate the device\n",
3831 ret = xhci_alloc_dev(hcd, udev);
3838 /* If device is not setup, there is no point in resetting it */
3839 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3840 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3841 SLOT_STATE_DISABLED)
3844 trace_xhci_discover_or_reset_device(slot_ctx);
3846 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3847 /* Allocate the command structure that holds the struct completion.
3848 * Assume we're in process context, since the normal device reset
3849 * process has to wait for the device anyway. Storage devices are
3850 * reset as part of error handling, so use GFP_NOIO instead of
3853 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3854 if (!reset_device_cmd) {
3855 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3859 /* Attempt to submit the Reset Device command to the command ring */
3860 spin_lock_irqsave(&xhci->lock, flags);
3862 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3864 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3865 spin_unlock_irqrestore(&xhci->lock, flags);
3866 goto command_cleanup;
3868 xhci_ring_cmd_db(xhci);
3869 spin_unlock_irqrestore(&xhci->lock, flags);
3871 /* Wait for the Reset Device command to finish */
3872 wait_for_completion(reset_device_cmd->completion);
3874 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3875 * unless we tried to reset a slot ID that wasn't enabled,
3876 * or the device wasn't in the addressed or configured state.
3878 ret = reset_device_cmd->status;
3880 case COMP_COMMAND_ABORTED:
3881 case COMP_COMMAND_RING_STOPPED:
3882 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3884 goto command_cleanup;
3885 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3886 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3887 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3889 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3890 xhci_dbg(xhci, "Not freeing device rings.\n");
3891 /* Don't treat this as an error. May change my mind later. */
3893 goto command_cleanup;
3895 xhci_dbg(xhci, "Successful reset device command.\n");
3898 if (xhci_is_vendor_info_code(xhci, ret))
3900 xhci_warn(xhci, "Unknown completion code %u for "
3901 "reset device command.\n", ret);
3903 goto command_cleanup;
3906 /* Free up host controller endpoint resources */
3907 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3908 spin_lock_irqsave(&xhci->lock, flags);
3909 /* Don't delete the default control endpoint resources */
3910 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3911 spin_unlock_irqrestore(&xhci->lock, flags);
3914 /* Everything but endpoint 0 is disabled, so free the rings. */
3915 for (i = 1; i < 31; i++) {
3916 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3918 if (ep->ep_state & EP_HAS_STREAMS) {
3919 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3920 xhci_get_endpoint_address(i));
3921 xhci_free_stream_info(xhci, ep->stream_info);
3922 ep->stream_info = NULL;
3923 ep->ep_state &= ~EP_HAS_STREAMS;
3927 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3928 xhci_free_endpoint_ring(xhci, virt_dev, i);
3930 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3931 xhci_drop_ep_from_interval_table(xhci,
3932 &virt_dev->eps[i].bw_info,
3937 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3939 /* If necessary, update the number of active TTs on this root port */
3940 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3941 virt_dev->flags = 0;
3945 xhci_free_command(xhci, reset_device_cmd);
3950 * At this point, the struct usb_device is about to go away, the device has
3951 * disconnected, and all traffic has been stopped and the endpoints have been
3952 * disabled. Free any HC data structures associated with that device.
3954 static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3956 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3957 struct xhci_virt_device *virt_dev;
3958 struct xhci_slot_ctx *slot_ctx;
3962 * We called pm_runtime_get_noresume when the device was attached.
3963 * Decrement the counter here to allow controller to runtime suspend
3964 * if no devices remain.
3966 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3967 pm_runtime_put_noidle(hcd->self.controller);
3969 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3970 /* If the host is halted due to driver unload, we still need to free the
3973 if (ret <= 0 && ret != -ENODEV)
3976 virt_dev = xhci->devs[udev->slot_id];
3977 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3978 trace_xhci_free_dev(slot_ctx);
3980 /* Stop any wayward timer functions (which may grab the lock) */
3981 for (i = 0; i < 31; i++)
3982 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3983 virt_dev->udev = NULL;
3984 xhci_disable_slot(xhci, udev->slot_id);
3985 xhci_free_virt_device(xhci, udev->slot_id);
3988 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
3990 struct xhci_command *command;
3991 unsigned long flags;
3995 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3999 xhci_debugfs_remove_slot(xhci, slot_id);
4001 spin_lock_irqsave(&xhci->lock, flags);
4002 /* Don't disable the slot if the host controller is dead. */
4003 state = readl(&xhci->op_regs->status);
4004 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
4005 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4006 spin_unlock_irqrestore(&xhci->lock, flags);
4011 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
4014 spin_unlock_irqrestore(&xhci->lock, flags);
4018 xhci_ring_cmd_db(xhci);
4019 spin_unlock_irqrestore(&xhci->lock, flags);
4021 wait_for_completion(command->completion);
4023 if (command->status != COMP_SUCCESS)
4024 xhci_warn(xhci, "Unsuccessful disable slot %u command, status %d\n",
4025 slot_id, command->status);
4027 xhci_free_command(xhci, command);
4033 * Checks if we have enough host controller resources for the default control
4036 * Must be called with xhci->lock held.
4038 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
4040 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
4041 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4042 "Not enough ep ctxs: "
4043 "%u active, need to add 1, limit is %u.",
4044 xhci->num_active_eps, xhci->limit_active_eps);
4047 xhci->num_active_eps += 1;
4048 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4049 "Adding 1 ep ctx, %u now active.",
4050 xhci->num_active_eps);
4056 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
4057 * timed out, or allocating memory failed. Returns 1 on success.
4059 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
4061 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4062 struct xhci_virt_device *vdev;
4063 struct xhci_slot_ctx *slot_ctx;
4064 unsigned long flags;
4066 struct xhci_command *command;
4068 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4072 spin_lock_irqsave(&xhci->lock, flags);
4073 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
4075 spin_unlock_irqrestore(&xhci->lock, flags);
4076 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
4077 xhci_free_command(xhci, command);
4080 xhci_ring_cmd_db(xhci);
4081 spin_unlock_irqrestore(&xhci->lock, flags);
4083 wait_for_completion(command->completion);
4084 slot_id = command->slot_id;
4086 if (!slot_id || command->status != COMP_SUCCESS) {
4087 xhci_err(xhci, "Error while assigning device slot ID\n");
4088 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
4090 readl(&xhci->cap_regs->hcs_params1)));
4091 xhci_free_command(xhci, command);
4095 xhci_free_command(xhci, command);
4097 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
4098 spin_lock_irqsave(&xhci->lock, flags);
4099 ret = xhci_reserve_host_control_ep_resources(xhci);
4101 spin_unlock_irqrestore(&xhci->lock, flags);
4102 xhci_warn(xhci, "Not enough host resources, "
4103 "active endpoint contexts = %u\n",
4104 xhci->num_active_eps);
4107 spin_unlock_irqrestore(&xhci->lock, flags);
4109 /* Use GFP_NOIO, since this function can be called from
4110 * xhci_discover_or_reset_device(), which may be called as part of
4111 * mass storage driver error handling.
4113 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4114 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4117 vdev = xhci->devs[slot_id];
4118 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4119 trace_xhci_alloc_dev(slot_ctx);
4121 udev->slot_id = slot_id;
4123 xhci_debugfs_create_slot(xhci, slot_id);
4126 * If resetting upon resume, we can't put the controller into runtime
4127 * suspend if there is a device attached.
4129 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4130 pm_runtime_get_noresume(hcd->self.controller);
4132 /* Is this a LS or FS device under a HS hub? */
4133 /* Hub or peripherial? */
4137 xhci_disable_slot(xhci, udev->slot_id);
4138 xhci_free_virt_device(xhci, udev->slot_id);
4144 * Issue an Address Device command and optionally send a corresponding
4145 * SetAddress request to the device.
4147 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4148 enum xhci_setup_dev setup)
4150 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4151 unsigned long flags;
4152 struct xhci_virt_device *virt_dev;
4154 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4155 struct xhci_slot_ctx *slot_ctx;
4156 struct xhci_input_control_ctx *ctrl_ctx;
4158 struct xhci_command *command = NULL;
4160 mutex_lock(&xhci->mutex);
4162 if (xhci->xhc_state) { /* dying, removing or halted */
4167 if (!udev->slot_id) {
4168 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4169 "Bad Slot ID %d", udev->slot_id);
4174 virt_dev = xhci->devs[udev->slot_id];
4176 if (WARN_ON(!virt_dev)) {
4178 * In plug/unplug torture test with an NEC controller,
4179 * a zero-dereference was observed once due to virt_dev = 0.
4180 * Print useful debug rather than crash if it is observed again!
4182 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4187 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4188 trace_xhci_setup_device_slot(slot_ctx);
4190 if (setup == SETUP_CONTEXT_ONLY) {
4191 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4192 SLOT_STATE_DEFAULT) {
4193 xhci_dbg(xhci, "Slot already in default state\n");
4198 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4204 command->in_ctx = virt_dev->in_ctx;
4206 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4207 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4209 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4215 * If this is the first Set Address since device plug-in or
4216 * virt_device realloaction after a resume with an xHCI power loss,
4217 * then set up the slot context.
4219 if (!slot_ctx->dev_info)
4220 xhci_setup_addressable_virt_dev(xhci, udev);
4221 /* Otherwise, update the control endpoint ring enqueue pointer. */
4223 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4224 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4225 ctrl_ctx->drop_flags = 0;
4227 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4228 le32_to_cpu(slot_ctx->dev_info) >> 27);
4230 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4231 spin_lock_irqsave(&xhci->lock, flags);
4232 trace_xhci_setup_device(virt_dev);
4233 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4234 udev->slot_id, setup);
4236 spin_unlock_irqrestore(&xhci->lock, flags);
4237 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4238 "FIXME: allocate a command ring segment");
4241 xhci_ring_cmd_db(xhci);
4242 spin_unlock_irqrestore(&xhci->lock, flags);
4244 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4245 wait_for_completion(command->completion);
4247 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4248 * the SetAddress() "recovery interval" required by USB and aborting the
4249 * command on a timeout.
4251 switch (command->status) {
4252 case COMP_COMMAND_ABORTED:
4253 case COMP_COMMAND_RING_STOPPED:
4254 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4257 case COMP_CONTEXT_STATE_ERROR:
4258 case COMP_SLOT_NOT_ENABLED_ERROR:
4259 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4260 act, udev->slot_id);
4263 case COMP_USB_TRANSACTION_ERROR:
4264 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4266 mutex_unlock(&xhci->mutex);
4267 ret = xhci_disable_slot(xhci, udev->slot_id);
4268 xhci_free_virt_device(xhci, udev->slot_id);
4270 xhci_alloc_dev(hcd, udev);
4271 kfree(command->completion);
4274 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4275 dev_warn(&udev->dev,
4276 "ERROR: Incompatible device for setup %s command\n", act);
4280 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4281 "Successful setup %s command", act);
4285 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4286 act, command->status);
4287 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4293 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4294 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4295 "Op regs DCBAA ptr = %#016llx", temp_64);
4296 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4297 "Slot ID %d dcbaa entry @%p = %#016llx",
4299 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4300 (unsigned long long)
4301 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4302 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4303 "Output Context DMA address = %#08llx",
4304 (unsigned long long)virt_dev->out_ctx->dma);
4305 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4306 le32_to_cpu(slot_ctx->dev_info) >> 27);
4308 * USB core uses address 1 for the roothubs, so we add one to the
4309 * address given back to us by the HC.
4311 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4312 le32_to_cpu(slot_ctx->dev_info) >> 27);
4313 /* Zero the input context control for later use */
4314 ctrl_ctx->add_flags = 0;
4315 ctrl_ctx->drop_flags = 0;
4316 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4317 udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4319 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4320 "Internal device address = %d",
4321 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4323 mutex_unlock(&xhci->mutex);
4325 kfree(command->completion);
4331 static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4333 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4336 static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4338 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4342 * Transfer the port index into real index in the HW port status
4343 * registers. Caculate offset between the port's PORTSC register
4344 * and port status base. Divide the number of per port register
4345 * to get the real index. The raw port number bases 1.
4347 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4349 struct xhci_hub *rhub;
4351 rhub = xhci_get_rhub(hcd);
4352 return rhub->ports[port1 - 1]->hw_portnum + 1;
4356 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4357 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4359 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4360 struct usb_device *udev, u16 max_exit_latency)
4362 struct xhci_virt_device *virt_dev;
4363 struct xhci_command *command;
4364 struct xhci_input_control_ctx *ctrl_ctx;
4365 struct xhci_slot_ctx *slot_ctx;
4366 unsigned long flags;
4369 command = xhci_alloc_command_with_ctx(xhci, true, GFP_KERNEL);
4373 spin_lock_irqsave(&xhci->lock, flags);
4375 virt_dev = xhci->devs[udev->slot_id];
4378 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4379 * xHC was re-initialized. Exit latency will be set later after
4380 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4383 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4384 spin_unlock_irqrestore(&xhci->lock, flags);
4388 /* Attempt to issue an Evaluate Context command to change the MEL. */
4389 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4391 spin_unlock_irqrestore(&xhci->lock, flags);
4392 xhci_free_command(xhci, command);
4393 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4398 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4399 spin_unlock_irqrestore(&xhci->lock, flags);
4401 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4402 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4403 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4404 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4405 slot_ctx->dev_state = 0;
4407 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4408 "Set up evaluate context for LPM MEL change.");
4410 /* Issue and wait for the evaluate context command. */
4411 ret = xhci_configure_endpoint(xhci, udev, command,
4415 spin_lock_irqsave(&xhci->lock, flags);
4416 virt_dev->current_mel = max_exit_latency;
4417 spin_unlock_irqrestore(&xhci->lock, flags);
4420 xhci_free_command(xhci, command);
4427 /* BESL to HIRD Encoding array for USB2 LPM */
4428 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4429 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4431 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4432 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4433 struct usb_device *udev)
4435 int u2del, besl, besl_host;
4436 int besl_device = 0;
4439 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4440 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4442 if (field & USB_BESL_SUPPORT) {
4443 for (besl_host = 0; besl_host < 16; besl_host++) {
4444 if (xhci_besl_encoding[besl_host] >= u2del)
4447 /* Use baseline BESL value as default */
4448 if (field & USB_BESL_BASELINE_VALID)
4449 besl_device = USB_GET_BESL_BASELINE(field);
4450 else if (field & USB_BESL_DEEP_VALID)
4451 besl_device = USB_GET_BESL_DEEP(field);
4456 besl_host = (u2del - 51) / 75 + 1;
4459 besl = besl_host + besl_device;
4466 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4467 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4474 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4476 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4477 l1 = udev->l1_params.timeout / 256;
4479 /* device has preferred BESLD */
4480 if (field & USB_BESL_DEEP_VALID) {
4481 besld = USB_GET_BESL_DEEP(field);
4485 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4488 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4489 struct usb_device *udev, int enable)
4491 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4492 struct xhci_port **ports;
4493 __le32 __iomem *pm_addr, *hlpm_addr;
4494 u32 pm_val, hlpm_val, field;
4495 unsigned int port_num;
4496 unsigned long flags;
4497 int hird, exit_latency;
4500 if (xhci->quirks & XHCI_HW_LPM_DISABLE)
4503 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4507 if (!udev->parent || udev->parent->parent ||
4508 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4511 if (udev->usb2_hw_lpm_capable != 1)
4514 spin_lock_irqsave(&xhci->lock, flags);
4516 ports = xhci->usb2_rhub.ports;
4517 port_num = udev->portnum - 1;
4518 pm_addr = ports[port_num]->addr + PORTPMSC;
4519 pm_val = readl(pm_addr);
4520 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4522 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4523 enable ? "enable" : "disable", port_num + 1);
4526 /* Host supports BESL timeout instead of HIRD */
4527 if (udev->usb2_hw_lpm_besl_capable) {
4528 /* if device doesn't have a preferred BESL value use a
4529 * default one which works with mixed HIRD and BESL
4530 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4532 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4533 if ((field & USB_BESL_SUPPORT) &&
4534 (field & USB_BESL_BASELINE_VALID))
4535 hird = USB_GET_BESL_BASELINE(field);
4537 hird = udev->l1_params.besl;
4539 exit_latency = xhci_besl_encoding[hird];
4540 spin_unlock_irqrestore(&xhci->lock, flags);
4542 ret = xhci_change_max_exit_latency(xhci, udev,
4546 spin_lock_irqsave(&xhci->lock, flags);
4548 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4549 writel(hlpm_val, hlpm_addr);
4553 hird = xhci_calculate_hird_besl(xhci, udev);
4556 pm_val &= ~PORT_HIRD_MASK;
4557 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4558 writel(pm_val, pm_addr);
4559 pm_val = readl(pm_addr);
4561 writel(pm_val, pm_addr);
4565 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4566 writel(pm_val, pm_addr);
4569 if (udev->usb2_hw_lpm_besl_capable) {
4570 spin_unlock_irqrestore(&xhci->lock, flags);
4571 xhci_change_max_exit_latency(xhci, udev, 0);
4572 readl_poll_timeout(ports[port_num]->addr, pm_val,
4573 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4579 spin_unlock_irqrestore(&xhci->lock, flags);
4583 /* check if a usb2 port supports a given extened capability protocol
4584 * only USB2 ports extended protocol capability values are cached.
4585 * Return 1 if capability is supported
4587 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4588 unsigned capability)
4590 u32 port_offset, port_count;
4593 for (i = 0; i < xhci->num_ext_caps; i++) {
4594 if (xhci->ext_caps[i] & capability) {
4595 /* port offsets starts at 1 */
4596 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4597 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4598 if (port >= port_offset &&
4599 port < port_offset + port_count)
4606 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4608 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4609 int portnum = udev->portnum - 1;
4611 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
4614 /* we only support lpm for non-hub device connected to root hub yet */
4615 if (!udev->parent || udev->parent->parent ||
4616 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4619 if (xhci->hw_lpm_support == 1 &&
4620 xhci_check_usb2_port_capability(
4621 xhci, portnum, XHCI_HLC)) {
4622 udev->usb2_hw_lpm_capable = 1;
4623 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4624 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4625 if (xhci_check_usb2_port_capability(xhci, portnum,
4627 udev->usb2_hw_lpm_besl_capable = 1;
4633 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4635 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4636 static unsigned long long xhci_service_interval_to_ns(
4637 struct usb_endpoint_descriptor *desc)
4639 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4642 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4643 enum usb3_link_state state)
4645 unsigned long long sel;
4646 unsigned long long pel;
4647 unsigned int max_sel_pel;
4652 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4653 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4654 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4655 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4659 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4660 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4661 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4665 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4667 return USB3_LPM_DISABLED;
4670 if (sel <= max_sel_pel && pel <= max_sel_pel)
4671 return USB3_LPM_DEVICE_INITIATED;
4673 if (sel > max_sel_pel)
4674 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4675 "due to long SEL %llu ms\n",
4678 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4679 "due to long PEL %llu ms\n",
4681 return USB3_LPM_DISABLED;
4684 /* The U1 timeout should be the maximum of the following values:
4685 * - For control endpoints, U1 system exit latency (SEL) * 3
4686 * - For bulk endpoints, U1 SEL * 5
4687 * - For interrupt endpoints:
4688 * - Notification EPs, U1 SEL * 3
4689 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4690 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4692 static unsigned long long xhci_calculate_intel_u1_timeout(
4693 struct usb_device *udev,
4694 struct usb_endpoint_descriptor *desc)
4696 unsigned long long timeout_ns;
4700 ep_type = usb_endpoint_type(desc);
4702 case USB_ENDPOINT_XFER_CONTROL:
4703 timeout_ns = udev->u1_params.sel * 3;
4705 case USB_ENDPOINT_XFER_BULK:
4706 timeout_ns = udev->u1_params.sel * 5;
4708 case USB_ENDPOINT_XFER_INT:
4709 intr_type = usb_endpoint_interrupt_type(desc);
4710 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4711 timeout_ns = udev->u1_params.sel * 3;
4714 /* Otherwise the calculation is the same as isoc eps */
4716 case USB_ENDPOINT_XFER_ISOC:
4717 timeout_ns = xhci_service_interval_to_ns(desc);
4718 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4719 if (timeout_ns < udev->u1_params.sel * 2)
4720 timeout_ns = udev->u1_params.sel * 2;
4729 /* Returns the hub-encoded U1 timeout value. */
4730 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4731 struct usb_device *udev,
4732 struct usb_endpoint_descriptor *desc)
4734 unsigned long long timeout_ns;
4736 /* Prevent U1 if service interval is shorter than U1 exit latency */
4737 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4738 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4739 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4740 return USB3_LPM_DISABLED;
4744 if (xhci->quirks & XHCI_INTEL_HOST)
4745 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4747 timeout_ns = udev->u1_params.sel;
4749 /* The U1 timeout is encoded in 1us intervals.
4750 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4752 if (timeout_ns == USB3_LPM_DISABLED)
4755 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4757 /* If the necessary timeout value is bigger than what we can set in the
4758 * USB 3.0 hub, we have to disable hub-initiated U1.
4760 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4762 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4763 "due to long timeout %llu ms\n", timeout_ns);
4764 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4767 /* The U2 timeout should be the maximum of:
4768 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4769 * - largest bInterval of any active periodic endpoint (to avoid going
4770 * into lower power link states between intervals).
4771 * - the U2 Exit Latency of the device
4773 static unsigned long long xhci_calculate_intel_u2_timeout(
4774 struct usb_device *udev,
4775 struct usb_endpoint_descriptor *desc)
4777 unsigned long long timeout_ns;
4778 unsigned long long u2_del_ns;
4780 timeout_ns = 10 * 1000 * 1000;
4782 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4783 (xhci_service_interval_to_ns(desc) > timeout_ns))
4784 timeout_ns = xhci_service_interval_to_ns(desc);
4786 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4787 if (u2_del_ns > timeout_ns)
4788 timeout_ns = u2_del_ns;
4793 /* Returns the hub-encoded U2 timeout value. */
4794 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4795 struct usb_device *udev,
4796 struct usb_endpoint_descriptor *desc)
4798 unsigned long long timeout_ns;
4800 /* Prevent U2 if service interval is shorter than U2 exit latency */
4801 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4802 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4803 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4804 return USB3_LPM_DISABLED;
4808 if (xhci->quirks & XHCI_INTEL_HOST)
4809 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4811 timeout_ns = udev->u2_params.sel;
4813 /* The U2 timeout is encoded in 256us intervals */
4814 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4815 /* If the necessary timeout value is bigger than what we can set in the
4816 * USB 3.0 hub, we have to disable hub-initiated U2.
4818 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4820 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4821 "due to long timeout %llu ms\n", timeout_ns);
4822 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4825 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4826 struct usb_device *udev,
4827 struct usb_endpoint_descriptor *desc,
4828 enum usb3_link_state state,
4831 if (state == USB3_LPM_U1)
4832 return xhci_calculate_u1_timeout(xhci, udev, desc);
4833 else if (state == USB3_LPM_U2)
4834 return xhci_calculate_u2_timeout(xhci, udev, desc);
4836 return USB3_LPM_DISABLED;
4839 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4840 struct usb_device *udev,
4841 struct usb_endpoint_descriptor *desc,
4842 enum usb3_link_state state,
4847 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4848 desc, state, timeout);
4850 /* If we found we can't enable hub-initiated LPM, and
4851 * the U1 or U2 exit latency was too high to allow
4852 * device-initiated LPM as well, then we will disable LPM
4853 * for this device, so stop searching any further.
4855 if (alt_timeout == USB3_LPM_DISABLED) {
4856 *timeout = alt_timeout;
4859 if (alt_timeout > *timeout)
4860 *timeout = alt_timeout;
4864 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4865 struct usb_device *udev,
4866 struct usb_host_interface *alt,
4867 enum usb3_link_state state,
4872 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4873 if (xhci_update_timeout_for_endpoint(xhci, udev,
4874 &alt->endpoint[j].desc, state, timeout))
4880 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4881 enum usb3_link_state state)
4883 struct usb_device *parent;
4884 unsigned int num_hubs;
4886 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4887 for (parent = udev->parent, num_hubs = 0; parent->parent;
4888 parent = parent->parent)
4894 dev_dbg(&udev->dev, "Disabling U1/U2 link state for device"
4895 " below second-tier hub.\n");
4896 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4897 "to decrease power consumption.\n");
4901 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4902 struct usb_device *udev,
4903 enum usb3_link_state state)
4905 if (xhci->quirks & XHCI_INTEL_HOST)
4906 return xhci_check_intel_tier_policy(udev, state);
4911 /* Returns the U1 or U2 timeout that should be enabled.
4912 * If the tier check or timeout setting functions return with a non-zero exit
4913 * code, that means the timeout value has been finalized and we shouldn't look
4914 * at any more endpoints.
4916 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4917 struct usb_device *udev, enum usb3_link_state state)
4919 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4920 struct usb_host_config *config;
4923 u16 timeout = USB3_LPM_DISABLED;
4925 if (state == USB3_LPM_U1)
4927 else if (state == USB3_LPM_U2)
4930 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4935 /* Gather some information about the currently installed configuration
4936 * and alternate interface settings.
4938 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4942 config = udev->actconfig;
4946 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4947 struct usb_driver *driver;
4948 struct usb_interface *intf = config->interface[i];
4953 /* Check if any currently bound drivers want hub-initiated LPM
4956 if (intf->dev.driver) {
4957 driver = to_usb_driver(intf->dev.driver);
4958 if (driver && driver->disable_hub_initiated_lpm) {
4959 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4960 state_name, driver->name);
4961 timeout = xhci_get_timeout_no_hub_lpm(udev,
4963 if (timeout == USB3_LPM_DISABLED)
4968 /* Not sure how this could happen... */
4969 if (!intf->cur_altsetting)
4972 if (xhci_update_timeout_for_interface(xhci, udev,
4973 intf->cur_altsetting,
4980 static int calculate_max_exit_latency(struct usb_device *udev,
4981 enum usb3_link_state state_changed,
4982 u16 hub_encoded_timeout)
4984 unsigned long long u1_mel_us = 0;
4985 unsigned long long u2_mel_us = 0;
4986 unsigned long long mel_us = 0;
4992 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4993 hub_encoded_timeout == USB3_LPM_DISABLED);
4994 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4995 hub_encoded_timeout == USB3_LPM_DISABLED);
4997 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4998 hub_encoded_timeout != USB3_LPM_DISABLED);
4999 enabling_u2 = (state_changed == USB3_LPM_U2 &&
5000 hub_encoded_timeout != USB3_LPM_DISABLED);
5002 /* If U1 was already enabled and we're not disabling it,
5003 * or we're going to enable U1, account for the U1 max exit latency.
5005 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
5007 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
5008 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
5010 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
5012 mel_us = max(u1_mel_us, u2_mel_us);
5014 /* xHCI host controller max exit latency field is only 16 bits wide. */
5015 if (mel_us > MAX_EXIT) {
5016 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
5017 "is too big.\n", mel_us);
5023 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
5024 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5025 struct usb_device *udev, enum usb3_link_state state)
5027 struct xhci_hcd *xhci;
5028 u16 hub_encoded_timeout;
5032 xhci = hcd_to_xhci(hcd);
5033 /* The LPM timeout values are pretty host-controller specific, so don't
5034 * enable hub-initiated timeouts unless the vendor has provided
5035 * information about their timeout algorithm.
5037 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5038 !xhci->devs[udev->slot_id])
5039 return USB3_LPM_DISABLED;
5041 if (xhci_check_tier_policy(xhci, udev, state) < 0)
5042 return USB3_LPM_DISABLED;
5044 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
5045 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
5047 /* Max Exit Latency is too big, disable LPM. */
5048 hub_encoded_timeout = USB3_LPM_DISABLED;
5052 ret = xhci_change_max_exit_latency(xhci, udev, mel);
5055 return hub_encoded_timeout;
5058 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5059 struct usb_device *udev, enum usb3_link_state state)
5061 struct xhci_hcd *xhci;
5064 xhci = hcd_to_xhci(hcd);
5065 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5066 !xhci->devs[udev->slot_id])
5069 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
5070 return xhci_change_max_exit_latency(xhci, udev, mel);
5072 #else /* CONFIG_PM */
5074 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
5075 struct usb_device *udev, int enable)
5080 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
5085 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5086 struct usb_device *udev, enum usb3_link_state state)
5088 return USB3_LPM_DISABLED;
5091 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5092 struct usb_device *udev, enum usb3_link_state state)
5096 #endif /* CONFIG_PM */
5098 /*-------------------------------------------------------------------------*/
5100 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
5101 * internal data structures for the device.
5103 static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
5104 struct usb_tt *tt, gfp_t mem_flags)
5106 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5107 struct xhci_virt_device *vdev;
5108 struct xhci_command *config_cmd;
5109 struct xhci_input_control_ctx *ctrl_ctx;
5110 struct xhci_slot_ctx *slot_ctx;
5111 unsigned long flags;
5112 unsigned think_time;
5115 /* Ignore root hubs */
5119 vdev = xhci->devs[hdev->slot_id];
5121 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5125 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5129 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5131 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5133 xhci_free_command(xhci, config_cmd);
5137 spin_lock_irqsave(&xhci->lock, flags);
5138 if (hdev->speed == USB_SPEED_HIGH &&
5139 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5140 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5141 xhci_free_command(xhci, config_cmd);
5142 spin_unlock_irqrestore(&xhci->lock, flags);
5146 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5147 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5148 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5149 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5151 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5152 * but it may be already set to 1 when setup an xHCI virtual
5153 * device, so clear it anyway.
5156 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5157 else if (hdev->speed == USB_SPEED_FULL)
5158 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5160 if (xhci->hci_version > 0x95) {
5161 xhci_dbg(xhci, "xHCI version %x needs hub "
5162 "TT think time and number of ports\n",
5163 (unsigned int) xhci->hci_version);
5164 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5165 /* Set TT think time - convert from ns to FS bit times.
5166 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5167 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5169 * xHCI 1.0: this field shall be 0 if the device is not a
5172 think_time = tt->think_time;
5173 if (think_time != 0)
5174 think_time = (think_time / 666) - 1;
5175 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5176 slot_ctx->tt_info |=
5177 cpu_to_le32(TT_THINK_TIME(think_time));
5179 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5180 "TT think time or number of ports\n",
5181 (unsigned int) xhci->hci_version);
5183 slot_ctx->dev_state = 0;
5184 spin_unlock_irqrestore(&xhci->lock, flags);
5186 xhci_dbg(xhci, "Set up %s for hub device.\n",
5187 (xhci->hci_version > 0x95) ?
5188 "configure endpoint" : "evaluate context");
5190 /* Issue and wait for the configure endpoint or
5191 * evaluate context command.
5193 if (xhci->hci_version > 0x95)
5194 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5197 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5200 xhci_free_command(xhci, config_cmd);
5204 static int xhci_get_frame(struct usb_hcd *hcd)
5206 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5207 /* EHCI mods by the periodic size. Why? */
5208 return readl(&xhci->run_regs->microframe_index) >> 3;
5211 static void xhci_hcd_init_usb2_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5213 xhci->usb2_rhub.hcd = hcd;
5214 hcd->speed = HCD_USB2;
5215 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5217 * USB 2.0 roothub under xHCI has an integrated TT,
5218 * (rate matching hub) as opposed to having an OHCI/UHCI
5219 * companion controller.
5224 static void xhci_hcd_init_usb3_data(struct xhci_hcd *xhci, struct usb_hcd *hcd)
5226 unsigned int minor_rev;
5229 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5230 * should return 0x31 for sbrn, or that the minor revision
5231 * is a two digit BCD containig minor and sub-minor numbers.
5232 * This was later clarified in xHCI 1.2.
5234 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5235 * minor revision set to 0x1 instead of 0x10.
5237 if (xhci->usb3_rhub.min_rev == 0x1)
5240 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5242 switch (minor_rev) {
5244 hcd->speed = HCD_USB32;
5245 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5246 hcd->self.root_hub->rx_lanes = 2;
5247 hcd->self.root_hub->tx_lanes = 2;
5248 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x2;
5251 hcd->speed = HCD_USB31;
5252 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5253 hcd->self.root_hub->ssp_rate = USB_SSP_GEN_2x1;
5256 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5257 minor_rev, minor_rev ? "Enhanced " : "");
5259 xhci->usb3_rhub.hcd = hcd;
5262 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5264 struct xhci_hcd *xhci;
5266 * TODO: Check with DWC3 clients for sysdev according to
5269 struct device *dev = hcd->self.sysdev;
5272 /* Accept arbitrarily long scatter-gather lists */
5273 hcd->self.sg_tablesize = ~0;
5275 /* support to build packet from discontinuous buffers */
5276 hcd->self.no_sg_constraint = 1;
5278 /* XHCI controllers don't stop the ep queue on short packets :| */
5279 hcd->self.no_stop_on_short = 1;
5281 xhci = hcd_to_xhci(hcd);
5283 if (!usb_hcd_is_primary_hcd(hcd)) {
5284 xhci_hcd_init_usb3_data(xhci, hcd);
5288 mutex_init(&xhci->mutex);
5289 xhci->main_hcd = hcd;
5290 xhci->cap_regs = hcd->regs;
5291 xhci->op_regs = hcd->regs +
5292 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5293 xhci->run_regs = hcd->regs +
5294 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5295 /* Cache read-only capability registers */
5296 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5297 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5298 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5299 xhci->hci_version = HC_VERSION(readl(&xhci->cap_regs->hc_capbase));
5300 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5301 if (xhci->hci_version > 0x100)
5302 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5304 xhci->quirks |= quirks;
5306 get_quirks(dev, xhci);
5308 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5309 * success event after a short transfer. This quirk will ignore such
5312 if (xhci->hci_version > 0x96)
5313 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5315 /* Make sure the HC is halted. */
5316 retval = xhci_halt(xhci);
5320 xhci_zero_64b_regs(xhci);
5322 xhci_dbg(xhci, "Resetting HCD\n");
5323 /* Reset the internal HC memory state and registers. */
5324 retval = xhci_reset(xhci, XHCI_RESET_LONG_USEC);
5327 xhci_dbg(xhci, "Reset complete\n");
5330 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5331 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5332 * address memory pointers actually. So, this driver clears the AC64
5333 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5334 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5336 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5337 xhci->hcc_params &= ~BIT(0);
5339 /* Set dma_mask and coherent_dma_mask to 64-bits,
5340 * if xHC supports 64-bit addressing */
5341 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5342 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5343 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5344 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5347 * This is to avoid error in cases where a 32-bit USB
5348 * controller is used on a 64-bit capable system.
5350 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5353 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5354 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5357 xhci_dbg(xhci, "Calling HCD init\n");
5358 /* Initialize HCD and host controller data structures. */
5359 retval = xhci_init(hcd);
5362 xhci_dbg(xhci, "Called HCD init\n");
5364 if (xhci_hcd_is_usb3(hcd))
5365 xhci_hcd_init_usb3_data(xhci, hcd);
5367 xhci_hcd_init_usb2_data(xhci, hcd);
5369 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5370 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5374 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5376 static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5377 struct usb_host_endpoint *ep)
5379 struct xhci_hcd *xhci;
5380 struct usb_device *udev;
5381 unsigned int slot_id;
5382 unsigned int ep_index;
5383 unsigned long flags;
5385 xhci = hcd_to_xhci(hcd);
5387 spin_lock_irqsave(&xhci->lock, flags);
5388 udev = (struct usb_device *)ep->hcpriv;
5389 slot_id = udev->slot_id;
5390 ep_index = xhci_get_endpoint_index(&ep->desc);
5392 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5393 xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5394 spin_unlock_irqrestore(&xhci->lock, flags);
5397 static const struct hc_driver xhci_hc_driver = {
5398 .description = "xhci-hcd",
5399 .product_desc = "xHCI Host Controller",
5400 .hcd_priv_size = sizeof(struct xhci_hcd),
5403 * generic hardware linkage
5406 .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED |
5410 * basic lifecycle operations
5412 .reset = NULL, /* set in xhci_init_driver() */
5415 .shutdown = xhci_shutdown,
5418 * managing i/o requests and associated device resources
5420 .map_urb_for_dma = xhci_map_urb_for_dma,
5421 .unmap_urb_for_dma = xhci_unmap_urb_for_dma,
5422 .urb_enqueue = xhci_urb_enqueue,
5423 .urb_dequeue = xhci_urb_dequeue,
5424 .alloc_dev = xhci_alloc_dev,
5425 .free_dev = xhci_free_dev,
5426 .alloc_streams = xhci_alloc_streams,
5427 .free_streams = xhci_free_streams,
5428 .add_endpoint = xhci_add_endpoint,
5429 .drop_endpoint = xhci_drop_endpoint,
5430 .endpoint_disable = xhci_endpoint_disable,
5431 .endpoint_reset = xhci_endpoint_reset,
5432 .check_bandwidth = xhci_check_bandwidth,
5433 .reset_bandwidth = xhci_reset_bandwidth,
5434 .address_device = xhci_address_device,
5435 .enable_device = xhci_enable_device,
5436 .update_hub_device = xhci_update_hub_device,
5437 .reset_device = xhci_discover_or_reset_device,
5440 * scheduling support
5442 .get_frame_number = xhci_get_frame,
5447 .hub_control = xhci_hub_control,
5448 .hub_status_data = xhci_hub_status_data,
5449 .bus_suspend = xhci_bus_suspend,
5450 .bus_resume = xhci_bus_resume,
5451 .get_resuming_ports = xhci_get_resuming_ports,
5454 * call back when device connected and addressed
5456 .update_device = xhci_update_device,
5457 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5458 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5459 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5460 .find_raw_port_number = xhci_find_raw_port_number,
5461 .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5464 void xhci_init_driver(struct hc_driver *drv,
5465 const struct xhci_driver_overrides *over)
5469 /* Copy the generic table to drv then apply the overrides */
5470 *drv = xhci_hc_driver;
5473 drv->hcd_priv_size += over->extra_priv_size;
5475 drv->reset = over->reset;
5477 drv->start = over->start;
5478 if (over->add_endpoint)
5479 drv->add_endpoint = over->add_endpoint;
5480 if (over->drop_endpoint)
5481 drv->drop_endpoint = over->drop_endpoint;
5482 if (over->check_bandwidth)
5483 drv->check_bandwidth = over->check_bandwidth;
5484 if (over->reset_bandwidth)
5485 drv->reset_bandwidth = over->reset_bandwidth;
5488 EXPORT_SYMBOL_GPL(xhci_init_driver);
5490 MODULE_DESCRIPTION(DRIVER_DESC);
5491 MODULE_AUTHOR(DRIVER_AUTHOR);
5492 MODULE_LICENSE("GPL");
5494 static int __init xhci_hcd_init(void)
5497 * Check the compiler generated sizes of structures that must be laid
5498 * out in specific ways for hardware access.
5500 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5501 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5502 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5503 /* xhci_device_control has eight fields, and also
5504 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5506 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5507 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5508 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5509 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5510 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5511 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5512 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5517 xhci_debugfs_create_root();
5524 * If an init function is provided, an exit function must also be provided
5525 * to allow module unload.
5527 static void __exit xhci_hcd_fini(void)
5529 xhci_debugfs_remove_root();
5533 module_init(xhci_hcd_init);
5534 module_exit(xhci_hcd_fini);