1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/iopoll.h>
13 #include <linux/irq.h>
14 #include <linux/log2.h>
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/slab.h>
18 #include <linux/dmi.h>
19 #include <linux/dma-mapping.h>
22 #include "xhci-trace.h"
24 #include "xhci-debugfs.h"
25 #include "xhci-dbgcap.h"
27 #define DRIVER_AUTHOR "Sarah Sharp"
28 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
30 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
32 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
33 static int link_quirk;
34 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
35 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
37 static unsigned long long quirks;
38 module_param(quirks, ullong, S_IRUGO);
39 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
41 static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
43 struct xhci_segment *seg = ring->first_seg;
45 if (!td || !td->start_seg)
48 if (seg == td->start_seg)
51 } while (seg && seg != ring->first_seg);
57 * xhci_handshake - spin reading hc until handshake completes or fails
58 * @ptr: address of hc register to be read
59 * @mask: bits to look at in result of read
60 * @done: value of those bits when handshake succeeds
61 * @usec: timeout in microseconds
63 * Returns negative errno, or zero on success
65 * Success happens when the "mask" bits have the specified value (hardware
66 * handshake done). There are two failure modes: "usec" have passed (major
67 * hardware flakeout), or the register reads as all-ones (hardware removed).
69 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
74 ret = readl_poll_timeout_atomic(ptr, result,
75 (result & mask) == done ||
78 if (result == U32_MAX) /* card removed */
85 * Disable interrupts and begin the xHCI halting process.
87 void xhci_quiesce(struct xhci_hcd *xhci)
94 halted = readl(&xhci->op_regs->status) & STS_HALT;
98 cmd = readl(&xhci->op_regs->command);
100 writel(cmd, &xhci->op_regs->command);
104 * Force HC into halt state.
106 * Disable any IRQs and clear the run/stop bit.
107 * HC will complete any current and actively pipelined transactions, and
108 * should halt within 16 ms of the run/stop bit being cleared.
109 * Read HC Halted bit in the status register to see when the HC is finished.
111 int xhci_halt(struct xhci_hcd *xhci)
114 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
117 ret = xhci_handshake(&xhci->op_regs->status,
118 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
120 xhci_warn(xhci, "Host halt failed, %d\n", ret);
123 xhci->xhc_state |= XHCI_STATE_HALTED;
124 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
129 * Set the run bit and wait for the host to be running.
131 int xhci_start(struct xhci_hcd *xhci)
136 temp = readl(&xhci->op_regs->command);
138 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
140 writel(temp, &xhci->op_regs->command);
143 * Wait for the HCHalted Status bit to be 0 to indicate the host is
146 ret = xhci_handshake(&xhci->op_regs->status,
147 STS_HALT, 0, XHCI_MAX_HALT_USEC);
148 if (ret == -ETIMEDOUT)
149 xhci_err(xhci, "Host took too long to start, "
150 "waited %u microseconds.\n",
153 /* clear state flags. Including dying, halted or removing */
162 * This resets pipelines, timers, counters, state machines, etc.
163 * Transactions will be terminated immediately, and operational registers
164 * will be set to their defaults.
166 int xhci_reset(struct xhci_hcd *xhci)
172 state = readl(&xhci->op_regs->status);
174 if (state == ~(u32)0) {
175 xhci_warn(xhci, "Host not accessible, reset failed.\n");
179 if ((state & STS_HALT) == 0) {
180 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
184 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
185 command = readl(&xhci->op_regs->command);
186 command |= CMD_RESET;
187 writel(command, &xhci->op_regs->command);
189 /* Existing Intel xHCI controllers require a delay of 1 mS,
190 * after setting the CMD_RESET bit, and before accessing any
191 * HC registers. This allows the HC to complete the
192 * reset operation and be ready for HC register access.
193 * Without this delay, the subsequent HC register access,
194 * may result in a system hang very rarely.
196 if (xhci->quirks & XHCI_INTEL_HOST)
199 ret = xhci_handshake(&xhci->op_regs->command,
200 CMD_RESET, 0, 10 * 1000 * 1000);
204 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
205 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
207 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
208 "Wait for controller to be ready for doorbell rings");
210 * xHCI cannot write to any doorbells or operational registers other
211 * than status until the "Controller Not Ready" flag is cleared.
213 ret = xhci_handshake(&xhci->op_regs->status,
214 STS_CNR, 0, 10 * 1000 * 1000);
216 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
217 xhci->usb2_rhub.bus_state.suspended_ports = 0;
218 xhci->usb2_rhub.bus_state.resuming_ports = 0;
219 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
220 xhci->usb3_rhub.bus_state.suspended_ports = 0;
221 xhci->usb3_rhub.bus_state.resuming_ports = 0;
226 static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
228 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
233 * Some Renesas controllers get into a weird state if they are
234 * reset while programmed with 64bit addresses (they will preserve
235 * the top half of the address in internal, non visible
236 * registers). You end up with half the address coming from the
237 * kernel, and the other half coming from the firmware. Also,
238 * changing the programming leads to extra accesses even if the
239 * controller is supposed to be halted. The controller ends up with
240 * a fatal fault, and is then ripe for being properly reset.
242 * Special care is taken to only apply this if the device is behind
243 * an iommu. Doing anything when there is no iommu is definitely
246 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !device_iommu_mapped(dev))
249 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
251 /* Clear HSEIE so that faults do not get signaled */
252 val = readl(&xhci->op_regs->command);
254 writel(val, &xhci->op_regs->command);
256 /* Clear HSE (aka FATAL) */
257 val = readl(&xhci->op_regs->status);
259 writel(val, &xhci->op_regs->status);
261 /* Now zero the registers, and brace for impact */
262 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
263 if (upper_32_bits(val))
264 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
265 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
266 if (upper_32_bits(val))
267 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
269 for (i = 0; i < HCS_MAX_INTRS(xhci->hcs_params1); i++) {
270 struct xhci_intr_reg __iomem *ir;
272 ir = &xhci->run_regs->ir_set[i];
273 val = xhci_read_64(xhci, &ir->erst_base);
274 if (upper_32_bits(val))
275 xhci_write_64(xhci, 0, &ir->erst_base);
276 val= xhci_read_64(xhci, &ir->erst_dequeue);
277 if (upper_32_bits(val))
278 xhci_write_64(xhci, 0, &ir->erst_dequeue);
281 /* Wait for the fault to appear. It will be cleared on reset */
282 err = xhci_handshake(&xhci->op_regs->status,
283 STS_FATAL, STS_FATAL,
286 xhci_info(xhci, "Fault detected\n");
289 #ifdef CONFIG_USB_PCI
293 static int xhci_setup_msi(struct xhci_hcd *xhci)
297 * TODO:Check with MSI Soc for sysdev
299 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
301 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
303 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
304 "failed to allocate MSI entry");
308 ret = request_irq(pdev->irq, xhci_msi_irq,
309 0, "xhci_hcd", xhci_to_hcd(xhci));
311 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
312 "disable MSI interrupt");
313 pci_free_irq_vectors(pdev);
322 static int xhci_setup_msix(struct xhci_hcd *xhci)
325 struct usb_hcd *hcd = xhci_to_hcd(xhci);
326 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
329 * calculate number of msi-x vectors supported.
330 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
331 * with max number of interrupters based on the xhci HCSPARAMS1.
332 * - num_online_cpus: maximum msi-x vectors per CPUs core.
333 * Add additional 1 vector to ensure always available interrupt.
335 xhci->msix_count = min(num_online_cpus() + 1,
336 HCS_MAX_INTRS(xhci->hcs_params1));
338 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
341 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
342 "Failed to enable MSI-X");
346 for (i = 0; i < xhci->msix_count; i++) {
347 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
348 "xhci_hcd", xhci_to_hcd(xhci));
353 hcd->msix_enabled = 1;
357 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
359 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
360 pci_free_irq_vectors(pdev);
364 /* Free any IRQs and disable MSI-X */
365 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
367 struct usb_hcd *hcd = xhci_to_hcd(xhci);
368 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
370 if (xhci->quirks & XHCI_PLAT)
373 /* return if using legacy interrupt */
377 if (hcd->msix_enabled) {
380 for (i = 0; i < xhci->msix_count; i++)
381 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
383 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
386 pci_free_irq_vectors(pdev);
387 hcd->msix_enabled = 0;
390 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
392 struct usb_hcd *hcd = xhci_to_hcd(xhci);
394 if (hcd->msix_enabled) {
395 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
398 for (i = 0; i < xhci->msix_count; i++)
399 synchronize_irq(pci_irq_vector(pdev, i));
403 static int xhci_try_enable_msi(struct usb_hcd *hcd)
405 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
406 struct pci_dev *pdev;
409 /* The xhci platform device has set up IRQs through usb_add_hcd. */
410 if (xhci->quirks & XHCI_PLAT)
413 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
415 * Some Fresco Logic host controllers advertise MSI, but fail to
416 * generate interrupts. Don't even try to enable MSI.
418 if (xhci->quirks & XHCI_BROKEN_MSI)
421 /* unregister the legacy interrupt */
423 free_irq(hcd->irq, hcd);
426 ret = xhci_setup_msix(xhci);
428 /* fall back to msi*/
429 ret = xhci_setup_msi(xhci);
432 hcd->msi_enabled = 1;
437 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
442 if (!strlen(hcd->irq_descr))
443 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
444 hcd->driver->description, hcd->self.busnum);
446 /* fall back to legacy interrupt*/
447 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
448 hcd->irq_descr, hcd);
450 xhci_err(xhci, "request interrupt %d failed\n",
454 hcd->irq = pdev->irq;
460 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
465 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
469 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
475 static void compliance_mode_recovery(struct timer_list *t)
477 struct xhci_hcd *xhci;
479 struct xhci_hub *rhub;
483 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
484 rhub = &xhci->usb3_rhub;
486 for (i = 0; i < rhub->num_ports; i++) {
487 temp = readl(rhub->ports[i]->addr);
488 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
490 * Compliance Mode Detected. Letting USB Core
491 * handle the Warm Reset
493 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
494 "Compliance mode detected->port %d",
496 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
497 "Attempting compliance mode recovery");
498 hcd = xhci->shared_hcd;
500 if (hcd->state == HC_STATE_SUSPENDED)
501 usb_hcd_resume_root_hub(hcd);
503 usb_hcd_poll_rh_status(hcd);
507 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
508 mod_timer(&xhci->comp_mode_recovery_timer,
509 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
513 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
514 * that causes ports behind that hardware to enter compliance mode sometimes.
515 * The quirk creates a timer that polls every 2 seconds the link state of
516 * each host controller's port and recovers it by issuing a Warm reset
517 * if Compliance mode is detected, otherwise the port will become "dead" (no
518 * device connections or disconnections will be detected anymore). Becasue no
519 * status event is generated when entering compliance mode (per xhci spec),
520 * this quirk is needed on systems that have the failing hardware installed.
522 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
524 xhci->port_status_u0 = 0;
525 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
527 xhci->comp_mode_recovery_timer.expires = jiffies +
528 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
530 add_timer(&xhci->comp_mode_recovery_timer);
531 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
532 "Compliance mode recovery timer initialized");
536 * This function identifies the systems that have installed the SN65LVPE502CP
537 * USB3.0 re-driver and that need the Compliance Mode Quirk.
539 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
541 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
543 const char *dmi_product_name, *dmi_sys_vendor;
545 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
546 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
547 if (!dmi_product_name || !dmi_sys_vendor)
550 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
553 if (strstr(dmi_product_name, "Z420") ||
554 strstr(dmi_product_name, "Z620") ||
555 strstr(dmi_product_name, "Z820") ||
556 strstr(dmi_product_name, "Z1 Workstation"))
562 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
564 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
569 * Initialize memory for HCD and xHC (one-time init).
571 * Program the PAGESIZE register, initialize the device context array, create
572 * device contexts (?), set up a command ring segment (or two?), create event
573 * ring (one for now).
575 static int xhci_init(struct usb_hcd *hcd)
577 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
580 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
581 spin_lock_init(&xhci->lock);
582 if (xhci->hci_version == 0x95 && link_quirk) {
583 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
584 "QUIRK: Not clearing Link TRB chain bits.");
585 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
587 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
588 "xHCI doesn't need link TRB QUIRK");
590 retval = xhci_mem_init(xhci, GFP_KERNEL);
591 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
593 /* Initializing Compliance Mode Recovery Data If Needed */
594 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
595 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
596 compliance_mode_recovery_timer_init(xhci);
602 /*-------------------------------------------------------------------------*/
605 static int xhci_run_finished(struct xhci_hcd *xhci)
607 if (xhci_start(xhci)) {
611 xhci->shared_hcd->state = HC_STATE_RUNNING;
612 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
614 if (xhci->quirks & XHCI_NEC_HOST)
615 xhci_ring_cmd_db(xhci);
617 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
618 "Finished xhci_run for USB3 roothub");
623 * Start the HC after it was halted.
625 * This function is called by the USB core when the HC driver is added.
626 * Its opposite is xhci_stop().
628 * xhci_init() must be called once before this function can be called.
629 * Reset the HC, enable device slot contexts, program DCBAAP, and
630 * set command ring pointer and event ring pointer.
632 * Setup MSI-X vectors and enable interrupts.
634 int xhci_run(struct usb_hcd *hcd)
639 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
641 /* Start the xHCI host controller running only after the USB 2.0 roothub
645 hcd->uses_new_polling = 1;
646 if (!usb_hcd_is_primary_hcd(hcd))
647 return xhci_run_finished(xhci);
649 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
651 ret = xhci_try_enable_msi(hcd);
655 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
656 temp_64 &= ~ERST_PTR_MASK;
657 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
658 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
660 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
661 "// Set the interrupt modulation register");
662 temp = readl(&xhci->ir_set->irq_control);
663 temp &= ~ER_IRQ_INTERVAL_MASK;
664 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
665 writel(temp, &xhci->ir_set->irq_control);
667 /* Set the HCD state before we enable the irqs */
668 temp = readl(&xhci->op_regs->command);
670 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
671 "// Enable interrupts, cmd = 0x%x.", temp);
672 writel(temp, &xhci->op_regs->command);
674 temp = readl(&xhci->ir_set->irq_pending);
675 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
676 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
677 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
678 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
680 if (xhci->quirks & XHCI_NEC_HOST) {
681 struct xhci_command *command;
683 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
687 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
688 TRB_TYPE(TRB_NEC_GET_FW));
690 xhci_free_command(xhci, command);
692 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
693 "Finished xhci_run for USB2 roothub");
697 xhci_debugfs_init(xhci);
701 EXPORT_SYMBOL_GPL(xhci_run);
706 * This function is called by the USB core when the HC driver is removed.
707 * Its opposite is xhci_run().
709 * Disable device contexts, disable IRQs, and quiesce the HC.
710 * Reset the HC, finish any completed transactions, and cleanup memory.
712 static void xhci_stop(struct usb_hcd *hcd)
715 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
717 mutex_lock(&xhci->mutex);
719 /* Only halt host and free memory after both hcds are removed */
720 if (!usb_hcd_is_primary_hcd(hcd)) {
721 mutex_unlock(&xhci->mutex);
727 spin_lock_irq(&xhci->lock);
728 xhci->xhc_state |= XHCI_STATE_HALTED;
729 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
732 spin_unlock_irq(&xhci->lock);
734 xhci_cleanup_msix(xhci);
736 /* Deleting Compliance Mode Recovery Timer */
737 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
738 (!(xhci_all_ports_seen_u0(xhci)))) {
739 del_timer_sync(&xhci->comp_mode_recovery_timer);
740 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
741 "%s: compliance mode recovery timer deleted",
745 if (xhci->quirks & XHCI_AMD_PLL_FIX)
748 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
749 "// Disabling event ring interrupts");
750 temp = readl(&xhci->op_regs->status);
751 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
752 temp = readl(&xhci->ir_set->irq_pending);
753 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
755 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
756 xhci_mem_cleanup(xhci);
757 xhci_debugfs_exit(xhci);
758 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
759 "xhci_stop completed - status = %x",
760 readl(&xhci->op_regs->status));
761 mutex_unlock(&xhci->mutex);
765 * Shutdown HC (not bus-specific)
767 * This is called when the machine is rebooting or halting. We assume that the
768 * machine will be powered off, and the HC's internal state will be reset.
769 * Don't bother to free memory.
771 * This will only ever be called with the main usb_hcd (the USB3 roothub).
773 void xhci_shutdown(struct usb_hcd *hcd)
775 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
777 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
778 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
780 spin_lock_irq(&xhci->lock);
782 /* Workaround for spurious wakeups at shutdown with HSW */
783 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
785 spin_unlock_irq(&xhci->lock);
787 xhci_cleanup_msix(xhci);
789 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
790 "xhci_shutdown completed - status = %x",
791 readl(&xhci->op_regs->status));
793 EXPORT_SYMBOL_GPL(xhci_shutdown);
796 static void xhci_save_registers(struct xhci_hcd *xhci)
798 xhci->s3.command = readl(&xhci->op_regs->command);
799 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
800 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
801 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
802 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
803 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
804 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
805 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
806 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
809 static void xhci_restore_registers(struct xhci_hcd *xhci)
811 writel(xhci->s3.command, &xhci->op_regs->command);
812 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
813 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
814 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
815 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
816 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
817 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
818 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
819 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
822 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
826 /* step 2: initialize command ring buffer */
827 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
828 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
829 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
830 xhci->cmd_ring->dequeue) &
831 (u64) ~CMD_RING_RSVD_BITS) |
832 xhci->cmd_ring->cycle_state;
833 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
834 "// Setting command ring address to 0x%llx",
835 (long unsigned long) val_64);
836 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
840 * The whole command ring must be cleared to zero when we suspend the host.
842 * The host doesn't save the command ring pointer in the suspend well, so we
843 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
844 * aligned, because of the reserved bits in the command ring dequeue pointer
845 * register. Therefore, we can't just set the dequeue pointer back in the
846 * middle of the ring (TRBs are 16-byte aligned).
848 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
850 struct xhci_ring *ring;
851 struct xhci_segment *seg;
853 ring = xhci->cmd_ring;
857 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
858 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
859 cpu_to_le32(~TRB_CYCLE);
861 } while (seg != ring->deq_seg);
863 /* Reset the software enqueue and dequeue pointers */
864 ring->deq_seg = ring->first_seg;
865 ring->dequeue = ring->first_seg->trbs;
866 ring->enq_seg = ring->deq_seg;
867 ring->enqueue = ring->dequeue;
869 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
871 * Ring is now zeroed, so the HW should look for change of ownership
872 * when the cycle bit is set to 1.
874 ring->cycle_state = 1;
877 * Reset the hardware dequeue pointer.
878 * Yes, this will need to be re-written after resume, but we're paranoid
879 * and want to make sure the hardware doesn't access bogus memory
880 * because, say, the BIOS or an SMI started the host without changing
881 * the command ring pointers.
883 xhci_set_cmd_ring_deq(xhci);
886 static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
888 struct xhci_port **ports;
893 spin_lock_irqsave(&xhci->lock, flags);
895 /* disable usb3 ports Wake bits */
896 port_index = xhci->usb3_rhub.num_ports;
897 ports = xhci->usb3_rhub.ports;
898 while (port_index--) {
899 t1 = readl(ports[port_index]->addr);
901 t1 = xhci_port_state_to_neutral(t1);
902 t2 = t1 & ~PORT_WAKE_BITS;
904 writel(t2, ports[port_index]->addr);
905 xhci_dbg(xhci, "disable wake bits port %d-%d, portsc: 0x%x, write: 0x%x\n",
906 xhci->usb3_rhub.hcd->self.busnum,
907 port_index + 1, portsc, t2);
911 /* disable usb2 ports Wake bits */
912 port_index = xhci->usb2_rhub.num_ports;
913 ports = xhci->usb2_rhub.ports;
914 while (port_index--) {
915 t1 = readl(ports[port_index]->addr);
917 t1 = xhci_port_state_to_neutral(t1);
918 t2 = t1 & ~PORT_WAKE_BITS;
920 writel(t2, ports[port_index]->addr);
921 xhci_dbg(xhci, "disable wake bits port %d-%d, portsc: 0x%x, write: 0x%x\n",
922 xhci->usb2_rhub.hcd->self.busnum,
923 port_index + 1, portsc, t2);
926 spin_unlock_irqrestore(&xhci->lock, flags);
929 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
931 struct xhci_port **ports;
936 status = readl(&xhci->op_regs->status);
937 if (status & STS_EINT)
940 * Checking STS_EINT is not enough as there is a lag between a change
941 * bit being set and the Port Status Change Event that it generated
942 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
945 port_index = xhci->usb2_rhub.num_ports;
946 ports = xhci->usb2_rhub.ports;
947 while (port_index--) {
948 portsc = readl(ports[port_index]->addr);
949 if (portsc & PORT_CHANGE_MASK ||
950 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
953 port_index = xhci->usb3_rhub.num_ports;
954 ports = xhci->usb3_rhub.ports;
955 while (port_index--) {
956 portsc = readl(ports[port_index]->addr);
957 if (portsc & PORT_CHANGE_MASK ||
958 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
965 * Stop HC (not bus-specific)
967 * This is called when the machine transition into S3/S4 mode.
970 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
973 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
974 struct usb_hcd *hcd = xhci_to_hcd(xhci);
981 if (hcd->state != HC_STATE_SUSPENDED ||
982 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
985 /* Clear root port wake on bits if wakeup not allowed. */
987 xhci_disable_port_wake_on_bits(xhci);
989 if (!HCD_HW_ACCESSIBLE(hcd))
992 xhci_dbc_suspend(xhci);
994 /* Don't poll the roothubs on bus suspend. */
995 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
996 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
997 del_timer_sync(&hcd->rh_timer);
998 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
999 del_timer_sync(&xhci->shared_hcd->rh_timer);
1001 if (xhci->quirks & XHCI_SUSPEND_DELAY)
1002 usleep_range(1000, 1500);
1004 spin_lock_irq(&xhci->lock);
1005 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1006 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1007 /* step 1: stop endpoint */
1008 /* skipped assuming that port suspend has done */
1010 /* step 2: clear Run/Stop bit */
1011 command = readl(&xhci->op_regs->command);
1012 command &= ~CMD_RUN;
1013 writel(command, &xhci->op_regs->command);
1015 /* Some chips from Fresco Logic need an extraordinary delay */
1016 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
1018 if (xhci_handshake(&xhci->op_regs->status,
1019 STS_HALT, STS_HALT, delay)) {
1020 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
1021 spin_unlock_irq(&xhci->lock);
1024 xhci_clear_command_ring(xhci);
1026 /* step 3: save registers */
1027 xhci_save_registers(xhci);
1029 /* step 4: set CSS flag */
1030 command = readl(&xhci->op_regs->command);
1032 writel(command, &xhci->op_regs->command);
1033 xhci->broken_suspend = 0;
1034 if (xhci_handshake(&xhci->op_regs->status,
1035 STS_SAVE, 0, 20 * 1000)) {
1037 * AMD SNPS xHC 3.0 occasionally does not clear the
1038 * SSS bit of USBSTS and when driver tries to poll
1039 * to see if the xHC clears BIT(8) which never happens
1040 * and driver assumes that controller is not responding
1041 * and times out. To workaround this, its good to check
1042 * if SRE and HCE bits are not set (as per xhci
1043 * Section 5.4.2) and bypass the timeout.
1045 res = readl(&xhci->op_regs->status);
1046 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
1047 (((res & STS_SRE) == 0) &&
1048 ((res & STS_HCE) == 0))) {
1049 xhci->broken_suspend = 1;
1051 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1052 spin_unlock_irq(&xhci->lock);
1056 spin_unlock_irq(&xhci->lock);
1059 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1060 * is about to be suspended.
1062 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1063 (!(xhci_all_ports_seen_u0(xhci)))) {
1064 del_timer_sync(&xhci->comp_mode_recovery_timer);
1065 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1066 "%s: compliance mode recovery timer deleted",
1070 /* step 5: remove core well power */
1071 /* synchronize irq when using MSI-X */
1072 xhci_msix_sync_irqs(xhci);
1076 EXPORT_SYMBOL_GPL(xhci_suspend);
1079 * start xHC (not bus-specific)
1081 * This is called when the machine transition from S3/S4 mode.
1084 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1086 u32 command, temp = 0;
1087 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1088 struct usb_hcd *secondary_hcd;
1090 bool comp_timer_running = false;
1095 /* Wait a bit if either of the roothubs need to settle from the
1096 * transition into bus suspend.
1099 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1100 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1103 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1104 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1106 spin_lock_irq(&xhci->lock);
1107 if ((xhci->quirks & XHCI_RESET_ON_RESUME) || xhci->broken_suspend)
1112 * Some controllers might lose power during suspend, so wait
1113 * for controller not ready bit to clear, just as in xHC init.
1115 retval = xhci_handshake(&xhci->op_regs->status,
1116 STS_CNR, 0, 10 * 1000 * 1000);
1118 xhci_warn(xhci, "Controller not ready at resume %d\n",
1120 spin_unlock_irq(&xhci->lock);
1123 /* step 1: restore register */
1124 xhci_restore_registers(xhci);
1125 /* step 2: initialize command ring buffer */
1126 xhci_set_cmd_ring_deq(xhci);
1127 /* step 3: restore state and start state*/
1128 /* step 3: set CRS flag */
1129 command = readl(&xhci->op_regs->command);
1131 writel(command, &xhci->op_regs->command);
1133 * Some controllers take up to 55+ ms to complete the controller
1134 * restore so setting the timeout to 100ms. Xhci specification
1135 * doesn't mention any timeout value.
1137 if (xhci_handshake(&xhci->op_regs->status,
1138 STS_RESTORE, 0, 100 * 1000)) {
1139 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1140 spin_unlock_irq(&xhci->lock);
1143 temp = readl(&xhci->op_regs->status);
1146 /* If restore operation fails, re-initialize the HC during resume */
1147 if ((temp & STS_SRE) || hibernated) {
1149 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1150 !(xhci_all_ports_seen_u0(xhci))) {
1151 del_timer_sync(&xhci->comp_mode_recovery_timer);
1152 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1153 "Compliance Mode Recovery Timer deleted!");
1156 /* Let the USB core know _both_ roothubs lost power. */
1157 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1158 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1160 xhci_dbg(xhci, "Stop HCD\n");
1162 xhci_zero_64b_regs(xhci);
1163 retval = xhci_reset(xhci);
1164 spin_unlock_irq(&xhci->lock);
1167 xhci_cleanup_msix(xhci);
1169 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1170 temp = readl(&xhci->op_regs->status);
1171 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1172 temp = readl(&xhci->ir_set->irq_pending);
1173 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1175 xhci_dbg(xhci, "cleaning up memory\n");
1176 xhci_mem_cleanup(xhci);
1177 xhci_debugfs_exit(xhci);
1178 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1179 readl(&xhci->op_regs->status));
1181 /* USB core calls the PCI reinit and start functions twice:
1182 * first with the primary HCD, and then with the secondary HCD.
1183 * If we don't do the same, the host will never be started.
1185 if (!usb_hcd_is_primary_hcd(hcd))
1186 secondary_hcd = hcd;
1188 secondary_hcd = xhci->shared_hcd;
1190 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1191 retval = xhci_init(hcd->primary_hcd);
1194 comp_timer_running = true;
1196 xhci_dbg(xhci, "Start the primary HCD\n");
1197 retval = xhci_run(hcd->primary_hcd);
1199 xhci_dbg(xhci, "Start the secondary HCD\n");
1200 retval = xhci_run(secondary_hcd);
1202 hcd->state = HC_STATE_SUSPENDED;
1203 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1207 /* step 4: set Run/Stop bit */
1208 command = readl(&xhci->op_regs->command);
1210 writel(command, &xhci->op_regs->command);
1211 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1214 /* step 5: walk topology and initialize portsc,
1215 * portpmsc and portli
1217 /* this is done in bus_resume */
1219 /* step 6: restart each of the previously
1220 * Running endpoints by ringing their doorbells
1223 spin_unlock_irq(&xhci->lock);
1225 xhci_dbc_resume(xhci);
1229 /* Resume root hubs only when have pending events. */
1230 if (xhci_pending_portevent(xhci)) {
1231 usb_hcd_resume_root_hub(xhci->shared_hcd);
1232 usb_hcd_resume_root_hub(hcd);
1237 * If system is subject to the Quirk, Compliance Mode Timer needs to
1238 * be re-initialized Always after a system resume. Ports are subject
1239 * to suffer the Compliance Mode issue again. It doesn't matter if
1240 * ports have entered previously to U0 before system's suspension.
1242 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1243 compliance_mode_recovery_timer_init(xhci);
1245 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1246 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1248 /* Re-enable port polling. */
1249 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1250 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1251 usb_hcd_poll_rh_status(xhci->shared_hcd);
1252 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1253 usb_hcd_poll_rh_status(hcd);
1257 EXPORT_SYMBOL_GPL(xhci_resume);
1258 #endif /* CONFIG_PM */
1260 /*-------------------------------------------------------------------------*/
1262 static int xhci_map_temp_buffer(struct usb_hcd *hcd, struct urb *urb)
1266 unsigned int buf_len;
1267 enum dma_data_direction dir;
1269 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1270 buf_len = urb->transfer_buffer_length;
1272 temp = kzalloc_node(buf_len, GFP_ATOMIC,
1273 dev_to_node(hcd->self.sysdev));
1275 if (usb_urb_dir_out(urb))
1276 sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
1279 urb->transfer_buffer = temp;
1280 urb->transfer_dma = dma_map_single(hcd->self.sysdev,
1281 urb->transfer_buffer,
1282 urb->transfer_buffer_length,
1285 if (dma_mapping_error(hcd->self.sysdev,
1286 urb->transfer_dma)) {
1290 urb->transfer_flags |= URB_DMA_MAP_SINGLE;
1296 static bool xhci_urb_temp_buffer_required(struct usb_hcd *hcd,
1301 unsigned int len = 0;
1302 unsigned int trb_size;
1303 unsigned int max_pkt;
1304 struct scatterlist *sg;
1305 struct scatterlist *tail_sg;
1308 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
1313 if (urb->dev->speed >= USB_SPEED_SUPER)
1314 trb_size = TRB_CACHE_SIZE_SS;
1316 trb_size = TRB_CACHE_SIZE_HS;
1318 if (urb->transfer_buffer_length != 0 &&
1319 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)) {
1320 for_each_sg(urb->sg, sg, urb->num_sgs, i) {
1321 len = len + sg->length;
1322 if (i > trb_size - 2) {
1323 len = len - tail_sg->length;
1324 if (len < max_pkt) {
1329 tail_sg = sg_next(tail_sg);
1336 static void xhci_unmap_temp_buf(struct usb_hcd *hcd, struct urb *urb)
1339 unsigned int buf_len;
1340 enum dma_data_direction dir;
1342 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1344 buf_len = urb->transfer_buffer_length;
1346 if (IS_ENABLED(CONFIG_HAS_DMA) &&
1347 (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1348 dma_unmap_single(hcd->self.sysdev,
1350 urb->transfer_buffer_length,
1353 if (usb_urb_dir_in(urb))
1354 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs,
1355 urb->transfer_buffer,
1359 urb->transfer_flags &= ~URB_DMA_MAP_SINGLE;
1360 kfree(urb->transfer_buffer);
1361 urb->transfer_buffer = NULL;
1365 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1366 * we'll copy the actual data into the TRB address register. This is limited to
1367 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1368 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1370 static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1373 struct xhci_hcd *xhci;
1375 xhci = hcd_to_xhci(hcd);
1377 if (xhci_urb_suitable_for_idt(urb))
1380 if (xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) {
1381 if (xhci_urb_temp_buffer_required(hcd, urb))
1382 return xhci_map_temp_buffer(hcd, urb);
1384 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1387 static void xhci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
1389 struct xhci_hcd *xhci;
1390 bool unmap_temp_buf = false;
1392 xhci = hcd_to_xhci(hcd);
1394 if (urb->num_sgs && (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1395 unmap_temp_buf = true;
1397 if ((xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) && unmap_temp_buf)
1398 xhci_unmap_temp_buf(hcd, urb);
1400 usb_hcd_unmap_urb_for_dma(hcd, urb);
1404 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1405 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1406 * value to right shift 1 for the bitmask.
1408 * Index = (epnum * 2) + direction - 1,
1409 * where direction = 0 for OUT, 1 for IN.
1410 * For control endpoints, the IN index is used (OUT index is unused), so
1411 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1413 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1416 if (usb_endpoint_xfer_control(desc))
1417 index = (unsigned int) (usb_endpoint_num(desc)*2);
1419 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1420 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1424 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1425 * address from the XHCI endpoint index.
1427 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1429 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1430 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1431 return direction | number;
1434 /* Find the flag for this endpoint (for use in the control context). Use the
1435 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1438 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1440 return 1 << (xhci_get_endpoint_index(desc) + 1);
1443 /* Find the flag for this endpoint (for use in the control context). Use the
1444 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1447 static unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1449 return 1 << (ep_index + 1);
1452 /* Compute the last valid endpoint context index. Basically, this is the
1453 * endpoint index plus one. For slot contexts with more than valid endpoint,
1454 * we find the most significant bit set in the added contexts flags.
1455 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1456 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1458 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1460 return fls(added_ctxs) - 1;
1463 /* Returns 1 if the arguments are OK;
1464 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1466 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1467 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1469 struct xhci_hcd *xhci;
1470 struct xhci_virt_device *virt_dev;
1472 if (!hcd || (check_ep && !ep) || !udev) {
1473 pr_debug("xHCI %s called with invalid args\n", func);
1476 if (!udev->parent) {
1477 pr_debug("xHCI %s called for root hub\n", func);
1481 xhci = hcd_to_xhci(hcd);
1482 if (check_virt_dev) {
1483 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1484 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1489 virt_dev = xhci->devs[udev->slot_id];
1490 if (virt_dev->udev != udev) {
1491 xhci_dbg(xhci, "xHCI %s called with udev and "
1492 "virt_dev does not match\n", func);
1497 if (xhci->xhc_state & XHCI_STATE_HALTED)
1503 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1504 struct usb_device *udev, struct xhci_command *command,
1505 bool ctx_change, bool must_succeed);
1508 * Full speed devices may have a max packet size greater than 8 bytes, but the
1509 * USB core doesn't know that until it reads the first 8 bytes of the
1510 * descriptor. If the usb_device's max packet size changes after that point,
1511 * we need to issue an evaluate context command and wait on it.
1513 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1514 unsigned int ep_index, struct urb *urb)
1516 struct xhci_container_ctx *out_ctx;
1517 struct xhci_input_control_ctx *ctrl_ctx;
1518 struct xhci_ep_ctx *ep_ctx;
1519 struct xhci_command *command;
1520 int max_packet_size;
1521 int hw_max_packet_size;
1524 out_ctx = xhci->devs[slot_id]->out_ctx;
1525 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1526 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1527 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1528 if (hw_max_packet_size != max_packet_size) {
1529 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1530 "Max Packet Size for ep 0 changed.");
1531 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1532 "Max packet size in usb_device = %d",
1534 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1535 "Max packet size in xHCI HW = %d",
1536 hw_max_packet_size);
1537 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1538 "Issuing evaluate context command.");
1540 /* Set up the input context flags for the command */
1541 /* FIXME: This won't work if a non-default control endpoint
1542 * changes max packet sizes.
1545 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
1549 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1550 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1552 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1555 goto command_cleanup;
1557 /* Set up the modified control endpoint 0 */
1558 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1559 xhci->devs[slot_id]->out_ctx, ep_index);
1561 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1562 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1563 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1564 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1566 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1567 ctrl_ctx->drop_flags = 0;
1569 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1572 /* Clean up the input context for later use by bandwidth
1575 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1577 kfree(command->completion);
1584 * non-error returns are a promise to giveback() the urb later
1585 * we drop ownership so next owner (or urb unlink) can get it
1587 static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1589 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1590 unsigned long flags;
1592 unsigned int slot_id, ep_index;
1593 unsigned int *ep_state;
1594 struct urb_priv *urb_priv;
1597 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1598 true, true, __func__) <= 0)
1601 slot_id = urb->dev->slot_id;
1602 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1603 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1605 if (!HCD_HW_ACCESSIBLE(hcd))
1608 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1609 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1613 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1614 num_tds = urb->number_of_packets;
1615 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1616 urb->transfer_buffer_length > 0 &&
1617 urb->transfer_flags & URB_ZERO_PACKET &&
1618 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1623 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1627 urb_priv->num_tds = num_tds;
1628 urb_priv->num_tds_done = 0;
1629 urb->hcpriv = urb_priv;
1631 trace_xhci_urb_enqueue(urb);
1633 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1634 /* Check to see if the max packet size for the default control
1635 * endpoint changed during FS device enumeration
1637 if (urb->dev->speed == USB_SPEED_FULL) {
1638 ret = xhci_check_maxpacket(xhci, slot_id,
1641 xhci_urb_free_priv(urb_priv);
1648 spin_lock_irqsave(&xhci->lock, flags);
1650 if (xhci->xhc_state & XHCI_STATE_DYING) {
1651 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1652 urb->ep->desc.bEndpointAddress, urb);
1656 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1657 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1662 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1663 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1668 switch (usb_endpoint_type(&urb->ep->desc)) {
1670 case USB_ENDPOINT_XFER_CONTROL:
1671 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1674 case USB_ENDPOINT_XFER_BULK:
1675 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1678 case USB_ENDPOINT_XFER_INT:
1679 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1682 case USB_ENDPOINT_XFER_ISOC:
1683 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1689 xhci_urb_free_priv(urb_priv);
1692 spin_unlock_irqrestore(&xhci->lock, flags);
1697 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1698 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1699 * should pick up where it left off in the TD, unless a Set Transfer Ring
1700 * Dequeue Pointer is issued.
1702 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1703 * the ring. Since the ring is a contiguous structure, they can't be physically
1704 * removed. Instead, there are two options:
1706 * 1) If the HC is in the middle of processing the URB to be canceled, we
1707 * simply move the ring's dequeue pointer past those TRBs using the Set
1708 * Transfer Ring Dequeue Pointer command. This will be the common case,
1709 * when drivers timeout on the last submitted URB and attempt to cancel.
1711 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1712 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1713 * HC will need to invalidate the any TRBs it has cached after the stop
1714 * endpoint command, as noted in the xHCI 0.95 errata.
1716 * 3) The TD may have completed by the time the Stop Endpoint Command
1717 * completes, so software needs to handle that case too.
1719 * This function should protect against the TD enqueueing code ringing the
1720 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1721 * It also needs to account for multiple cancellations on happening at the same
1722 * time for the same endpoint.
1724 * Note that this function can be called in any context, or so says
1725 * usb_hcd_unlink_urb()
1727 static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1729 unsigned long flags;
1732 struct xhci_hcd *xhci;
1733 struct urb_priv *urb_priv;
1735 unsigned int ep_index;
1736 struct xhci_ring *ep_ring;
1737 struct xhci_virt_ep *ep;
1738 struct xhci_command *command;
1739 struct xhci_virt_device *vdev;
1741 xhci = hcd_to_xhci(hcd);
1742 spin_lock_irqsave(&xhci->lock, flags);
1744 trace_xhci_urb_dequeue(urb);
1746 /* Make sure the URB hasn't completed or been unlinked already */
1747 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1751 /* give back URB now if we can't queue it for cancel */
1752 vdev = xhci->devs[urb->dev->slot_id];
1753 urb_priv = urb->hcpriv;
1754 if (!vdev || !urb_priv)
1757 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1758 ep = &vdev->eps[ep_index];
1759 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1760 if (!ep || !ep_ring)
1763 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1764 temp = readl(&xhci->op_regs->status);
1765 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1771 * check ring is not re-allocated since URB was enqueued. If it is, then
1772 * make sure none of the ring related pointers in this URB private data
1773 * are touched, such as td_list, otherwise we overwrite freed data
1775 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1776 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1777 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1778 td = &urb_priv->td[i];
1779 if (!list_empty(&td->cancelled_td_list))
1780 list_del_init(&td->cancelled_td_list);
1785 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1786 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1787 "HC halted, freeing TD manually.");
1788 for (i = urb_priv->num_tds_done;
1789 i < urb_priv->num_tds;
1791 td = &urb_priv->td[i];
1792 if (!list_empty(&td->td_list))
1793 list_del_init(&td->td_list);
1794 if (!list_empty(&td->cancelled_td_list))
1795 list_del_init(&td->cancelled_td_list);
1800 i = urb_priv->num_tds_done;
1801 if (i < urb_priv->num_tds)
1802 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1803 "Cancel URB %p, dev %s, ep 0x%x, "
1804 "starting at offset 0x%llx",
1805 urb, urb->dev->devpath,
1806 urb->ep->desc.bEndpointAddress,
1807 (unsigned long long) xhci_trb_virt_to_dma(
1808 urb_priv->td[i].start_seg,
1809 urb_priv->td[i].first_trb));
1811 for (; i < urb_priv->num_tds; i++) {
1812 td = &urb_priv->td[i];
1813 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1816 /* Queue a stop endpoint command, but only if this is
1817 * the first cancellation to be handled.
1819 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1820 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1825 ep->ep_state |= EP_STOP_CMD_PENDING;
1826 ep->stop_cmd_timer.expires = jiffies +
1827 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1828 add_timer(&ep->stop_cmd_timer);
1829 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1831 xhci_ring_cmd_db(xhci);
1834 spin_unlock_irqrestore(&xhci->lock, flags);
1839 xhci_urb_free_priv(urb_priv);
1840 usb_hcd_unlink_urb_from_ep(hcd, urb);
1841 spin_unlock_irqrestore(&xhci->lock, flags);
1842 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1846 /* Drop an endpoint from a new bandwidth configuration for this device.
1847 * Only one call to this function is allowed per endpoint before
1848 * check_bandwidth() or reset_bandwidth() must be called.
1849 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1850 * add the endpoint to the schedule with possibly new parameters denoted by a
1851 * different endpoint descriptor in usb_host_endpoint.
1852 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1855 * The USB core will not allow URBs to be queued to an endpoint that is being
1856 * disabled, so there's no need for mutual exclusion to protect
1857 * the xhci->devs[slot_id] structure.
1859 static int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1860 struct usb_host_endpoint *ep)
1862 struct xhci_hcd *xhci;
1863 struct xhci_container_ctx *in_ctx, *out_ctx;
1864 struct xhci_input_control_ctx *ctrl_ctx;
1865 unsigned int ep_index;
1866 struct xhci_ep_ctx *ep_ctx;
1868 u32 new_add_flags, new_drop_flags;
1871 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1874 xhci = hcd_to_xhci(hcd);
1875 if (xhci->xhc_state & XHCI_STATE_DYING)
1878 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1879 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1880 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1881 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1882 __func__, drop_flag);
1886 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1887 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1888 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1890 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1895 ep_index = xhci_get_endpoint_index(&ep->desc);
1896 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1897 /* If the HC already knows the endpoint is disabled,
1898 * or the HCD has noted it is disabled, ignore this request
1900 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1901 le32_to_cpu(ctrl_ctx->drop_flags) &
1902 xhci_get_endpoint_flag(&ep->desc)) {
1903 /* Do not warn when called after a usb_device_reset */
1904 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1905 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1910 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1911 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1913 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1914 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1916 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1918 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1920 if (xhci->quirks & XHCI_MTK_HOST)
1921 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1923 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1924 (unsigned int) ep->desc.bEndpointAddress,
1926 (unsigned int) new_drop_flags,
1927 (unsigned int) new_add_flags);
1931 /* Add an endpoint to a new possible bandwidth configuration for this device.
1932 * Only one call to this function is allowed per endpoint before
1933 * check_bandwidth() or reset_bandwidth() must be called.
1934 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1935 * add the endpoint to the schedule with possibly new parameters denoted by a
1936 * different endpoint descriptor in usb_host_endpoint.
1937 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1940 * The USB core will not allow URBs to be queued to an endpoint until the
1941 * configuration or alt setting is installed in the device, so there's no need
1942 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1944 static int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1945 struct usb_host_endpoint *ep)
1947 struct xhci_hcd *xhci;
1948 struct xhci_container_ctx *in_ctx;
1949 unsigned int ep_index;
1950 struct xhci_input_control_ctx *ctrl_ctx;
1951 struct xhci_ep_ctx *ep_ctx;
1953 u32 new_add_flags, new_drop_flags;
1954 struct xhci_virt_device *virt_dev;
1957 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1959 /* So we won't queue a reset ep command for a root hub */
1963 xhci = hcd_to_xhci(hcd);
1964 if (xhci->xhc_state & XHCI_STATE_DYING)
1967 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1968 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1969 /* FIXME when we have to issue an evaluate endpoint command to
1970 * deal with ep0 max packet size changing once we get the
1973 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1974 __func__, added_ctxs);
1978 virt_dev = xhci->devs[udev->slot_id];
1979 in_ctx = virt_dev->in_ctx;
1980 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1982 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1987 ep_index = xhci_get_endpoint_index(&ep->desc);
1988 /* If this endpoint is already in use, and the upper layers are trying
1989 * to add it again without dropping it, reject the addition.
1991 if (virt_dev->eps[ep_index].ring &&
1992 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1993 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1994 "without dropping it.\n",
1995 (unsigned int) ep->desc.bEndpointAddress);
1999 /* If the HCD has already noted the endpoint is enabled,
2000 * ignore this request.
2002 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
2003 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
2009 * Configuration and alternate setting changes must be done in
2010 * process context, not interrupt context (or so documenation
2011 * for usb_set_interface() and usb_set_configuration() claim).
2013 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
2014 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
2015 __func__, ep->desc.bEndpointAddress);
2019 if (xhci->quirks & XHCI_MTK_HOST) {
2020 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
2022 xhci_ring_free(xhci, virt_dev->eps[ep_index].new_ring);
2023 virt_dev->eps[ep_index].new_ring = NULL;
2028 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
2029 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
2031 /* If xhci_endpoint_disable() was called for this endpoint, but the
2032 * xHC hasn't been notified yet through the check_bandwidth() call,
2033 * this re-adds a new state for the endpoint from the new endpoint
2034 * descriptors. We must drop and re-add this endpoint, so we leave the
2037 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
2039 /* Store the usb_device pointer for later use */
2042 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
2043 trace_xhci_add_endpoint(ep_ctx);
2045 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
2046 (unsigned int) ep->desc.bEndpointAddress,
2048 (unsigned int) new_drop_flags,
2049 (unsigned int) new_add_flags);
2053 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
2055 struct xhci_input_control_ctx *ctrl_ctx;
2056 struct xhci_ep_ctx *ep_ctx;
2057 struct xhci_slot_ctx *slot_ctx;
2060 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
2062 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2067 /* When a device's add flag and drop flag are zero, any subsequent
2068 * configure endpoint command will leave that endpoint's state
2069 * untouched. Make sure we don't leave any old state in the input
2070 * endpoint contexts.
2072 ctrl_ctx->drop_flags = 0;
2073 ctrl_ctx->add_flags = 0;
2074 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2075 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2076 /* Endpoint 0 is always valid */
2077 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
2078 for (i = 1; i < 31; i++) {
2079 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
2080 ep_ctx->ep_info = 0;
2081 ep_ctx->ep_info2 = 0;
2083 ep_ctx->tx_info = 0;
2087 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
2088 struct usb_device *udev, u32 *cmd_status)
2092 switch (*cmd_status) {
2093 case COMP_COMMAND_ABORTED:
2094 case COMP_COMMAND_RING_STOPPED:
2095 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
2098 case COMP_RESOURCE_ERROR:
2099 dev_warn(&udev->dev,
2100 "Not enough host controller resources for new device state.\n");
2102 /* FIXME: can we allocate more resources for the HC? */
2104 case COMP_BANDWIDTH_ERROR:
2105 case COMP_SECONDARY_BANDWIDTH_ERROR:
2106 dev_warn(&udev->dev,
2107 "Not enough bandwidth for new device state.\n");
2109 /* FIXME: can we go back to the old state? */
2111 case COMP_TRB_ERROR:
2112 /* the HCD set up something wrong */
2113 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
2115 "and endpoint is not disabled.\n");
2118 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2119 dev_warn(&udev->dev,
2120 "ERROR: Incompatible device for endpoint configure command.\n");
2124 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2125 "Successful Endpoint Configure command");
2129 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2137 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2138 struct usb_device *udev, u32 *cmd_status)
2142 switch (*cmd_status) {
2143 case COMP_COMMAND_ABORTED:
2144 case COMP_COMMAND_RING_STOPPED:
2145 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2148 case COMP_PARAMETER_ERROR:
2149 dev_warn(&udev->dev,
2150 "WARN: xHCI driver setup invalid evaluate context command.\n");
2153 case COMP_SLOT_NOT_ENABLED_ERROR:
2154 dev_warn(&udev->dev,
2155 "WARN: slot not enabled for evaluate context command.\n");
2158 case COMP_CONTEXT_STATE_ERROR:
2159 dev_warn(&udev->dev,
2160 "WARN: invalid context state for evaluate context command.\n");
2163 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2164 dev_warn(&udev->dev,
2165 "ERROR: Incompatible device for evaluate context command.\n");
2168 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2169 /* Max Exit Latency too large error */
2170 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2174 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2175 "Successful evaluate context command");
2179 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2187 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2188 struct xhci_input_control_ctx *ctrl_ctx)
2190 u32 valid_add_flags;
2191 u32 valid_drop_flags;
2193 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2194 * (bit 1). The default control endpoint is added during the Address
2195 * Device command and is never removed until the slot is disabled.
2197 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2198 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2200 /* Use hweight32 to count the number of ones in the add flags, or
2201 * number of endpoints added. Don't count endpoints that are changed
2202 * (both added and dropped).
2204 return hweight32(valid_add_flags) -
2205 hweight32(valid_add_flags & valid_drop_flags);
2208 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2209 struct xhci_input_control_ctx *ctrl_ctx)
2211 u32 valid_add_flags;
2212 u32 valid_drop_flags;
2214 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2215 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2217 return hweight32(valid_drop_flags) -
2218 hweight32(valid_add_flags & valid_drop_flags);
2222 * We need to reserve the new number of endpoints before the configure endpoint
2223 * command completes. We can't subtract the dropped endpoints from the number
2224 * of active endpoints until the command completes because we can oversubscribe
2225 * the host in this case:
2227 * - the first configure endpoint command drops more endpoints than it adds
2228 * - a second configure endpoint command that adds more endpoints is queued
2229 * - the first configure endpoint command fails, so the config is unchanged
2230 * - the second command may succeed, even though there isn't enough resources
2232 * Must be called with xhci->lock held.
2234 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2235 struct xhci_input_control_ctx *ctrl_ctx)
2239 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2240 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2241 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2242 "Not enough ep ctxs: "
2243 "%u active, need to add %u, limit is %u.",
2244 xhci->num_active_eps, added_eps,
2245 xhci->limit_active_eps);
2248 xhci->num_active_eps += added_eps;
2249 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2250 "Adding %u ep ctxs, %u now active.", added_eps,
2251 xhci->num_active_eps);
2256 * The configure endpoint was failed by the xHC for some other reason, so we
2257 * need to revert the resources that failed configuration would have used.
2259 * Must be called with xhci->lock held.
2261 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2262 struct xhci_input_control_ctx *ctrl_ctx)
2266 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2267 xhci->num_active_eps -= num_failed_eps;
2268 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2269 "Removing %u failed ep ctxs, %u now active.",
2271 xhci->num_active_eps);
2275 * Now that the command has completed, clean up the active endpoint count by
2276 * subtracting out the endpoints that were dropped (but not changed).
2278 * Must be called with xhci->lock held.
2280 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2281 struct xhci_input_control_ctx *ctrl_ctx)
2283 u32 num_dropped_eps;
2285 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2286 xhci->num_active_eps -= num_dropped_eps;
2287 if (num_dropped_eps)
2288 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2289 "Removing %u dropped ep ctxs, %u now active.",
2291 xhci->num_active_eps);
2294 static unsigned int xhci_get_block_size(struct usb_device *udev)
2296 switch (udev->speed) {
2298 case USB_SPEED_FULL:
2300 case USB_SPEED_HIGH:
2302 case USB_SPEED_SUPER:
2303 case USB_SPEED_SUPER_PLUS:
2305 case USB_SPEED_UNKNOWN:
2306 case USB_SPEED_WIRELESS:
2308 /* Should never happen */
2314 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2316 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2318 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2323 /* If we are changing a LS/FS device under a HS hub,
2324 * make sure (if we are activating a new TT) that the HS bus has enough
2325 * bandwidth for this new TT.
2327 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2328 struct xhci_virt_device *virt_dev,
2331 struct xhci_interval_bw_table *bw_table;
2332 struct xhci_tt_bw_info *tt_info;
2334 /* Find the bandwidth table for the root port this TT is attached to. */
2335 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2336 tt_info = virt_dev->tt_info;
2337 /* If this TT already had active endpoints, the bandwidth for this TT
2338 * has already been added. Removing all periodic endpoints (and thus
2339 * making the TT enactive) will only decrease the bandwidth used.
2343 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2344 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2348 /* Not sure why we would have no new active endpoints...
2350 * Maybe because of an Evaluate Context change for a hub update or a
2351 * control endpoint 0 max packet size change?
2352 * FIXME: skip the bandwidth calculation in that case.
2357 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2358 struct xhci_virt_device *virt_dev)
2360 unsigned int bw_reserved;
2362 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2363 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2366 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2367 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2374 * This algorithm is a very conservative estimate of the worst-case scheduling
2375 * scenario for any one interval. The hardware dynamically schedules the
2376 * packets, so we can't tell which microframe could be the limiting factor in
2377 * the bandwidth scheduling. This only takes into account periodic endpoints.
2379 * Obviously, we can't solve an NP complete problem to find the minimum worst
2380 * case scenario. Instead, we come up with an estimate that is no less than
2381 * the worst case bandwidth used for any one microframe, but may be an
2384 * We walk the requirements for each endpoint by interval, starting with the
2385 * smallest interval, and place packets in the schedule where there is only one
2386 * possible way to schedule packets for that interval. In order to simplify
2387 * this algorithm, we record the largest max packet size for each interval, and
2388 * assume all packets will be that size.
2390 * For interval 0, we obviously must schedule all packets for each interval.
2391 * The bandwidth for interval 0 is just the amount of data to be transmitted
2392 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2393 * the number of packets).
2395 * For interval 1, we have two possible microframes to schedule those packets
2396 * in. For this algorithm, if we can schedule the same number of packets for
2397 * each possible scheduling opportunity (each microframe), we will do so. The
2398 * remaining number of packets will be saved to be transmitted in the gaps in
2399 * the next interval's scheduling sequence.
2401 * As we move those remaining packets to be scheduled with interval 2 packets,
2402 * we have to double the number of remaining packets to transmit. This is
2403 * because the intervals are actually powers of 2, and we would be transmitting
2404 * the previous interval's packets twice in this interval. We also have to be
2405 * sure that when we look at the largest max packet size for this interval, we
2406 * also look at the largest max packet size for the remaining packets and take
2407 * the greater of the two.
2409 * The algorithm continues to evenly distribute packets in each scheduling
2410 * opportunity, and push the remaining packets out, until we get to the last
2411 * interval. Then those packets and their associated overhead are just added
2412 * to the bandwidth used.
2414 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2415 struct xhci_virt_device *virt_dev,
2418 unsigned int bw_reserved;
2419 unsigned int max_bandwidth;
2420 unsigned int bw_used;
2421 unsigned int block_size;
2422 struct xhci_interval_bw_table *bw_table;
2423 unsigned int packet_size = 0;
2424 unsigned int overhead = 0;
2425 unsigned int packets_transmitted = 0;
2426 unsigned int packets_remaining = 0;
2429 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2430 return xhci_check_ss_bw(xhci, virt_dev);
2432 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2433 max_bandwidth = HS_BW_LIMIT;
2434 /* Convert percent of bus BW reserved to blocks reserved */
2435 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2437 max_bandwidth = FS_BW_LIMIT;
2438 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2441 bw_table = virt_dev->bw_table;
2442 /* We need to translate the max packet size and max ESIT payloads into
2443 * the units the hardware uses.
2445 block_size = xhci_get_block_size(virt_dev->udev);
2447 /* If we are manipulating a LS/FS device under a HS hub, double check
2448 * that the HS bus has enough bandwidth if we are activing a new TT.
2450 if (virt_dev->tt_info) {
2451 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2452 "Recalculating BW for rootport %u",
2453 virt_dev->real_port);
2454 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2455 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2456 "newly activated TT.\n");
2459 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2460 "Recalculating BW for TT slot %u port %u",
2461 virt_dev->tt_info->slot_id,
2462 virt_dev->tt_info->ttport);
2464 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2465 "Recalculating BW for rootport %u",
2466 virt_dev->real_port);
2469 /* Add in how much bandwidth will be used for interval zero, or the
2470 * rounded max ESIT payload + number of packets * largest overhead.
2472 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2473 bw_table->interval_bw[0].num_packets *
2474 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2476 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2477 unsigned int bw_added;
2478 unsigned int largest_mps;
2479 unsigned int interval_overhead;
2482 * How many packets could we transmit in this interval?
2483 * If packets didn't fit in the previous interval, we will need
2484 * to transmit that many packets twice within this interval.
2486 packets_remaining = 2 * packets_remaining +
2487 bw_table->interval_bw[i].num_packets;
2489 /* Find the largest max packet size of this or the previous
2492 if (list_empty(&bw_table->interval_bw[i].endpoints))
2495 struct xhci_virt_ep *virt_ep;
2496 struct list_head *ep_entry;
2498 ep_entry = bw_table->interval_bw[i].endpoints.next;
2499 virt_ep = list_entry(ep_entry,
2500 struct xhci_virt_ep, bw_endpoint_list);
2501 /* Convert to blocks, rounding up */
2502 largest_mps = DIV_ROUND_UP(
2503 virt_ep->bw_info.max_packet_size,
2506 if (largest_mps > packet_size)
2507 packet_size = largest_mps;
2509 /* Use the larger overhead of this or the previous interval. */
2510 interval_overhead = xhci_get_largest_overhead(
2511 &bw_table->interval_bw[i]);
2512 if (interval_overhead > overhead)
2513 overhead = interval_overhead;
2515 /* How many packets can we evenly distribute across
2516 * (1 << (i + 1)) possible scheduling opportunities?
2518 packets_transmitted = packets_remaining >> (i + 1);
2520 /* Add in the bandwidth used for those scheduled packets */
2521 bw_added = packets_transmitted * (overhead + packet_size);
2523 /* How many packets do we have remaining to transmit? */
2524 packets_remaining = packets_remaining % (1 << (i + 1));
2526 /* What largest max packet size should those packets have? */
2527 /* If we've transmitted all packets, don't carry over the
2528 * largest packet size.
2530 if (packets_remaining == 0) {
2533 } else if (packets_transmitted > 0) {
2534 /* Otherwise if we do have remaining packets, and we've
2535 * scheduled some packets in this interval, take the
2536 * largest max packet size from endpoints with this
2539 packet_size = largest_mps;
2540 overhead = interval_overhead;
2542 /* Otherwise carry over packet_size and overhead from the last
2543 * time we had a remainder.
2545 bw_used += bw_added;
2546 if (bw_used > max_bandwidth) {
2547 xhci_warn(xhci, "Not enough bandwidth. "
2548 "Proposed: %u, Max: %u\n",
2549 bw_used, max_bandwidth);
2554 * Ok, we know we have some packets left over after even-handedly
2555 * scheduling interval 15. We don't know which microframes they will
2556 * fit into, so we over-schedule and say they will be scheduled every
2559 if (packets_remaining > 0)
2560 bw_used += overhead + packet_size;
2562 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2563 unsigned int port_index = virt_dev->real_port - 1;
2565 /* OK, we're manipulating a HS device attached to a
2566 * root port bandwidth domain. Include the number of active TTs
2567 * in the bandwidth used.
2569 bw_used += TT_HS_OVERHEAD *
2570 xhci->rh_bw[port_index].num_active_tts;
2573 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2574 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2575 "Available: %u " "percent",
2576 bw_used, max_bandwidth, bw_reserved,
2577 (max_bandwidth - bw_used - bw_reserved) * 100 /
2580 bw_used += bw_reserved;
2581 if (bw_used > max_bandwidth) {
2582 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2583 bw_used, max_bandwidth);
2587 bw_table->bw_used = bw_used;
2591 static bool xhci_is_async_ep(unsigned int ep_type)
2593 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2594 ep_type != ISOC_IN_EP &&
2595 ep_type != INT_IN_EP);
2598 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2600 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2603 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2605 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2607 if (ep_bw->ep_interval == 0)
2608 return SS_OVERHEAD_BURST +
2609 (ep_bw->mult * ep_bw->num_packets *
2610 (SS_OVERHEAD + mps));
2611 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2612 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2613 1 << ep_bw->ep_interval);
2617 static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2618 struct xhci_bw_info *ep_bw,
2619 struct xhci_interval_bw_table *bw_table,
2620 struct usb_device *udev,
2621 struct xhci_virt_ep *virt_ep,
2622 struct xhci_tt_bw_info *tt_info)
2624 struct xhci_interval_bw *interval_bw;
2625 int normalized_interval;
2627 if (xhci_is_async_ep(ep_bw->type))
2630 if (udev->speed >= USB_SPEED_SUPER) {
2631 if (xhci_is_sync_in_ep(ep_bw->type))
2632 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2633 xhci_get_ss_bw_consumed(ep_bw);
2635 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2636 xhci_get_ss_bw_consumed(ep_bw);
2640 /* SuperSpeed endpoints never get added to intervals in the table, so
2641 * this check is only valid for HS/FS/LS devices.
2643 if (list_empty(&virt_ep->bw_endpoint_list))
2645 /* For LS/FS devices, we need to translate the interval expressed in
2646 * microframes to frames.
2648 if (udev->speed == USB_SPEED_HIGH)
2649 normalized_interval = ep_bw->ep_interval;
2651 normalized_interval = ep_bw->ep_interval - 3;
2653 if (normalized_interval == 0)
2654 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2655 interval_bw = &bw_table->interval_bw[normalized_interval];
2656 interval_bw->num_packets -= ep_bw->num_packets;
2657 switch (udev->speed) {
2659 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2661 case USB_SPEED_FULL:
2662 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2664 case USB_SPEED_HIGH:
2665 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2667 case USB_SPEED_SUPER:
2668 case USB_SPEED_SUPER_PLUS:
2669 case USB_SPEED_UNKNOWN:
2670 case USB_SPEED_WIRELESS:
2671 /* Should never happen because only LS/FS/HS endpoints will get
2672 * added to the endpoint list.
2677 tt_info->active_eps -= 1;
2678 list_del_init(&virt_ep->bw_endpoint_list);
2681 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2682 struct xhci_bw_info *ep_bw,
2683 struct xhci_interval_bw_table *bw_table,
2684 struct usb_device *udev,
2685 struct xhci_virt_ep *virt_ep,
2686 struct xhci_tt_bw_info *tt_info)
2688 struct xhci_interval_bw *interval_bw;
2689 struct xhci_virt_ep *smaller_ep;
2690 int normalized_interval;
2692 if (xhci_is_async_ep(ep_bw->type))
2695 if (udev->speed == USB_SPEED_SUPER) {
2696 if (xhci_is_sync_in_ep(ep_bw->type))
2697 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2698 xhci_get_ss_bw_consumed(ep_bw);
2700 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2701 xhci_get_ss_bw_consumed(ep_bw);
2705 /* For LS/FS devices, we need to translate the interval expressed in
2706 * microframes to frames.
2708 if (udev->speed == USB_SPEED_HIGH)
2709 normalized_interval = ep_bw->ep_interval;
2711 normalized_interval = ep_bw->ep_interval - 3;
2713 if (normalized_interval == 0)
2714 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2715 interval_bw = &bw_table->interval_bw[normalized_interval];
2716 interval_bw->num_packets += ep_bw->num_packets;
2717 switch (udev->speed) {
2719 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2721 case USB_SPEED_FULL:
2722 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2724 case USB_SPEED_HIGH:
2725 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2727 case USB_SPEED_SUPER:
2728 case USB_SPEED_SUPER_PLUS:
2729 case USB_SPEED_UNKNOWN:
2730 case USB_SPEED_WIRELESS:
2731 /* Should never happen because only LS/FS/HS endpoints will get
2732 * added to the endpoint list.
2738 tt_info->active_eps += 1;
2739 /* Insert the endpoint into the list, largest max packet size first. */
2740 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2742 if (ep_bw->max_packet_size >=
2743 smaller_ep->bw_info.max_packet_size) {
2744 /* Add the new ep before the smaller endpoint */
2745 list_add_tail(&virt_ep->bw_endpoint_list,
2746 &smaller_ep->bw_endpoint_list);
2750 /* Add the new endpoint at the end of the list. */
2751 list_add_tail(&virt_ep->bw_endpoint_list,
2752 &interval_bw->endpoints);
2755 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2756 struct xhci_virt_device *virt_dev,
2759 struct xhci_root_port_bw_info *rh_bw_info;
2760 if (!virt_dev->tt_info)
2763 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2764 if (old_active_eps == 0 &&
2765 virt_dev->tt_info->active_eps != 0) {
2766 rh_bw_info->num_active_tts += 1;
2767 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2768 } else if (old_active_eps != 0 &&
2769 virt_dev->tt_info->active_eps == 0) {
2770 rh_bw_info->num_active_tts -= 1;
2771 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2775 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2776 struct xhci_virt_device *virt_dev,
2777 struct xhci_container_ctx *in_ctx)
2779 struct xhci_bw_info ep_bw_info[31];
2781 struct xhci_input_control_ctx *ctrl_ctx;
2782 int old_active_eps = 0;
2784 if (virt_dev->tt_info)
2785 old_active_eps = virt_dev->tt_info->active_eps;
2787 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2789 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2794 for (i = 0; i < 31; i++) {
2795 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2798 /* Make a copy of the BW info in case we need to revert this */
2799 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2800 sizeof(ep_bw_info[i]));
2801 /* Drop the endpoint from the interval table if the endpoint is
2802 * being dropped or changed.
2804 if (EP_IS_DROPPED(ctrl_ctx, i))
2805 xhci_drop_ep_from_interval_table(xhci,
2806 &virt_dev->eps[i].bw_info,
2812 /* Overwrite the information stored in the endpoints' bw_info */
2813 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2814 for (i = 0; i < 31; i++) {
2815 /* Add any changed or added endpoints to the interval table */
2816 if (EP_IS_ADDED(ctrl_ctx, i))
2817 xhci_add_ep_to_interval_table(xhci,
2818 &virt_dev->eps[i].bw_info,
2825 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2826 /* Ok, this fits in the bandwidth we have.
2827 * Update the number of active TTs.
2829 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2833 /* We don't have enough bandwidth for this, revert the stored info. */
2834 for (i = 0; i < 31; i++) {
2835 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2838 /* Drop the new copies of any added or changed endpoints from
2839 * the interval table.
2841 if (EP_IS_ADDED(ctrl_ctx, i)) {
2842 xhci_drop_ep_from_interval_table(xhci,
2843 &virt_dev->eps[i].bw_info,
2849 /* Revert the endpoint back to its old information */
2850 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2851 sizeof(ep_bw_info[i]));
2852 /* Add any changed or dropped endpoints back into the table */
2853 if (EP_IS_DROPPED(ctrl_ctx, i))
2854 xhci_add_ep_to_interval_table(xhci,
2855 &virt_dev->eps[i].bw_info,
2865 /* Issue a configure endpoint command or evaluate context command
2866 * and wait for it to finish.
2868 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2869 struct usb_device *udev,
2870 struct xhci_command *command,
2871 bool ctx_change, bool must_succeed)
2874 unsigned long flags;
2875 struct xhci_input_control_ctx *ctrl_ctx;
2876 struct xhci_virt_device *virt_dev;
2877 struct xhci_slot_ctx *slot_ctx;
2882 spin_lock_irqsave(&xhci->lock, flags);
2884 if (xhci->xhc_state & XHCI_STATE_DYING) {
2885 spin_unlock_irqrestore(&xhci->lock, flags);
2889 virt_dev = xhci->devs[udev->slot_id];
2891 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2893 spin_unlock_irqrestore(&xhci->lock, flags);
2894 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2899 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2900 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2901 spin_unlock_irqrestore(&xhci->lock, flags);
2902 xhci_warn(xhci, "Not enough host resources, "
2903 "active endpoint contexts = %u\n",
2904 xhci->num_active_eps);
2907 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2908 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2909 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2910 xhci_free_host_resources(xhci, ctrl_ctx);
2911 spin_unlock_irqrestore(&xhci->lock, flags);
2912 xhci_warn(xhci, "Not enough bandwidth\n");
2916 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2918 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
2919 trace_xhci_configure_endpoint(slot_ctx);
2922 ret = xhci_queue_configure_endpoint(xhci, command,
2923 command->in_ctx->dma,
2924 udev->slot_id, must_succeed);
2926 ret = xhci_queue_evaluate_context(xhci, command,
2927 command->in_ctx->dma,
2928 udev->slot_id, must_succeed);
2930 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2931 xhci_free_host_resources(xhci, ctrl_ctx);
2932 spin_unlock_irqrestore(&xhci->lock, flags);
2933 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2934 "FIXME allocate a new ring segment");
2937 xhci_ring_cmd_db(xhci);
2938 spin_unlock_irqrestore(&xhci->lock, flags);
2940 /* Wait for the configure endpoint command to complete */
2941 wait_for_completion(command->completion);
2944 ret = xhci_configure_endpoint_result(xhci, udev,
2947 ret = xhci_evaluate_context_result(xhci, udev,
2950 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2951 spin_lock_irqsave(&xhci->lock, flags);
2952 /* If the command failed, remove the reserved resources.
2953 * Otherwise, clean up the estimate to include dropped eps.
2956 xhci_free_host_resources(xhci, ctrl_ctx);
2958 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2959 spin_unlock_irqrestore(&xhci->lock, flags);
2964 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2965 struct xhci_virt_device *vdev, int i)
2967 struct xhci_virt_ep *ep = &vdev->eps[i];
2969 if (ep->ep_state & EP_HAS_STREAMS) {
2970 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2971 xhci_get_endpoint_address(i));
2972 xhci_free_stream_info(xhci, ep->stream_info);
2973 ep->stream_info = NULL;
2974 ep->ep_state &= ~EP_HAS_STREAMS;
2978 /* Called after one or more calls to xhci_add_endpoint() or
2979 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2980 * to call xhci_reset_bandwidth().
2982 * Since we are in the middle of changing either configuration or
2983 * installing a new alt setting, the USB core won't allow URBs to be
2984 * enqueued for any endpoint on the old config or interface. Nothing
2985 * else should be touching the xhci->devs[slot_id] structure, so we
2986 * don't need to take the xhci->lock for manipulating that.
2988 static int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2992 struct xhci_hcd *xhci;
2993 struct xhci_virt_device *virt_dev;
2994 struct xhci_input_control_ctx *ctrl_ctx;
2995 struct xhci_slot_ctx *slot_ctx;
2996 struct xhci_command *command;
2998 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3001 xhci = hcd_to_xhci(hcd);
3002 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3003 (xhci->xhc_state & XHCI_STATE_REMOVING))
3006 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3007 virt_dev = xhci->devs[udev->slot_id];
3009 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3013 command->in_ctx = virt_dev->in_ctx;
3015 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
3016 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3018 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3021 goto command_cleanup;
3023 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3024 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
3025 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
3027 /* Don't issue the command if there's no endpoints to update. */
3028 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
3029 ctrl_ctx->drop_flags == 0) {
3031 goto command_cleanup;
3033 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
3034 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3035 for (i = 31; i >= 1; i--) {
3036 __le32 le32 = cpu_to_le32(BIT(i));
3038 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
3039 || (ctrl_ctx->add_flags & le32) || i == 1) {
3040 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
3041 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
3046 ret = xhci_configure_endpoint(xhci, udev, command,
3049 /* Callee should call reset_bandwidth() */
3050 goto command_cleanup;
3052 /* Free any rings that were dropped, but not changed. */
3053 for (i = 1; i < 31; i++) {
3054 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
3055 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
3056 xhci_free_endpoint_ring(xhci, virt_dev, i);
3057 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3060 xhci_zero_in_ctx(xhci, virt_dev);
3062 * Install any rings for completely new endpoints or changed endpoints,
3063 * and free any old rings from changed endpoints.
3065 for (i = 1; i < 31; i++) {
3066 if (!virt_dev->eps[i].new_ring)
3068 /* Only free the old ring if it exists.
3069 * It may not if this is the first add of an endpoint.
3071 if (virt_dev->eps[i].ring) {
3072 xhci_free_endpoint_ring(xhci, virt_dev, i);
3074 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3075 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
3076 virt_dev->eps[i].new_ring = NULL;
3077 xhci_debugfs_create_endpoint(xhci, virt_dev, i);
3080 kfree(command->completion);
3086 static void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3088 struct xhci_hcd *xhci;
3089 struct xhci_virt_device *virt_dev;
3092 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3095 xhci = hcd_to_xhci(hcd);
3097 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3098 virt_dev = xhci->devs[udev->slot_id];
3099 /* Free any rings allocated for added endpoints */
3100 for (i = 0; i < 31; i++) {
3101 if (virt_dev->eps[i].new_ring) {
3102 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3103 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
3104 virt_dev->eps[i].new_ring = NULL;
3107 xhci_zero_in_ctx(xhci, virt_dev);
3110 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
3111 struct xhci_container_ctx *in_ctx,
3112 struct xhci_container_ctx *out_ctx,
3113 struct xhci_input_control_ctx *ctrl_ctx,
3114 u32 add_flags, u32 drop_flags)
3116 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
3117 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
3118 xhci_slot_copy(xhci, in_ctx, out_ctx);
3119 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3122 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
3123 unsigned int slot_id, unsigned int ep_index,
3124 struct xhci_dequeue_state *deq_state)
3126 struct xhci_input_control_ctx *ctrl_ctx;
3127 struct xhci_container_ctx *in_ctx;
3128 struct xhci_ep_ctx *ep_ctx;
3132 in_ctx = xhci->devs[slot_id]->in_ctx;
3133 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
3135 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3140 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
3141 xhci->devs[slot_id]->out_ctx, ep_index);
3142 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
3143 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
3144 deq_state->new_deq_ptr);
3146 xhci_warn(xhci, "WARN Cannot submit config ep after "
3147 "reset ep command\n");
3148 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
3149 deq_state->new_deq_seg,
3150 deq_state->new_deq_ptr);
3153 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
3155 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
3156 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
3157 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
3158 added_ctxs, added_ctxs);
3161 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id,
3162 unsigned int ep_index, unsigned int stream_id,
3165 struct xhci_dequeue_state deq_state;
3167 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
3168 "Cleaning up stalled endpoint ring");
3169 /* We need to move the HW's dequeue pointer past this TD,
3170 * or it will attempt to resend it on the next doorbell ring.
3172 xhci_find_new_dequeue_state(xhci, slot_id, ep_index, stream_id, td,
3175 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
3178 /* HW with the reset endpoint quirk will use the saved dequeue state to
3179 * issue a configure endpoint command later.
3181 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
3182 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
3183 "Queueing new dequeue state");
3184 xhci_queue_new_dequeue_state(xhci, slot_id,
3185 ep_index, &deq_state);
3187 /* Better hope no one uses the input context between now and the
3188 * reset endpoint completion!
3189 * XXX: No idea how this hardware will react when stream rings
3192 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3193 "Setting up input context for "
3194 "configure endpoint command");
3195 xhci_setup_input_ctx_for_quirk(xhci, slot_id,
3196 ep_index, &deq_state);
3200 static void xhci_endpoint_disable(struct usb_hcd *hcd,
3201 struct usb_host_endpoint *host_ep)
3203 struct xhci_hcd *xhci;
3204 struct xhci_virt_device *vdev;
3205 struct xhci_virt_ep *ep;
3206 struct usb_device *udev;
3207 unsigned long flags;
3208 unsigned int ep_index;
3210 xhci = hcd_to_xhci(hcd);
3212 spin_lock_irqsave(&xhci->lock, flags);
3214 udev = (struct usb_device *)host_ep->hcpriv;
3215 if (!udev || !udev->slot_id)
3218 vdev = xhci->devs[udev->slot_id];
3222 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3223 ep = &vdev->eps[ep_index];
3227 /* wait for hub_tt_work to finish clearing hub TT */
3228 if (ep->ep_state & EP_CLEARING_TT) {
3229 spin_unlock_irqrestore(&xhci->lock, flags);
3230 schedule_timeout_uninterruptible(1);
3235 xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3238 host_ep->hcpriv = NULL;
3239 spin_unlock_irqrestore(&xhci->lock, flags);
3243 * Called after usb core issues a clear halt control message.
3244 * The host side of the halt should already be cleared by a reset endpoint
3245 * command issued when the STALL event was received.
3247 * The reset endpoint command may only be issued to endpoints in the halted
3248 * state. For software that wishes to reset the data toggle or sequence number
3249 * of an endpoint that isn't in the halted state this function will issue a
3250 * configure endpoint command with the Drop and Add bits set for the target
3251 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3254 static void xhci_endpoint_reset(struct usb_hcd *hcd,
3255 struct usb_host_endpoint *host_ep)
3257 struct xhci_hcd *xhci;
3258 struct usb_device *udev;
3259 struct xhci_virt_device *vdev;
3260 struct xhci_virt_ep *ep;
3261 struct xhci_input_control_ctx *ctrl_ctx;
3262 struct xhci_command *stop_cmd, *cfg_cmd;
3263 unsigned int ep_index;
3264 unsigned long flags;
3268 xhci = hcd_to_xhci(hcd);
3269 if (!host_ep->hcpriv)
3271 udev = (struct usb_device *) host_ep->hcpriv;
3272 vdev = xhci->devs[udev->slot_id];
3275 * vdev may be lost due to xHC restore error and re-initialization
3276 * during S3/S4 resume. A new vdev will be allocated later by
3277 * xhci_discover_or_reset_device()
3279 if (!udev->slot_id || !vdev)
3281 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3282 ep = &vdev->eps[ep_index];
3286 /* Bail out if toggle is already being cleared by a endpoint reset */
3287 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3288 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3291 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3292 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3293 usb_endpoint_xfer_isoc(&host_ep->desc))
3296 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3298 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3301 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3305 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3309 spin_lock_irqsave(&xhci->lock, flags);
3311 /* block queuing new trbs and ringing ep doorbell */
3312 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3315 * Make sure endpoint ring is empty before resetting the toggle/seq.
3316 * Driver is required to synchronously cancel all transfer request.
3317 * Stop the endpoint to force xHC to update the output context
3320 if (!list_empty(&ep->ring->td_list)) {
3321 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3322 spin_unlock_irqrestore(&xhci->lock, flags);
3323 xhci_free_command(xhci, cfg_cmd);
3327 err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3330 spin_unlock_irqrestore(&xhci->lock, flags);
3331 xhci_free_command(xhci, cfg_cmd);
3332 xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3337 xhci_ring_cmd_db(xhci);
3338 spin_unlock_irqrestore(&xhci->lock, flags);
3340 wait_for_completion(stop_cmd->completion);
3342 spin_lock_irqsave(&xhci->lock, flags);
3344 /* config ep command clears toggle if add and drop ep flags are set */
3345 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3346 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3347 ctrl_ctx, ep_flag, ep_flag);
3348 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3350 err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3351 udev->slot_id, false);
3353 spin_unlock_irqrestore(&xhci->lock, flags);
3354 xhci_free_command(xhci, cfg_cmd);
3355 xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3360 xhci_ring_cmd_db(xhci);
3361 spin_unlock_irqrestore(&xhci->lock, flags);
3363 wait_for_completion(cfg_cmd->completion);
3365 xhci_free_command(xhci, cfg_cmd);
3367 xhci_free_command(xhci, stop_cmd);
3368 if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE)
3369 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3372 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3373 struct usb_device *udev, struct usb_host_endpoint *ep,
3374 unsigned int slot_id)
3377 unsigned int ep_index;
3378 unsigned int ep_state;
3382 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3385 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3386 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3387 " descriptor for ep 0x%x does not support streams\n",
3388 ep->desc.bEndpointAddress);
3392 ep_index = xhci_get_endpoint_index(&ep->desc);
3393 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3394 if (ep_state & EP_HAS_STREAMS ||
3395 ep_state & EP_GETTING_STREAMS) {
3396 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3397 "already has streams set up.\n",
3398 ep->desc.bEndpointAddress);
3399 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3400 "dynamic stream context array reallocation.\n");
3403 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3404 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3405 "endpoint 0x%x; URBs are pending.\n",
3406 ep->desc.bEndpointAddress);
3412 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3413 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3415 unsigned int max_streams;
3417 /* The stream context array size must be a power of two */
3418 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3420 * Find out how many primary stream array entries the host controller
3421 * supports. Later we may use secondary stream arrays (similar to 2nd
3422 * level page entries), but that's an optional feature for xHCI host
3423 * controllers. xHCs must support at least 4 stream IDs.
3425 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3426 if (*num_stream_ctxs > max_streams) {
3427 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3429 *num_stream_ctxs = max_streams;
3430 *num_streams = max_streams;
3434 /* Returns an error code if one of the endpoint already has streams.
3435 * This does not change any data structures, it only checks and gathers
3438 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3439 struct usb_device *udev,
3440 struct usb_host_endpoint **eps, unsigned int num_eps,
3441 unsigned int *num_streams, u32 *changed_ep_bitmask)
3443 unsigned int max_streams;
3444 unsigned int endpoint_flag;
3448 for (i = 0; i < num_eps; i++) {
3449 ret = xhci_check_streams_endpoint(xhci, udev,
3450 eps[i], udev->slot_id);
3454 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3455 if (max_streams < (*num_streams - 1)) {
3456 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3457 eps[i]->desc.bEndpointAddress,
3459 *num_streams = max_streams+1;
3462 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3463 if (*changed_ep_bitmask & endpoint_flag)
3465 *changed_ep_bitmask |= endpoint_flag;
3470 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3471 struct usb_device *udev,
3472 struct usb_host_endpoint **eps, unsigned int num_eps)
3474 u32 changed_ep_bitmask = 0;
3475 unsigned int slot_id;
3476 unsigned int ep_index;
3477 unsigned int ep_state;
3480 slot_id = udev->slot_id;
3481 if (!xhci->devs[slot_id])
3484 for (i = 0; i < num_eps; i++) {
3485 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3486 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3487 /* Are streams already being freed for the endpoint? */
3488 if (ep_state & EP_GETTING_NO_STREAMS) {
3489 xhci_warn(xhci, "WARN Can't disable streams for "
3491 "streams are being disabled already\n",
3492 eps[i]->desc.bEndpointAddress);
3495 /* Are there actually any streams to free? */
3496 if (!(ep_state & EP_HAS_STREAMS) &&
3497 !(ep_state & EP_GETTING_STREAMS)) {
3498 xhci_warn(xhci, "WARN Can't disable streams for "
3500 "streams are already disabled!\n",
3501 eps[i]->desc.bEndpointAddress);
3502 xhci_warn(xhci, "WARN xhci_free_streams() called "
3503 "with non-streams endpoint\n");
3506 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3508 return changed_ep_bitmask;
3512 * The USB device drivers use this function (through the HCD interface in USB
3513 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3514 * coordinate mass storage command queueing across multiple endpoints (basically
3515 * a stream ID == a task ID).
3517 * Setting up streams involves allocating the same size stream context array
3518 * for each endpoint and issuing a configure endpoint command for all endpoints.
3520 * Don't allow the call to succeed if one endpoint only supports one stream
3521 * (which means it doesn't support streams at all).
3523 * Drivers may get less stream IDs than they asked for, if the host controller
3524 * hardware or endpoints claim they can't support the number of requested
3527 static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3528 struct usb_host_endpoint **eps, unsigned int num_eps,
3529 unsigned int num_streams, gfp_t mem_flags)
3532 struct xhci_hcd *xhci;
3533 struct xhci_virt_device *vdev;
3534 struct xhci_command *config_cmd;
3535 struct xhci_input_control_ctx *ctrl_ctx;
3536 unsigned int ep_index;
3537 unsigned int num_stream_ctxs;
3538 unsigned int max_packet;
3539 unsigned long flags;
3540 u32 changed_ep_bitmask = 0;
3545 /* Add one to the number of streams requested to account for
3546 * stream 0 that is reserved for xHCI usage.
3549 xhci = hcd_to_xhci(hcd);
3550 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3553 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3554 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3555 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3556 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3560 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3564 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3566 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3568 xhci_free_command(xhci, config_cmd);
3572 /* Check to make sure all endpoints are not already configured for
3573 * streams. While we're at it, find the maximum number of streams that
3574 * all the endpoints will support and check for duplicate endpoints.
3576 spin_lock_irqsave(&xhci->lock, flags);
3577 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3578 num_eps, &num_streams, &changed_ep_bitmask);
3580 xhci_free_command(xhci, config_cmd);
3581 spin_unlock_irqrestore(&xhci->lock, flags);
3584 if (num_streams <= 1) {
3585 xhci_warn(xhci, "WARN: endpoints can't handle "
3586 "more than one stream.\n");
3587 xhci_free_command(xhci, config_cmd);
3588 spin_unlock_irqrestore(&xhci->lock, flags);
3591 vdev = xhci->devs[udev->slot_id];
3592 /* Mark each endpoint as being in transition, so
3593 * xhci_urb_enqueue() will reject all URBs.
3595 for (i = 0; i < num_eps; i++) {
3596 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3597 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3599 spin_unlock_irqrestore(&xhci->lock, flags);
3601 /* Setup internal data structures and allocate HW data structures for
3602 * streams (but don't install the HW structures in the input context
3603 * until we're sure all memory allocation succeeded).
3605 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3606 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3607 num_stream_ctxs, num_streams);
3609 for (i = 0; i < num_eps; i++) {
3610 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3611 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3612 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3615 max_packet, mem_flags);
3616 if (!vdev->eps[ep_index].stream_info)
3618 /* Set maxPstreams in endpoint context and update deq ptr to
3619 * point to stream context array. FIXME
3623 /* Set up the input context for a configure endpoint command. */
3624 for (i = 0; i < num_eps; i++) {
3625 struct xhci_ep_ctx *ep_ctx;
3627 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3628 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3630 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3631 vdev->out_ctx, ep_index);
3632 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3633 vdev->eps[ep_index].stream_info);
3635 /* Tell the HW to drop its old copy of the endpoint context info
3636 * and add the updated copy from the input context.
3638 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3639 vdev->out_ctx, ctrl_ctx,
3640 changed_ep_bitmask, changed_ep_bitmask);
3642 /* Issue and wait for the configure endpoint command */
3643 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3646 /* xHC rejected the configure endpoint command for some reason, so we
3647 * leave the old ring intact and free our internal streams data
3653 spin_lock_irqsave(&xhci->lock, flags);
3654 for (i = 0; i < num_eps; i++) {
3655 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3656 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3657 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3658 udev->slot_id, ep_index);
3659 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3661 xhci_free_command(xhci, config_cmd);
3662 spin_unlock_irqrestore(&xhci->lock, flags);
3664 for (i = 0; i < num_eps; i++) {
3665 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3666 xhci_debugfs_create_stream_files(xhci, vdev, ep_index);
3668 /* Subtract 1 for stream 0, which drivers can't use */
3669 return num_streams - 1;
3672 /* If it didn't work, free the streams! */
3673 for (i = 0; i < num_eps; i++) {
3674 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3675 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3676 vdev->eps[ep_index].stream_info = NULL;
3677 /* FIXME Unset maxPstreams in endpoint context and
3678 * update deq ptr to point to normal string ring.
3680 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3681 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3682 xhci_endpoint_zero(xhci, vdev, eps[i]);
3684 xhci_free_command(xhci, config_cmd);
3688 /* Transition the endpoint from using streams to being a "normal" endpoint
3691 * Modify the endpoint context state, submit a configure endpoint command,
3692 * and free all endpoint rings for streams if that completes successfully.
3694 static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3695 struct usb_host_endpoint **eps, unsigned int num_eps,
3699 struct xhci_hcd *xhci;
3700 struct xhci_virt_device *vdev;
3701 struct xhci_command *command;
3702 struct xhci_input_control_ctx *ctrl_ctx;
3703 unsigned int ep_index;
3704 unsigned long flags;
3705 u32 changed_ep_bitmask;
3707 xhci = hcd_to_xhci(hcd);
3708 vdev = xhci->devs[udev->slot_id];
3710 /* Set up a configure endpoint command to remove the streams rings */
3711 spin_lock_irqsave(&xhci->lock, flags);
3712 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3713 udev, eps, num_eps);
3714 if (changed_ep_bitmask == 0) {
3715 spin_unlock_irqrestore(&xhci->lock, flags);
3719 /* Use the xhci_command structure from the first endpoint. We may have
3720 * allocated too many, but the driver may call xhci_free_streams() for
3721 * each endpoint it grouped into one call to xhci_alloc_streams().
3723 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3724 command = vdev->eps[ep_index].stream_info->free_streams_command;
3725 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3727 spin_unlock_irqrestore(&xhci->lock, flags);
3728 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3733 for (i = 0; i < num_eps; i++) {
3734 struct xhci_ep_ctx *ep_ctx;
3736 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3737 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3738 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3739 EP_GETTING_NO_STREAMS;
3741 xhci_endpoint_copy(xhci, command->in_ctx,
3742 vdev->out_ctx, ep_index);
3743 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3744 &vdev->eps[ep_index]);
3746 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3747 vdev->out_ctx, ctrl_ctx,
3748 changed_ep_bitmask, changed_ep_bitmask);
3749 spin_unlock_irqrestore(&xhci->lock, flags);
3751 /* Issue and wait for the configure endpoint command,
3752 * which must succeed.
3754 ret = xhci_configure_endpoint(xhci, udev, command,
3757 /* xHC rejected the configure endpoint command for some reason, so we
3758 * leave the streams rings intact.
3763 spin_lock_irqsave(&xhci->lock, flags);
3764 for (i = 0; i < num_eps; i++) {
3765 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3766 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3767 vdev->eps[ep_index].stream_info = NULL;
3768 /* FIXME Unset maxPstreams in endpoint context and
3769 * update deq ptr to point to normal string ring.
3771 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3772 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3774 spin_unlock_irqrestore(&xhci->lock, flags);
3780 * Deletes endpoint resources for endpoints that were active before a Reset
3781 * Device command, or a Disable Slot command. The Reset Device command leaves
3782 * the control endpoint intact, whereas the Disable Slot command deletes it.
3784 * Must be called with xhci->lock held.
3786 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3787 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3790 unsigned int num_dropped_eps = 0;
3791 unsigned int drop_flags = 0;
3793 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3794 if (virt_dev->eps[i].ring) {
3795 drop_flags |= 1 << i;
3799 xhci->num_active_eps -= num_dropped_eps;
3800 if (num_dropped_eps)
3801 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3802 "Dropped %u ep ctxs, flags = 0x%x, "
3804 num_dropped_eps, drop_flags,
3805 xhci->num_active_eps);
3809 * This submits a Reset Device Command, which will set the device state to 0,
3810 * set the device address to 0, and disable all the endpoints except the default
3811 * control endpoint. The USB core should come back and call
3812 * xhci_address_device(), and then re-set up the configuration. If this is
3813 * called because of a usb_reset_and_verify_device(), then the old alternate
3814 * settings will be re-installed through the normal bandwidth allocation
3817 * Wait for the Reset Device command to finish. Remove all structures
3818 * associated with the endpoints that were disabled. Clear the input device
3819 * structure? Reset the control endpoint 0 max packet size?
3821 * If the virt_dev to be reset does not exist or does not match the udev,
3822 * it means the device is lost, possibly due to the xHC restore error and
3823 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3824 * re-allocate the device.
3826 static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3827 struct usb_device *udev)
3830 unsigned long flags;
3831 struct xhci_hcd *xhci;
3832 unsigned int slot_id;
3833 struct xhci_virt_device *virt_dev;
3834 struct xhci_command *reset_device_cmd;
3835 struct xhci_slot_ctx *slot_ctx;
3836 int old_active_eps = 0;
3838 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3841 xhci = hcd_to_xhci(hcd);
3842 slot_id = udev->slot_id;
3843 virt_dev = xhci->devs[slot_id];
3845 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3846 "not exist. Re-allocate the device\n", slot_id);
3847 ret = xhci_alloc_dev(hcd, udev);
3854 if (virt_dev->tt_info)
3855 old_active_eps = virt_dev->tt_info->active_eps;
3857 if (virt_dev->udev != udev) {
3858 /* If the virt_dev and the udev does not match, this virt_dev
3859 * may belong to another udev.
3860 * Re-allocate the device.
3862 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3863 "not match the udev. Re-allocate the device\n",
3865 ret = xhci_alloc_dev(hcd, udev);
3872 /* If device is not setup, there is no point in resetting it */
3873 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3874 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3875 SLOT_STATE_DISABLED)
3878 trace_xhci_discover_or_reset_device(slot_ctx);
3880 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3881 /* Allocate the command structure that holds the struct completion.
3882 * Assume we're in process context, since the normal device reset
3883 * process has to wait for the device anyway. Storage devices are
3884 * reset as part of error handling, so use GFP_NOIO instead of
3887 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3888 if (!reset_device_cmd) {
3889 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3893 /* Attempt to submit the Reset Device command to the command ring */
3894 spin_lock_irqsave(&xhci->lock, flags);
3896 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3898 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3899 spin_unlock_irqrestore(&xhci->lock, flags);
3900 goto command_cleanup;
3902 xhci_ring_cmd_db(xhci);
3903 spin_unlock_irqrestore(&xhci->lock, flags);
3905 /* Wait for the Reset Device command to finish */
3906 wait_for_completion(reset_device_cmd->completion);
3908 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3909 * unless we tried to reset a slot ID that wasn't enabled,
3910 * or the device wasn't in the addressed or configured state.
3912 ret = reset_device_cmd->status;
3914 case COMP_COMMAND_ABORTED:
3915 case COMP_COMMAND_RING_STOPPED:
3916 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3918 goto command_cleanup;
3919 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3920 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3921 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3923 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3924 xhci_dbg(xhci, "Not freeing device rings.\n");
3925 /* Don't treat this as an error. May change my mind later. */
3927 goto command_cleanup;
3929 xhci_dbg(xhci, "Successful reset device command.\n");
3932 if (xhci_is_vendor_info_code(xhci, ret))
3934 xhci_warn(xhci, "Unknown completion code %u for "
3935 "reset device command.\n", ret);
3937 goto command_cleanup;
3940 /* Free up host controller endpoint resources */
3941 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3942 spin_lock_irqsave(&xhci->lock, flags);
3943 /* Don't delete the default control endpoint resources */
3944 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3945 spin_unlock_irqrestore(&xhci->lock, flags);
3948 /* Everything but endpoint 0 is disabled, so free the rings. */
3949 for (i = 1; i < 31; i++) {
3950 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3952 if (ep->ep_state & EP_HAS_STREAMS) {
3953 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3954 xhci_get_endpoint_address(i));
3955 xhci_free_stream_info(xhci, ep->stream_info);
3956 ep->stream_info = NULL;
3957 ep->ep_state &= ~EP_HAS_STREAMS;
3961 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3962 xhci_free_endpoint_ring(xhci, virt_dev, i);
3964 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3965 xhci_drop_ep_from_interval_table(xhci,
3966 &virt_dev->eps[i].bw_info,
3971 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3973 /* If necessary, update the number of active TTs on this root port */
3974 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3975 virt_dev->flags = 0;
3979 xhci_free_command(xhci, reset_device_cmd);
3984 * At this point, the struct usb_device is about to go away, the device has
3985 * disconnected, and all traffic has been stopped and the endpoints have been
3986 * disabled. Free any HC data structures associated with that device.
3988 static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3990 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3991 struct xhci_virt_device *virt_dev;
3992 struct xhci_slot_ctx *slot_ctx;
3995 #ifndef CONFIG_USB_DEFAULT_PERSIST
3997 * We called pm_runtime_get_noresume when the device was attached.
3998 * Decrement the counter here to allow controller to runtime suspend
3999 * if no devices remain.
4001 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4002 pm_runtime_put_noidle(hcd->self.controller);
4005 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
4006 /* If the host is halted due to driver unload, we still need to free the
4009 if (ret <= 0 && ret != -ENODEV)
4012 virt_dev = xhci->devs[udev->slot_id];
4013 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4014 trace_xhci_free_dev(slot_ctx);
4016 /* Stop any wayward timer functions (which may grab the lock) */
4017 for (i = 0; i < 31; i++) {
4018 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
4019 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
4021 virt_dev->udev = NULL;
4022 ret = xhci_disable_slot(xhci, udev->slot_id);
4024 xhci_free_virt_device(xhci, udev->slot_id);
4027 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
4029 struct xhci_command *command;
4030 unsigned long flags;
4034 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
4038 xhci_debugfs_remove_slot(xhci, slot_id);
4040 spin_lock_irqsave(&xhci->lock, flags);
4041 /* Don't disable the slot if the host controller is dead. */
4042 state = readl(&xhci->op_regs->status);
4043 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
4044 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4045 spin_unlock_irqrestore(&xhci->lock, flags);
4050 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
4053 spin_unlock_irqrestore(&xhci->lock, flags);
4057 xhci_ring_cmd_db(xhci);
4058 spin_unlock_irqrestore(&xhci->lock, flags);
4063 * Checks if we have enough host controller resources for the default control
4066 * Must be called with xhci->lock held.
4068 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
4070 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
4071 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4072 "Not enough ep ctxs: "
4073 "%u active, need to add 1, limit is %u.",
4074 xhci->num_active_eps, xhci->limit_active_eps);
4077 xhci->num_active_eps += 1;
4078 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4079 "Adding 1 ep ctx, %u now active.",
4080 xhci->num_active_eps);
4086 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
4087 * timed out, or allocating memory failed. Returns 1 on success.
4089 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
4091 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4092 struct xhci_virt_device *vdev;
4093 struct xhci_slot_ctx *slot_ctx;
4094 unsigned long flags;
4096 struct xhci_command *command;
4098 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4102 spin_lock_irqsave(&xhci->lock, flags);
4103 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
4105 spin_unlock_irqrestore(&xhci->lock, flags);
4106 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
4107 xhci_free_command(xhci, command);
4110 xhci_ring_cmd_db(xhci);
4111 spin_unlock_irqrestore(&xhci->lock, flags);
4113 wait_for_completion(command->completion);
4114 slot_id = command->slot_id;
4116 if (!slot_id || command->status != COMP_SUCCESS) {
4117 xhci_err(xhci, "Error while assigning device slot ID\n");
4118 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
4120 readl(&xhci->cap_regs->hcs_params1)));
4121 xhci_free_command(xhci, command);
4125 xhci_free_command(xhci, command);
4127 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
4128 spin_lock_irqsave(&xhci->lock, flags);
4129 ret = xhci_reserve_host_control_ep_resources(xhci);
4131 spin_unlock_irqrestore(&xhci->lock, flags);
4132 xhci_warn(xhci, "Not enough host resources, "
4133 "active endpoint contexts = %u\n",
4134 xhci->num_active_eps);
4137 spin_unlock_irqrestore(&xhci->lock, flags);
4139 /* Use GFP_NOIO, since this function can be called from
4140 * xhci_discover_or_reset_device(), which may be called as part of
4141 * mass storage driver error handling.
4143 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4144 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4147 vdev = xhci->devs[slot_id];
4148 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4149 trace_xhci_alloc_dev(slot_ctx);
4151 udev->slot_id = slot_id;
4153 xhci_debugfs_create_slot(xhci, slot_id);
4155 #ifndef CONFIG_USB_DEFAULT_PERSIST
4157 * If resetting upon resume, we can't put the controller into runtime
4158 * suspend if there is a device attached.
4160 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4161 pm_runtime_get_noresume(hcd->self.controller);
4164 /* Is this a LS or FS device under a HS hub? */
4165 /* Hub or peripherial? */
4169 ret = xhci_disable_slot(xhci, udev->slot_id);
4171 xhci_free_virt_device(xhci, udev->slot_id);
4177 * Issue an Address Device command and optionally send a corresponding
4178 * SetAddress request to the device.
4180 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4181 enum xhci_setup_dev setup)
4183 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4184 unsigned long flags;
4185 struct xhci_virt_device *virt_dev;
4187 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4188 struct xhci_slot_ctx *slot_ctx;
4189 struct xhci_input_control_ctx *ctrl_ctx;
4191 struct xhci_command *command = NULL;
4193 mutex_lock(&xhci->mutex);
4195 if (xhci->xhc_state) { /* dying, removing or halted */
4200 if (!udev->slot_id) {
4201 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4202 "Bad Slot ID %d", udev->slot_id);
4207 virt_dev = xhci->devs[udev->slot_id];
4209 if (WARN_ON(!virt_dev)) {
4211 * In plug/unplug torture test with an NEC controller,
4212 * a zero-dereference was observed once due to virt_dev = 0.
4213 * Print useful debug rather than crash if it is observed again!
4215 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4220 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4221 trace_xhci_setup_device_slot(slot_ctx);
4223 if (setup == SETUP_CONTEXT_ONLY) {
4224 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4225 SLOT_STATE_DEFAULT) {
4226 xhci_dbg(xhci, "Slot already in default state\n");
4231 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4237 command->in_ctx = virt_dev->in_ctx;
4239 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4240 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4242 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4248 * If this is the first Set Address since device plug-in or
4249 * virt_device realloaction after a resume with an xHCI power loss,
4250 * then set up the slot context.
4252 if (!slot_ctx->dev_info)
4253 xhci_setup_addressable_virt_dev(xhci, udev);
4254 /* Otherwise, update the control endpoint ring enqueue pointer. */
4256 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4257 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4258 ctrl_ctx->drop_flags = 0;
4260 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4261 le32_to_cpu(slot_ctx->dev_info) >> 27);
4263 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4264 spin_lock_irqsave(&xhci->lock, flags);
4265 trace_xhci_setup_device(virt_dev);
4266 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4267 udev->slot_id, setup);
4269 spin_unlock_irqrestore(&xhci->lock, flags);
4270 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4271 "FIXME: allocate a command ring segment");
4274 xhci_ring_cmd_db(xhci);
4275 spin_unlock_irqrestore(&xhci->lock, flags);
4277 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4278 wait_for_completion(command->completion);
4280 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4281 * the SetAddress() "recovery interval" required by USB and aborting the
4282 * command on a timeout.
4284 switch (command->status) {
4285 case COMP_COMMAND_ABORTED:
4286 case COMP_COMMAND_RING_STOPPED:
4287 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4290 case COMP_CONTEXT_STATE_ERROR:
4291 case COMP_SLOT_NOT_ENABLED_ERROR:
4292 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4293 act, udev->slot_id);
4296 case COMP_USB_TRANSACTION_ERROR:
4297 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4299 mutex_unlock(&xhci->mutex);
4300 ret = xhci_disable_slot(xhci, udev->slot_id);
4302 xhci_alloc_dev(hcd, udev);
4303 kfree(command->completion);
4306 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4307 dev_warn(&udev->dev,
4308 "ERROR: Incompatible device for setup %s command\n", act);
4312 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4313 "Successful setup %s command", act);
4317 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4318 act, command->status);
4319 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4325 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4326 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4327 "Op regs DCBAA ptr = %#016llx", temp_64);
4328 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4329 "Slot ID %d dcbaa entry @%p = %#016llx",
4331 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4332 (unsigned long long)
4333 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4334 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4335 "Output Context DMA address = %#08llx",
4336 (unsigned long long)virt_dev->out_ctx->dma);
4337 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4338 le32_to_cpu(slot_ctx->dev_info) >> 27);
4340 * USB core uses address 1 for the roothubs, so we add one to the
4341 * address given back to us by the HC.
4343 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4344 le32_to_cpu(slot_ctx->dev_info) >> 27);
4345 /* Zero the input context control for later use */
4346 ctrl_ctx->add_flags = 0;
4347 ctrl_ctx->drop_flags = 0;
4348 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4349 udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4351 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4352 "Internal device address = %d",
4353 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4355 mutex_unlock(&xhci->mutex);
4357 kfree(command->completion);
4363 static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4365 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4368 static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4370 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4374 * Transfer the port index into real index in the HW port status
4375 * registers. Caculate offset between the port's PORTSC register
4376 * and port status base. Divide the number of per port register
4377 * to get the real index. The raw port number bases 1.
4379 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4381 struct xhci_hub *rhub;
4383 rhub = xhci_get_rhub(hcd);
4384 return rhub->ports[port1 - 1]->hw_portnum + 1;
4388 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4389 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4391 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4392 struct usb_device *udev, u16 max_exit_latency)
4394 struct xhci_virt_device *virt_dev;
4395 struct xhci_command *command;
4396 struct xhci_input_control_ctx *ctrl_ctx;
4397 struct xhci_slot_ctx *slot_ctx;
4398 unsigned long flags;
4401 spin_lock_irqsave(&xhci->lock, flags);
4403 virt_dev = xhci->devs[udev->slot_id];
4406 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4407 * xHC was re-initialized. Exit latency will be set later after
4408 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4411 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4412 spin_unlock_irqrestore(&xhci->lock, flags);
4416 /* Attempt to issue an Evaluate Context command to change the MEL. */
4417 command = xhci->lpm_command;
4418 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4420 spin_unlock_irqrestore(&xhci->lock, flags);
4421 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4426 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4427 spin_unlock_irqrestore(&xhci->lock, flags);
4429 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4430 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4431 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4432 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4433 slot_ctx->dev_state = 0;
4435 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4436 "Set up evaluate context for LPM MEL change.");
4438 /* Issue and wait for the evaluate context command. */
4439 ret = xhci_configure_endpoint(xhci, udev, command,
4443 spin_lock_irqsave(&xhci->lock, flags);
4444 virt_dev->current_mel = max_exit_latency;
4445 spin_unlock_irqrestore(&xhci->lock, flags);
4452 /* BESL to HIRD Encoding array for USB2 LPM */
4453 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4454 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4456 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4457 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4458 struct usb_device *udev)
4460 int u2del, besl, besl_host;
4461 int besl_device = 0;
4464 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4465 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4467 if (field & USB_BESL_SUPPORT) {
4468 for (besl_host = 0; besl_host < 16; besl_host++) {
4469 if (xhci_besl_encoding[besl_host] >= u2del)
4472 /* Use baseline BESL value as default */
4473 if (field & USB_BESL_BASELINE_VALID)
4474 besl_device = USB_GET_BESL_BASELINE(field);
4475 else if (field & USB_BESL_DEEP_VALID)
4476 besl_device = USB_GET_BESL_DEEP(field);
4481 besl_host = (u2del - 51) / 75 + 1;
4484 besl = besl_host + besl_device;
4491 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4492 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4499 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4501 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4502 l1 = udev->l1_params.timeout / 256;
4504 /* device has preferred BESLD */
4505 if (field & USB_BESL_DEEP_VALID) {
4506 besld = USB_GET_BESL_DEEP(field);
4510 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4513 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4514 struct usb_device *udev, int enable)
4516 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4517 struct xhci_port **ports;
4518 __le32 __iomem *pm_addr, *hlpm_addr;
4519 u32 pm_val, hlpm_val, field;
4520 unsigned int port_num;
4521 unsigned long flags;
4522 int hird, exit_latency;
4525 if (xhci->quirks & XHCI_HW_LPM_DISABLE)
4528 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4532 if (!udev->parent || udev->parent->parent ||
4533 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4536 if (udev->usb2_hw_lpm_capable != 1)
4539 spin_lock_irqsave(&xhci->lock, flags);
4541 ports = xhci->usb2_rhub.ports;
4542 port_num = udev->portnum - 1;
4543 pm_addr = ports[port_num]->addr + PORTPMSC;
4544 pm_val = readl(pm_addr);
4545 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4547 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4548 enable ? "enable" : "disable", port_num + 1);
4551 /* Host supports BESL timeout instead of HIRD */
4552 if (udev->usb2_hw_lpm_besl_capable) {
4553 /* if device doesn't have a preferred BESL value use a
4554 * default one which works with mixed HIRD and BESL
4555 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4557 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4558 if ((field & USB_BESL_SUPPORT) &&
4559 (field & USB_BESL_BASELINE_VALID))
4560 hird = USB_GET_BESL_BASELINE(field);
4562 hird = udev->l1_params.besl;
4564 exit_latency = xhci_besl_encoding[hird];
4565 spin_unlock_irqrestore(&xhci->lock, flags);
4567 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4568 * input context for link powermanagement evaluate
4569 * context commands. It is protected by hcd->bandwidth
4570 * mutex and is shared by all devices. We need to set
4571 * the max ext latency in USB 2 BESL LPM as well, so
4572 * use the same mutex and xhci_change_max_exit_latency()
4574 mutex_lock(hcd->bandwidth_mutex);
4575 ret = xhci_change_max_exit_latency(xhci, udev,
4577 mutex_unlock(hcd->bandwidth_mutex);
4581 spin_lock_irqsave(&xhci->lock, flags);
4583 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4584 writel(hlpm_val, hlpm_addr);
4588 hird = xhci_calculate_hird_besl(xhci, udev);
4591 pm_val &= ~PORT_HIRD_MASK;
4592 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4593 writel(pm_val, pm_addr);
4594 pm_val = readl(pm_addr);
4596 writel(pm_val, pm_addr);
4600 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4601 writel(pm_val, pm_addr);
4604 if (udev->usb2_hw_lpm_besl_capable) {
4605 spin_unlock_irqrestore(&xhci->lock, flags);
4606 mutex_lock(hcd->bandwidth_mutex);
4607 xhci_change_max_exit_latency(xhci, udev, 0);
4608 mutex_unlock(hcd->bandwidth_mutex);
4609 readl_poll_timeout(ports[port_num]->addr, pm_val,
4610 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4616 spin_unlock_irqrestore(&xhci->lock, flags);
4620 /* check if a usb2 port supports a given extened capability protocol
4621 * only USB2 ports extended protocol capability values are cached.
4622 * Return 1 if capability is supported
4624 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4625 unsigned capability)
4627 u32 port_offset, port_count;
4630 for (i = 0; i < xhci->num_ext_caps; i++) {
4631 if (xhci->ext_caps[i] & capability) {
4632 /* port offsets starts at 1 */
4633 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4634 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4635 if (port >= port_offset &&
4636 port < port_offset + port_count)
4643 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4645 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4646 int portnum = udev->portnum - 1;
4648 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
4651 /* we only support lpm for non-hub device connected to root hub yet */
4652 if (!udev->parent || udev->parent->parent ||
4653 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4656 if (xhci->hw_lpm_support == 1 &&
4657 xhci_check_usb2_port_capability(
4658 xhci, portnum, XHCI_HLC)) {
4659 udev->usb2_hw_lpm_capable = 1;
4660 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4661 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4662 if (xhci_check_usb2_port_capability(xhci, portnum,
4664 udev->usb2_hw_lpm_besl_capable = 1;
4670 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4672 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4673 static unsigned long long xhci_service_interval_to_ns(
4674 struct usb_endpoint_descriptor *desc)
4676 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4679 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4680 enum usb3_link_state state)
4682 unsigned long long sel;
4683 unsigned long long pel;
4684 unsigned int max_sel_pel;
4689 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4690 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4691 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4692 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4696 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4697 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4698 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4702 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4704 return USB3_LPM_DISABLED;
4707 if (sel <= max_sel_pel && pel <= max_sel_pel)
4708 return USB3_LPM_DEVICE_INITIATED;
4710 if (sel > max_sel_pel)
4711 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4712 "due to long SEL %llu ms\n",
4715 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4716 "due to long PEL %llu ms\n",
4718 return USB3_LPM_DISABLED;
4721 /* The U1 timeout should be the maximum of the following values:
4722 * - For control endpoints, U1 system exit latency (SEL) * 3
4723 * - For bulk endpoints, U1 SEL * 5
4724 * - For interrupt endpoints:
4725 * - Notification EPs, U1 SEL * 3
4726 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4727 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4729 static unsigned long long xhci_calculate_intel_u1_timeout(
4730 struct usb_device *udev,
4731 struct usb_endpoint_descriptor *desc)
4733 unsigned long long timeout_ns;
4737 ep_type = usb_endpoint_type(desc);
4739 case USB_ENDPOINT_XFER_CONTROL:
4740 timeout_ns = udev->u1_params.sel * 3;
4742 case USB_ENDPOINT_XFER_BULK:
4743 timeout_ns = udev->u1_params.sel * 5;
4745 case USB_ENDPOINT_XFER_INT:
4746 intr_type = usb_endpoint_interrupt_type(desc);
4747 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4748 timeout_ns = udev->u1_params.sel * 3;
4751 /* Otherwise the calculation is the same as isoc eps */
4753 case USB_ENDPOINT_XFER_ISOC:
4754 timeout_ns = xhci_service_interval_to_ns(desc);
4755 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4756 if (timeout_ns < udev->u1_params.sel * 2)
4757 timeout_ns = udev->u1_params.sel * 2;
4766 /* Returns the hub-encoded U1 timeout value. */
4767 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4768 struct usb_device *udev,
4769 struct usb_endpoint_descriptor *desc)
4771 unsigned long long timeout_ns;
4773 /* Prevent U1 if service interval is shorter than U1 exit latency */
4774 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4775 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4776 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4777 return USB3_LPM_DISABLED;
4781 if (xhci->quirks & XHCI_INTEL_HOST)
4782 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4784 timeout_ns = udev->u1_params.sel;
4786 /* The U1 timeout is encoded in 1us intervals.
4787 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4789 if (timeout_ns == USB3_LPM_DISABLED)
4792 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4794 /* If the necessary timeout value is bigger than what we can set in the
4795 * USB 3.0 hub, we have to disable hub-initiated U1.
4797 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4799 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4800 "due to long timeout %llu ms\n", timeout_ns);
4801 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4804 /* The U2 timeout should be the maximum of:
4805 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4806 * - largest bInterval of any active periodic endpoint (to avoid going
4807 * into lower power link states between intervals).
4808 * - the U2 Exit Latency of the device
4810 static unsigned long long xhci_calculate_intel_u2_timeout(
4811 struct usb_device *udev,
4812 struct usb_endpoint_descriptor *desc)
4814 unsigned long long timeout_ns;
4815 unsigned long long u2_del_ns;
4817 timeout_ns = 10 * 1000 * 1000;
4819 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4820 (xhci_service_interval_to_ns(desc) > timeout_ns))
4821 timeout_ns = xhci_service_interval_to_ns(desc);
4823 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4824 if (u2_del_ns > timeout_ns)
4825 timeout_ns = u2_del_ns;
4830 /* Returns the hub-encoded U2 timeout value. */
4831 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4832 struct usb_device *udev,
4833 struct usb_endpoint_descriptor *desc)
4835 unsigned long long timeout_ns;
4837 /* Prevent U2 if service interval is shorter than U2 exit latency */
4838 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4839 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4840 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4841 return USB3_LPM_DISABLED;
4845 if (xhci->quirks & XHCI_INTEL_HOST)
4846 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4848 timeout_ns = udev->u2_params.sel;
4850 /* The U2 timeout is encoded in 256us intervals */
4851 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4852 /* If the necessary timeout value is bigger than what we can set in the
4853 * USB 3.0 hub, we have to disable hub-initiated U2.
4855 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4857 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4858 "due to long timeout %llu ms\n", timeout_ns);
4859 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4862 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4863 struct usb_device *udev,
4864 struct usb_endpoint_descriptor *desc,
4865 enum usb3_link_state state,
4868 if (state == USB3_LPM_U1)
4869 return xhci_calculate_u1_timeout(xhci, udev, desc);
4870 else if (state == USB3_LPM_U2)
4871 return xhci_calculate_u2_timeout(xhci, udev, desc);
4873 return USB3_LPM_DISABLED;
4876 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4877 struct usb_device *udev,
4878 struct usb_endpoint_descriptor *desc,
4879 enum usb3_link_state state,
4884 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4885 desc, state, timeout);
4887 /* If we found we can't enable hub-initiated LPM, and
4888 * the U1 or U2 exit latency was too high to allow
4889 * device-initiated LPM as well, then we will disable LPM
4890 * for this device, so stop searching any further.
4892 if (alt_timeout == USB3_LPM_DISABLED) {
4893 *timeout = alt_timeout;
4896 if (alt_timeout > *timeout)
4897 *timeout = alt_timeout;
4901 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4902 struct usb_device *udev,
4903 struct usb_host_interface *alt,
4904 enum usb3_link_state state,
4909 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4910 if (xhci_update_timeout_for_endpoint(xhci, udev,
4911 &alt->endpoint[j].desc, state, timeout))
4918 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4919 enum usb3_link_state state)
4921 struct usb_device *parent;
4922 unsigned int num_hubs;
4924 if (state == USB3_LPM_U2)
4927 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4928 for (parent = udev->parent, num_hubs = 0; parent->parent;
4929 parent = parent->parent)
4935 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4936 " below second-tier hub.\n");
4937 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4938 "to decrease power consumption.\n");
4942 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4943 struct usb_device *udev,
4944 enum usb3_link_state state)
4946 if (xhci->quirks & XHCI_INTEL_HOST)
4947 return xhci_check_intel_tier_policy(udev, state);
4952 /* Returns the U1 or U2 timeout that should be enabled.
4953 * If the tier check or timeout setting functions return with a non-zero exit
4954 * code, that means the timeout value has been finalized and we shouldn't look
4955 * at any more endpoints.
4957 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4958 struct usb_device *udev, enum usb3_link_state state)
4960 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4961 struct usb_host_config *config;
4964 u16 timeout = USB3_LPM_DISABLED;
4966 if (state == USB3_LPM_U1)
4968 else if (state == USB3_LPM_U2)
4971 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4976 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4979 /* Gather some information about the currently installed configuration
4980 * and alternate interface settings.
4982 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4986 config = udev->actconfig;
4990 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4991 struct usb_driver *driver;
4992 struct usb_interface *intf = config->interface[i];
4997 /* Check if any currently bound drivers want hub-initiated LPM
5000 if (intf->dev.driver) {
5001 driver = to_usb_driver(intf->dev.driver);
5002 if (driver && driver->disable_hub_initiated_lpm) {
5003 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
5004 state_name, driver->name);
5005 timeout = xhci_get_timeout_no_hub_lpm(udev,
5007 if (timeout == USB3_LPM_DISABLED)
5012 /* Not sure how this could happen... */
5013 if (!intf->cur_altsetting)
5016 if (xhci_update_timeout_for_interface(xhci, udev,
5017 intf->cur_altsetting,
5024 static int calculate_max_exit_latency(struct usb_device *udev,
5025 enum usb3_link_state state_changed,
5026 u16 hub_encoded_timeout)
5028 unsigned long long u1_mel_us = 0;
5029 unsigned long long u2_mel_us = 0;
5030 unsigned long long mel_us = 0;
5036 disabling_u1 = (state_changed == USB3_LPM_U1 &&
5037 hub_encoded_timeout == USB3_LPM_DISABLED);
5038 disabling_u2 = (state_changed == USB3_LPM_U2 &&
5039 hub_encoded_timeout == USB3_LPM_DISABLED);
5041 enabling_u1 = (state_changed == USB3_LPM_U1 &&
5042 hub_encoded_timeout != USB3_LPM_DISABLED);
5043 enabling_u2 = (state_changed == USB3_LPM_U2 &&
5044 hub_encoded_timeout != USB3_LPM_DISABLED);
5046 /* If U1 was already enabled and we're not disabling it,
5047 * or we're going to enable U1, account for the U1 max exit latency.
5049 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
5051 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
5052 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
5054 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
5056 if (u1_mel_us > u2_mel_us)
5060 /* xHCI host controller max exit latency field is only 16 bits wide. */
5061 if (mel_us > MAX_EXIT) {
5062 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
5063 "is too big.\n", mel_us);
5069 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
5070 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5071 struct usb_device *udev, enum usb3_link_state state)
5073 struct xhci_hcd *xhci;
5074 u16 hub_encoded_timeout;
5078 xhci = hcd_to_xhci(hcd);
5079 /* The LPM timeout values are pretty host-controller specific, so don't
5080 * enable hub-initiated timeouts unless the vendor has provided
5081 * information about their timeout algorithm.
5083 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5084 !xhci->devs[udev->slot_id])
5085 return USB3_LPM_DISABLED;
5087 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
5088 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
5090 /* Max Exit Latency is too big, disable LPM. */
5091 hub_encoded_timeout = USB3_LPM_DISABLED;
5095 ret = xhci_change_max_exit_latency(xhci, udev, mel);
5098 return hub_encoded_timeout;
5101 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5102 struct usb_device *udev, enum usb3_link_state state)
5104 struct xhci_hcd *xhci;
5107 xhci = hcd_to_xhci(hcd);
5108 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5109 !xhci->devs[udev->slot_id])
5112 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
5113 return xhci_change_max_exit_latency(xhci, udev, mel);
5115 #else /* CONFIG_PM */
5117 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
5118 struct usb_device *udev, int enable)
5123 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
5128 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5129 struct usb_device *udev, enum usb3_link_state state)
5131 return USB3_LPM_DISABLED;
5134 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5135 struct usb_device *udev, enum usb3_link_state state)
5139 #endif /* CONFIG_PM */
5141 /*-------------------------------------------------------------------------*/
5143 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
5144 * internal data structures for the device.
5146 static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
5147 struct usb_tt *tt, gfp_t mem_flags)
5149 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5150 struct xhci_virt_device *vdev;
5151 struct xhci_command *config_cmd;
5152 struct xhci_input_control_ctx *ctrl_ctx;
5153 struct xhci_slot_ctx *slot_ctx;
5154 unsigned long flags;
5155 unsigned think_time;
5158 /* Ignore root hubs */
5162 vdev = xhci->devs[hdev->slot_id];
5164 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5168 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5172 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5174 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5176 xhci_free_command(xhci, config_cmd);
5180 spin_lock_irqsave(&xhci->lock, flags);
5181 if (hdev->speed == USB_SPEED_HIGH &&
5182 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5183 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5184 xhci_free_command(xhci, config_cmd);
5185 spin_unlock_irqrestore(&xhci->lock, flags);
5189 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5190 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5191 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5192 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5194 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5195 * but it may be already set to 1 when setup an xHCI virtual
5196 * device, so clear it anyway.
5199 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5200 else if (hdev->speed == USB_SPEED_FULL)
5201 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5203 if (xhci->hci_version > 0x95) {
5204 xhci_dbg(xhci, "xHCI version %x needs hub "
5205 "TT think time and number of ports\n",
5206 (unsigned int) xhci->hci_version);
5207 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5208 /* Set TT think time - convert from ns to FS bit times.
5209 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5210 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5212 * xHCI 1.0: this field shall be 0 if the device is not a
5215 think_time = tt->think_time;
5216 if (think_time != 0)
5217 think_time = (think_time / 666) - 1;
5218 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5219 slot_ctx->tt_info |=
5220 cpu_to_le32(TT_THINK_TIME(think_time));
5222 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5223 "TT think time or number of ports\n",
5224 (unsigned int) xhci->hci_version);
5226 slot_ctx->dev_state = 0;
5227 spin_unlock_irqrestore(&xhci->lock, flags);
5229 xhci_dbg(xhci, "Set up %s for hub device.\n",
5230 (xhci->hci_version > 0x95) ?
5231 "configure endpoint" : "evaluate context");
5233 /* Issue and wait for the configure endpoint or
5234 * evaluate context command.
5236 if (xhci->hci_version > 0x95)
5237 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5240 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5243 xhci_free_command(xhci, config_cmd);
5247 static int xhci_get_frame(struct usb_hcd *hcd)
5249 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5250 /* EHCI mods by the periodic size. Why? */
5251 return readl(&xhci->run_regs->microframe_index) >> 3;
5254 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5256 struct xhci_hcd *xhci;
5258 * TODO: Check with DWC3 clients for sysdev according to
5261 struct device *dev = hcd->self.sysdev;
5262 unsigned int minor_rev;
5265 /* Accept arbitrarily long scatter-gather lists */
5266 hcd->self.sg_tablesize = ~0;
5268 /* support to build packet from discontinuous buffers */
5269 hcd->self.no_sg_constraint = 1;
5271 /* XHCI controllers don't stop the ep queue on short packets :| */
5272 hcd->self.no_stop_on_short = 1;
5274 xhci = hcd_to_xhci(hcd);
5276 if (usb_hcd_is_primary_hcd(hcd)) {
5277 xhci->main_hcd = hcd;
5278 xhci->usb2_rhub.hcd = hcd;
5279 /* Mark the first roothub as being USB 2.0.
5280 * The xHCI driver will register the USB 3.0 roothub.
5282 hcd->speed = HCD_USB2;
5283 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5285 * USB 2.0 roothub under xHCI has an integrated TT,
5286 * (rate matching hub) as opposed to having an OHCI/UHCI
5287 * companion controller.
5292 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5293 * should return 0x31 for sbrn, or that the minor revision
5294 * is a two digit BCD containig minor and sub-minor numbers.
5295 * This was later clarified in xHCI 1.2.
5297 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5298 * minor revision set to 0x1 instead of 0x10.
5300 if (xhci->usb3_rhub.min_rev == 0x1)
5303 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5305 switch (minor_rev) {
5307 hcd->speed = HCD_USB32;
5308 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5309 hcd->self.root_hub->rx_lanes = 2;
5310 hcd->self.root_hub->tx_lanes = 2;
5313 hcd->speed = HCD_USB31;
5314 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5317 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5319 minor_rev ? "Enhanced " : "");
5321 xhci->usb3_rhub.hcd = hcd;
5322 /* xHCI private pointer was set in xhci_pci_probe for the second
5323 * registered roothub.
5328 mutex_init(&xhci->mutex);
5329 xhci->cap_regs = hcd->regs;
5330 xhci->op_regs = hcd->regs +
5331 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5332 xhci->run_regs = hcd->regs +
5333 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5334 /* Cache read-only capability registers */
5335 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5336 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5337 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5338 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
5339 xhci->hci_version = HC_VERSION(xhci->hcc_params);
5340 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5341 if (xhci->hci_version > 0x100)
5342 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5344 xhci->quirks |= quirks;
5346 get_quirks(dev, xhci);
5348 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5349 * success event after a short transfer. This quirk will ignore such
5352 if (xhci->hci_version > 0x96)
5353 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5355 /* Make sure the HC is halted. */
5356 retval = xhci_halt(xhci);
5360 xhci_zero_64b_regs(xhci);
5362 xhci_dbg(xhci, "Resetting HCD\n");
5363 /* Reset the internal HC memory state and registers. */
5364 retval = xhci_reset(xhci);
5367 xhci_dbg(xhci, "Reset complete\n");
5370 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5371 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5372 * address memory pointers actually. So, this driver clears the AC64
5373 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5374 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5376 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5377 xhci->hcc_params &= ~BIT(0);
5379 /* Set dma_mask and coherent_dma_mask to 64-bits,
5380 * if xHC supports 64-bit addressing */
5381 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5382 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5383 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5384 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5387 * This is to avoid error in cases where a 32-bit USB
5388 * controller is used on a 64-bit capable system.
5390 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5393 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5394 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5397 xhci_dbg(xhci, "Calling HCD init\n");
5398 /* Initialize HCD and host controller data structures. */
5399 retval = xhci_init(hcd);
5402 xhci_dbg(xhci, "Called HCD init\n");
5404 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5405 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5409 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5411 static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5412 struct usb_host_endpoint *ep)
5414 struct xhci_hcd *xhci;
5415 struct usb_device *udev;
5416 unsigned int slot_id;
5417 unsigned int ep_index;
5418 unsigned long flags;
5420 xhci = hcd_to_xhci(hcd);
5422 spin_lock_irqsave(&xhci->lock, flags);
5423 udev = (struct usb_device *)ep->hcpriv;
5424 slot_id = udev->slot_id;
5425 ep_index = xhci_get_endpoint_index(&ep->desc);
5427 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5428 xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5429 spin_unlock_irqrestore(&xhci->lock, flags);
5432 static const struct hc_driver xhci_hc_driver = {
5433 .description = "xhci-hcd",
5434 .product_desc = "xHCI Host Controller",
5435 .hcd_priv_size = sizeof(struct xhci_hcd),
5438 * generic hardware linkage
5441 .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED |
5445 * basic lifecycle operations
5447 .reset = NULL, /* set in xhci_init_driver() */
5450 .shutdown = xhci_shutdown,
5453 * managing i/o requests and associated device resources
5455 .map_urb_for_dma = xhci_map_urb_for_dma,
5456 .unmap_urb_for_dma = xhci_unmap_urb_for_dma,
5457 .urb_enqueue = xhci_urb_enqueue,
5458 .urb_dequeue = xhci_urb_dequeue,
5459 .alloc_dev = xhci_alloc_dev,
5460 .free_dev = xhci_free_dev,
5461 .alloc_streams = xhci_alloc_streams,
5462 .free_streams = xhci_free_streams,
5463 .add_endpoint = xhci_add_endpoint,
5464 .drop_endpoint = xhci_drop_endpoint,
5465 .endpoint_disable = xhci_endpoint_disable,
5466 .endpoint_reset = xhci_endpoint_reset,
5467 .check_bandwidth = xhci_check_bandwidth,
5468 .reset_bandwidth = xhci_reset_bandwidth,
5469 .address_device = xhci_address_device,
5470 .enable_device = xhci_enable_device,
5471 .update_hub_device = xhci_update_hub_device,
5472 .reset_device = xhci_discover_or_reset_device,
5475 * scheduling support
5477 .get_frame_number = xhci_get_frame,
5482 .hub_control = xhci_hub_control,
5483 .hub_status_data = xhci_hub_status_data,
5484 .bus_suspend = xhci_bus_suspend,
5485 .bus_resume = xhci_bus_resume,
5486 .get_resuming_ports = xhci_get_resuming_ports,
5489 * call back when device connected and addressed
5491 .update_device = xhci_update_device,
5492 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5493 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5494 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5495 .find_raw_port_number = xhci_find_raw_port_number,
5496 .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5499 void xhci_init_driver(struct hc_driver *drv,
5500 const struct xhci_driver_overrides *over)
5504 /* Copy the generic table to drv then apply the overrides */
5505 *drv = xhci_hc_driver;
5508 drv->hcd_priv_size += over->extra_priv_size;
5510 drv->reset = over->reset;
5512 drv->start = over->start;
5515 EXPORT_SYMBOL_GPL(xhci_init_driver);
5517 MODULE_DESCRIPTION(DRIVER_DESC);
5518 MODULE_AUTHOR(DRIVER_AUTHOR);
5519 MODULE_LICENSE("GPL");
5521 static int __init xhci_hcd_init(void)
5524 * Check the compiler generated sizes of structures that must be laid
5525 * out in specific ways for hardware access.
5527 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5528 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5529 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5530 /* xhci_device_control has eight fields, and also
5531 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5533 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5534 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5535 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5536 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5537 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5538 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5539 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5544 xhci_debugfs_create_root();
5550 * If an init function is provided, an exit function must also be provided
5551 * to allow module unload.
5553 static void __exit xhci_hcd_fini(void)
5555 xhci_debugfs_remove_root();
5558 module_init(xhci_hcd_init);
5559 module_exit(xhci_hcd_fini);