1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/iopoll.h>
13 #include <linux/irq.h>
14 #include <linux/log2.h>
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/slab.h>
18 #include <linux/dmi.h>
19 #include <linux/dma-mapping.h>
22 #include "xhci-trace.h"
24 #include "xhci-debugfs.h"
25 #include "xhci-dbgcap.h"
27 #define DRIVER_AUTHOR "Sarah Sharp"
28 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
30 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
32 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
33 static int link_quirk;
34 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
35 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
37 static unsigned long long quirks;
38 module_param(quirks, ullong, S_IRUGO);
39 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
41 static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
43 struct xhci_segment *seg = ring->first_seg;
45 if (!td || !td->start_seg)
48 if (seg == td->start_seg)
51 } while (seg && seg != ring->first_seg);
57 * xhci_handshake - spin reading hc until handshake completes or fails
58 * @ptr: address of hc register to be read
59 * @mask: bits to look at in result of read
60 * @done: value of those bits when handshake succeeds
61 * @usec: timeout in microseconds
63 * Returns negative errno, or zero on success
65 * Success happens when the "mask" bits have the specified value (hardware
66 * handshake done). There are two failure modes: "usec" have passed (major
67 * hardware flakeout), or the register reads as all-ones (hardware removed).
69 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
74 ret = readl_poll_timeout_atomic(ptr, result,
75 (result & mask) == done ||
78 if (result == U32_MAX) /* card removed */
85 * Disable interrupts and begin the xHCI halting process.
87 void xhci_quiesce(struct xhci_hcd *xhci)
94 halted = readl(&xhci->op_regs->status) & STS_HALT;
98 cmd = readl(&xhci->op_regs->command);
100 writel(cmd, &xhci->op_regs->command);
104 * Force HC into halt state.
106 * Disable any IRQs and clear the run/stop bit.
107 * HC will complete any current and actively pipelined transactions, and
108 * should halt within 16 ms of the run/stop bit being cleared.
109 * Read HC Halted bit in the status register to see when the HC is finished.
111 int xhci_halt(struct xhci_hcd *xhci)
114 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
117 ret = xhci_handshake(&xhci->op_regs->status,
118 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
120 xhci_warn(xhci, "Host halt failed, %d\n", ret);
123 xhci->xhc_state |= XHCI_STATE_HALTED;
124 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
129 * Set the run bit and wait for the host to be running.
131 int xhci_start(struct xhci_hcd *xhci)
136 temp = readl(&xhci->op_regs->command);
138 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
140 writel(temp, &xhci->op_regs->command);
143 * Wait for the HCHalted Status bit to be 0 to indicate the host is
146 ret = xhci_handshake(&xhci->op_regs->status,
147 STS_HALT, 0, XHCI_MAX_HALT_USEC);
148 if (ret == -ETIMEDOUT)
149 xhci_err(xhci, "Host took too long to start, "
150 "waited %u microseconds.\n",
153 /* clear state flags. Including dying, halted or removing */
162 * This resets pipelines, timers, counters, state machines, etc.
163 * Transactions will be terminated immediately, and operational registers
164 * will be set to their defaults.
166 int xhci_reset(struct xhci_hcd *xhci)
172 state = readl(&xhci->op_regs->status);
174 if (state == ~(u32)0) {
175 xhci_warn(xhci, "Host not accessible, reset failed.\n");
179 if ((state & STS_HALT) == 0) {
180 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
184 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
185 command = readl(&xhci->op_regs->command);
186 command |= CMD_RESET;
187 writel(command, &xhci->op_regs->command);
189 /* Existing Intel xHCI controllers require a delay of 1 mS,
190 * after setting the CMD_RESET bit, and before accessing any
191 * HC registers. This allows the HC to complete the
192 * reset operation and be ready for HC register access.
193 * Without this delay, the subsequent HC register access,
194 * may result in a system hang very rarely.
196 if (xhci->quirks & XHCI_INTEL_HOST)
199 ret = xhci_handshake(&xhci->op_regs->command,
200 CMD_RESET, 0, 10 * 1000 * 1000);
204 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
205 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
207 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
208 "Wait for controller to be ready for doorbell rings");
210 * xHCI cannot write to any doorbells or operational registers other
211 * than status until the "Controller Not Ready" flag is cleared.
213 ret = xhci_handshake(&xhci->op_regs->status,
214 STS_CNR, 0, 10 * 1000 * 1000);
216 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
217 xhci->usb2_rhub.bus_state.suspended_ports = 0;
218 xhci->usb2_rhub.bus_state.resuming_ports = 0;
219 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
220 xhci->usb3_rhub.bus_state.suspended_ports = 0;
221 xhci->usb3_rhub.bus_state.resuming_ports = 0;
226 static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
228 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
233 * Some Renesas controllers get into a weird state if they are
234 * reset while programmed with 64bit addresses (they will preserve
235 * the top half of the address in internal, non visible
236 * registers). You end up with half the address coming from the
237 * kernel, and the other half coming from the firmware. Also,
238 * changing the programming leads to extra accesses even if the
239 * controller is supposed to be halted. The controller ends up with
240 * a fatal fault, and is then ripe for being properly reset.
242 * Special care is taken to only apply this if the device is behind
243 * an iommu. Doing anything when there is no iommu is definitely
246 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !device_iommu_mapped(dev))
249 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
251 /* Clear HSEIE so that faults do not get signaled */
252 val = readl(&xhci->op_regs->command);
254 writel(val, &xhci->op_regs->command);
256 /* Clear HSE (aka FATAL) */
257 val = readl(&xhci->op_regs->status);
259 writel(val, &xhci->op_regs->status);
261 /* Now zero the registers, and brace for impact */
262 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
263 if (upper_32_bits(val))
264 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
265 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
266 if (upper_32_bits(val))
267 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
269 for (i = 0; i < HCS_MAX_INTRS(xhci->hcs_params1); i++) {
270 struct xhci_intr_reg __iomem *ir;
272 ir = &xhci->run_regs->ir_set[i];
273 val = xhci_read_64(xhci, &ir->erst_base);
274 if (upper_32_bits(val))
275 xhci_write_64(xhci, 0, &ir->erst_base);
276 val= xhci_read_64(xhci, &ir->erst_dequeue);
277 if (upper_32_bits(val))
278 xhci_write_64(xhci, 0, &ir->erst_dequeue);
281 /* Wait for the fault to appear. It will be cleared on reset */
282 err = xhci_handshake(&xhci->op_regs->status,
283 STS_FATAL, STS_FATAL,
286 xhci_info(xhci, "Fault detected\n");
289 #ifdef CONFIG_USB_PCI
293 static int xhci_setup_msi(struct xhci_hcd *xhci)
297 * TODO:Check with MSI Soc for sysdev
299 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
301 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
303 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
304 "failed to allocate MSI entry");
308 ret = request_irq(pdev->irq, xhci_msi_irq,
309 0, "xhci_hcd", xhci_to_hcd(xhci));
311 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
312 "disable MSI interrupt");
313 pci_free_irq_vectors(pdev);
322 static int xhci_setup_msix(struct xhci_hcd *xhci)
325 struct usb_hcd *hcd = xhci_to_hcd(xhci);
326 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
329 * calculate number of msi-x vectors supported.
330 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
331 * with max number of interrupters based on the xhci HCSPARAMS1.
332 * - num_online_cpus: maximum msi-x vectors per CPUs core.
333 * Add additional 1 vector to ensure always available interrupt.
335 xhci->msix_count = min(num_online_cpus() + 1,
336 HCS_MAX_INTRS(xhci->hcs_params1));
338 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
341 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
342 "Failed to enable MSI-X");
346 for (i = 0; i < xhci->msix_count; i++) {
347 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
348 "xhci_hcd", xhci_to_hcd(xhci));
353 hcd->msix_enabled = 1;
357 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
359 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
360 pci_free_irq_vectors(pdev);
364 /* Free any IRQs and disable MSI-X */
365 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
367 struct usb_hcd *hcd = xhci_to_hcd(xhci);
368 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
370 if (xhci->quirks & XHCI_PLAT)
373 /* return if using legacy interrupt */
377 if (hcd->msix_enabled) {
380 for (i = 0; i < xhci->msix_count; i++)
381 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
383 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
386 pci_free_irq_vectors(pdev);
387 hcd->msix_enabled = 0;
390 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
392 struct usb_hcd *hcd = xhci_to_hcd(xhci);
394 if (hcd->msix_enabled) {
395 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
398 for (i = 0; i < xhci->msix_count; i++)
399 synchronize_irq(pci_irq_vector(pdev, i));
403 static int xhci_try_enable_msi(struct usb_hcd *hcd)
405 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
406 struct pci_dev *pdev;
409 /* The xhci platform device has set up IRQs through usb_add_hcd. */
410 if (xhci->quirks & XHCI_PLAT)
413 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
415 * Some Fresco Logic host controllers advertise MSI, but fail to
416 * generate interrupts. Don't even try to enable MSI.
418 if (xhci->quirks & XHCI_BROKEN_MSI)
421 /* unregister the legacy interrupt */
423 free_irq(hcd->irq, hcd);
426 ret = xhci_setup_msix(xhci);
428 /* fall back to msi*/
429 ret = xhci_setup_msi(xhci);
432 hcd->msi_enabled = 1;
437 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
442 if (!strlen(hcd->irq_descr))
443 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
444 hcd->driver->description, hcd->self.busnum);
446 /* fall back to legacy interrupt*/
447 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
448 hcd->irq_descr, hcd);
450 xhci_err(xhci, "request interrupt %d failed\n",
454 hcd->irq = pdev->irq;
460 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
465 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
469 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
475 static void compliance_mode_recovery(struct timer_list *t)
477 struct xhci_hcd *xhci;
479 struct xhci_hub *rhub;
483 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
484 rhub = &xhci->usb3_rhub;
486 for (i = 0; i < rhub->num_ports; i++) {
487 temp = readl(rhub->ports[i]->addr);
488 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
490 * Compliance Mode Detected. Letting USB Core
491 * handle the Warm Reset
493 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
494 "Compliance mode detected->port %d",
496 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
497 "Attempting compliance mode recovery");
498 hcd = xhci->shared_hcd;
500 if (hcd->state == HC_STATE_SUSPENDED)
501 usb_hcd_resume_root_hub(hcd);
503 usb_hcd_poll_rh_status(hcd);
507 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
508 mod_timer(&xhci->comp_mode_recovery_timer,
509 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
513 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
514 * that causes ports behind that hardware to enter compliance mode sometimes.
515 * The quirk creates a timer that polls every 2 seconds the link state of
516 * each host controller's port and recovers it by issuing a Warm reset
517 * if Compliance mode is detected, otherwise the port will become "dead" (no
518 * device connections or disconnections will be detected anymore). Becasue no
519 * status event is generated when entering compliance mode (per xhci spec),
520 * this quirk is needed on systems that have the failing hardware installed.
522 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
524 xhci->port_status_u0 = 0;
525 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
527 xhci->comp_mode_recovery_timer.expires = jiffies +
528 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
530 add_timer(&xhci->comp_mode_recovery_timer);
531 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
532 "Compliance mode recovery timer initialized");
536 * This function identifies the systems that have installed the SN65LVPE502CP
537 * USB3.0 re-driver and that need the Compliance Mode Quirk.
539 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
541 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
543 const char *dmi_product_name, *dmi_sys_vendor;
545 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
546 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
547 if (!dmi_product_name || !dmi_sys_vendor)
550 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
553 if (strstr(dmi_product_name, "Z420") ||
554 strstr(dmi_product_name, "Z620") ||
555 strstr(dmi_product_name, "Z820") ||
556 strstr(dmi_product_name, "Z1 Workstation"))
562 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
564 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
569 * Initialize memory for HCD and xHC (one-time init).
571 * Program the PAGESIZE register, initialize the device context array, create
572 * device contexts (?), set up a command ring segment (or two?), create event
573 * ring (one for now).
575 static int xhci_init(struct usb_hcd *hcd)
577 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
580 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
581 spin_lock_init(&xhci->lock);
582 if (xhci->hci_version == 0x95 && link_quirk) {
583 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
584 "QUIRK: Not clearing Link TRB chain bits.");
585 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
587 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
588 "xHCI doesn't need link TRB QUIRK");
590 retval = xhci_mem_init(xhci, GFP_KERNEL);
591 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
593 /* Initializing Compliance Mode Recovery Data If Needed */
594 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
595 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
596 compliance_mode_recovery_timer_init(xhci);
602 /*-------------------------------------------------------------------------*/
605 static int xhci_run_finished(struct xhci_hcd *xhci)
607 if (xhci_start(xhci)) {
611 xhci->shared_hcd->state = HC_STATE_RUNNING;
612 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
614 if (xhci->quirks & XHCI_NEC_HOST)
615 xhci_ring_cmd_db(xhci);
617 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
618 "Finished xhci_run for USB3 roothub");
623 * Start the HC after it was halted.
625 * This function is called by the USB core when the HC driver is added.
626 * Its opposite is xhci_stop().
628 * xhci_init() must be called once before this function can be called.
629 * Reset the HC, enable device slot contexts, program DCBAAP, and
630 * set command ring pointer and event ring pointer.
632 * Setup MSI-X vectors and enable interrupts.
634 int xhci_run(struct usb_hcd *hcd)
639 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
641 /* Start the xHCI host controller running only after the USB 2.0 roothub
645 hcd->uses_new_polling = 1;
646 if (!usb_hcd_is_primary_hcd(hcd))
647 return xhci_run_finished(xhci);
649 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
651 ret = xhci_try_enable_msi(hcd);
655 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
656 temp_64 &= ~ERST_PTR_MASK;
657 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
658 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
660 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
661 "// Set the interrupt modulation register");
662 temp = readl(&xhci->ir_set->irq_control);
663 temp &= ~ER_IRQ_INTERVAL_MASK;
664 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
665 writel(temp, &xhci->ir_set->irq_control);
667 /* Set the HCD state before we enable the irqs */
668 temp = readl(&xhci->op_regs->command);
670 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
671 "// Enable interrupts, cmd = 0x%x.", temp);
672 writel(temp, &xhci->op_regs->command);
674 temp = readl(&xhci->ir_set->irq_pending);
675 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
676 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
677 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
678 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
680 if (xhci->quirks & XHCI_NEC_HOST) {
681 struct xhci_command *command;
683 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
687 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
688 TRB_TYPE(TRB_NEC_GET_FW));
690 xhci_free_command(xhci, command);
692 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
693 "Finished xhci_run for USB2 roothub");
697 xhci_debugfs_init(xhci);
701 EXPORT_SYMBOL_GPL(xhci_run);
706 * This function is called by the USB core when the HC driver is removed.
707 * Its opposite is xhci_run().
709 * Disable device contexts, disable IRQs, and quiesce the HC.
710 * Reset the HC, finish any completed transactions, and cleanup memory.
712 static void xhci_stop(struct usb_hcd *hcd)
715 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
717 mutex_lock(&xhci->mutex);
719 /* Only halt host and free memory after both hcds are removed */
720 if (!usb_hcd_is_primary_hcd(hcd)) {
721 mutex_unlock(&xhci->mutex);
727 spin_lock_irq(&xhci->lock);
728 xhci->xhc_state |= XHCI_STATE_HALTED;
729 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
732 spin_unlock_irq(&xhci->lock);
734 xhci_cleanup_msix(xhci);
736 /* Deleting Compliance Mode Recovery Timer */
737 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
738 (!(xhci_all_ports_seen_u0(xhci)))) {
739 del_timer_sync(&xhci->comp_mode_recovery_timer);
740 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
741 "%s: compliance mode recovery timer deleted",
745 if (xhci->quirks & XHCI_AMD_PLL_FIX)
748 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
749 "// Disabling event ring interrupts");
750 temp = readl(&xhci->op_regs->status);
751 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
752 temp = readl(&xhci->ir_set->irq_pending);
753 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
755 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
756 xhci_mem_cleanup(xhci);
757 xhci_debugfs_exit(xhci);
758 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
759 "xhci_stop completed - status = %x",
760 readl(&xhci->op_regs->status));
761 mutex_unlock(&xhci->mutex);
765 * Shutdown HC (not bus-specific)
767 * This is called when the machine is rebooting or halting. We assume that the
768 * machine will be powered off, and the HC's internal state will be reset.
769 * Don't bother to free memory.
771 * This will only ever be called with the main usb_hcd (the USB3 roothub).
773 void xhci_shutdown(struct usb_hcd *hcd)
775 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
777 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
778 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
780 spin_lock_irq(&xhci->lock);
782 /* Workaround for spurious wakeups at shutdown with HSW */
783 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
785 spin_unlock_irq(&xhci->lock);
787 xhci_cleanup_msix(xhci);
789 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
790 "xhci_shutdown completed - status = %x",
791 readl(&xhci->op_regs->status));
793 EXPORT_SYMBOL_GPL(xhci_shutdown);
796 static void xhci_save_registers(struct xhci_hcd *xhci)
798 xhci->s3.command = readl(&xhci->op_regs->command);
799 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
800 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
801 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
802 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
803 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
804 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
805 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
806 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
809 static void xhci_restore_registers(struct xhci_hcd *xhci)
811 writel(xhci->s3.command, &xhci->op_regs->command);
812 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
813 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
814 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
815 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
816 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
817 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
818 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
819 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
822 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
826 /* step 2: initialize command ring buffer */
827 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
828 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
829 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
830 xhci->cmd_ring->dequeue) &
831 (u64) ~CMD_RING_RSVD_BITS) |
832 xhci->cmd_ring->cycle_state;
833 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
834 "// Setting command ring address to 0x%llx",
835 (long unsigned long) val_64);
836 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
840 * The whole command ring must be cleared to zero when we suspend the host.
842 * The host doesn't save the command ring pointer in the suspend well, so we
843 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
844 * aligned, because of the reserved bits in the command ring dequeue pointer
845 * register. Therefore, we can't just set the dequeue pointer back in the
846 * middle of the ring (TRBs are 16-byte aligned).
848 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
850 struct xhci_ring *ring;
851 struct xhci_segment *seg;
853 ring = xhci->cmd_ring;
857 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
858 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
859 cpu_to_le32(~TRB_CYCLE);
861 } while (seg != ring->deq_seg);
863 /* Reset the software enqueue and dequeue pointers */
864 ring->deq_seg = ring->first_seg;
865 ring->dequeue = ring->first_seg->trbs;
866 ring->enq_seg = ring->deq_seg;
867 ring->enqueue = ring->dequeue;
869 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
871 * Ring is now zeroed, so the HW should look for change of ownership
872 * when the cycle bit is set to 1.
874 ring->cycle_state = 1;
877 * Reset the hardware dequeue pointer.
878 * Yes, this will need to be re-written after resume, but we're paranoid
879 * and want to make sure the hardware doesn't access bogus memory
880 * because, say, the BIOS or an SMI started the host without changing
881 * the command ring pointers.
883 xhci_set_cmd_ring_deq(xhci);
886 static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
888 struct xhci_port **ports;
893 spin_lock_irqsave(&xhci->lock, flags);
895 /* disable usb3 ports Wake bits */
896 port_index = xhci->usb3_rhub.num_ports;
897 ports = xhci->usb3_rhub.ports;
898 while (port_index--) {
899 t1 = readl(ports[port_index]->addr);
901 t1 = xhci_port_state_to_neutral(t1);
902 t2 = t1 & ~PORT_WAKE_BITS;
904 writel(t2, ports[port_index]->addr);
905 xhci_dbg(xhci, "disable wake bits port %d-%d, portsc: 0x%x, write: 0x%x\n",
906 xhci->usb3_rhub.hcd->self.busnum,
907 port_index + 1, portsc, t2);
911 /* disable usb2 ports Wake bits */
912 port_index = xhci->usb2_rhub.num_ports;
913 ports = xhci->usb2_rhub.ports;
914 while (port_index--) {
915 t1 = readl(ports[port_index]->addr);
917 t1 = xhci_port_state_to_neutral(t1);
918 t2 = t1 & ~PORT_WAKE_BITS;
920 writel(t2, ports[port_index]->addr);
921 xhci_dbg(xhci, "disable wake bits port %d-%d, portsc: 0x%x, write: 0x%x\n",
922 xhci->usb2_rhub.hcd->self.busnum,
923 port_index + 1, portsc, t2);
926 spin_unlock_irqrestore(&xhci->lock, flags);
929 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
931 struct xhci_port **ports;
936 status = readl(&xhci->op_regs->status);
937 if (status & STS_EINT)
940 * Checking STS_EINT is not enough as there is a lag between a change
941 * bit being set and the Port Status Change Event that it generated
942 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
945 port_index = xhci->usb2_rhub.num_ports;
946 ports = xhci->usb2_rhub.ports;
947 while (port_index--) {
948 portsc = readl(ports[port_index]->addr);
949 if (portsc & PORT_CHANGE_MASK ||
950 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
953 port_index = xhci->usb3_rhub.num_ports;
954 ports = xhci->usb3_rhub.ports;
955 while (port_index--) {
956 portsc = readl(ports[port_index]->addr);
957 if (portsc & PORT_CHANGE_MASK ||
958 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
965 * Stop HC (not bus-specific)
967 * This is called when the machine transition into S3/S4 mode.
970 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
973 unsigned int delay = XHCI_MAX_HALT_USEC * 2;
974 struct usb_hcd *hcd = xhci_to_hcd(xhci);
981 if (hcd->state != HC_STATE_SUSPENDED ||
982 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
985 /* Clear root port wake on bits if wakeup not allowed. */
987 xhci_disable_port_wake_on_bits(xhci);
989 if (!HCD_HW_ACCESSIBLE(hcd))
992 xhci_dbc_suspend(xhci);
994 /* Don't poll the roothubs on bus suspend. */
995 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
996 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
997 del_timer_sync(&hcd->rh_timer);
998 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
999 del_timer_sync(&xhci->shared_hcd->rh_timer);
1001 if (xhci->quirks & XHCI_SUSPEND_DELAY)
1002 usleep_range(1000, 1500);
1004 spin_lock_irq(&xhci->lock);
1005 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1006 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1007 /* step 1: stop endpoint */
1008 /* skipped assuming that port suspend has done */
1010 /* step 2: clear Run/Stop bit */
1011 command = readl(&xhci->op_regs->command);
1012 command &= ~CMD_RUN;
1013 writel(command, &xhci->op_regs->command);
1015 /* Some chips from Fresco Logic need an extraordinary delay */
1016 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
1018 if (xhci_handshake(&xhci->op_regs->status,
1019 STS_HALT, STS_HALT, delay)) {
1020 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
1021 spin_unlock_irq(&xhci->lock);
1024 xhci_clear_command_ring(xhci);
1026 /* step 3: save registers */
1027 xhci_save_registers(xhci);
1029 /* step 4: set CSS flag */
1030 command = readl(&xhci->op_regs->command);
1032 writel(command, &xhci->op_regs->command);
1033 xhci->broken_suspend = 0;
1034 if (xhci_handshake(&xhci->op_regs->status,
1035 STS_SAVE, 0, 20 * 1000)) {
1037 * AMD SNPS xHC 3.0 occasionally does not clear the
1038 * SSS bit of USBSTS and when driver tries to poll
1039 * to see if the xHC clears BIT(8) which never happens
1040 * and driver assumes that controller is not responding
1041 * and times out. To workaround this, its good to check
1042 * if SRE and HCE bits are not set (as per xhci
1043 * Section 5.4.2) and bypass the timeout.
1045 res = readl(&xhci->op_regs->status);
1046 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
1047 (((res & STS_SRE) == 0) &&
1048 ((res & STS_HCE) == 0))) {
1049 xhci->broken_suspend = 1;
1051 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1052 spin_unlock_irq(&xhci->lock);
1056 spin_unlock_irq(&xhci->lock);
1059 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1060 * is about to be suspended.
1062 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1063 (!(xhci_all_ports_seen_u0(xhci)))) {
1064 del_timer_sync(&xhci->comp_mode_recovery_timer);
1065 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1066 "%s: compliance mode recovery timer deleted",
1070 /* step 5: remove core well power */
1071 /* synchronize irq when using MSI-X */
1072 xhci_msix_sync_irqs(xhci);
1076 EXPORT_SYMBOL_GPL(xhci_suspend);
1079 * start xHC (not bus-specific)
1081 * This is called when the machine transition from S3/S4 mode.
1084 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1086 u32 command, temp = 0;
1087 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1088 struct usb_hcd *secondary_hcd;
1090 bool comp_timer_running = false;
1091 bool pending_portevent = false;
1096 /* Wait a bit if either of the roothubs need to settle from the
1097 * transition into bus suspend.
1100 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1101 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1104 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1105 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1107 spin_lock_irq(&xhci->lock);
1108 if ((xhci->quirks & XHCI_RESET_ON_RESUME) || xhci->broken_suspend)
1113 * Some controllers might lose power during suspend, so wait
1114 * for controller not ready bit to clear, just as in xHC init.
1116 retval = xhci_handshake(&xhci->op_regs->status,
1117 STS_CNR, 0, 10 * 1000 * 1000);
1119 xhci_warn(xhci, "Controller not ready at resume %d\n",
1121 spin_unlock_irq(&xhci->lock);
1124 /* step 1: restore register */
1125 xhci_restore_registers(xhci);
1126 /* step 2: initialize command ring buffer */
1127 xhci_set_cmd_ring_deq(xhci);
1128 /* step 3: restore state and start state*/
1129 /* step 3: set CRS flag */
1130 command = readl(&xhci->op_regs->command);
1132 writel(command, &xhci->op_regs->command);
1134 * Some controllers take up to 55+ ms to complete the controller
1135 * restore so setting the timeout to 100ms. Xhci specification
1136 * doesn't mention any timeout value.
1138 if (xhci_handshake(&xhci->op_regs->status,
1139 STS_RESTORE, 0, 100 * 1000)) {
1140 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1141 spin_unlock_irq(&xhci->lock);
1144 temp = readl(&xhci->op_regs->status);
1147 /* If restore operation fails, re-initialize the HC during resume */
1148 if ((temp & STS_SRE) || hibernated) {
1150 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1151 !(xhci_all_ports_seen_u0(xhci))) {
1152 del_timer_sync(&xhci->comp_mode_recovery_timer);
1153 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1154 "Compliance Mode Recovery Timer deleted!");
1157 /* Let the USB core know _both_ roothubs lost power. */
1158 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1159 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1161 xhci_dbg(xhci, "Stop HCD\n");
1163 xhci_zero_64b_regs(xhci);
1164 retval = xhci_reset(xhci);
1165 spin_unlock_irq(&xhci->lock);
1168 xhci_cleanup_msix(xhci);
1170 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1171 temp = readl(&xhci->op_regs->status);
1172 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1173 temp = readl(&xhci->ir_set->irq_pending);
1174 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1176 xhci_dbg(xhci, "cleaning up memory\n");
1177 xhci_mem_cleanup(xhci);
1178 xhci_debugfs_exit(xhci);
1179 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1180 readl(&xhci->op_regs->status));
1182 /* USB core calls the PCI reinit and start functions twice:
1183 * first with the primary HCD, and then with the secondary HCD.
1184 * If we don't do the same, the host will never be started.
1186 if (!usb_hcd_is_primary_hcd(hcd))
1187 secondary_hcd = hcd;
1189 secondary_hcd = xhci->shared_hcd;
1191 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1192 retval = xhci_init(hcd->primary_hcd);
1195 comp_timer_running = true;
1197 xhci_dbg(xhci, "Start the primary HCD\n");
1198 retval = xhci_run(hcd->primary_hcd);
1200 xhci_dbg(xhci, "Start the secondary HCD\n");
1201 retval = xhci_run(secondary_hcd);
1203 hcd->state = HC_STATE_SUSPENDED;
1204 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1208 /* step 4: set Run/Stop bit */
1209 command = readl(&xhci->op_regs->command);
1211 writel(command, &xhci->op_regs->command);
1212 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1215 /* step 5: walk topology and initialize portsc,
1216 * portpmsc and portli
1218 /* this is done in bus_resume */
1220 /* step 6: restart each of the previously
1221 * Running endpoints by ringing their doorbells
1224 spin_unlock_irq(&xhci->lock);
1226 xhci_dbc_resume(xhci);
1231 * Resume roothubs only if there are pending events.
1232 * USB 3 devices resend U3 LFPS wake after a 100ms delay if
1233 * the first wake signalling failed, give it that chance.
1235 pending_portevent = xhci_pending_portevent(xhci);
1236 if (!pending_portevent) {
1238 pending_portevent = xhci_pending_portevent(xhci);
1241 if (pending_portevent) {
1242 usb_hcd_resume_root_hub(xhci->shared_hcd);
1243 usb_hcd_resume_root_hub(hcd);
1247 * If system is subject to the Quirk, Compliance Mode Timer needs to
1248 * be re-initialized Always after a system resume. Ports are subject
1249 * to suffer the Compliance Mode issue again. It doesn't matter if
1250 * ports have entered previously to U0 before system's suspension.
1252 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1253 compliance_mode_recovery_timer_init(xhci);
1255 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1256 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1258 /* Re-enable port polling. */
1259 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1260 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1261 usb_hcd_poll_rh_status(xhci->shared_hcd);
1262 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1263 usb_hcd_poll_rh_status(hcd);
1267 EXPORT_SYMBOL_GPL(xhci_resume);
1268 #endif /* CONFIG_PM */
1270 /*-------------------------------------------------------------------------*/
1272 static int xhci_map_temp_buffer(struct usb_hcd *hcd, struct urb *urb)
1276 unsigned int buf_len;
1277 enum dma_data_direction dir;
1279 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1280 buf_len = urb->transfer_buffer_length;
1282 temp = kzalloc_node(buf_len, GFP_ATOMIC,
1283 dev_to_node(hcd->self.sysdev));
1285 if (usb_urb_dir_out(urb))
1286 sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
1289 urb->transfer_buffer = temp;
1290 urb->transfer_dma = dma_map_single(hcd->self.sysdev,
1291 urb->transfer_buffer,
1292 urb->transfer_buffer_length,
1295 if (dma_mapping_error(hcd->self.sysdev,
1296 urb->transfer_dma)) {
1300 urb->transfer_flags |= URB_DMA_MAP_SINGLE;
1306 static bool xhci_urb_temp_buffer_required(struct usb_hcd *hcd,
1311 unsigned int len = 0;
1312 unsigned int trb_size;
1313 unsigned int max_pkt;
1314 struct scatterlist *sg;
1315 struct scatterlist *tail_sg;
1318 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
1323 if (urb->dev->speed >= USB_SPEED_SUPER)
1324 trb_size = TRB_CACHE_SIZE_SS;
1326 trb_size = TRB_CACHE_SIZE_HS;
1328 if (urb->transfer_buffer_length != 0 &&
1329 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)) {
1330 for_each_sg(urb->sg, sg, urb->num_sgs, i) {
1331 len = len + sg->length;
1332 if (i > trb_size - 2) {
1333 len = len - tail_sg->length;
1334 if (len < max_pkt) {
1339 tail_sg = sg_next(tail_sg);
1346 static void xhci_unmap_temp_buf(struct usb_hcd *hcd, struct urb *urb)
1349 unsigned int buf_len;
1350 enum dma_data_direction dir;
1352 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1354 buf_len = urb->transfer_buffer_length;
1356 if (IS_ENABLED(CONFIG_HAS_DMA) &&
1357 (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1358 dma_unmap_single(hcd->self.sysdev,
1360 urb->transfer_buffer_length,
1363 if (usb_urb_dir_in(urb))
1364 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs,
1365 urb->transfer_buffer,
1369 urb->transfer_flags &= ~URB_DMA_MAP_SINGLE;
1370 kfree(urb->transfer_buffer);
1371 urb->transfer_buffer = NULL;
1375 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1376 * we'll copy the actual data into the TRB address register. This is limited to
1377 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1378 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1380 static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1383 struct xhci_hcd *xhci;
1385 xhci = hcd_to_xhci(hcd);
1387 if (xhci_urb_suitable_for_idt(urb))
1390 if (xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) {
1391 if (xhci_urb_temp_buffer_required(hcd, urb))
1392 return xhci_map_temp_buffer(hcd, urb);
1394 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1397 static void xhci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
1399 struct xhci_hcd *xhci;
1400 bool unmap_temp_buf = false;
1402 xhci = hcd_to_xhci(hcd);
1404 if (urb->num_sgs && (urb->transfer_flags & URB_DMA_MAP_SINGLE))
1405 unmap_temp_buf = true;
1407 if ((xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) && unmap_temp_buf)
1408 xhci_unmap_temp_buf(hcd, urb);
1410 usb_hcd_unmap_urb_for_dma(hcd, urb);
1414 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1415 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1416 * value to right shift 1 for the bitmask.
1418 * Index = (epnum * 2) + direction - 1,
1419 * where direction = 0 for OUT, 1 for IN.
1420 * For control endpoints, the IN index is used (OUT index is unused), so
1421 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1423 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1426 if (usb_endpoint_xfer_control(desc))
1427 index = (unsigned int) (usb_endpoint_num(desc)*2);
1429 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1430 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1434 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1435 * address from the XHCI endpoint index.
1437 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1439 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1440 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1441 return direction | number;
1444 /* Find the flag for this endpoint (for use in the control context). Use the
1445 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1448 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1450 return 1 << (xhci_get_endpoint_index(desc) + 1);
1453 /* Compute the last valid endpoint context index. Basically, this is the
1454 * endpoint index plus one. For slot contexts with more than valid endpoint,
1455 * we find the most significant bit set in the added contexts flags.
1456 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1457 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1459 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1461 return fls(added_ctxs) - 1;
1464 /* Returns 1 if the arguments are OK;
1465 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1467 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1468 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1470 struct xhci_hcd *xhci;
1471 struct xhci_virt_device *virt_dev;
1473 if (!hcd || (check_ep && !ep) || !udev) {
1474 pr_debug("xHCI %s called with invalid args\n", func);
1477 if (!udev->parent) {
1478 pr_debug("xHCI %s called for root hub\n", func);
1482 xhci = hcd_to_xhci(hcd);
1483 if (check_virt_dev) {
1484 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1485 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1490 virt_dev = xhci->devs[udev->slot_id];
1491 if (virt_dev->udev != udev) {
1492 xhci_dbg(xhci, "xHCI %s called with udev and "
1493 "virt_dev does not match\n", func);
1498 if (xhci->xhc_state & XHCI_STATE_HALTED)
1504 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1505 struct usb_device *udev, struct xhci_command *command,
1506 bool ctx_change, bool must_succeed);
1509 * Full speed devices may have a max packet size greater than 8 bytes, but the
1510 * USB core doesn't know that until it reads the first 8 bytes of the
1511 * descriptor. If the usb_device's max packet size changes after that point,
1512 * we need to issue an evaluate context command and wait on it.
1514 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1515 unsigned int ep_index, struct urb *urb)
1517 struct xhci_container_ctx *out_ctx;
1518 struct xhci_input_control_ctx *ctrl_ctx;
1519 struct xhci_ep_ctx *ep_ctx;
1520 struct xhci_command *command;
1521 int max_packet_size;
1522 int hw_max_packet_size;
1525 out_ctx = xhci->devs[slot_id]->out_ctx;
1526 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1527 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1528 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1529 if (hw_max_packet_size != max_packet_size) {
1530 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1531 "Max Packet Size for ep 0 changed.");
1532 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1533 "Max packet size in usb_device = %d",
1535 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1536 "Max packet size in xHCI HW = %d",
1537 hw_max_packet_size);
1538 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1539 "Issuing evaluate context command.");
1541 /* Set up the input context flags for the command */
1542 /* FIXME: This won't work if a non-default control endpoint
1543 * changes max packet sizes.
1546 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
1550 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1551 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1553 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1556 goto command_cleanup;
1558 /* Set up the modified control endpoint 0 */
1559 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1560 xhci->devs[slot_id]->out_ctx, ep_index);
1562 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1563 ep_ctx->ep_info &= cpu_to_le32(~EP_STATE_MASK);/* must clear */
1564 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1565 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1567 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1568 ctrl_ctx->drop_flags = 0;
1570 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1573 /* Clean up the input context for later use by bandwidth
1576 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1578 kfree(command->completion);
1585 * non-error returns are a promise to giveback() the urb later
1586 * we drop ownership so next owner (or urb unlink) can get it
1588 static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1590 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1591 unsigned long flags;
1593 unsigned int slot_id, ep_index;
1594 unsigned int *ep_state;
1595 struct urb_priv *urb_priv;
1598 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1599 true, true, __func__) <= 0)
1602 slot_id = urb->dev->slot_id;
1603 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1604 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1606 if (!HCD_HW_ACCESSIBLE(hcd))
1609 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1610 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1614 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1615 num_tds = urb->number_of_packets;
1616 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1617 urb->transfer_buffer_length > 0 &&
1618 urb->transfer_flags & URB_ZERO_PACKET &&
1619 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1624 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1628 urb_priv->num_tds = num_tds;
1629 urb_priv->num_tds_done = 0;
1630 urb->hcpriv = urb_priv;
1632 trace_xhci_urb_enqueue(urb);
1634 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1635 /* Check to see if the max packet size for the default control
1636 * endpoint changed during FS device enumeration
1638 if (urb->dev->speed == USB_SPEED_FULL) {
1639 ret = xhci_check_maxpacket(xhci, slot_id,
1642 xhci_urb_free_priv(urb_priv);
1649 spin_lock_irqsave(&xhci->lock, flags);
1651 if (xhci->xhc_state & XHCI_STATE_DYING) {
1652 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1653 urb->ep->desc.bEndpointAddress, urb);
1657 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1658 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1663 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1664 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1669 switch (usb_endpoint_type(&urb->ep->desc)) {
1671 case USB_ENDPOINT_XFER_CONTROL:
1672 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1675 case USB_ENDPOINT_XFER_BULK:
1676 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1679 case USB_ENDPOINT_XFER_INT:
1680 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1683 case USB_ENDPOINT_XFER_ISOC:
1684 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1690 xhci_urb_free_priv(urb_priv);
1693 spin_unlock_irqrestore(&xhci->lock, flags);
1698 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1699 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1700 * should pick up where it left off in the TD, unless a Set Transfer Ring
1701 * Dequeue Pointer is issued.
1703 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1704 * the ring. Since the ring is a contiguous structure, they can't be physically
1705 * removed. Instead, there are two options:
1707 * 1) If the HC is in the middle of processing the URB to be canceled, we
1708 * simply move the ring's dequeue pointer past those TRBs using the Set
1709 * Transfer Ring Dequeue Pointer command. This will be the common case,
1710 * when drivers timeout on the last submitted URB and attempt to cancel.
1712 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1713 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1714 * HC will need to invalidate the any TRBs it has cached after the stop
1715 * endpoint command, as noted in the xHCI 0.95 errata.
1717 * 3) The TD may have completed by the time the Stop Endpoint Command
1718 * completes, so software needs to handle that case too.
1720 * This function should protect against the TD enqueueing code ringing the
1721 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1722 * It also needs to account for multiple cancellations on happening at the same
1723 * time for the same endpoint.
1725 * Note that this function can be called in any context, or so says
1726 * usb_hcd_unlink_urb()
1728 static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1730 unsigned long flags;
1733 struct xhci_hcd *xhci;
1734 struct urb_priv *urb_priv;
1736 unsigned int ep_index;
1737 struct xhci_ring *ep_ring;
1738 struct xhci_virt_ep *ep;
1739 struct xhci_command *command;
1740 struct xhci_virt_device *vdev;
1742 xhci = hcd_to_xhci(hcd);
1743 spin_lock_irqsave(&xhci->lock, flags);
1745 trace_xhci_urb_dequeue(urb);
1747 /* Make sure the URB hasn't completed or been unlinked already */
1748 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1752 /* give back URB now if we can't queue it for cancel */
1753 vdev = xhci->devs[urb->dev->slot_id];
1754 urb_priv = urb->hcpriv;
1755 if (!vdev || !urb_priv)
1758 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1759 ep = &vdev->eps[ep_index];
1760 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1761 if (!ep || !ep_ring)
1764 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1765 temp = readl(&xhci->op_regs->status);
1766 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1772 * check ring is not re-allocated since URB was enqueued. If it is, then
1773 * make sure none of the ring related pointers in this URB private data
1774 * are touched, such as td_list, otherwise we overwrite freed data
1776 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1777 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1778 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1779 td = &urb_priv->td[i];
1780 if (!list_empty(&td->cancelled_td_list))
1781 list_del_init(&td->cancelled_td_list);
1786 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1787 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1788 "HC halted, freeing TD manually.");
1789 for (i = urb_priv->num_tds_done;
1790 i < urb_priv->num_tds;
1792 td = &urb_priv->td[i];
1793 if (!list_empty(&td->td_list))
1794 list_del_init(&td->td_list);
1795 if (!list_empty(&td->cancelled_td_list))
1796 list_del_init(&td->cancelled_td_list);
1801 i = urb_priv->num_tds_done;
1802 if (i < urb_priv->num_tds)
1803 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1804 "Cancel URB %p, dev %s, ep 0x%x, "
1805 "starting at offset 0x%llx",
1806 urb, urb->dev->devpath,
1807 urb->ep->desc.bEndpointAddress,
1808 (unsigned long long) xhci_trb_virt_to_dma(
1809 urb_priv->td[i].start_seg,
1810 urb_priv->td[i].first_trb));
1812 for (; i < urb_priv->num_tds; i++) {
1813 td = &urb_priv->td[i];
1814 /* TD can already be on cancelled list if ep halted on it */
1815 if (list_empty(&td->cancelled_td_list)) {
1816 td->cancel_status = TD_DIRTY;
1817 list_add_tail(&td->cancelled_td_list,
1818 &ep->cancelled_td_list);
1822 /* Queue a stop endpoint command, but only if this is
1823 * the first cancellation to be handled.
1825 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1826 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1831 ep->ep_state |= EP_STOP_CMD_PENDING;
1832 ep->stop_cmd_timer.expires = jiffies +
1833 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1834 add_timer(&ep->stop_cmd_timer);
1835 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1837 xhci_ring_cmd_db(xhci);
1840 spin_unlock_irqrestore(&xhci->lock, flags);
1845 xhci_urb_free_priv(urb_priv);
1846 usb_hcd_unlink_urb_from_ep(hcd, urb);
1847 spin_unlock_irqrestore(&xhci->lock, flags);
1848 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1852 /* Drop an endpoint from a new bandwidth configuration for this device.
1853 * Only one call to this function is allowed per endpoint before
1854 * check_bandwidth() or reset_bandwidth() must be called.
1855 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1856 * add the endpoint to the schedule with possibly new parameters denoted by a
1857 * different endpoint descriptor in usb_host_endpoint.
1858 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1861 * The USB core will not allow URBs to be queued to an endpoint that is being
1862 * disabled, so there's no need for mutual exclusion to protect
1863 * the xhci->devs[slot_id] structure.
1865 static int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1866 struct usb_host_endpoint *ep)
1868 struct xhci_hcd *xhci;
1869 struct xhci_container_ctx *in_ctx, *out_ctx;
1870 struct xhci_input_control_ctx *ctrl_ctx;
1871 unsigned int ep_index;
1872 struct xhci_ep_ctx *ep_ctx;
1874 u32 new_add_flags, new_drop_flags;
1877 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1880 xhci = hcd_to_xhci(hcd);
1881 if (xhci->xhc_state & XHCI_STATE_DYING)
1884 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1885 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1886 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1887 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1888 __func__, drop_flag);
1892 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1893 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1894 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1896 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1901 ep_index = xhci_get_endpoint_index(&ep->desc);
1902 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1903 /* If the HC already knows the endpoint is disabled,
1904 * or the HCD has noted it is disabled, ignore this request
1906 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1907 le32_to_cpu(ctrl_ctx->drop_flags) &
1908 xhci_get_endpoint_flag(&ep->desc)) {
1909 /* Do not warn when called after a usb_device_reset */
1910 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1911 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1916 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1917 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1919 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1920 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1922 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1924 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1926 if (xhci->quirks & XHCI_MTK_HOST)
1927 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1929 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1930 (unsigned int) ep->desc.bEndpointAddress,
1932 (unsigned int) new_drop_flags,
1933 (unsigned int) new_add_flags);
1937 /* Add an endpoint to a new possible bandwidth configuration for this device.
1938 * Only one call to this function is allowed per endpoint before
1939 * check_bandwidth() or reset_bandwidth() must be called.
1940 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1941 * add the endpoint to the schedule with possibly new parameters denoted by a
1942 * different endpoint descriptor in usb_host_endpoint.
1943 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1946 * The USB core will not allow URBs to be queued to an endpoint until the
1947 * configuration or alt setting is installed in the device, so there's no need
1948 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1950 static int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1951 struct usb_host_endpoint *ep)
1953 struct xhci_hcd *xhci;
1954 struct xhci_container_ctx *in_ctx;
1955 unsigned int ep_index;
1956 struct xhci_input_control_ctx *ctrl_ctx;
1957 struct xhci_ep_ctx *ep_ctx;
1959 u32 new_add_flags, new_drop_flags;
1960 struct xhci_virt_device *virt_dev;
1963 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1965 /* So we won't queue a reset ep command for a root hub */
1969 xhci = hcd_to_xhci(hcd);
1970 if (xhci->xhc_state & XHCI_STATE_DYING)
1973 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1974 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1975 /* FIXME when we have to issue an evaluate endpoint command to
1976 * deal with ep0 max packet size changing once we get the
1979 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1980 __func__, added_ctxs);
1984 virt_dev = xhci->devs[udev->slot_id];
1985 in_ctx = virt_dev->in_ctx;
1986 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1988 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1993 ep_index = xhci_get_endpoint_index(&ep->desc);
1994 /* If this endpoint is already in use, and the upper layers are trying
1995 * to add it again without dropping it, reject the addition.
1997 if (virt_dev->eps[ep_index].ring &&
1998 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1999 xhci_warn(xhci, "Trying to add endpoint 0x%x "
2000 "without dropping it.\n",
2001 (unsigned int) ep->desc.bEndpointAddress);
2005 /* If the HCD has already noted the endpoint is enabled,
2006 * ignore this request.
2008 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
2009 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
2015 * Configuration and alternate setting changes must be done in
2016 * process context, not interrupt context (or so documenation
2017 * for usb_set_interface() and usb_set_configuration() claim).
2019 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
2020 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
2021 __func__, ep->desc.bEndpointAddress);
2025 if (xhci->quirks & XHCI_MTK_HOST) {
2026 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
2028 xhci_ring_free(xhci, virt_dev->eps[ep_index].new_ring);
2029 virt_dev->eps[ep_index].new_ring = NULL;
2034 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
2035 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
2037 /* If xhci_endpoint_disable() was called for this endpoint, but the
2038 * xHC hasn't been notified yet through the check_bandwidth() call,
2039 * this re-adds a new state for the endpoint from the new endpoint
2040 * descriptors. We must drop and re-add this endpoint, so we leave the
2043 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
2045 /* Store the usb_device pointer for later use */
2048 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
2049 trace_xhci_add_endpoint(ep_ctx);
2051 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
2052 (unsigned int) ep->desc.bEndpointAddress,
2054 (unsigned int) new_drop_flags,
2055 (unsigned int) new_add_flags);
2059 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
2061 struct xhci_input_control_ctx *ctrl_ctx;
2062 struct xhci_ep_ctx *ep_ctx;
2063 struct xhci_slot_ctx *slot_ctx;
2066 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
2068 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2073 /* When a device's add flag and drop flag are zero, any subsequent
2074 * configure endpoint command will leave that endpoint's state
2075 * untouched. Make sure we don't leave any old state in the input
2076 * endpoint contexts.
2078 ctrl_ctx->drop_flags = 0;
2079 ctrl_ctx->add_flags = 0;
2080 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2081 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2082 /* Endpoint 0 is always valid */
2083 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
2084 for (i = 1; i < 31; i++) {
2085 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
2086 ep_ctx->ep_info = 0;
2087 ep_ctx->ep_info2 = 0;
2089 ep_ctx->tx_info = 0;
2093 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
2094 struct usb_device *udev, u32 *cmd_status)
2098 switch (*cmd_status) {
2099 case COMP_COMMAND_ABORTED:
2100 case COMP_COMMAND_RING_STOPPED:
2101 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
2104 case COMP_RESOURCE_ERROR:
2105 dev_warn(&udev->dev,
2106 "Not enough host controller resources for new device state.\n");
2108 /* FIXME: can we allocate more resources for the HC? */
2110 case COMP_BANDWIDTH_ERROR:
2111 case COMP_SECONDARY_BANDWIDTH_ERROR:
2112 dev_warn(&udev->dev,
2113 "Not enough bandwidth for new device state.\n");
2115 /* FIXME: can we go back to the old state? */
2117 case COMP_TRB_ERROR:
2118 /* the HCD set up something wrong */
2119 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
2121 "and endpoint is not disabled.\n");
2124 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2125 dev_warn(&udev->dev,
2126 "ERROR: Incompatible device for endpoint configure command.\n");
2130 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2131 "Successful Endpoint Configure command");
2135 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2143 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2144 struct usb_device *udev, u32 *cmd_status)
2148 switch (*cmd_status) {
2149 case COMP_COMMAND_ABORTED:
2150 case COMP_COMMAND_RING_STOPPED:
2151 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2154 case COMP_PARAMETER_ERROR:
2155 dev_warn(&udev->dev,
2156 "WARN: xHCI driver setup invalid evaluate context command.\n");
2159 case COMP_SLOT_NOT_ENABLED_ERROR:
2160 dev_warn(&udev->dev,
2161 "WARN: slot not enabled for evaluate context command.\n");
2164 case COMP_CONTEXT_STATE_ERROR:
2165 dev_warn(&udev->dev,
2166 "WARN: invalid context state for evaluate context command.\n");
2169 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2170 dev_warn(&udev->dev,
2171 "ERROR: Incompatible device for evaluate context command.\n");
2174 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2175 /* Max Exit Latency too large error */
2176 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2180 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2181 "Successful evaluate context command");
2185 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2193 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2194 struct xhci_input_control_ctx *ctrl_ctx)
2196 u32 valid_add_flags;
2197 u32 valid_drop_flags;
2199 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2200 * (bit 1). The default control endpoint is added during the Address
2201 * Device command and is never removed until the slot is disabled.
2203 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2204 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2206 /* Use hweight32 to count the number of ones in the add flags, or
2207 * number of endpoints added. Don't count endpoints that are changed
2208 * (both added and dropped).
2210 return hweight32(valid_add_flags) -
2211 hweight32(valid_add_flags & valid_drop_flags);
2214 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2215 struct xhci_input_control_ctx *ctrl_ctx)
2217 u32 valid_add_flags;
2218 u32 valid_drop_flags;
2220 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2221 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2223 return hweight32(valid_drop_flags) -
2224 hweight32(valid_add_flags & valid_drop_flags);
2228 * We need to reserve the new number of endpoints before the configure endpoint
2229 * command completes. We can't subtract the dropped endpoints from the number
2230 * of active endpoints until the command completes because we can oversubscribe
2231 * the host in this case:
2233 * - the first configure endpoint command drops more endpoints than it adds
2234 * - a second configure endpoint command that adds more endpoints is queued
2235 * - the first configure endpoint command fails, so the config is unchanged
2236 * - the second command may succeed, even though there isn't enough resources
2238 * Must be called with xhci->lock held.
2240 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2241 struct xhci_input_control_ctx *ctrl_ctx)
2245 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2246 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2247 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2248 "Not enough ep ctxs: "
2249 "%u active, need to add %u, limit is %u.",
2250 xhci->num_active_eps, added_eps,
2251 xhci->limit_active_eps);
2254 xhci->num_active_eps += added_eps;
2255 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2256 "Adding %u ep ctxs, %u now active.", added_eps,
2257 xhci->num_active_eps);
2262 * The configure endpoint was failed by the xHC for some other reason, so we
2263 * need to revert the resources that failed configuration would have used.
2265 * Must be called with xhci->lock held.
2267 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2268 struct xhci_input_control_ctx *ctrl_ctx)
2272 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2273 xhci->num_active_eps -= num_failed_eps;
2274 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2275 "Removing %u failed ep ctxs, %u now active.",
2277 xhci->num_active_eps);
2281 * Now that the command has completed, clean up the active endpoint count by
2282 * subtracting out the endpoints that were dropped (but not changed).
2284 * Must be called with xhci->lock held.
2286 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2287 struct xhci_input_control_ctx *ctrl_ctx)
2289 u32 num_dropped_eps;
2291 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2292 xhci->num_active_eps -= num_dropped_eps;
2293 if (num_dropped_eps)
2294 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2295 "Removing %u dropped ep ctxs, %u now active.",
2297 xhci->num_active_eps);
2300 static unsigned int xhci_get_block_size(struct usb_device *udev)
2302 switch (udev->speed) {
2304 case USB_SPEED_FULL:
2306 case USB_SPEED_HIGH:
2308 case USB_SPEED_SUPER:
2309 case USB_SPEED_SUPER_PLUS:
2311 case USB_SPEED_UNKNOWN:
2312 case USB_SPEED_WIRELESS:
2314 /* Should never happen */
2320 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2322 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2324 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2329 /* If we are changing a LS/FS device under a HS hub,
2330 * make sure (if we are activating a new TT) that the HS bus has enough
2331 * bandwidth for this new TT.
2333 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2334 struct xhci_virt_device *virt_dev,
2337 struct xhci_interval_bw_table *bw_table;
2338 struct xhci_tt_bw_info *tt_info;
2340 /* Find the bandwidth table for the root port this TT is attached to. */
2341 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2342 tt_info = virt_dev->tt_info;
2343 /* If this TT already had active endpoints, the bandwidth for this TT
2344 * has already been added. Removing all periodic endpoints (and thus
2345 * making the TT enactive) will only decrease the bandwidth used.
2349 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2350 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2354 /* Not sure why we would have no new active endpoints...
2356 * Maybe because of an Evaluate Context change for a hub update or a
2357 * control endpoint 0 max packet size change?
2358 * FIXME: skip the bandwidth calculation in that case.
2363 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2364 struct xhci_virt_device *virt_dev)
2366 unsigned int bw_reserved;
2368 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2369 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2372 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2373 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2380 * This algorithm is a very conservative estimate of the worst-case scheduling
2381 * scenario for any one interval. The hardware dynamically schedules the
2382 * packets, so we can't tell which microframe could be the limiting factor in
2383 * the bandwidth scheduling. This only takes into account periodic endpoints.
2385 * Obviously, we can't solve an NP complete problem to find the minimum worst
2386 * case scenario. Instead, we come up with an estimate that is no less than
2387 * the worst case bandwidth used for any one microframe, but may be an
2390 * We walk the requirements for each endpoint by interval, starting with the
2391 * smallest interval, and place packets in the schedule where there is only one
2392 * possible way to schedule packets for that interval. In order to simplify
2393 * this algorithm, we record the largest max packet size for each interval, and
2394 * assume all packets will be that size.
2396 * For interval 0, we obviously must schedule all packets for each interval.
2397 * The bandwidth for interval 0 is just the amount of data to be transmitted
2398 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2399 * the number of packets).
2401 * For interval 1, we have two possible microframes to schedule those packets
2402 * in. For this algorithm, if we can schedule the same number of packets for
2403 * each possible scheduling opportunity (each microframe), we will do so. The
2404 * remaining number of packets will be saved to be transmitted in the gaps in
2405 * the next interval's scheduling sequence.
2407 * As we move those remaining packets to be scheduled with interval 2 packets,
2408 * we have to double the number of remaining packets to transmit. This is
2409 * because the intervals are actually powers of 2, and we would be transmitting
2410 * the previous interval's packets twice in this interval. We also have to be
2411 * sure that when we look at the largest max packet size for this interval, we
2412 * also look at the largest max packet size for the remaining packets and take
2413 * the greater of the two.
2415 * The algorithm continues to evenly distribute packets in each scheduling
2416 * opportunity, and push the remaining packets out, until we get to the last
2417 * interval. Then those packets and their associated overhead are just added
2418 * to the bandwidth used.
2420 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2421 struct xhci_virt_device *virt_dev,
2424 unsigned int bw_reserved;
2425 unsigned int max_bandwidth;
2426 unsigned int bw_used;
2427 unsigned int block_size;
2428 struct xhci_interval_bw_table *bw_table;
2429 unsigned int packet_size = 0;
2430 unsigned int overhead = 0;
2431 unsigned int packets_transmitted = 0;
2432 unsigned int packets_remaining = 0;
2435 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2436 return xhci_check_ss_bw(xhci, virt_dev);
2438 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2439 max_bandwidth = HS_BW_LIMIT;
2440 /* Convert percent of bus BW reserved to blocks reserved */
2441 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2443 max_bandwidth = FS_BW_LIMIT;
2444 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2447 bw_table = virt_dev->bw_table;
2448 /* We need to translate the max packet size and max ESIT payloads into
2449 * the units the hardware uses.
2451 block_size = xhci_get_block_size(virt_dev->udev);
2453 /* If we are manipulating a LS/FS device under a HS hub, double check
2454 * that the HS bus has enough bandwidth if we are activing a new TT.
2456 if (virt_dev->tt_info) {
2457 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2458 "Recalculating BW for rootport %u",
2459 virt_dev->real_port);
2460 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2461 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2462 "newly activated TT.\n");
2465 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2466 "Recalculating BW for TT slot %u port %u",
2467 virt_dev->tt_info->slot_id,
2468 virt_dev->tt_info->ttport);
2470 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2471 "Recalculating BW for rootport %u",
2472 virt_dev->real_port);
2475 /* Add in how much bandwidth will be used for interval zero, or the
2476 * rounded max ESIT payload + number of packets * largest overhead.
2478 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2479 bw_table->interval_bw[0].num_packets *
2480 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2482 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2483 unsigned int bw_added;
2484 unsigned int largest_mps;
2485 unsigned int interval_overhead;
2488 * How many packets could we transmit in this interval?
2489 * If packets didn't fit in the previous interval, we will need
2490 * to transmit that many packets twice within this interval.
2492 packets_remaining = 2 * packets_remaining +
2493 bw_table->interval_bw[i].num_packets;
2495 /* Find the largest max packet size of this or the previous
2498 if (list_empty(&bw_table->interval_bw[i].endpoints))
2501 struct xhci_virt_ep *virt_ep;
2502 struct list_head *ep_entry;
2504 ep_entry = bw_table->interval_bw[i].endpoints.next;
2505 virt_ep = list_entry(ep_entry,
2506 struct xhci_virt_ep, bw_endpoint_list);
2507 /* Convert to blocks, rounding up */
2508 largest_mps = DIV_ROUND_UP(
2509 virt_ep->bw_info.max_packet_size,
2512 if (largest_mps > packet_size)
2513 packet_size = largest_mps;
2515 /* Use the larger overhead of this or the previous interval. */
2516 interval_overhead = xhci_get_largest_overhead(
2517 &bw_table->interval_bw[i]);
2518 if (interval_overhead > overhead)
2519 overhead = interval_overhead;
2521 /* How many packets can we evenly distribute across
2522 * (1 << (i + 1)) possible scheduling opportunities?
2524 packets_transmitted = packets_remaining >> (i + 1);
2526 /* Add in the bandwidth used for those scheduled packets */
2527 bw_added = packets_transmitted * (overhead + packet_size);
2529 /* How many packets do we have remaining to transmit? */
2530 packets_remaining = packets_remaining % (1 << (i + 1));
2532 /* What largest max packet size should those packets have? */
2533 /* If we've transmitted all packets, don't carry over the
2534 * largest packet size.
2536 if (packets_remaining == 0) {
2539 } else if (packets_transmitted > 0) {
2540 /* Otherwise if we do have remaining packets, and we've
2541 * scheduled some packets in this interval, take the
2542 * largest max packet size from endpoints with this
2545 packet_size = largest_mps;
2546 overhead = interval_overhead;
2548 /* Otherwise carry over packet_size and overhead from the last
2549 * time we had a remainder.
2551 bw_used += bw_added;
2552 if (bw_used > max_bandwidth) {
2553 xhci_warn(xhci, "Not enough bandwidth. "
2554 "Proposed: %u, Max: %u\n",
2555 bw_used, max_bandwidth);
2560 * Ok, we know we have some packets left over after even-handedly
2561 * scheduling interval 15. We don't know which microframes they will
2562 * fit into, so we over-schedule and say they will be scheduled every
2565 if (packets_remaining > 0)
2566 bw_used += overhead + packet_size;
2568 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2569 unsigned int port_index = virt_dev->real_port - 1;
2571 /* OK, we're manipulating a HS device attached to a
2572 * root port bandwidth domain. Include the number of active TTs
2573 * in the bandwidth used.
2575 bw_used += TT_HS_OVERHEAD *
2576 xhci->rh_bw[port_index].num_active_tts;
2579 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2580 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2581 "Available: %u " "percent",
2582 bw_used, max_bandwidth, bw_reserved,
2583 (max_bandwidth - bw_used - bw_reserved) * 100 /
2586 bw_used += bw_reserved;
2587 if (bw_used > max_bandwidth) {
2588 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2589 bw_used, max_bandwidth);
2593 bw_table->bw_used = bw_used;
2597 static bool xhci_is_async_ep(unsigned int ep_type)
2599 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2600 ep_type != ISOC_IN_EP &&
2601 ep_type != INT_IN_EP);
2604 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2606 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2609 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2611 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2613 if (ep_bw->ep_interval == 0)
2614 return SS_OVERHEAD_BURST +
2615 (ep_bw->mult * ep_bw->num_packets *
2616 (SS_OVERHEAD + mps));
2617 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2618 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2619 1 << ep_bw->ep_interval);
2623 static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2624 struct xhci_bw_info *ep_bw,
2625 struct xhci_interval_bw_table *bw_table,
2626 struct usb_device *udev,
2627 struct xhci_virt_ep *virt_ep,
2628 struct xhci_tt_bw_info *tt_info)
2630 struct xhci_interval_bw *interval_bw;
2631 int normalized_interval;
2633 if (xhci_is_async_ep(ep_bw->type))
2636 if (udev->speed >= USB_SPEED_SUPER) {
2637 if (xhci_is_sync_in_ep(ep_bw->type))
2638 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2639 xhci_get_ss_bw_consumed(ep_bw);
2641 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2642 xhci_get_ss_bw_consumed(ep_bw);
2646 /* SuperSpeed endpoints never get added to intervals in the table, so
2647 * this check is only valid for HS/FS/LS devices.
2649 if (list_empty(&virt_ep->bw_endpoint_list))
2651 /* For LS/FS devices, we need to translate the interval expressed in
2652 * microframes to frames.
2654 if (udev->speed == USB_SPEED_HIGH)
2655 normalized_interval = ep_bw->ep_interval;
2657 normalized_interval = ep_bw->ep_interval - 3;
2659 if (normalized_interval == 0)
2660 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2661 interval_bw = &bw_table->interval_bw[normalized_interval];
2662 interval_bw->num_packets -= ep_bw->num_packets;
2663 switch (udev->speed) {
2665 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2667 case USB_SPEED_FULL:
2668 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2670 case USB_SPEED_HIGH:
2671 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2673 case USB_SPEED_SUPER:
2674 case USB_SPEED_SUPER_PLUS:
2675 case USB_SPEED_UNKNOWN:
2676 case USB_SPEED_WIRELESS:
2677 /* Should never happen because only LS/FS/HS endpoints will get
2678 * added to the endpoint list.
2683 tt_info->active_eps -= 1;
2684 list_del_init(&virt_ep->bw_endpoint_list);
2687 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2688 struct xhci_bw_info *ep_bw,
2689 struct xhci_interval_bw_table *bw_table,
2690 struct usb_device *udev,
2691 struct xhci_virt_ep *virt_ep,
2692 struct xhci_tt_bw_info *tt_info)
2694 struct xhci_interval_bw *interval_bw;
2695 struct xhci_virt_ep *smaller_ep;
2696 int normalized_interval;
2698 if (xhci_is_async_ep(ep_bw->type))
2701 if (udev->speed == USB_SPEED_SUPER) {
2702 if (xhci_is_sync_in_ep(ep_bw->type))
2703 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2704 xhci_get_ss_bw_consumed(ep_bw);
2706 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2707 xhci_get_ss_bw_consumed(ep_bw);
2711 /* For LS/FS devices, we need to translate the interval expressed in
2712 * microframes to frames.
2714 if (udev->speed == USB_SPEED_HIGH)
2715 normalized_interval = ep_bw->ep_interval;
2717 normalized_interval = ep_bw->ep_interval - 3;
2719 if (normalized_interval == 0)
2720 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2721 interval_bw = &bw_table->interval_bw[normalized_interval];
2722 interval_bw->num_packets += ep_bw->num_packets;
2723 switch (udev->speed) {
2725 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2727 case USB_SPEED_FULL:
2728 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2730 case USB_SPEED_HIGH:
2731 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2733 case USB_SPEED_SUPER:
2734 case USB_SPEED_SUPER_PLUS:
2735 case USB_SPEED_UNKNOWN:
2736 case USB_SPEED_WIRELESS:
2737 /* Should never happen because only LS/FS/HS endpoints will get
2738 * added to the endpoint list.
2744 tt_info->active_eps += 1;
2745 /* Insert the endpoint into the list, largest max packet size first. */
2746 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2748 if (ep_bw->max_packet_size >=
2749 smaller_ep->bw_info.max_packet_size) {
2750 /* Add the new ep before the smaller endpoint */
2751 list_add_tail(&virt_ep->bw_endpoint_list,
2752 &smaller_ep->bw_endpoint_list);
2756 /* Add the new endpoint at the end of the list. */
2757 list_add_tail(&virt_ep->bw_endpoint_list,
2758 &interval_bw->endpoints);
2761 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2762 struct xhci_virt_device *virt_dev,
2765 struct xhci_root_port_bw_info *rh_bw_info;
2766 if (!virt_dev->tt_info)
2769 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2770 if (old_active_eps == 0 &&
2771 virt_dev->tt_info->active_eps != 0) {
2772 rh_bw_info->num_active_tts += 1;
2773 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2774 } else if (old_active_eps != 0 &&
2775 virt_dev->tt_info->active_eps == 0) {
2776 rh_bw_info->num_active_tts -= 1;
2777 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2781 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2782 struct xhci_virt_device *virt_dev,
2783 struct xhci_container_ctx *in_ctx)
2785 struct xhci_bw_info ep_bw_info[31];
2787 struct xhci_input_control_ctx *ctrl_ctx;
2788 int old_active_eps = 0;
2790 if (virt_dev->tt_info)
2791 old_active_eps = virt_dev->tt_info->active_eps;
2793 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2795 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2800 for (i = 0; i < 31; i++) {
2801 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2804 /* Make a copy of the BW info in case we need to revert this */
2805 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2806 sizeof(ep_bw_info[i]));
2807 /* Drop the endpoint from the interval table if the endpoint is
2808 * being dropped or changed.
2810 if (EP_IS_DROPPED(ctrl_ctx, i))
2811 xhci_drop_ep_from_interval_table(xhci,
2812 &virt_dev->eps[i].bw_info,
2818 /* Overwrite the information stored in the endpoints' bw_info */
2819 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2820 for (i = 0; i < 31; i++) {
2821 /* Add any changed or added endpoints to the interval table */
2822 if (EP_IS_ADDED(ctrl_ctx, i))
2823 xhci_add_ep_to_interval_table(xhci,
2824 &virt_dev->eps[i].bw_info,
2831 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2832 /* Ok, this fits in the bandwidth we have.
2833 * Update the number of active TTs.
2835 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2839 /* We don't have enough bandwidth for this, revert the stored info. */
2840 for (i = 0; i < 31; i++) {
2841 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2844 /* Drop the new copies of any added or changed endpoints from
2845 * the interval table.
2847 if (EP_IS_ADDED(ctrl_ctx, i)) {
2848 xhci_drop_ep_from_interval_table(xhci,
2849 &virt_dev->eps[i].bw_info,
2855 /* Revert the endpoint back to its old information */
2856 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2857 sizeof(ep_bw_info[i]));
2858 /* Add any changed or dropped endpoints back into the table */
2859 if (EP_IS_DROPPED(ctrl_ctx, i))
2860 xhci_add_ep_to_interval_table(xhci,
2861 &virt_dev->eps[i].bw_info,
2871 /* Issue a configure endpoint command or evaluate context command
2872 * and wait for it to finish.
2874 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2875 struct usb_device *udev,
2876 struct xhci_command *command,
2877 bool ctx_change, bool must_succeed)
2880 unsigned long flags;
2881 struct xhci_input_control_ctx *ctrl_ctx;
2882 struct xhci_virt_device *virt_dev;
2883 struct xhci_slot_ctx *slot_ctx;
2888 spin_lock_irqsave(&xhci->lock, flags);
2890 if (xhci->xhc_state & XHCI_STATE_DYING) {
2891 spin_unlock_irqrestore(&xhci->lock, flags);
2895 virt_dev = xhci->devs[udev->slot_id];
2897 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2899 spin_unlock_irqrestore(&xhci->lock, flags);
2900 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2905 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2906 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2907 spin_unlock_irqrestore(&xhci->lock, flags);
2908 xhci_warn(xhci, "Not enough host resources, "
2909 "active endpoint contexts = %u\n",
2910 xhci->num_active_eps);
2913 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2914 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2915 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2916 xhci_free_host_resources(xhci, ctrl_ctx);
2917 spin_unlock_irqrestore(&xhci->lock, flags);
2918 xhci_warn(xhci, "Not enough bandwidth\n");
2922 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2924 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
2925 trace_xhci_configure_endpoint(slot_ctx);
2928 ret = xhci_queue_configure_endpoint(xhci, command,
2929 command->in_ctx->dma,
2930 udev->slot_id, must_succeed);
2932 ret = xhci_queue_evaluate_context(xhci, command,
2933 command->in_ctx->dma,
2934 udev->slot_id, must_succeed);
2936 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2937 xhci_free_host_resources(xhci, ctrl_ctx);
2938 spin_unlock_irqrestore(&xhci->lock, flags);
2939 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2940 "FIXME allocate a new ring segment");
2943 xhci_ring_cmd_db(xhci);
2944 spin_unlock_irqrestore(&xhci->lock, flags);
2946 /* Wait for the configure endpoint command to complete */
2947 wait_for_completion(command->completion);
2950 ret = xhci_configure_endpoint_result(xhci, udev,
2953 ret = xhci_evaluate_context_result(xhci, udev,
2956 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2957 spin_lock_irqsave(&xhci->lock, flags);
2958 /* If the command failed, remove the reserved resources.
2959 * Otherwise, clean up the estimate to include dropped eps.
2962 xhci_free_host_resources(xhci, ctrl_ctx);
2964 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2965 spin_unlock_irqrestore(&xhci->lock, flags);
2970 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2971 struct xhci_virt_device *vdev, int i)
2973 struct xhci_virt_ep *ep = &vdev->eps[i];
2975 if (ep->ep_state & EP_HAS_STREAMS) {
2976 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2977 xhci_get_endpoint_address(i));
2978 xhci_free_stream_info(xhci, ep->stream_info);
2979 ep->stream_info = NULL;
2980 ep->ep_state &= ~EP_HAS_STREAMS;
2984 /* Called after one or more calls to xhci_add_endpoint() or
2985 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2986 * to call xhci_reset_bandwidth().
2988 * Since we are in the middle of changing either configuration or
2989 * installing a new alt setting, the USB core won't allow URBs to be
2990 * enqueued for any endpoint on the old config or interface. Nothing
2991 * else should be touching the xhci->devs[slot_id] structure, so we
2992 * don't need to take the xhci->lock for manipulating that.
2994 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2998 struct xhci_hcd *xhci;
2999 struct xhci_virt_device *virt_dev;
3000 struct xhci_input_control_ctx *ctrl_ctx;
3001 struct xhci_slot_ctx *slot_ctx;
3002 struct xhci_command *command;
3004 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3007 xhci = hcd_to_xhci(hcd);
3008 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3009 (xhci->xhc_state & XHCI_STATE_REMOVING))
3012 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3013 virt_dev = xhci->devs[udev->slot_id];
3015 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3019 command->in_ctx = virt_dev->in_ctx;
3021 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
3022 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3024 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3027 goto command_cleanup;
3029 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3030 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
3031 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
3033 /* Don't issue the command if there's no endpoints to update. */
3034 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
3035 ctrl_ctx->drop_flags == 0) {
3037 goto command_cleanup;
3039 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
3040 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3041 for (i = 31; i >= 1; i--) {
3042 __le32 le32 = cpu_to_le32(BIT(i));
3044 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
3045 || (ctrl_ctx->add_flags & le32) || i == 1) {
3046 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
3047 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
3052 ret = xhci_configure_endpoint(xhci, udev, command,
3055 /* Callee should call reset_bandwidth() */
3056 goto command_cleanup;
3058 /* Free any rings that were dropped, but not changed. */
3059 for (i = 1; i < 31; i++) {
3060 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
3061 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
3062 xhci_free_endpoint_ring(xhci, virt_dev, i);
3063 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3066 xhci_zero_in_ctx(xhci, virt_dev);
3068 * Install any rings for completely new endpoints or changed endpoints,
3069 * and free any old rings from changed endpoints.
3071 for (i = 1; i < 31; i++) {
3072 if (!virt_dev->eps[i].new_ring)
3074 /* Only free the old ring if it exists.
3075 * It may not if this is the first add of an endpoint.
3077 if (virt_dev->eps[i].ring) {
3078 xhci_free_endpoint_ring(xhci, virt_dev, i);
3080 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
3081 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
3082 virt_dev->eps[i].new_ring = NULL;
3083 xhci_debugfs_create_endpoint(xhci, virt_dev, i);
3086 kfree(command->completion);
3092 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
3094 struct xhci_hcd *xhci;
3095 struct xhci_virt_device *virt_dev;
3098 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3101 xhci = hcd_to_xhci(hcd);
3103 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
3104 virt_dev = xhci->devs[udev->slot_id];
3105 /* Free any rings allocated for added endpoints */
3106 for (i = 0; i < 31; i++) {
3107 if (virt_dev->eps[i].new_ring) {
3108 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3109 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
3110 virt_dev->eps[i].new_ring = NULL;
3113 xhci_zero_in_ctx(xhci, virt_dev);
3116 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
3117 struct xhci_container_ctx *in_ctx,
3118 struct xhci_container_ctx *out_ctx,
3119 struct xhci_input_control_ctx *ctrl_ctx,
3120 u32 add_flags, u32 drop_flags)
3122 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
3123 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
3124 xhci_slot_copy(xhci, in_ctx, out_ctx);
3125 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
3128 static void xhci_endpoint_disable(struct usb_hcd *hcd,
3129 struct usb_host_endpoint *host_ep)
3131 struct xhci_hcd *xhci;
3132 struct xhci_virt_device *vdev;
3133 struct xhci_virt_ep *ep;
3134 struct usb_device *udev;
3135 unsigned long flags;
3136 unsigned int ep_index;
3138 xhci = hcd_to_xhci(hcd);
3140 spin_lock_irqsave(&xhci->lock, flags);
3142 udev = (struct usb_device *)host_ep->hcpriv;
3143 if (!udev || !udev->slot_id)
3146 vdev = xhci->devs[udev->slot_id];
3150 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3151 ep = &vdev->eps[ep_index];
3155 /* wait for hub_tt_work to finish clearing hub TT */
3156 if (ep->ep_state & EP_CLEARING_TT) {
3157 spin_unlock_irqrestore(&xhci->lock, flags);
3158 schedule_timeout_uninterruptible(1);
3163 xhci_dbg(xhci, "endpoint disable with ep_state 0x%x\n",
3166 host_ep->hcpriv = NULL;
3167 spin_unlock_irqrestore(&xhci->lock, flags);
3171 * Called after usb core issues a clear halt control message.
3172 * The host side of the halt should already be cleared by a reset endpoint
3173 * command issued when the STALL event was received.
3175 * The reset endpoint command may only be issued to endpoints in the halted
3176 * state. For software that wishes to reset the data toggle or sequence number
3177 * of an endpoint that isn't in the halted state this function will issue a
3178 * configure endpoint command with the Drop and Add bits set for the target
3179 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3182 static void xhci_endpoint_reset(struct usb_hcd *hcd,
3183 struct usb_host_endpoint *host_ep)
3185 struct xhci_hcd *xhci;
3186 struct usb_device *udev;
3187 struct xhci_virt_device *vdev;
3188 struct xhci_virt_ep *ep;
3189 struct xhci_input_control_ctx *ctrl_ctx;
3190 struct xhci_command *stop_cmd, *cfg_cmd;
3191 unsigned int ep_index;
3192 unsigned long flags;
3196 xhci = hcd_to_xhci(hcd);
3197 if (!host_ep->hcpriv)
3199 udev = (struct usb_device *) host_ep->hcpriv;
3200 vdev = xhci->devs[udev->slot_id];
3203 * vdev may be lost due to xHC restore error and re-initialization
3204 * during S3/S4 resume. A new vdev will be allocated later by
3205 * xhci_discover_or_reset_device()
3207 if (!udev->slot_id || !vdev)
3209 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3210 ep = &vdev->eps[ep_index];
3214 /* Bail out if toggle is already being cleared by a endpoint reset */
3215 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3216 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3219 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3220 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3221 usb_endpoint_xfer_isoc(&host_ep->desc))
3224 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3226 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3229 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3233 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3237 spin_lock_irqsave(&xhci->lock, flags);
3239 /* block queuing new trbs and ringing ep doorbell */
3240 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3243 * Make sure endpoint ring is empty before resetting the toggle/seq.
3244 * Driver is required to synchronously cancel all transfer request.
3245 * Stop the endpoint to force xHC to update the output context
3248 if (!list_empty(&ep->ring->td_list)) {
3249 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3250 spin_unlock_irqrestore(&xhci->lock, flags);
3251 xhci_free_command(xhci, cfg_cmd);
3255 err = xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id,
3258 spin_unlock_irqrestore(&xhci->lock, flags);
3259 xhci_free_command(xhci, cfg_cmd);
3260 xhci_dbg(xhci, "%s: Failed to queue stop ep command, %d ",
3265 xhci_ring_cmd_db(xhci);
3266 spin_unlock_irqrestore(&xhci->lock, flags);
3268 wait_for_completion(stop_cmd->completion);
3270 spin_lock_irqsave(&xhci->lock, flags);
3272 /* config ep command clears toggle if add and drop ep flags are set */
3273 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3274 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3275 ctrl_ctx, ep_flag, ep_flag);
3276 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3278 err = xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3279 udev->slot_id, false);
3281 spin_unlock_irqrestore(&xhci->lock, flags);
3282 xhci_free_command(xhci, cfg_cmd);
3283 xhci_dbg(xhci, "%s: Failed to queue config ep command, %d ",
3288 xhci_ring_cmd_db(xhci);
3289 spin_unlock_irqrestore(&xhci->lock, flags);
3291 wait_for_completion(cfg_cmd->completion);
3293 xhci_free_command(xhci, cfg_cmd);
3295 xhci_free_command(xhci, stop_cmd);
3296 if (ep->ep_state & EP_SOFT_CLEAR_TOGGLE)
3297 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3300 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3301 struct usb_device *udev, struct usb_host_endpoint *ep,
3302 unsigned int slot_id)
3305 unsigned int ep_index;
3306 unsigned int ep_state;
3310 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3313 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3314 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3315 " descriptor for ep 0x%x does not support streams\n",
3316 ep->desc.bEndpointAddress);
3320 ep_index = xhci_get_endpoint_index(&ep->desc);
3321 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3322 if (ep_state & EP_HAS_STREAMS ||
3323 ep_state & EP_GETTING_STREAMS) {
3324 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3325 "already has streams set up.\n",
3326 ep->desc.bEndpointAddress);
3327 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3328 "dynamic stream context array reallocation.\n");
3331 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3332 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3333 "endpoint 0x%x; URBs are pending.\n",
3334 ep->desc.bEndpointAddress);
3340 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3341 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3343 unsigned int max_streams;
3345 /* The stream context array size must be a power of two */
3346 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3348 * Find out how many primary stream array entries the host controller
3349 * supports. Later we may use secondary stream arrays (similar to 2nd
3350 * level page entries), but that's an optional feature for xHCI host
3351 * controllers. xHCs must support at least 4 stream IDs.
3353 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3354 if (*num_stream_ctxs > max_streams) {
3355 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3357 *num_stream_ctxs = max_streams;
3358 *num_streams = max_streams;
3362 /* Returns an error code if one of the endpoint already has streams.
3363 * This does not change any data structures, it only checks and gathers
3366 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3367 struct usb_device *udev,
3368 struct usb_host_endpoint **eps, unsigned int num_eps,
3369 unsigned int *num_streams, u32 *changed_ep_bitmask)
3371 unsigned int max_streams;
3372 unsigned int endpoint_flag;
3376 for (i = 0; i < num_eps; i++) {
3377 ret = xhci_check_streams_endpoint(xhci, udev,
3378 eps[i], udev->slot_id);
3382 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3383 if (max_streams < (*num_streams - 1)) {
3384 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3385 eps[i]->desc.bEndpointAddress,
3387 *num_streams = max_streams+1;
3390 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3391 if (*changed_ep_bitmask & endpoint_flag)
3393 *changed_ep_bitmask |= endpoint_flag;
3398 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3399 struct usb_device *udev,
3400 struct usb_host_endpoint **eps, unsigned int num_eps)
3402 u32 changed_ep_bitmask = 0;
3403 unsigned int slot_id;
3404 unsigned int ep_index;
3405 unsigned int ep_state;
3408 slot_id = udev->slot_id;
3409 if (!xhci->devs[slot_id])
3412 for (i = 0; i < num_eps; i++) {
3413 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3414 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3415 /* Are streams already being freed for the endpoint? */
3416 if (ep_state & EP_GETTING_NO_STREAMS) {
3417 xhci_warn(xhci, "WARN Can't disable streams for "
3419 "streams are being disabled already\n",
3420 eps[i]->desc.bEndpointAddress);
3423 /* Are there actually any streams to free? */
3424 if (!(ep_state & EP_HAS_STREAMS) &&
3425 !(ep_state & EP_GETTING_STREAMS)) {
3426 xhci_warn(xhci, "WARN Can't disable streams for "
3428 "streams are already disabled!\n",
3429 eps[i]->desc.bEndpointAddress);
3430 xhci_warn(xhci, "WARN xhci_free_streams() called "
3431 "with non-streams endpoint\n");
3434 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3436 return changed_ep_bitmask;
3440 * The USB device drivers use this function (through the HCD interface in USB
3441 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3442 * coordinate mass storage command queueing across multiple endpoints (basically
3443 * a stream ID == a task ID).
3445 * Setting up streams involves allocating the same size stream context array
3446 * for each endpoint and issuing a configure endpoint command for all endpoints.
3448 * Don't allow the call to succeed if one endpoint only supports one stream
3449 * (which means it doesn't support streams at all).
3451 * Drivers may get less stream IDs than they asked for, if the host controller
3452 * hardware or endpoints claim they can't support the number of requested
3455 static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3456 struct usb_host_endpoint **eps, unsigned int num_eps,
3457 unsigned int num_streams, gfp_t mem_flags)
3460 struct xhci_hcd *xhci;
3461 struct xhci_virt_device *vdev;
3462 struct xhci_command *config_cmd;
3463 struct xhci_input_control_ctx *ctrl_ctx;
3464 unsigned int ep_index;
3465 unsigned int num_stream_ctxs;
3466 unsigned int max_packet;
3467 unsigned long flags;
3468 u32 changed_ep_bitmask = 0;
3473 /* Add one to the number of streams requested to account for
3474 * stream 0 that is reserved for xHCI usage.
3477 xhci = hcd_to_xhci(hcd);
3478 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3481 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3482 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3483 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3484 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3488 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3492 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3494 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3496 xhci_free_command(xhci, config_cmd);
3500 /* Check to make sure all endpoints are not already configured for
3501 * streams. While we're at it, find the maximum number of streams that
3502 * all the endpoints will support and check for duplicate endpoints.
3504 spin_lock_irqsave(&xhci->lock, flags);
3505 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3506 num_eps, &num_streams, &changed_ep_bitmask);
3508 xhci_free_command(xhci, config_cmd);
3509 spin_unlock_irqrestore(&xhci->lock, flags);
3512 if (num_streams <= 1) {
3513 xhci_warn(xhci, "WARN: endpoints can't handle "
3514 "more than one stream.\n");
3515 xhci_free_command(xhci, config_cmd);
3516 spin_unlock_irqrestore(&xhci->lock, flags);
3519 vdev = xhci->devs[udev->slot_id];
3520 /* Mark each endpoint as being in transition, so
3521 * xhci_urb_enqueue() will reject all URBs.
3523 for (i = 0; i < num_eps; i++) {
3524 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3525 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3527 spin_unlock_irqrestore(&xhci->lock, flags);
3529 /* Setup internal data structures and allocate HW data structures for
3530 * streams (but don't install the HW structures in the input context
3531 * until we're sure all memory allocation succeeded).
3533 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3534 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3535 num_stream_ctxs, num_streams);
3537 for (i = 0; i < num_eps; i++) {
3538 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3539 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3540 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3543 max_packet, mem_flags);
3544 if (!vdev->eps[ep_index].stream_info)
3546 /* Set maxPstreams in endpoint context and update deq ptr to
3547 * point to stream context array. FIXME
3551 /* Set up the input context for a configure endpoint command. */
3552 for (i = 0; i < num_eps; i++) {
3553 struct xhci_ep_ctx *ep_ctx;
3555 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3556 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3558 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3559 vdev->out_ctx, ep_index);
3560 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3561 vdev->eps[ep_index].stream_info);
3563 /* Tell the HW to drop its old copy of the endpoint context info
3564 * and add the updated copy from the input context.
3566 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3567 vdev->out_ctx, ctrl_ctx,
3568 changed_ep_bitmask, changed_ep_bitmask);
3570 /* Issue and wait for the configure endpoint command */
3571 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3574 /* xHC rejected the configure endpoint command for some reason, so we
3575 * leave the old ring intact and free our internal streams data
3581 spin_lock_irqsave(&xhci->lock, flags);
3582 for (i = 0; i < num_eps; i++) {
3583 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3584 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3585 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3586 udev->slot_id, ep_index);
3587 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3589 xhci_free_command(xhci, config_cmd);
3590 spin_unlock_irqrestore(&xhci->lock, flags);
3592 for (i = 0; i < num_eps; i++) {
3593 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3594 xhci_debugfs_create_stream_files(xhci, vdev, ep_index);
3596 /* Subtract 1 for stream 0, which drivers can't use */
3597 return num_streams - 1;
3600 /* If it didn't work, free the streams! */
3601 for (i = 0; i < num_eps; i++) {
3602 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3603 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3604 vdev->eps[ep_index].stream_info = NULL;
3605 /* FIXME Unset maxPstreams in endpoint context and
3606 * update deq ptr to point to normal string ring.
3608 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3609 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3610 xhci_endpoint_zero(xhci, vdev, eps[i]);
3612 xhci_free_command(xhci, config_cmd);
3616 /* Transition the endpoint from using streams to being a "normal" endpoint
3619 * Modify the endpoint context state, submit a configure endpoint command,
3620 * and free all endpoint rings for streams if that completes successfully.
3622 static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3623 struct usb_host_endpoint **eps, unsigned int num_eps,
3627 struct xhci_hcd *xhci;
3628 struct xhci_virt_device *vdev;
3629 struct xhci_command *command;
3630 struct xhci_input_control_ctx *ctrl_ctx;
3631 unsigned int ep_index;
3632 unsigned long flags;
3633 u32 changed_ep_bitmask;
3635 xhci = hcd_to_xhci(hcd);
3636 vdev = xhci->devs[udev->slot_id];
3638 /* Set up a configure endpoint command to remove the streams rings */
3639 spin_lock_irqsave(&xhci->lock, flags);
3640 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3641 udev, eps, num_eps);
3642 if (changed_ep_bitmask == 0) {
3643 spin_unlock_irqrestore(&xhci->lock, flags);
3647 /* Use the xhci_command structure from the first endpoint. We may have
3648 * allocated too many, but the driver may call xhci_free_streams() for
3649 * each endpoint it grouped into one call to xhci_alloc_streams().
3651 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3652 command = vdev->eps[ep_index].stream_info->free_streams_command;
3653 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3655 spin_unlock_irqrestore(&xhci->lock, flags);
3656 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3661 for (i = 0; i < num_eps; i++) {
3662 struct xhci_ep_ctx *ep_ctx;
3664 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3665 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3666 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3667 EP_GETTING_NO_STREAMS;
3669 xhci_endpoint_copy(xhci, command->in_ctx,
3670 vdev->out_ctx, ep_index);
3671 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3672 &vdev->eps[ep_index]);
3674 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3675 vdev->out_ctx, ctrl_ctx,
3676 changed_ep_bitmask, changed_ep_bitmask);
3677 spin_unlock_irqrestore(&xhci->lock, flags);
3679 /* Issue and wait for the configure endpoint command,
3680 * which must succeed.
3682 ret = xhci_configure_endpoint(xhci, udev, command,
3685 /* xHC rejected the configure endpoint command for some reason, so we
3686 * leave the streams rings intact.
3691 spin_lock_irqsave(&xhci->lock, flags);
3692 for (i = 0; i < num_eps; i++) {
3693 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3694 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3695 vdev->eps[ep_index].stream_info = NULL;
3696 /* FIXME Unset maxPstreams in endpoint context and
3697 * update deq ptr to point to normal string ring.
3699 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3700 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3702 spin_unlock_irqrestore(&xhci->lock, flags);
3708 * Deletes endpoint resources for endpoints that were active before a Reset
3709 * Device command, or a Disable Slot command. The Reset Device command leaves
3710 * the control endpoint intact, whereas the Disable Slot command deletes it.
3712 * Must be called with xhci->lock held.
3714 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3715 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3718 unsigned int num_dropped_eps = 0;
3719 unsigned int drop_flags = 0;
3721 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3722 if (virt_dev->eps[i].ring) {
3723 drop_flags |= 1 << i;
3727 xhci->num_active_eps -= num_dropped_eps;
3728 if (num_dropped_eps)
3729 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3730 "Dropped %u ep ctxs, flags = 0x%x, "
3732 num_dropped_eps, drop_flags,
3733 xhci->num_active_eps);
3737 * This submits a Reset Device Command, which will set the device state to 0,
3738 * set the device address to 0, and disable all the endpoints except the default
3739 * control endpoint. The USB core should come back and call
3740 * xhci_address_device(), and then re-set up the configuration. If this is
3741 * called because of a usb_reset_and_verify_device(), then the old alternate
3742 * settings will be re-installed through the normal bandwidth allocation
3745 * Wait for the Reset Device command to finish. Remove all structures
3746 * associated with the endpoints that were disabled. Clear the input device
3747 * structure? Reset the control endpoint 0 max packet size?
3749 * If the virt_dev to be reset does not exist or does not match the udev,
3750 * it means the device is lost, possibly due to the xHC restore error and
3751 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3752 * re-allocate the device.
3754 static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3755 struct usb_device *udev)
3758 unsigned long flags;
3759 struct xhci_hcd *xhci;
3760 unsigned int slot_id;
3761 struct xhci_virt_device *virt_dev;
3762 struct xhci_command *reset_device_cmd;
3763 struct xhci_slot_ctx *slot_ctx;
3764 int old_active_eps = 0;
3766 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3769 xhci = hcd_to_xhci(hcd);
3770 slot_id = udev->slot_id;
3771 virt_dev = xhci->devs[slot_id];
3773 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3774 "not exist. Re-allocate the device\n", slot_id);
3775 ret = xhci_alloc_dev(hcd, udev);
3782 if (virt_dev->tt_info)
3783 old_active_eps = virt_dev->tt_info->active_eps;
3785 if (virt_dev->udev != udev) {
3786 /* If the virt_dev and the udev does not match, this virt_dev
3787 * may belong to another udev.
3788 * Re-allocate the device.
3790 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3791 "not match the udev. Re-allocate the device\n",
3793 ret = xhci_alloc_dev(hcd, udev);
3800 /* If device is not setup, there is no point in resetting it */
3801 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3802 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3803 SLOT_STATE_DISABLED)
3806 trace_xhci_discover_or_reset_device(slot_ctx);
3808 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3809 /* Allocate the command structure that holds the struct completion.
3810 * Assume we're in process context, since the normal device reset
3811 * process has to wait for the device anyway. Storage devices are
3812 * reset as part of error handling, so use GFP_NOIO instead of
3815 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3816 if (!reset_device_cmd) {
3817 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3821 /* Attempt to submit the Reset Device command to the command ring */
3822 spin_lock_irqsave(&xhci->lock, flags);
3824 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3826 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3827 spin_unlock_irqrestore(&xhci->lock, flags);
3828 goto command_cleanup;
3830 xhci_ring_cmd_db(xhci);
3831 spin_unlock_irqrestore(&xhci->lock, flags);
3833 /* Wait for the Reset Device command to finish */
3834 wait_for_completion(reset_device_cmd->completion);
3836 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3837 * unless we tried to reset a slot ID that wasn't enabled,
3838 * or the device wasn't in the addressed or configured state.
3840 ret = reset_device_cmd->status;
3842 case COMP_COMMAND_ABORTED:
3843 case COMP_COMMAND_RING_STOPPED:
3844 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3846 goto command_cleanup;
3847 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3848 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3849 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3851 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3852 xhci_dbg(xhci, "Not freeing device rings.\n");
3853 /* Don't treat this as an error. May change my mind later. */
3855 goto command_cleanup;
3857 xhci_dbg(xhci, "Successful reset device command.\n");
3860 if (xhci_is_vendor_info_code(xhci, ret))
3862 xhci_warn(xhci, "Unknown completion code %u for "
3863 "reset device command.\n", ret);
3865 goto command_cleanup;
3868 /* Free up host controller endpoint resources */
3869 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3870 spin_lock_irqsave(&xhci->lock, flags);
3871 /* Don't delete the default control endpoint resources */
3872 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3873 spin_unlock_irqrestore(&xhci->lock, flags);
3876 /* Everything but endpoint 0 is disabled, so free the rings. */
3877 for (i = 1; i < 31; i++) {
3878 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3880 if (ep->ep_state & EP_HAS_STREAMS) {
3881 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3882 xhci_get_endpoint_address(i));
3883 xhci_free_stream_info(xhci, ep->stream_info);
3884 ep->stream_info = NULL;
3885 ep->ep_state &= ~EP_HAS_STREAMS;
3889 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3890 xhci_free_endpoint_ring(xhci, virt_dev, i);
3892 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3893 xhci_drop_ep_from_interval_table(xhci,
3894 &virt_dev->eps[i].bw_info,
3899 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3901 /* If necessary, update the number of active TTs on this root port */
3902 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3903 virt_dev->flags = 0;
3907 xhci_free_command(xhci, reset_device_cmd);
3912 * At this point, the struct usb_device is about to go away, the device has
3913 * disconnected, and all traffic has been stopped and the endpoints have been
3914 * disabled. Free any HC data structures associated with that device.
3916 static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3918 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3919 struct xhci_virt_device *virt_dev;
3920 struct xhci_slot_ctx *slot_ctx;
3923 #ifndef CONFIG_USB_DEFAULT_PERSIST
3925 * We called pm_runtime_get_noresume when the device was attached.
3926 * Decrement the counter here to allow controller to runtime suspend
3927 * if no devices remain.
3929 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3930 pm_runtime_put_noidle(hcd->self.controller);
3933 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3934 /* If the host is halted due to driver unload, we still need to free the
3937 if (ret <= 0 && ret != -ENODEV)
3940 virt_dev = xhci->devs[udev->slot_id];
3941 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3942 trace_xhci_free_dev(slot_ctx);
3944 /* Stop any wayward timer functions (which may grab the lock) */
3945 for (i = 0; i < 31; i++) {
3946 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3947 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3949 virt_dev->udev = NULL;
3950 ret = xhci_disable_slot(xhci, udev->slot_id);
3952 xhci_free_virt_device(xhci, udev->slot_id);
3955 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
3957 struct xhci_command *command;
3958 unsigned long flags;
3962 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
3966 xhci_debugfs_remove_slot(xhci, slot_id);
3968 spin_lock_irqsave(&xhci->lock, flags);
3969 /* Don't disable the slot if the host controller is dead. */
3970 state = readl(&xhci->op_regs->status);
3971 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3972 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3973 spin_unlock_irqrestore(&xhci->lock, flags);
3978 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3981 spin_unlock_irqrestore(&xhci->lock, flags);
3985 xhci_ring_cmd_db(xhci);
3986 spin_unlock_irqrestore(&xhci->lock, flags);
3991 * Checks if we have enough host controller resources for the default control
3994 * Must be called with xhci->lock held.
3996 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3998 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3999 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4000 "Not enough ep ctxs: "
4001 "%u active, need to add 1, limit is %u.",
4002 xhci->num_active_eps, xhci->limit_active_eps);
4005 xhci->num_active_eps += 1;
4006 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
4007 "Adding 1 ep ctx, %u now active.",
4008 xhci->num_active_eps);
4014 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
4015 * timed out, or allocating memory failed. Returns 1 on success.
4017 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
4019 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4020 struct xhci_virt_device *vdev;
4021 struct xhci_slot_ctx *slot_ctx;
4022 unsigned long flags;
4024 struct xhci_command *command;
4026 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4030 spin_lock_irqsave(&xhci->lock, flags);
4031 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
4033 spin_unlock_irqrestore(&xhci->lock, flags);
4034 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
4035 xhci_free_command(xhci, command);
4038 xhci_ring_cmd_db(xhci);
4039 spin_unlock_irqrestore(&xhci->lock, flags);
4041 wait_for_completion(command->completion);
4042 slot_id = command->slot_id;
4044 if (!slot_id || command->status != COMP_SUCCESS) {
4045 xhci_err(xhci, "Error while assigning device slot ID\n");
4046 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
4048 readl(&xhci->cap_regs->hcs_params1)));
4049 xhci_free_command(xhci, command);
4053 xhci_free_command(xhci, command);
4055 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
4056 spin_lock_irqsave(&xhci->lock, flags);
4057 ret = xhci_reserve_host_control_ep_resources(xhci);
4059 spin_unlock_irqrestore(&xhci->lock, flags);
4060 xhci_warn(xhci, "Not enough host resources, "
4061 "active endpoint contexts = %u\n",
4062 xhci->num_active_eps);
4065 spin_unlock_irqrestore(&xhci->lock, flags);
4067 /* Use GFP_NOIO, since this function can be called from
4068 * xhci_discover_or_reset_device(), which may be called as part of
4069 * mass storage driver error handling.
4071 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
4072 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
4075 vdev = xhci->devs[slot_id];
4076 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
4077 trace_xhci_alloc_dev(slot_ctx);
4079 udev->slot_id = slot_id;
4081 xhci_debugfs_create_slot(xhci, slot_id);
4083 #ifndef CONFIG_USB_DEFAULT_PERSIST
4085 * If resetting upon resume, we can't put the controller into runtime
4086 * suspend if there is a device attached.
4088 if (xhci->quirks & XHCI_RESET_ON_RESUME)
4089 pm_runtime_get_noresume(hcd->self.controller);
4092 /* Is this a LS or FS device under a HS hub? */
4093 /* Hub or peripherial? */
4097 ret = xhci_disable_slot(xhci, udev->slot_id);
4099 xhci_free_virt_device(xhci, udev->slot_id);
4105 * Issue an Address Device command and optionally send a corresponding
4106 * SetAddress request to the device.
4108 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
4109 enum xhci_setup_dev setup)
4111 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
4112 unsigned long flags;
4113 struct xhci_virt_device *virt_dev;
4115 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4116 struct xhci_slot_ctx *slot_ctx;
4117 struct xhci_input_control_ctx *ctrl_ctx;
4119 struct xhci_command *command = NULL;
4121 mutex_lock(&xhci->mutex);
4123 if (xhci->xhc_state) { /* dying, removing or halted */
4128 if (!udev->slot_id) {
4129 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4130 "Bad Slot ID %d", udev->slot_id);
4135 virt_dev = xhci->devs[udev->slot_id];
4137 if (WARN_ON(!virt_dev)) {
4139 * In plug/unplug torture test with an NEC controller,
4140 * a zero-dereference was observed once due to virt_dev = 0.
4141 * Print useful debug rather than crash if it is observed again!
4143 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4148 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4149 trace_xhci_setup_device_slot(slot_ctx);
4151 if (setup == SETUP_CONTEXT_ONLY) {
4152 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4153 SLOT_STATE_DEFAULT) {
4154 xhci_dbg(xhci, "Slot already in default state\n");
4159 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4165 command->in_ctx = virt_dev->in_ctx;
4167 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4168 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4170 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4176 * If this is the first Set Address since device plug-in or
4177 * virt_device realloaction after a resume with an xHCI power loss,
4178 * then set up the slot context.
4180 if (!slot_ctx->dev_info)
4181 xhci_setup_addressable_virt_dev(xhci, udev);
4182 /* Otherwise, update the control endpoint ring enqueue pointer. */
4184 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4185 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4186 ctrl_ctx->drop_flags = 0;
4188 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4189 le32_to_cpu(slot_ctx->dev_info) >> 27);
4191 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4192 spin_lock_irqsave(&xhci->lock, flags);
4193 trace_xhci_setup_device(virt_dev);
4194 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4195 udev->slot_id, setup);
4197 spin_unlock_irqrestore(&xhci->lock, flags);
4198 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4199 "FIXME: allocate a command ring segment");
4202 xhci_ring_cmd_db(xhci);
4203 spin_unlock_irqrestore(&xhci->lock, flags);
4205 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4206 wait_for_completion(command->completion);
4208 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4209 * the SetAddress() "recovery interval" required by USB and aborting the
4210 * command on a timeout.
4212 switch (command->status) {
4213 case COMP_COMMAND_ABORTED:
4214 case COMP_COMMAND_RING_STOPPED:
4215 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4218 case COMP_CONTEXT_STATE_ERROR:
4219 case COMP_SLOT_NOT_ENABLED_ERROR:
4220 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4221 act, udev->slot_id);
4224 case COMP_USB_TRANSACTION_ERROR:
4225 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4227 mutex_unlock(&xhci->mutex);
4228 ret = xhci_disable_slot(xhci, udev->slot_id);
4230 xhci_alloc_dev(hcd, udev);
4231 kfree(command->completion);
4234 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4235 dev_warn(&udev->dev,
4236 "ERROR: Incompatible device for setup %s command\n", act);
4240 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4241 "Successful setup %s command", act);
4245 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4246 act, command->status);
4247 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4253 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4254 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4255 "Op regs DCBAA ptr = %#016llx", temp_64);
4256 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4257 "Slot ID %d dcbaa entry @%p = %#016llx",
4259 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4260 (unsigned long long)
4261 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4262 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4263 "Output Context DMA address = %#08llx",
4264 (unsigned long long)virt_dev->out_ctx->dma);
4265 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4266 le32_to_cpu(slot_ctx->dev_info) >> 27);
4268 * USB core uses address 1 for the roothubs, so we add one to the
4269 * address given back to us by the HC.
4271 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4272 le32_to_cpu(slot_ctx->dev_info) >> 27);
4273 /* Zero the input context control for later use */
4274 ctrl_ctx->add_flags = 0;
4275 ctrl_ctx->drop_flags = 0;
4276 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4277 udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4279 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4280 "Internal device address = %d",
4281 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4283 mutex_unlock(&xhci->mutex);
4285 kfree(command->completion);
4291 static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4293 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4296 static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4298 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4302 * Transfer the port index into real index in the HW port status
4303 * registers. Caculate offset between the port's PORTSC register
4304 * and port status base. Divide the number of per port register
4305 * to get the real index. The raw port number bases 1.
4307 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4309 struct xhci_hub *rhub;
4311 rhub = xhci_get_rhub(hcd);
4312 return rhub->ports[port1 - 1]->hw_portnum + 1;
4316 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4317 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4319 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4320 struct usb_device *udev, u16 max_exit_latency)
4322 struct xhci_virt_device *virt_dev;
4323 struct xhci_command *command;
4324 struct xhci_input_control_ctx *ctrl_ctx;
4325 struct xhci_slot_ctx *slot_ctx;
4326 unsigned long flags;
4329 spin_lock_irqsave(&xhci->lock, flags);
4331 virt_dev = xhci->devs[udev->slot_id];
4334 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4335 * xHC was re-initialized. Exit latency will be set later after
4336 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4339 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4340 spin_unlock_irqrestore(&xhci->lock, flags);
4344 /* Attempt to issue an Evaluate Context command to change the MEL. */
4345 command = xhci->lpm_command;
4346 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4348 spin_unlock_irqrestore(&xhci->lock, flags);
4349 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4354 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4355 spin_unlock_irqrestore(&xhci->lock, flags);
4357 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4358 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4359 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4360 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4361 slot_ctx->dev_state = 0;
4363 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4364 "Set up evaluate context for LPM MEL change.");
4366 /* Issue and wait for the evaluate context command. */
4367 ret = xhci_configure_endpoint(xhci, udev, command,
4371 spin_lock_irqsave(&xhci->lock, flags);
4372 virt_dev->current_mel = max_exit_latency;
4373 spin_unlock_irqrestore(&xhci->lock, flags);
4380 /* BESL to HIRD Encoding array for USB2 LPM */
4381 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4382 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4384 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4385 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4386 struct usb_device *udev)
4388 int u2del, besl, besl_host;
4389 int besl_device = 0;
4392 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4393 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4395 if (field & USB_BESL_SUPPORT) {
4396 for (besl_host = 0; besl_host < 16; besl_host++) {
4397 if (xhci_besl_encoding[besl_host] >= u2del)
4400 /* Use baseline BESL value as default */
4401 if (field & USB_BESL_BASELINE_VALID)
4402 besl_device = USB_GET_BESL_BASELINE(field);
4403 else if (field & USB_BESL_DEEP_VALID)
4404 besl_device = USB_GET_BESL_DEEP(field);
4409 besl_host = (u2del - 51) / 75 + 1;
4412 besl = besl_host + besl_device;
4419 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4420 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4427 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4429 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4430 l1 = udev->l1_params.timeout / 256;
4432 /* device has preferred BESLD */
4433 if (field & USB_BESL_DEEP_VALID) {
4434 besld = USB_GET_BESL_DEEP(field);
4438 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4441 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4442 struct usb_device *udev, int enable)
4444 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4445 struct xhci_port **ports;
4446 __le32 __iomem *pm_addr, *hlpm_addr;
4447 u32 pm_val, hlpm_val, field;
4448 unsigned int port_num;
4449 unsigned long flags;
4450 int hird, exit_latency;
4453 if (xhci->quirks & XHCI_HW_LPM_DISABLE)
4456 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4460 if (!udev->parent || udev->parent->parent ||
4461 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4464 if (udev->usb2_hw_lpm_capable != 1)
4467 spin_lock_irqsave(&xhci->lock, flags);
4469 ports = xhci->usb2_rhub.ports;
4470 port_num = udev->portnum - 1;
4471 pm_addr = ports[port_num]->addr + PORTPMSC;
4472 pm_val = readl(pm_addr);
4473 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4475 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4476 enable ? "enable" : "disable", port_num + 1);
4479 /* Host supports BESL timeout instead of HIRD */
4480 if (udev->usb2_hw_lpm_besl_capable) {
4481 /* if device doesn't have a preferred BESL value use a
4482 * default one which works with mixed HIRD and BESL
4483 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4485 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4486 if ((field & USB_BESL_SUPPORT) &&
4487 (field & USB_BESL_BASELINE_VALID))
4488 hird = USB_GET_BESL_BASELINE(field);
4490 hird = udev->l1_params.besl;
4492 exit_latency = xhci_besl_encoding[hird];
4493 spin_unlock_irqrestore(&xhci->lock, flags);
4495 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4496 * input context for link powermanagement evaluate
4497 * context commands. It is protected by hcd->bandwidth
4498 * mutex and is shared by all devices. We need to set
4499 * the max ext latency in USB 2 BESL LPM as well, so
4500 * use the same mutex and xhci_change_max_exit_latency()
4502 mutex_lock(hcd->bandwidth_mutex);
4503 ret = xhci_change_max_exit_latency(xhci, udev,
4505 mutex_unlock(hcd->bandwidth_mutex);
4509 spin_lock_irqsave(&xhci->lock, flags);
4511 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4512 writel(hlpm_val, hlpm_addr);
4516 hird = xhci_calculate_hird_besl(xhci, udev);
4519 pm_val &= ~PORT_HIRD_MASK;
4520 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4521 writel(pm_val, pm_addr);
4522 pm_val = readl(pm_addr);
4524 writel(pm_val, pm_addr);
4528 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4529 writel(pm_val, pm_addr);
4532 if (udev->usb2_hw_lpm_besl_capable) {
4533 spin_unlock_irqrestore(&xhci->lock, flags);
4534 mutex_lock(hcd->bandwidth_mutex);
4535 xhci_change_max_exit_latency(xhci, udev, 0);
4536 mutex_unlock(hcd->bandwidth_mutex);
4537 readl_poll_timeout(ports[port_num]->addr, pm_val,
4538 (pm_val & PORT_PLS_MASK) == XDEV_U0,
4544 spin_unlock_irqrestore(&xhci->lock, flags);
4548 /* check if a usb2 port supports a given extened capability protocol
4549 * only USB2 ports extended protocol capability values are cached.
4550 * Return 1 if capability is supported
4552 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4553 unsigned capability)
4555 u32 port_offset, port_count;
4558 for (i = 0; i < xhci->num_ext_caps; i++) {
4559 if (xhci->ext_caps[i] & capability) {
4560 /* port offsets starts at 1 */
4561 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4562 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4563 if (port >= port_offset &&
4564 port < port_offset + port_count)
4571 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4573 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4574 int portnum = udev->portnum - 1;
4576 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
4579 /* we only support lpm for non-hub device connected to root hub yet */
4580 if (!udev->parent || udev->parent->parent ||
4581 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4584 if (xhci->hw_lpm_support == 1 &&
4585 xhci_check_usb2_port_capability(
4586 xhci, portnum, XHCI_HLC)) {
4587 udev->usb2_hw_lpm_capable = 1;
4588 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4589 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4590 if (xhci_check_usb2_port_capability(xhci, portnum,
4592 udev->usb2_hw_lpm_besl_capable = 1;
4598 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4600 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4601 static unsigned long long xhci_service_interval_to_ns(
4602 struct usb_endpoint_descriptor *desc)
4604 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4607 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4608 enum usb3_link_state state)
4610 unsigned long long sel;
4611 unsigned long long pel;
4612 unsigned int max_sel_pel;
4617 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4618 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4619 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4620 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4624 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4625 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4626 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4630 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4632 return USB3_LPM_DISABLED;
4635 if (sel <= max_sel_pel && pel <= max_sel_pel)
4636 return USB3_LPM_DEVICE_INITIATED;
4638 if (sel > max_sel_pel)
4639 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4640 "due to long SEL %llu ms\n",
4643 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4644 "due to long PEL %llu ms\n",
4646 return USB3_LPM_DISABLED;
4649 /* The U1 timeout should be the maximum of the following values:
4650 * - For control endpoints, U1 system exit latency (SEL) * 3
4651 * - For bulk endpoints, U1 SEL * 5
4652 * - For interrupt endpoints:
4653 * - Notification EPs, U1 SEL * 3
4654 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4655 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4657 static unsigned long long xhci_calculate_intel_u1_timeout(
4658 struct usb_device *udev,
4659 struct usb_endpoint_descriptor *desc)
4661 unsigned long long timeout_ns;
4665 ep_type = usb_endpoint_type(desc);
4667 case USB_ENDPOINT_XFER_CONTROL:
4668 timeout_ns = udev->u1_params.sel * 3;
4670 case USB_ENDPOINT_XFER_BULK:
4671 timeout_ns = udev->u1_params.sel * 5;
4673 case USB_ENDPOINT_XFER_INT:
4674 intr_type = usb_endpoint_interrupt_type(desc);
4675 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4676 timeout_ns = udev->u1_params.sel * 3;
4679 /* Otherwise the calculation is the same as isoc eps */
4681 case USB_ENDPOINT_XFER_ISOC:
4682 timeout_ns = xhci_service_interval_to_ns(desc);
4683 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4684 if (timeout_ns < udev->u1_params.sel * 2)
4685 timeout_ns = udev->u1_params.sel * 2;
4694 /* Returns the hub-encoded U1 timeout value. */
4695 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4696 struct usb_device *udev,
4697 struct usb_endpoint_descriptor *desc)
4699 unsigned long long timeout_ns;
4701 if (xhci->quirks & XHCI_INTEL_HOST)
4702 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4704 timeout_ns = udev->u1_params.sel;
4706 /* Prevent U1 if service interval is shorter than U1 exit latency */
4707 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4708 if (xhci_service_interval_to_ns(desc) <= timeout_ns) {
4709 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4710 return USB3_LPM_DISABLED;
4714 /* The U1 timeout is encoded in 1us intervals.
4715 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4717 if (timeout_ns == USB3_LPM_DISABLED)
4720 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4722 /* If the necessary timeout value is bigger than what we can set in the
4723 * USB 3.0 hub, we have to disable hub-initiated U1.
4725 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4727 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4728 "due to long timeout %llu ms\n", timeout_ns);
4729 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4732 /* The U2 timeout should be the maximum of:
4733 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4734 * - largest bInterval of any active periodic endpoint (to avoid going
4735 * into lower power link states between intervals).
4736 * - the U2 Exit Latency of the device
4738 static unsigned long long xhci_calculate_intel_u2_timeout(
4739 struct usb_device *udev,
4740 struct usb_endpoint_descriptor *desc)
4742 unsigned long long timeout_ns;
4743 unsigned long long u2_del_ns;
4745 timeout_ns = 10 * 1000 * 1000;
4747 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4748 (xhci_service_interval_to_ns(desc) > timeout_ns))
4749 timeout_ns = xhci_service_interval_to_ns(desc);
4751 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4752 if (u2_del_ns > timeout_ns)
4753 timeout_ns = u2_del_ns;
4758 /* Returns the hub-encoded U2 timeout value. */
4759 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4760 struct usb_device *udev,
4761 struct usb_endpoint_descriptor *desc)
4763 unsigned long long timeout_ns;
4765 if (xhci->quirks & XHCI_INTEL_HOST)
4766 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4768 timeout_ns = udev->u2_params.sel;
4770 /* Prevent U2 if service interval is shorter than U2 exit latency */
4771 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4772 if (xhci_service_interval_to_ns(desc) <= timeout_ns) {
4773 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4774 return USB3_LPM_DISABLED;
4778 /* The U2 timeout is encoded in 256us intervals */
4779 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4780 /* If the necessary timeout value is bigger than what we can set in the
4781 * USB 3.0 hub, we have to disable hub-initiated U2.
4783 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4785 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4786 "due to long timeout %llu ms\n", timeout_ns);
4787 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4790 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4791 struct usb_device *udev,
4792 struct usb_endpoint_descriptor *desc,
4793 enum usb3_link_state state,
4796 if (state == USB3_LPM_U1)
4797 return xhci_calculate_u1_timeout(xhci, udev, desc);
4798 else if (state == USB3_LPM_U2)
4799 return xhci_calculate_u2_timeout(xhci, udev, desc);
4801 return USB3_LPM_DISABLED;
4804 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4805 struct usb_device *udev,
4806 struct usb_endpoint_descriptor *desc,
4807 enum usb3_link_state state,
4812 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4813 desc, state, timeout);
4815 /* If we found we can't enable hub-initiated LPM, and
4816 * the U1 or U2 exit latency was too high to allow
4817 * device-initiated LPM as well, then we will disable LPM
4818 * for this device, so stop searching any further.
4820 if (alt_timeout == USB3_LPM_DISABLED) {
4821 *timeout = alt_timeout;
4824 if (alt_timeout > *timeout)
4825 *timeout = alt_timeout;
4829 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4830 struct usb_device *udev,
4831 struct usb_host_interface *alt,
4832 enum usb3_link_state state,
4837 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4838 if (xhci_update_timeout_for_endpoint(xhci, udev,
4839 &alt->endpoint[j].desc, state, timeout))
4846 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4847 enum usb3_link_state state)
4849 struct usb_device *parent;
4850 unsigned int num_hubs;
4852 if (state == USB3_LPM_U2)
4855 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4856 for (parent = udev->parent, num_hubs = 0; parent->parent;
4857 parent = parent->parent)
4863 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4864 " below second-tier hub.\n");
4865 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4866 "to decrease power consumption.\n");
4870 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4871 struct usb_device *udev,
4872 enum usb3_link_state state)
4874 if (xhci->quirks & XHCI_INTEL_HOST)
4875 return xhci_check_intel_tier_policy(udev, state);
4880 /* Returns the U1 or U2 timeout that should be enabled.
4881 * If the tier check or timeout setting functions return with a non-zero exit
4882 * code, that means the timeout value has been finalized and we shouldn't look
4883 * at any more endpoints.
4885 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4886 struct usb_device *udev, enum usb3_link_state state)
4888 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4889 struct usb_host_config *config;
4892 u16 timeout = USB3_LPM_DISABLED;
4894 if (state == USB3_LPM_U1)
4896 else if (state == USB3_LPM_U2)
4899 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4904 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4907 /* Gather some information about the currently installed configuration
4908 * and alternate interface settings.
4910 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4914 config = udev->actconfig;
4918 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4919 struct usb_driver *driver;
4920 struct usb_interface *intf = config->interface[i];
4925 /* Check if any currently bound drivers want hub-initiated LPM
4928 if (intf->dev.driver) {
4929 driver = to_usb_driver(intf->dev.driver);
4930 if (driver && driver->disable_hub_initiated_lpm) {
4931 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4932 state_name, driver->name);
4933 timeout = xhci_get_timeout_no_hub_lpm(udev,
4935 if (timeout == USB3_LPM_DISABLED)
4940 /* Not sure how this could happen... */
4941 if (!intf->cur_altsetting)
4944 if (xhci_update_timeout_for_interface(xhci, udev,
4945 intf->cur_altsetting,
4952 static int calculate_max_exit_latency(struct usb_device *udev,
4953 enum usb3_link_state state_changed,
4954 u16 hub_encoded_timeout)
4956 unsigned long long u1_mel_us = 0;
4957 unsigned long long u2_mel_us = 0;
4958 unsigned long long mel_us = 0;
4964 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4965 hub_encoded_timeout == USB3_LPM_DISABLED);
4966 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4967 hub_encoded_timeout == USB3_LPM_DISABLED);
4969 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4970 hub_encoded_timeout != USB3_LPM_DISABLED);
4971 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4972 hub_encoded_timeout != USB3_LPM_DISABLED);
4974 /* If U1 was already enabled and we're not disabling it,
4975 * or we're going to enable U1, account for the U1 max exit latency.
4977 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4979 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4980 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4982 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4984 if (u1_mel_us > u2_mel_us)
4988 /* xHCI host controller max exit latency field is only 16 bits wide. */
4989 if (mel_us > MAX_EXIT) {
4990 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4991 "is too big.\n", mel_us);
4997 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4998 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4999 struct usb_device *udev, enum usb3_link_state state)
5001 struct xhci_hcd *xhci;
5002 u16 hub_encoded_timeout;
5006 xhci = hcd_to_xhci(hcd);
5007 /* The LPM timeout values are pretty host-controller specific, so don't
5008 * enable hub-initiated timeouts unless the vendor has provided
5009 * information about their timeout algorithm.
5011 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5012 !xhci->devs[udev->slot_id])
5013 return USB3_LPM_DISABLED;
5015 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
5016 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
5018 /* Max Exit Latency is too big, disable LPM. */
5019 hub_encoded_timeout = USB3_LPM_DISABLED;
5023 ret = xhci_change_max_exit_latency(xhci, udev, mel);
5026 return hub_encoded_timeout;
5029 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5030 struct usb_device *udev, enum usb3_link_state state)
5032 struct xhci_hcd *xhci;
5035 xhci = hcd_to_xhci(hcd);
5036 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
5037 !xhci->devs[udev->slot_id])
5040 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
5041 return xhci_change_max_exit_latency(xhci, udev, mel);
5043 #else /* CONFIG_PM */
5045 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
5046 struct usb_device *udev, int enable)
5051 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
5056 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
5057 struct usb_device *udev, enum usb3_link_state state)
5059 return USB3_LPM_DISABLED;
5062 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
5063 struct usb_device *udev, enum usb3_link_state state)
5067 #endif /* CONFIG_PM */
5069 /*-------------------------------------------------------------------------*/
5071 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
5072 * internal data structures for the device.
5074 static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
5075 struct usb_tt *tt, gfp_t mem_flags)
5077 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5078 struct xhci_virt_device *vdev;
5079 struct xhci_command *config_cmd;
5080 struct xhci_input_control_ctx *ctrl_ctx;
5081 struct xhci_slot_ctx *slot_ctx;
5082 unsigned long flags;
5083 unsigned think_time;
5086 /* Ignore root hubs */
5090 vdev = xhci->devs[hdev->slot_id];
5092 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
5096 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
5100 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
5102 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
5104 xhci_free_command(xhci, config_cmd);
5108 spin_lock_irqsave(&xhci->lock, flags);
5109 if (hdev->speed == USB_SPEED_HIGH &&
5110 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
5111 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
5112 xhci_free_command(xhci, config_cmd);
5113 spin_unlock_irqrestore(&xhci->lock, flags);
5117 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
5118 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
5119 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
5120 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
5122 * refer to section 6.2.2: MTT should be 0 for full speed hub,
5123 * but it may be already set to 1 when setup an xHCI virtual
5124 * device, so clear it anyway.
5127 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
5128 else if (hdev->speed == USB_SPEED_FULL)
5129 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
5131 if (xhci->hci_version > 0x95) {
5132 xhci_dbg(xhci, "xHCI version %x needs hub "
5133 "TT think time and number of ports\n",
5134 (unsigned int) xhci->hci_version);
5135 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
5136 /* Set TT think time - convert from ns to FS bit times.
5137 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5138 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5140 * xHCI 1.0: this field shall be 0 if the device is not a
5143 think_time = tt->think_time;
5144 if (think_time != 0)
5145 think_time = (think_time / 666) - 1;
5146 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5147 slot_ctx->tt_info |=
5148 cpu_to_le32(TT_THINK_TIME(think_time));
5150 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5151 "TT think time or number of ports\n",
5152 (unsigned int) xhci->hci_version);
5154 slot_ctx->dev_state = 0;
5155 spin_unlock_irqrestore(&xhci->lock, flags);
5157 xhci_dbg(xhci, "Set up %s for hub device.\n",
5158 (xhci->hci_version > 0x95) ?
5159 "configure endpoint" : "evaluate context");
5161 /* Issue and wait for the configure endpoint or
5162 * evaluate context command.
5164 if (xhci->hci_version > 0x95)
5165 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5168 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5171 xhci_free_command(xhci, config_cmd);
5175 static int xhci_get_frame(struct usb_hcd *hcd)
5177 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5178 /* EHCI mods by the periodic size. Why? */
5179 return readl(&xhci->run_regs->microframe_index) >> 3;
5182 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5184 struct xhci_hcd *xhci;
5186 * TODO: Check with DWC3 clients for sysdev according to
5189 struct device *dev = hcd->self.sysdev;
5190 unsigned int minor_rev;
5193 /* Accept arbitrarily long scatter-gather lists */
5194 hcd->self.sg_tablesize = ~0;
5196 /* support to build packet from discontinuous buffers */
5197 hcd->self.no_sg_constraint = 1;
5199 /* XHCI controllers don't stop the ep queue on short packets :| */
5200 hcd->self.no_stop_on_short = 1;
5202 xhci = hcd_to_xhci(hcd);
5204 if (usb_hcd_is_primary_hcd(hcd)) {
5205 xhci->main_hcd = hcd;
5206 xhci->usb2_rhub.hcd = hcd;
5207 /* Mark the first roothub as being USB 2.0.
5208 * The xHCI driver will register the USB 3.0 roothub.
5210 hcd->speed = HCD_USB2;
5211 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5213 * USB 2.0 roothub under xHCI has an integrated TT,
5214 * (rate matching hub) as opposed to having an OHCI/UHCI
5215 * companion controller.
5220 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5221 * should return 0x31 for sbrn, or that the minor revision
5222 * is a two digit BCD containig minor and sub-minor numbers.
5223 * This was later clarified in xHCI 1.2.
5225 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5226 * minor revision set to 0x1 instead of 0x10.
5228 if (xhci->usb3_rhub.min_rev == 0x1)
5231 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5233 switch (minor_rev) {
5235 hcd->speed = HCD_USB32;
5236 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5237 hcd->self.root_hub->rx_lanes = 2;
5238 hcd->self.root_hub->tx_lanes = 2;
5241 hcd->speed = HCD_USB31;
5242 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5245 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5247 minor_rev ? "Enhanced " : "");
5249 xhci->usb3_rhub.hcd = hcd;
5250 /* xHCI private pointer was set in xhci_pci_probe for the second
5251 * registered roothub.
5256 mutex_init(&xhci->mutex);
5257 xhci->cap_regs = hcd->regs;
5258 xhci->op_regs = hcd->regs +
5259 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5260 xhci->run_regs = hcd->regs +
5261 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5262 /* Cache read-only capability registers */
5263 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5264 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5265 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5266 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
5267 xhci->hci_version = HC_VERSION(xhci->hcc_params);
5268 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5269 if (xhci->hci_version > 0x100)
5270 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5272 xhci->quirks |= quirks;
5274 get_quirks(dev, xhci);
5276 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5277 * success event after a short transfer. This quirk will ignore such
5280 if (xhci->hci_version > 0x96)
5281 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5283 /* Make sure the HC is halted. */
5284 retval = xhci_halt(xhci);
5288 xhci_zero_64b_regs(xhci);
5290 xhci_dbg(xhci, "Resetting HCD\n");
5291 /* Reset the internal HC memory state and registers. */
5292 retval = xhci_reset(xhci);
5295 xhci_dbg(xhci, "Reset complete\n");
5298 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5299 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5300 * address memory pointers actually. So, this driver clears the AC64
5301 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5302 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5304 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5305 xhci->hcc_params &= ~BIT(0);
5307 /* Set dma_mask and coherent_dma_mask to 64-bits,
5308 * if xHC supports 64-bit addressing */
5309 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5310 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5311 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5312 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5315 * This is to avoid error in cases where a 32-bit USB
5316 * controller is used on a 64-bit capable system.
5318 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5321 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5322 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5325 xhci_dbg(xhci, "Calling HCD init\n");
5326 /* Initialize HCD and host controller data structures. */
5327 retval = xhci_init(hcd);
5330 xhci_dbg(xhci, "Called HCD init\n");
5332 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5333 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5337 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5339 static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5340 struct usb_host_endpoint *ep)
5342 struct xhci_hcd *xhci;
5343 struct usb_device *udev;
5344 unsigned int slot_id;
5345 unsigned int ep_index;
5346 unsigned long flags;
5348 xhci = hcd_to_xhci(hcd);
5350 spin_lock_irqsave(&xhci->lock, flags);
5351 udev = (struct usb_device *)ep->hcpriv;
5352 slot_id = udev->slot_id;
5353 ep_index = xhci_get_endpoint_index(&ep->desc);
5355 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5356 xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5357 spin_unlock_irqrestore(&xhci->lock, flags);
5360 static const struct hc_driver xhci_hc_driver = {
5361 .description = "xhci-hcd",
5362 .product_desc = "xHCI Host Controller",
5363 .hcd_priv_size = sizeof(struct xhci_hcd),
5366 * generic hardware linkage
5369 .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED |
5373 * basic lifecycle operations
5375 .reset = NULL, /* set in xhci_init_driver() */
5378 .shutdown = xhci_shutdown,
5381 * managing i/o requests and associated device resources
5383 .map_urb_for_dma = xhci_map_urb_for_dma,
5384 .unmap_urb_for_dma = xhci_unmap_urb_for_dma,
5385 .urb_enqueue = xhci_urb_enqueue,
5386 .urb_dequeue = xhci_urb_dequeue,
5387 .alloc_dev = xhci_alloc_dev,
5388 .free_dev = xhci_free_dev,
5389 .alloc_streams = xhci_alloc_streams,
5390 .free_streams = xhci_free_streams,
5391 .add_endpoint = xhci_add_endpoint,
5392 .drop_endpoint = xhci_drop_endpoint,
5393 .endpoint_disable = xhci_endpoint_disable,
5394 .endpoint_reset = xhci_endpoint_reset,
5395 .check_bandwidth = xhci_check_bandwidth,
5396 .reset_bandwidth = xhci_reset_bandwidth,
5397 .address_device = xhci_address_device,
5398 .enable_device = xhci_enable_device,
5399 .update_hub_device = xhci_update_hub_device,
5400 .reset_device = xhci_discover_or_reset_device,
5403 * scheduling support
5405 .get_frame_number = xhci_get_frame,
5410 .hub_control = xhci_hub_control,
5411 .hub_status_data = xhci_hub_status_data,
5412 .bus_suspend = xhci_bus_suspend,
5413 .bus_resume = xhci_bus_resume,
5414 .get_resuming_ports = xhci_get_resuming_ports,
5417 * call back when device connected and addressed
5419 .update_device = xhci_update_device,
5420 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5421 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5422 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5423 .find_raw_port_number = xhci_find_raw_port_number,
5424 .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5427 void xhci_init_driver(struct hc_driver *drv,
5428 const struct xhci_driver_overrides *over)
5432 /* Copy the generic table to drv then apply the overrides */
5433 *drv = xhci_hc_driver;
5436 drv->hcd_priv_size += over->extra_priv_size;
5438 drv->reset = over->reset;
5440 drv->start = over->start;
5441 if (over->check_bandwidth)
5442 drv->check_bandwidth = over->check_bandwidth;
5443 if (over->reset_bandwidth)
5444 drv->reset_bandwidth = over->reset_bandwidth;
5447 EXPORT_SYMBOL_GPL(xhci_init_driver);
5449 MODULE_DESCRIPTION(DRIVER_DESC);
5450 MODULE_AUTHOR(DRIVER_AUTHOR);
5451 MODULE_LICENSE("GPL");
5453 static int __init xhci_hcd_init(void)
5456 * Check the compiler generated sizes of structures that must be laid
5457 * out in specific ways for hardware access.
5459 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5460 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5461 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5462 /* xhci_device_control has eight fields, and also
5463 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5465 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5466 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5467 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5468 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5469 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5470 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5471 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5476 xhci_debugfs_create_root();
5482 * If an init function is provided, an exit function must also be provided
5483 * to allow module unload.
5485 static void __exit xhci_hcd_fini(void)
5487 xhci_debugfs_remove_root();
5490 module_init(xhci_hcd_init);
5491 module_exit(xhci_hcd_fini);