drivers/usb/host/xhci-tegra.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * NVIDIA Tegra xHCI host controller driver
   4  *
   5  * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
   6  * Copyright (C) 2014 Google, Inc.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/firmware.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/of_device.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/phy/phy.h>
  20 #include <linux/phy/tegra/xusb.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/usb/ch9.h>
  23 #include <linux/pm.h>
  24 #include <linux/pm_domain.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/regulator/consumer.h>
  27 #include <linux/reset.h>
  28 #include <linux/slab.h>
  29 #include <linux/usb/otg.h>
  30 #include <linux/usb/phy.h>
  31 #include <linux/usb/role.h>
  32 #include <soc/tegra/pmc.h>
  33
  34 #include "xhci.h"
  35
  36 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000
  37 #define TEGRA_XHCI_SS_LOW_SPEED   12000000
  38
  39 /* FPCI CFG registers */
  40 #define XUSB_CFG_1                              0x004
  41 #define  XUSB_IO_SPACE_EN                       BIT(0)
  42 #define  XUSB_MEM_SPACE_EN                      BIT(1)
  43 #define  XUSB_BUS_MASTER_EN                     BIT(2)
  44 #define XUSB_CFG_4                              0x010
  45 #define  XUSB_BASE_ADDR_SHIFT                   15
  46 #define  XUSB_BASE_ADDR_MASK                    0x1ffff
  47 #define XUSB_CFG_16                             0x040
  48 #define XUSB_CFG_24                             0x060
  49 #define XUSB_CFG_AXI_CFG                        0x0f8
  50 #define XUSB_CFG_ARU_C11_CSBRANGE               0x41c
  51 #define XUSB_CFG_ARU_CONTEXT                    0x43c
  52 #define XUSB_CFG_ARU_CONTEXT_HS_PLS             0x478
  53 #define XUSB_CFG_ARU_CONTEXT_FS_PLS             0x47c
  54 #define XUSB_CFG_ARU_CONTEXT_HSFS_SPEED         0x480
  55 #define XUSB_CFG_ARU_CONTEXT_HSFS_PP            0x484
  56 #define XUSB_CFG_CSB_BASE_ADDR                  0x800
  57
  58 /* FPCI mailbox registers */
  59 /* XUSB_CFG_ARU_MBOX_CMD */
  60 #define  MBOX_DEST_FALC                         BIT(27)
  61 #define  MBOX_DEST_PME                          BIT(28)
  62 #define  MBOX_DEST_SMI                          BIT(29)
  63 #define  MBOX_DEST_XHCI                         BIT(30)
  64 #define  MBOX_INT_EN                            BIT(31)
  65 /* XUSB_CFG_ARU_MBOX_DATA_IN and XUSB_CFG_ARU_MBOX_DATA_OUT */
  66 #define  CMD_DATA_SHIFT                         0
  67 #define  CMD_DATA_MASK                          0xffffff
  68 #define  CMD_TYPE_SHIFT                         24
  69 #define  CMD_TYPE_MASK                          0xff
  70 /* XUSB_CFG_ARU_MBOX_OWNER */
  71 #define  MBOX_OWNER_NONE                        0
  72 #define  MBOX_OWNER_FW                          1
  73 #define  MBOX_OWNER_SW                          2
  74 #define XUSB_CFG_ARU_SMI_INTR                   0x428
  75 #define  MBOX_SMI_INTR_FW_HANG                  BIT(1)
  76 #define  MBOX_SMI_INTR_EN                       BIT(3)
  77
  78 /* IPFS registers */
  79 #define IPFS_XUSB_HOST_MSI_BAR_SZ_0             0x0c0
  80 #define IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0         0x0c4
  81 #define IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0        0x0c8
  82 #define IPFS_XUSB_HOST_MSI_VEC0_0               0x100
  83 #define IPFS_XUSB_HOST_MSI_EN_VEC0_0            0x140
  84 #define IPFS_XUSB_HOST_CONFIGURATION_0          0x180
  85 #define  IPFS_EN_FPCI                           BIT(0)
  86 #define IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0       0x184
  87 #define IPFS_XUSB_HOST_INTR_MASK_0              0x188
  88 #define  IPFS_IP_INT_MASK                       BIT(16)
  89 #define IPFS_XUSB_HOST_INTR_ENABLE_0            0x198
  90 #define IPFS_XUSB_HOST_UFPCI_CONFIG_0           0x19c
  91 #define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0     0x1bc
  92 #define IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0         0x1dc
  93
  94 #define CSB_PAGE_SELECT_MASK                    0x7fffff
  95 #define CSB_PAGE_SELECT_SHIFT                   9
  96 #define CSB_PAGE_OFFSET_MASK                    0x1ff
  97 #define CSB_PAGE_SELECT(addr)   ((addr) >> (CSB_PAGE_SELECT_SHIFT) &    \
  98                                  CSB_PAGE_SELECT_MASK)
  99 #define CSB_PAGE_OFFSET(addr)   ((addr) & CSB_PAGE_OFFSET_MASK)
 100
 101 /* Falcon CSB registers */
 102 #define XUSB_FALC_CPUCTL                        0x100
 103 #define  CPUCTL_STARTCPU                        BIT(1)
 104 #define  CPUCTL_STATE_HALTED                    BIT(4)
 105 #define  CPUCTL_STATE_STOPPED                   BIT(5)
 106 #define XUSB_FALC_BOOTVEC                       0x104
 107 #define XUSB_FALC_DMACTL                        0x10c
 108 #define XUSB_FALC_IMFILLRNG1                    0x154
 109 #define  IMFILLRNG1_TAG_MASK                    0xffff
 110 #define  IMFILLRNG1_TAG_LO_SHIFT                0
 111 #define  IMFILLRNG1_TAG_HI_SHIFT                16
 112 #define XUSB_FALC_IMFILLCTL                     0x158
 113
 114 /* MP CSB registers */
 115 #define XUSB_CSB_MP_ILOAD_ATTR                  0x101a00
 116 #define XUSB_CSB_MP_ILOAD_BASE_LO               0x101a04
 117 #define XUSB_CSB_MP_ILOAD_BASE_HI               0x101a08
 118 #define XUSB_CSB_MP_L2IMEMOP_SIZE               0x101a10
 119 #define  L2IMEMOP_SIZE_SRC_OFFSET_SHIFT         8
 120 #define  L2IMEMOP_SIZE_SRC_OFFSET_MASK          0x3ff
 121 #define  L2IMEMOP_SIZE_SRC_COUNT_SHIFT          24
 122 #define  L2IMEMOP_SIZE_SRC_COUNT_MASK           0xff
 123 #define XUSB_CSB_MP_L2IMEMOP_TRIG               0x101a14
 124 #define  L2IMEMOP_ACTION_SHIFT                  24
 125 #define  L2IMEMOP_INVALIDATE_ALL                (0x40 << L2IMEMOP_ACTION_SHIFT)
 126 #define  L2IMEMOP_LOAD_LOCKED_RESULT            (0x11 << L2IMEMOP_ACTION_SHIFT)
 127 #define XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT        0x101a18
 128 #define  L2IMEMOP_RESULT_VLD                    BIT(31)
 129 #define XUSB_CSB_MP_APMAP                       0x10181c
 130 #define  APMAP_BOOTPATH                         BIT(31)
 131
 132 #define IMEM_BLOCK_SIZE                         256
 133
 134 struct tegra_xusb_fw_header {
 135         __le32 boot_loadaddr_in_imem;
 136         __le32 boot_codedfi_offset;
 137         __le32 boot_codetag;
 138         __le32 boot_codesize;
 139         __le32 phys_memaddr;
 140         __le16 reqphys_memsize;
 141         __le16 alloc_phys_memsize;
 142         __le32 rodata_img_offset;
 143         __le32 rodata_section_start;
 144         __le32 rodata_section_end;
 145         __le32 main_fnaddr;
 146         __le32 fwimg_cksum;
 147         __le32 fwimg_created_time;
 148         __le32 imem_resident_start;
 149         __le32 imem_resident_end;
 150         __le32 idirect_start;
 151         __le32 idirect_end;
 152         __le32 l2_imem_start;
 153         __le32 l2_imem_end;
 154         __le32 version_id;
 155         u8 init_ddirect;
 156         u8 reserved[3];
 157         __le32 phys_addr_log_buffer;
 158         __le32 total_log_entries;
 159         __le32 dequeue_ptr;
 160         __le32 dummy_var[2];
 161         __le32 fwimg_len;
 162         u8 magic[8];
 163         __le32 ss_low_power_entry_timeout;
 164         u8 num_hsic_port;
 165         u8 padding[139]; /* Pad to 256 bytes */
 166 };
 167
 168 struct tegra_xusb_phy_type {
 169         const char *name;
 170         unsigned int num;
 171 };
 172
 173 struct tegra_xusb_mbox_regs {
 174         u16 cmd;
 175         u16 data_in;
 176         u16 data_out;
 177         u16 owner;
 178 };
 179
 180 struct tegra_xusb_context_soc {
 181         struct {
 182                 const unsigned int *offsets;
 183                 unsigned int num_offsets;
 184         } ipfs;
 185
 186         struct {
 187                 const unsigned int *offsets;
 188                 unsigned int num_offsets;
 189         } fpci;
 190 };
 191
 192 struct tegra_xusb_soc {
 193         const char *firmware;
 194         const char * const *supply_names;
 195         unsigned int num_supplies;
 196         const struct tegra_xusb_phy_type *phy_types;
 197         unsigned int num_types;
 198         const struct tegra_xusb_context_soc *context;
 199
 200         struct {
 201                 struct {
 202                         unsigned int offset;
 203                         unsigned int count;
 204                 } usb2, ulpi, hsic, usb3;
 205         } ports;
 206
 207         struct tegra_xusb_mbox_regs mbox;
 208
 209         bool scale_ss_clock;
 210         bool has_ipfs;
 211         bool lpm_support;
 212         bool otg_reset_sspi;
 213 };
 214
 215 struct tegra_xusb_context {
 216         u32 *ipfs;
 217         u32 *fpci;
 218 };
 219
 220 struct tegra_xusb {
 221         struct device *dev;
 222         void __iomem *regs;
 223         struct usb_hcd *hcd;
 224
 225         struct mutex lock;
 226
 227         int xhci_irq;
 228         int mbox_irq;
 229         int padctl_irq;
 230
 231         void __iomem *ipfs_base;
 232         void __iomem *fpci_base;
 233
 234         const struct tegra_xusb_soc *soc;
 235
 236         struct regulator_bulk_data *supplies;
 237
 238         struct tegra_xusb_padctl *padctl;
 239
 240         struct clk *host_clk;
 241         struct clk *falcon_clk;
 242         struct clk *ss_clk;
 243         struct clk *ss_src_clk;
 244         struct clk *hs_src_clk;
 245         struct clk *fs_src_clk;
 246         struct clk *pll_u_480m;
 247         struct clk *clk_m;
 248         struct clk *pll_e;
 249
 250         struct reset_control *host_rst;
 251         struct reset_control *ss_rst;
 252
 253         struct device *genpd_dev_host;
 254         struct device *genpd_dev_ss;
 255         bool use_genpd;
 256
 257         struct phy **phys;
 258         unsigned int num_phys;
 259
 260         struct usb_phy **usbphy;
 261         unsigned int num_usb_phys;
 262         int otg_usb2_port;
 263         int otg_usb3_port;
 264         bool host_mode;
 265         struct notifier_block id_nb;
 266         struct work_struct id_work;
 267
 268         /* Firmware loading related */
 269         struct {
 270                 size_t size;
 271                 void *virt;
 272                 dma_addr_t phys;
 273         } fw;
 274
 275         bool suspended;
 276         struct tegra_xusb_context context;
 277 };
 278
 279 static struct hc_driver __read_mostly tegra_xhci_hc_driver;
 280
 281 static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset)
 282 {
 283         return readl(tegra->fpci_base + offset);
 284 }
 285
 286 static inline void fpci_writel(struct tegra_xusb *tegra, u32 value,
 287                                unsigned int offset)
 288 {
 289         writel(value, tegra->fpci_base + offset);
 290 }
 291
 292 static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset)
 293 {
 294         return readl(tegra->ipfs_base + offset);
 295 }
 296
 297 static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value,
 298                                unsigned int offset)
 299 {
 300         writel(value, tegra->ipfs_base + offset);
 301 }
 302
 303 static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset)
 304 {
 305         u32 page = CSB_PAGE_SELECT(offset);
 306         u32 ofs = CSB_PAGE_OFFSET(offset);
 307
 308         fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
 309
 310         return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs);
 311 }
 312
 313 static void csb_writel(struct tegra_xusb *tegra, u32 value,
 314                        unsigned int offset)
 315 {
 316         u32 page = CSB_PAGE_SELECT(offset);
 317         u32 ofs = CSB_PAGE_OFFSET(offset);
 318
 319         fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
 320         fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs);
 321 }
 322
 323 static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra,
 324                                  unsigned long rate)
 325 {
 326         unsigned long new_parent_rate, old_parent_rate;
 327         struct clk *clk = tegra->ss_src_clk;
 328         unsigned int div;
 329         int err;
 330
 331         if (clk_get_rate(clk) == rate)
 332                 return 0;
 333
 334         switch (rate) {
 335         case TEGRA_XHCI_SS_HIGH_SPEED:
 336                 /*
 337                  * Reparent to PLLU_480M. Set divider first to avoid
 338                  * overclocking.
 339                  */
 340                 old_parent_rate = clk_get_rate(clk_get_parent(clk));
 341                 new_parent_rate = clk_get_rate(tegra->pll_u_480m);
 342                 div = new_parent_rate / rate;
 343
 344                 err = clk_set_rate(clk, old_parent_rate / div);
 345                 if (err)
 346                         return err;
 347
 348                 err = clk_set_parent(clk, tegra->pll_u_480m);
 349                 if (err)
 350                         return err;
 351
 352                 /*
 353                  * The rate should already be correct, but set it again just
 354                  * to be sure.
 355                  */
 356                 err = clk_set_rate(clk, rate);
 357                 if (err)
 358                         return err;
 359
 360                 break;
 361
 362         case TEGRA_XHCI_SS_LOW_SPEED:
 363                 /* Reparent to CLK_M */
 364                 err = clk_set_parent(clk, tegra->clk_m);
 365                 if (err)
 366                         return err;
 367
 368                 err = clk_set_rate(clk, rate);
 369                 if (err)
 370                         return err;
 371
 372                 break;
 373
 374         default:
 375                 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate);
 376                 return -EINVAL;
 377         }
 378
 379         if (clk_get_rate(clk) != rate) {
 380                 dev_err(tegra->dev, "SS clock doesn't match requested rate\n");
 381                 return -EINVAL;
 382         }
 383
 384         return 0;
 385 }
 386
 387 static unsigned long extract_field(u32 value, unsigned int start,
 388                                    unsigned int count)
 389 {
 390         return (value >> start) & ((1 << count) - 1);
 391 }
 392
 393 /* Command requests from the firmware */
 394 enum tegra_xusb_mbox_cmd {
 395         MBOX_CMD_MSG_ENABLED = 1,
 396         MBOX_CMD_INC_FALC_CLOCK,
 397         MBOX_CMD_DEC_FALC_CLOCK,
 398         MBOX_CMD_INC_SSPI_CLOCK,
 399         MBOX_CMD_DEC_SSPI_CLOCK,
 400         MBOX_CMD_SET_BW, /* no ACK/NAK required */
 401         MBOX_CMD_SET_SS_PWR_GATING,
 402         MBOX_CMD_SET_SS_PWR_UNGATING,
 403         MBOX_CMD_SAVE_DFE_CTLE_CTX,
 404         MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
 405         MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */
 406         MBOX_CMD_START_HSIC_IDLE,
 407         MBOX_CMD_STOP_HSIC_IDLE,
 408         MBOX_CMD_DBC_WAKE_STACK, /* unused */
 409         MBOX_CMD_HSIC_PRETEND_CONNECT,
 410         MBOX_CMD_RESET_SSPI,
 411         MBOX_CMD_DISABLE_SS_LFPS_DETECTION,
 412         MBOX_CMD_ENABLE_SS_LFPS_DETECTION,
 413
 414         MBOX_CMD_MAX,
 415
 416         /* Response message to above commands */
 417         MBOX_CMD_ACK = 128,
 418         MBOX_CMD_NAK
 419 };
 420
 421 struct tegra_xusb_mbox_msg {
 422         u32 cmd;
 423         u32 data;
 424 };
 425
 426 static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg)
 427 {
 428         return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT |
 429                (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT;
 430 }
 431 static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg,
 432                                           u32 value)
 433 {
 434         msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
 435         msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
 436 }
 437
 438 static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd)
 439 {
 440         switch (cmd) {
 441         case MBOX_CMD_SET_BW:
 442         case MBOX_CMD_ACK:
 443         case MBOX_CMD_NAK:
 444                 return false;
 445
 446         default:
 447                 return true;
 448         }
 449 }
 450
 451 static int tegra_xusb_mbox_send(struct tegra_xusb *tegra,
 452                                 const struct tegra_xusb_mbox_msg *msg)
 453 {
 454         bool wait_for_idle = false;
 455         u32 value;
 456
 457         /*
 458          * Acquire the mailbox. The firmware still owns the mailbox for
 459          * ACK/NAK messages.
 460          */
 461         if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) {
 462                 value = fpci_readl(tegra, tegra->soc->mbox.owner);
 463                 if (value != MBOX_OWNER_NONE) {
 464                         dev_err(tegra->dev, "mailbox is busy\n");
 465                         return -EBUSY;
 466                 }
 467
 468                 fpci_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner);
 469
 470                 value = fpci_readl(tegra, tegra->soc->mbox.owner);
 471                 if (value != MBOX_OWNER_SW) {
 472                         dev_err(tegra->dev, "failed to acquire mailbox\n");
 473                         return -EBUSY;
 474                 }
 475
 476                 wait_for_idle = true;
 477         }
 478
 479         value = tegra_xusb_mbox_pack(msg);
 480         fpci_writel(tegra, value, tegra->soc->mbox.data_in);
 481
 482         value = fpci_readl(tegra, tegra->soc->mbox.cmd);
 483         value |= MBOX_INT_EN | MBOX_DEST_FALC;
 484         fpci_writel(tegra, value, tegra->soc->mbox.cmd);
 485
 486         if (wait_for_idle) {
 487                 unsigned long timeout = jiffies + msecs_to_jiffies(250);
 488
 489                 while (time_before(jiffies, timeout)) {
 490                         value = fpci_readl(tegra, tegra->soc->mbox.owner);
 491                         if (value == MBOX_OWNER_NONE)
 492                                 break;
 493
 494                         usleep_range(10, 20);
 495                 }
 496
 497                 if (time_after(jiffies, timeout))
 498                         value = fpci_readl(tegra, tegra->soc->mbox.owner);
 499
 500                 if (value != MBOX_OWNER_NONE)
 501                         return -ETIMEDOUT;
 502         }
 503
 504         return 0;
 505 }
 506
 507 static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data)
 508 {
 509         struct tegra_xusb *tegra = data;
 510         u32 value;
 511
 512         /* clear mailbox interrupts */
 513         value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR);
 514         fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR);
 515
 516         if (value & MBOX_SMI_INTR_FW_HANG)
 517                 dev_err(tegra->dev, "controller firmware hang\n");
 518
 519         return IRQ_WAKE_THREAD;
 520 }
 521
 522 static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
 523                                    const struct tegra_xusb_mbox_msg *msg)
 524 {
 525         struct tegra_xusb_padctl *padctl = tegra->padctl;
 526         const struct tegra_xusb_soc *soc = tegra->soc;
 527         struct device *dev = tegra->dev;
 528         struct tegra_xusb_mbox_msg rsp;
 529         unsigned long mask;
 530         unsigned int port;
 531         bool idle, enable;
 532         int err = 0;
 533
 534         memset(&rsp, 0, sizeof(rsp));
 535
 536         switch (msg->cmd) {
 537         case MBOX_CMD_INC_FALC_CLOCK:
 538         case MBOX_CMD_DEC_FALC_CLOCK:
 539                 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000;
 540                 if (rsp.data != msg->data)
 541                         rsp.cmd = MBOX_CMD_NAK;
 542                 else
 543                         rsp.cmd = MBOX_CMD_ACK;
 544
 545                 break;
 546
 547         case MBOX_CMD_INC_SSPI_CLOCK:
 548         case MBOX_CMD_DEC_SSPI_CLOCK:
 549                 if (tegra->soc->scale_ss_clock) {
 550                         err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000);
 551                         if (err < 0)
 552                                 rsp.cmd = MBOX_CMD_NAK;
 553                         else
 554                                 rsp.cmd = MBOX_CMD_ACK;
 555
 556                         rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000;
 557                 } else {
 558                         rsp.cmd = MBOX_CMD_ACK;
 559                         rsp.data = msg->data;
 560                 }
 561
 562                 break;
 563
 564         case MBOX_CMD_SET_BW:
 565                 /*
 566                  * TODO: Request bandwidth once EMC scaling is supported.
 567                  * Ignore for now since ACK/NAK is not required for SET_BW
 568                  * messages.
 569                  */
 570                 break;
 571
 572         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
 573                 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data);
 574                 if (err < 0) {
 575                         dev_err(dev, "failed to save context for USB3#%u: %d\n",
 576                                 msg->data, err);
 577                         rsp.cmd = MBOX_CMD_NAK;
 578                 } else {
 579                         rsp.cmd = MBOX_CMD_ACK;
 580                 }
 581
 582                 rsp.data = msg->data;
 583                 break;
 584
 585         case MBOX_CMD_START_HSIC_IDLE:
 586         case MBOX_CMD_STOP_HSIC_IDLE:
 587                 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE)
 588                         idle = false;
 589                 else
 590                         idle = true;
 591
 592                 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset,
 593                                      soc->ports.hsic.count);
 594
 595                 for_each_set_bit(port, &mask, 32) {
 596                         err = tegra_xusb_padctl_hsic_set_idle(padctl, port,
 597                                                               idle);
 598                         if (err < 0)
 599                                 break;
 600                 }
 601
 602                 if (err < 0) {
 603                         dev_err(dev, "failed to set HSIC#%u %s: %d\n", port,
 604                                 idle ? "idle" : "busy", err);
 605                         rsp.cmd = MBOX_CMD_NAK;
 606                 } else {
 607                         rsp.cmd = MBOX_CMD_ACK;
 608                 }
 609
 610                 rsp.data = msg->data;
 611                 break;
 612
 613         case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
 614         case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
 615                 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION)
 616                         enable = false;
 617                 else
 618                         enable = true;
 619
 620                 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset,
 621                                      soc->ports.usb3.count);
 622
 623                 for_each_set_bit(port, &mask, soc->ports.usb3.count) {
 624                         err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl,
 625                                                                      port,
 626                                                                      enable);
 627                         if (err < 0)
 628                                 break;
 629
 630                         /*
 631                          * wait 500us for LFPS detector to be disabled before
 632                          * sending ACK
 633                          */
 634                         if (!enable)
 635                                 usleep_range(500, 1000);
 636                 }
 637
 638                 if (err < 0) {
 639                         dev_err(dev,
 640                                 "failed to %s LFPS detection on USB3#%u: %d\n",
 641                                 enable ? "enable" : "disable", port, err);
 642                         rsp.cmd = MBOX_CMD_NAK;
 643                 } else {
 644                         rsp.cmd = MBOX_CMD_ACK;
 645                 }
 646
 647                 rsp.data = msg->data;
 648                 break;
 649
 650         default:
 651                 dev_warn(dev, "unknown message: %#x\n", msg->cmd);
 652                 break;
 653         }
 654
 655         if (rsp.cmd) {
 656                 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK";
 657
 658                 err = tegra_xusb_mbox_send(tegra, &rsp);
 659                 if (err < 0)
 660                         dev_err(dev, "failed to send %s: %d\n", cmd, err);
 661         }
 662 }
 663
 664 static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data)
 665 {
 666         struct tegra_xusb *tegra = data;
 667         struct tegra_xusb_mbox_msg msg;
 668         u32 value;
 669
 670         mutex_lock(&tegra->lock);
 671
 672         if (pm_runtime_suspended(tegra->dev) || tegra->suspended)
 673                 goto out;
 674
 675         value = fpci_readl(tegra, tegra->soc->mbox.data_out);
 676         tegra_xusb_mbox_unpack(&msg, value);
 677
 678         value = fpci_readl(tegra, tegra->soc->mbox.cmd);
 679         value &= ~MBOX_DEST_SMI;
 680         fpci_writel(tegra, value, tegra->soc->mbox.cmd);
 681
 682         /* clear mailbox owner if no ACK/NAK is required */
 683         if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd))
 684                 fpci_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner);
 685
 686         tegra_xusb_mbox_handle(tegra, &msg);
 687
 688 out:
 689         mutex_unlock(&tegra->lock);
 690         return IRQ_HANDLED;
 691 }
 692
 693 static void tegra_xusb_config(struct tegra_xusb *tegra)
 694 {
 695         u32 regs = tegra->hcd->rsrc_start;
 696         u32 value;
 697
 698         if (tegra->soc->has_ipfs) {
 699                 value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0);
 700                 value |= IPFS_EN_FPCI;
 701                 ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0);
 702
 703                 usleep_range(10, 20);
 704         }
 705
 706         /* Program BAR0 space */
 707         value = fpci_readl(tegra, XUSB_CFG_4);
 708         value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
 709         value |= regs & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
 710         fpci_writel(tegra, value, XUSB_CFG_4);
 711
 712         usleep_range(100, 200);
 713
 714         /* Enable bus master */
 715         value = fpci_readl(tegra, XUSB_CFG_1);
 716         value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN;
 717         fpci_writel(tegra, value, XUSB_CFG_1);
 718
 719         if (tegra->soc->has_ipfs) {
 720                 /* Enable interrupt assertion */
 721                 value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0);
 722                 value |= IPFS_IP_INT_MASK;
 723                 ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0);
 724
 725                 /* Set hysteresis */
 726                 ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
 727         }
 728 }
 729
 730 static int tegra_xusb_clk_enable(struct tegra_xusb *tegra)
 731 {
 732         int err;
 733
 734         err = clk_prepare_enable(tegra->pll_e);
 735         if (err < 0)
 736                 return err;
 737
 738         err = clk_prepare_enable(tegra->host_clk);
 739         if (err < 0)
 740                 goto disable_plle;
 741
 742         err = clk_prepare_enable(tegra->ss_clk);
 743         if (err < 0)
 744                 goto disable_host;
 745
 746         err = clk_prepare_enable(tegra->falcon_clk);
 747         if (err < 0)
 748                 goto disable_ss;
 749
 750         err = clk_prepare_enable(tegra->fs_src_clk);
 751         if (err < 0)
 752                 goto disable_falc;
 753
 754         err = clk_prepare_enable(tegra->hs_src_clk);
 755         if (err < 0)
 756                 goto disable_fs_src;
 757
 758         if (tegra->soc->scale_ss_clock) {
 759                 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED);
 760                 if (err < 0)
 761                         goto disable_hs_src;
 762         }
 763
 764         return 0;
 765
 766 disable_hs_src:
 767         clk_disable_unprepare(tegra->hs_src_clk);
 768 disable_fs_src:
 769         clk_disable_unprepare(tegra->fs_src_clk);
 770 disable_falc:
 771         clk_disable_unprepare(tegra->falcon_clk);
 772 disable_ss:
 773         clk_disable_unprepare(tegra->ss_clk);
 774 disable_host:
 775         clk_disable_unprepare(tegra->host_clk);
 776 disable_plle:
 777         clk_disable_unprepare(tegra->pll_e);
 778         return err;
 779 }
 780
 781 static void tegra_xusb_clk_disable(struct tegra_xusb *tegra)
 782 {
 783         clk_disable_unprepare(tegra->pll_e);
 784         clk_disable_unprepare(tegra->host_clk);
 785         clk_disable_unprepare(tegra->ss_clk);
 786         clk_disable_unprepare(tegra->falcon_clk);
 787         clk_disable_unprepare(tegra->fs_src_clk);
 788         clk_disable_unprepare(tegra->hs_src_clk);
 789 }
 790
 791 static int tegra_xusb_phy_enable(struct tegra_xusb *tegra)
 792 {
 793         unsigned int i;
 794         int err;
 795
 796         for (i = 0; i < tegra->num_phys; i++) {
 797                 err = phy_init(tegra->phys[i]);
 798                 if (err)
 799                         goto disable_phy;
 800
 801                 err = phy_power_on(tegra->phys[i]);
 802                 if (err) {
 803                         phy_exit(tegra->phys[i]);
 804                         goto disable_phy;
 805                 }
 806         }
 807
 808         return 0;
 809
 810 disable_phy:
 811         while (i--) {
 812                 phy_power_off(tegra->phys[i]);
 813                 phy_exit(tegra->phys[i]);
 814         }
 815
 816         return err;
 817 }
 818
 819 static void tegra_xusb_phy_disable(struct tegra_xusb *tegra)
 820 {
 821         unsigned int i;
 822
 823         for (i = 0; i < tegra->num_phys; i++) {
 824                 phy_power_off(tegra->phys[i]);
 825                 phy_exit(tegra->phys[i]);
 826         }
 827 }
 828
 829 #ifdef CONFIG_PM_SLEEP
 830 static int tegra_xusb_init_context(struct tegra_xusb *tegra)
 831 {
 832         const struct tegra_xusb_context_soc *soc = tegra->soc->context;
 833
 834         tegra->context.ipfs = devm_kcalloc(tegra->dev, soc->ipfs.num_offsets,
 835                                            sizeof(u32), GFP_KERNEL);
 836         if (!tegra->context.ipfs)
 837                 return -ENOMEM;
 838
 839         tegra->context.fpci = devm_kcalloc(tegra->dev, soc->fpci.num_offsets,
 840                                            sizeof(u32), GFP_KERNEL);
 841         if (!tegra->context.fpci)
 842                 return -ENOMEM;
 843
 844         return 0;
 845 }
 846 #else
 847 static inline int tegra_xusb_init_context(struct tegra_xusb *tegra)
 848 {
 849         return 0;
 850 }
 851 #endif
 852
 853 static int tegra_xusb_request_firmware(struct tegra_xusb *tegra)
 854 {
 855         struct tegra_xusb_fw_header *header;
 856         const struct firmware *fw;
 857         int err;
 858
 859         err = request_firmware(&fw, tegra->soc->firmware, tegra->dev);
 860         if (err < 0) {
 861                 dev_err(tegra->dev, "failed to request firmware: %d\n", err);
 862                 return err;
 863         }
 864
 865         /* Load Falcon controller with its firmware. */
 866         header = (struct tegra_xusb_fw_header *)fw->data;
 867         tegra->fw.size = le32_to_cpu(header->fwimg_len);
 868
 869         tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size,
 870                                             &tegra->fw.phys, GFP_KERNEL);
 871         if (!tegra->fw.virt) {
 872                 dev_err(tegra->dev, "failed to allocate memory for firmware\n");
 873                 release_firmware(fw);
 874                 return -ENOMEM;
 875         }
 876
 877         header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
 878         memcpy(tegra->fw.virt, fw->data, tegra->fw.size);
 879         release_firmware(fw);
 880
 881         return 0;
 882 }
 883
 884 static int tegra_xusb_load_firmware(struct tegra_xusb *tegra)
 885 {
 886         unsigned int code_tag_blocks, code_size_blocks, code_blocks;
 887         struct xhci_cap_regs __iomem *cap = tegra->regs;
 888         struct tegra_xusb_fw_header *header;
 889         struct device *dev = tegra->dev;
 890         struct xhci_op_regs __iomem *op;
 891         unsigned long timeout;
 892         time64_t timestamp;
 893         struct tm time;
 894         u64 address;
 895         u32 value;
 896         int err;
 897
 898         header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
 899         op = tegra->regs + HC_LENGTH(readl(&cap->hc_capbase));
 900
 901         if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
 902                 dev_info(dev, "Firmware already loaded, Falcon state %#x\n",
 903                          csb_readl(tegra, XUSB_FALC_CPUCTL));
 904                 return 0;
 905         }
 906
 907         /* Program the size of DFI into ILOAD_ATTR. */
 908         csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR);
 909
 910         /*
 911          * Boot code of the firmware reads the ILOAD_BASE registers
 912          * to get to the start of the DFI in system memory.
 913          */
 914         address = tegra->fw.phys + sizeof(*header);
 915         csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI);
 916         csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO);
 917
 918         /* Set BOOTPATH to 1 in APMAP. */
 919         csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP);
 920
 921         /* Invalidate L2IMEM. */
 922         csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG);
 923
 924         /*
 925          * Initiate fetch of bootcode from system memory into L2IMEM.
 926          * Program bootcode location and size in system memory.
 927          */
 928         code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag),
 929                                        IMEM_BLOCK_SIZE);
 930         code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize),
 931                                         IMEM_BLOCK_SIZE);
 932         code_blocks = code_tag_blocks + code_size_blocks;
 933
 934         value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) <<
 935                         L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) |
 936                 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) <<
 937                         L2IMEMOP_SIZE_SRC_COUNT_SHIFT);
 938         csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE);
 939
 940         /* Trigger L2IMEM load operation. */
 941         csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT,
 942                    XUSB_CSB_MP_L2IMEMOP_TRIG);
 943
 944         /* Setup Falcon auto-fill. */
 945         csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL);
 946
 947         value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) <<
 948                         IMFILLRNG1_TAG_LO_SHIFT) |
 949                 ((code_blocks & IMFILLRNG1_TAG_MASK) <<
 950                         IMFILLRNG1_TAG_HI_SHIFT);
 951         csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1);
 952
 953         csb_writel(tegra, 0, XUSB_FALC_DMACTL);
 954
 955         /* wait for RESULT_VLD to get set */
 956 #define tegra_csb_readl(offset) csb_readl(tegra, offset)
 957         err = readx_poll_timeout(tegra_csb_readl,
 958                                  XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT, value,
 959                                  value & L2IMEMOP_RESULT_VLD, 100, 10000);
 960         if (err < 0) {
 961                 dev_err(dev, "DMA controller not ready %#010x\n", value);
 962                 return err;
 963         }
 964 #undef tegra_csb_readl
 965
 966         csb_writel(tegra, le32_to_cpu(header->boot_codetag),
 967                    XUSB_FALC_BOOTVEC);
 968
 969         /* Boot Falcon CPU and wait for USBSTS_CNR to get cleared. */
 970         csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL);
 971
 972         timeout = jiffies + msecs_to_jiffies(200);
 973
 974         do {
 975                 value = readl(&op->status);
 976                 if ((value & STS_CNR) == 0)
 977                         break;
 978
 979                 usleep_range(1000, 2000);
 980         } while (time_is_after_jiffies(timeout));
 981
 982         value = readl(&op->status);
 983         if (value & STS_CNR) {
 984                 value = csb_readl(tegra, XUSB_FALC_CPUCTL);
 985                 dev_err(dev, "XHCI controller not read: %#010x\n", value);
 986                 return -EIO;
 987         }
 988
 989         timestamp = le32_to_cpu(header->fwimg_created_time);
 990         time64_to_tm(timestamp, 0, &time);
 991
 992         dev_info(dev, "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC\n",
 993                  time.tm_year + 1900, time.tm_mon + 1, time.tm_mday,
 994                  time.tm_hour, time.tm_min, time.tm_sec);
 995
 996         return 0;
 997 }
 998
 999 static void tegra_xusb_powerdomain_remove(struct device *dev,
1000                                           struct tegra_xusb *tegra)
1001 {
1002         if (!tegra->use_genpd)
1003                 return;
1004
1005         if (!IS_ERR_OR_NULL(tegra->genpd_dev_ss))
1006                 dev_pm_domain_detach(tegra->genpd_dev_ss, true);
1007         if (!IS_ERR_OR_NULL(tegra->genpd_dev_host))
1008                 dev_pm_domain_detach(tegra->genpd_dev_host, true);
1009 }
1010
1011 static int tegra_xusb_powerdomain_init(struct device *dev,
1012                                        struct tegra_xusb *tegra)
1013 {
1014         int err;
1015
1016         tegra->genpd_dev_host = dev_pm_domain_attach_by_name(dev, "xusb_host");
1017         if (IS_ERR(tegra->genpd_dev_host)) {
1018                 err = PTR_ERR(tegra->genpd_dev_host);
1019                 dev_err(dev, "failed to get host pm-domain: %d\n", err);
1020                 return err;
1021         }
1022
1023         tegra->genpd_dev_ss = dev_pm_domain_attach_by_name(dev, "xusb_ss");
1024         if (IS_ERR(tegra->genpd_dev_ss)) {
1025                 err = PTR_ERR(tegra->genpd_dev_ss);
1026                 dev_err(dev, "failed to get superspeed pm-domain: %d\n", err);
1027                 return err;
1028         }
1029
1030         tegra->use_genpd = true;
1031
1032         return 0;
1033 }
1034
1035 static int tegra_xusb_unpowergate_partitions(struct tegra_xusb *tegra)
1036 {
1037         struct device *dev = tegra->dev;
1038         int rc;
1039
1040         if (tegra->use_genpd) {
1041                 rc = pm_runtime_get_sync(tegra->genpd_dev_ss);
1042                 if (rc < 0) {
1043                         dev_err(dev, "failed to enable XUSB SS partition\n");
1044                         return rc;
1045                 }
1046
1047                 rc = pm_runtime_get_sync(tegra->genpd_dev_host);
1048                 if (rc < 0) {
1049                         dev_err(dev, "failed to enable XUSB Host partition\n");
1050                         pm_runtime_put_sync(tegra->genpd_dev_ss);
1051                         return rc;
1052                 }
1053         } else {
1054                 rc = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA,
1055                                                         tegra->ss_clk,
1056                                                         tegra->ss_rst);
1057                 if (rc < 0) {
1058                         dev_err(dev, "failed to enable XUSB SS partition\n");
1059                         return rc;
1060                 }
1061
1062                 rc = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
1063                                                         tegra->host_clk,
1064                                                         tegra->host_rst);
1065                 if (rc < 0) {
1066                         dev_err(dev, "failed to enable XUSB Host partition\n");
1067                         tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1068                         return rc;
1069                 }
1070         }
1071
1072         return 0;
1073 }
1074
1075 static int tegra_xusb_powergate_partitions(struct tegra_xusb *tegra)
1076 {
1077         struct device *dev = tegra->dev;
1078         int rc;
1079
1080         if (tegra->use_genpd) {
1081                 rc = pm_runtime_put_sync(tegra->genpd_dev_host);
1082                 if (rc < 0) {
1083                         dev_err(dev, "failed to disable XUSB Host partition\n");
1084                         return rc;
1085                 }
1086
1087                 rc = pm_runtime_put_sync(tegra->genpd_dev_ss);
1088                 if (rc < 0) {
1089                         dev_err(dev, "failed to disable XUSB SS partition\n");
1090                         pm_runtime_get_sync(tegra->genpd_dev_host);
1091                         return rc;
1092                 }
1093         } else {
1094                 rc = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
1095                 if (rc < 0) {
1096                         dev_err(dev, "failed to disable XUSB Host partition\n");
1097                         return rc;
1098                 }
1099
1100                 rc = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1101                 if (rc < 0) {
1102                         dev_err(dev, "failed to disable XUSB SS partition\n");
1103                         tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
1104                                                           tegra->host_clk,
1105                                                           tegra->host_rst);
1106                         return rc;
1107                 }
1108         }
1109
1110         return 0;
1111 }
1112
1113 static int __tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra)
1114 {
1115         struct tegra_xusb_mbox_msg msg;
1116         int err;
1117
1118         /* Enable firmware messages from controller. */
1119         msg.cmd = MBOX_CMD_MSG_ENABLED;
1120         msg.data = 0;
1121
1122         err = tegra_xusb_mbox_send(tegra, &msg);
1123         if (err < 0)
1124                 dev_err(tegra->dev, "failed to enable messages: %d\n", err);
1125
1126         return err;
1127 }
1128
1129 static irqreturn_t tegra_xusb_padctl_irq(int irq, void *data)
1130 {
1131         struct tegra_xusb *tegra = data;
1132
1133         mutex_lock(&tegra->lock);
1134
1135         if (tegra->suspended) {
1136                 mutex_unlock(&tegra->lock);
1137                 return IRQ_HANDLED;
1138         }
1139
1140         mutex_unlock(&tegra->lock);
1141
1142         pm_runtime_resume(tegra->dev);
1143
1144         return IRQ_HANDLED;
1145 }
1146
1147 static int tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra)
1148 {
1149         int err;
1150
1151         mutex_lock(&tegra->lock);
1152         err = __tegra_xusb_enable_firmware_messages(tegra);
1153         mutex_unlock(&tegra->lock);
1154
1155         return err;
1156 }
1157
1158 static void tegra_xhci_set_port_power(struct tegra_xusb *tegra, bool main,
1159                                                  bool set)
1160 {
1161         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1162         struct usb_hcd *hcd = main ?  xhci->main_hcd : xhci->shared_hcd;
1163         unsigned int wait = (!main && !set) ? 1000 : 10;
1164         u16 typeReq = set ? SetPortFeature : ClearPortFeature;
1165         u16 wIndex = main ? tegra->otg_usb2_port + 1 : tegra->otg_usb3_port + 1;
1166         u32 status;
1167         u32 stat_power = main ? USB_PORT_STAT_POWER : USB_SS_PORT_STAT_POWER;
1168         u32 status_val = set ? stat_power : 0;
1169
1170         dev_dbg(tegra->dev, "%s():%s %s port power\n", __func__,
1171                 set ? "set" : "clear", main ? "HS" : "SS");
1172
1173         hcd->driver->hub_control(hcd, typeReq, USB_PORT_FEAT_POWER, wIndex,
1174                                  NULL, 0);
1175
1176         do {
1177                 tegra_xhci_hc_driver.hub_control(hcd, GetPortStatus, 0, wIndex,
1178                                         (char *) &status, sizeof(status));
1179                 if (status_val == (status & stat_power))
1180                         break;
1181
1182                 if (!main && !set)
1183                         usleep_range(600, 700);
1184                 else
1185                         usleep_range(10, 20);
1186         } while (--wait > 0);
1187
1188         if (status_val != (status & stat_power))
1189                 dev_info(tegra->dev, "failed to %s %s PP %d\n",
1190                                                 set ? "set" : "clear",
1191                                                 main ? "HS" : "SS", status);
1192 }
1193
1194 static struct phy *tegra_xusb_get_phy(struct tegra_xusb *tegra, char *name,
1195                                                                 int port)
1196 {
1197         unsigned int i, phy_count = 0;
1198
1199         for (i = 0; i < tegra->soc->num_types; i++) {
1200                 if (!strncmp(tegra->soc->phy_types[i].name, name,
1201                                                             strlen(name)))
1202                         return tegra->phys[phy_count+port];
1203
1204                 phy_count += tegra->soc->phy_types[i].num;
1205         }
1206
1207         return NULL;
1208 }
1209
1210 static void tegra_xhci_id_work(struct work_struct *work)
1211 {
1212         struct tegra_xusb *tegra = container_of(work, struct tegra_xusb,
1213                                                 id_work);
1214         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1215         struct tegra_xusb_mbox_msg msg;
1216         struct phy *phy = tegra_xusb_get_phy(tegra, "usb2",
1217                                                     tegra->otg_usb2_port);
1218         u32 status;
1219         int ret;
1220
1221         dev_dbg(tegra->dev, "host mode %s\n", tegra->host_mode ? "on" : "off");
1222
1223         mutex_lock(&tegra->lock);
1224
1225         if (tegra->host_mode)
1226                 phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_HOST);
1227         else
1228                 phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_NONE);
1229
1230         mutex_unlock(&tegra->lock);
1231
1232         if (tegra->host_mode) {
1233                 /* switch to host mode */
1234                 if (tegra->otg_usb3_port >= 0) {
1235                         if (tegra->soc->otg_reset_sspi) {
1236                                 /* set PP=0 */
1237                                 tegra_xhci_hc_driver.hub_control(
1238                                         xhci->shared_hcd, GetPortStatus,
1239                                         0, tegra->otg_usb3_port+1,
1240                                         (char *) &status, sizeof(status));
1241                                 if (status & USB_SS_PORT_STAT_POWER)
1242                                         tegra_xhci_set_port_power(tegra, false,
1243                                                                   false);
1244
1245                                 /* reset OTG port SSPI */
1246                                 msg.cmd = MBOX_CMD_RESET_SSPI;
1247                                 msg.data = tegra->otg_usb3_port+1;
1248
1249                                 ret = tegra_xusb_mbox_send(tegra, &msg);
1250                                 if (ret < 0) {
1251                                         dev_info(tegra->dev,
1252                                                 "failed to RESET_SSPI %d\n",
1253                                                 ret);
1254                                 }
1255                         }
1256
1257                         tegra_xhci_set_port_power(tegra, false, true);
1258                 }
1259
1260                 tegra_xhci_set_port_power(tegra, true, true);
1261
1262         } else {
1263                 if (tegra->otg_usb3_port >= 0)
1264                         tegra_xhci_set_port_power(tegra, false, false);
1265
1266                 tegra_xhci_set_port_power(tegra, true, false);
1267         }
1268 }
1269
1270 #if IS_ENABLED(CONFIG_PM) || IS_ENABLED(CONFIG_PM_SLEEP)
1271 static bool is_usb2_otg_phy(struct tegra_xusb *tegra, unsigned int index)
1272 {
1273         return (tegra->usbphy[index] != NULL);
1274 }
1275
1276 static bool is_usb3_otg_phy(struct tegra_xusb *tegra, unsigned int index)
1277 {
1278         struct tegra_xusb_padctl *padctl = tegra->padctl;
1279         unsigned int i;
1280         int port;
1281
1282         for (i = 0; i < tegra->num_usb_phys; i++) {
1283                 if (is_usb2_otg_phy(tegra, i)) {
1284                         port = tegra_xusb_padctl_get_usb3_companion(padctl, i);
1285                         if ((port >= 0) && (index == (unsigned int)port))
1286                                 return true;
1287                 }
1288         }
1289
1290         return false;
1291 }
1292
1293 static bool is_host_mode_phy(struct tegra_xusb *tegra, unsigned int phy_type, unsigned int index)
1294 {
1295         if (strcmp(tegra->soc->phy_types[phy_type].name, "hsic") == 0)
1296                 return true;
1297
1298         if (strcmp(tegra->soc->phy_types[phy_type].name, "usb2") == 0) {
1299                 if (is_usb2_otg_phy(tegra, index))
1300                         return ((index == tegra->otg_usb2_port) && tegra->host_mode);
1301                 else
1302                         return true;
1303         }
1304
1305         if (strcmp(tegra->soc->phy_types[phy_type].name, "usb3") == 0) {
1306                 if (is_usb3_otg_phy(tegra, index))
1307                         return ((index == tegra->otg_usb3_port) && tegra->host_mode);
1308                 else
1309                         return true;
1310         }
1311
1312         return false;
1313 }
1314 #endif
1315
1316 static int tegra_xusb_get_usb2_port(struct tegra_xusb *tegra,
1317                                               struct usb_phy *usbphy)
1318 {
1319         unsigned int i;
1320
1321         for (i = 0; i < tegra->num_usb_phys; i++) {
1322                 if (tegra->usbphy[i] && usbphy == tegra->usbphy[i])
1323                         return i;
1324         }
1325
1326         return -1;
1327 }
1328
1329 static int tegra_xhci_id_notify(struct notifier_block *nb,
1330                                          unsigned long action, void *data)
1331 {
1332         struct tegra_xusb *tegra = container_of(nb, struct tegra_xusb,
1333                                                     id_nb);
1334         struct usb_phy *usbphy = (struct usb_phy *)data;
1335
1336         dev_dbg(tegra->dev, "%s(): action is %d", __func__, usbphy->last_event);
1337
1338         if ((tegra->host_mode && usbphy->last_event == USB_EVENT_ID) ||
1339                 (!tegra->host_mode && usbphy->last_event != USB_EVENT_ID)) {
1340                 dev_dbg(tegra->dev, "Same role(%d) received. Ignore",
1341                         tegra->host_mode);
1342                 return NOTIFY_OK;
1343         }
1344
1345         tegra->otg_usb2_port = tegra_xusb_get_usb2_port(tegra, usbphy);
1346         tegra->otg_usb3_port = tegra_xusb_padctl_get_usb3_companion(
1347                                                         tegra->padctl,
1348                                                         tegra->otg_usb2_port);
1349
1350         tegra->host_mode = (usbphy->last_event == USB_EVENT_ID) ? true : false;
1351
1352         schedule_work(&tegra->id_work);
1353
1354         return NOTIFY_OK;
1355 }
1356
1357 static int tegra_xusb_init_usb_phy(struct tegra_xusb *tegra)
1358 {
1359         unsigned int i;
1360
1361         tegra->usbphy = devm_kcalloc(tegra->dev, tegra->num_usb_phys,
1362                                    sizeof(*tegra->usbphy), GFP_KERNEL);
1363         if (!tegra->usbphy)
1364                 return -ENOMEM;
1365
1366         INIT_WORK(&tegra->id_work, tegra_xhci_id_work);
1367         tegra->id_nb.notifier_call = tegra_xhci_id_notify;
1368         tegra->otg_usb2_port = -EINVAL;
1369         tegra->otg_usb3_port = -EINVAL;
1370
1371         for (i = 0; i < tegra->num_usb_phys; i++) {
1372                 struct phy *phy = tegra_xusb_get_phy(tegra, "usb2", i);
1373
1374                 if (!phy)
1375                         continue;
1376
1377                 tegra->usbphy[i] = devm_usb_get_phy_by_node(tegra->dev,
1378                                                         phy->dev.of_node,
1379                                                         &tegra->id_nb);
1380                 if (!IS_ERR(tegra->usbphy[i])) {
1381                         dev_dbg(tegra->dev, "usbphy-%d registered", i);
1382                         otg_set_host(tegra->usbphy[i]->otg, &tegra->hcd->self);
1383                 } else {
1384                         /*
1385                          * usb-phy is optional, continue if its not available.
1386                          */
1387                         tegra->usbphy[i] = NULL;
1388                 }
1389         }
1390
1391         return 0;
1392 }
1393
1394 static void tegra_xusb_deinit_usb_phy(struct tegra_xusb *tegra)
1395 {
1396         unsigned int i;
1397
1398         cancel_work_sync(&tegra->id_work);
1399
1400         for (i = 0; i < tegra->num_usb_phys; i++)
1401                 if (tegra->usbphy[i])
1402                         otg_set_host(tegra->usbphy[i]->otg, NULL);
1403 }
1404
1405 static int tegra_xusb_probe(struct platform_device *pdev)
1406 {
1407         struct tegra_xusb *tegra;
1408         struct device_node *np;
1409         struct resource *regs;
1410         struct xhci_hcd *xhci;
1411         unsigned int i, j, k;
1412         struct phy *phy;
1413         int err;
1414
1415         BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256);
1416
1417         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
1418         if (!tegra)
1419                 return -ENOMEM;
1420
1421         tegra->soc = of_device_get_match_data(&pdev->dev);
1422         mutex_init(&tegra->lock);
1423         tegra->dev = &pdev->dev;
1424
1425         err = tegra_xusb_init_context(tegra);
1426         if (err < 0)
1427                 return err;
1428
1429         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1430         tegra->regs = devm_ioremap_resource(&pdev->dev, regs);
1431         if (IS_ERR(tegra->regs))
1432                 return PTR_ERR(tegra->regs);
1433
1434         tegra->fpci_base = devm_platform_ioremap_resource(pdev, 1);
1435         if (IS_ERR(tegra->fpci_base))
1436                 return PTR_ERR(tegra->fpci_base);
1437
1438         if (tegra->soc->has_ipfs) {
1439                 tegra->ipfs_base = devm_platform_ioremap_resource(pdev, 2);
1440                 if (IS_ERR(tegra->ipfs_base))
1441                         return PTR_ERR(tegra->ipfs_base);
1442         }
1443
1444         tegra->xhci_irq = platform_get_irq(pdev, 0);
1445         if (tegra->xhci_irq < 0)
1446                 return tegra->xhci_irq;
1447
1448         tegra->mbox_irq = platform_get_irq(pdev, 1);
1449         if (tegra->mbox_irq < 0)
1450                 return tegra->mbox_irq;
1451
1452         tegra->padctl = tegra_xusb_padctl_get(&pdev->dev);
1453         if (IS_ERR(tegra->padctl))
1454                 return PTR_ERR(tegra->padctl);
1455
1456         np = of_parse_phandle(pdev->dev.of_node, "nvidia,xusb-padctl", 0);
1457         if (!np)
1458                 return -ENODEV;
1459
1460         tegra->padctl_irq = of_irq_get(np, 0);
1461         if (tegra->padctl_irq <= 0)
1462                 return (tegra->padctl_irq == 0) ? -ENODEV : tegra->padctl_irq;
1463
1464         tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host");
1465         if (IS_ERR(tegra->host_clk)) {
1466                 err = PTR_ERR(tegra->host_clk);
1467                 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err);
1468                 goto put_padctl;
1469         }
1470
1471         tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src");
1472         if (IS_ERR(tegra->falcon_clk)) {
1473                 err = PTR_ERR(tegra->falcon_clk);
1474                 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err);
1475                 goto put_padctl;
1476         }
1477
1478         tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss");
1479         if (IS_ERR(tegra->ss_clk)) {
1480                 err = PTR_ERR(tegra->ss_clk);
1481                 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err);
1482                 goto put_padctl;
1483         }
1484
1485         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src");
1486         if (IS_ERR(tegra->ss_src_clk)) {
1487                 err = PTR_ERR(tegra->ss_src_clk);
1488                 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err);
1489                 goto put_padctl;
1490         }
1491
1492         tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src");
1493         if (IS_ERR(tegra->hs_src_clk)) {
1494                 err = PTR_ERR(tegra->hs_src_clk);
1495                 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err);
1496                 goto put_padctl;
1497         }
1498
1499         tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src");
1500         if (IS_ERR(tegra->fs_src_clk)) {
1501                 err = PTR_ERR(tegra->fs_src_clk);
1502                 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err);
1503                 goto put_padctl;
1504         }
1505
1506         tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m");
1507         if (IS_ERR(tegra->pll_u_480m)) {
1508                 err = PTR_ERR(tegra->pll_u_480m);
1509                 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err);
1510                 goto put_padctl;
1511         }
1512
1513         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1514         if (IS_ERR(tegra->clk_m)) {
1515                 err = PTR_ERR(tegra->clk_m);
1516                 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err);
1517                 goto put_padctl;
1518         }
1519
1520         tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e");
1521         if (IS_ERR(tegra->pll_e)) {
1522                 err = PTR_ERR(tegra->pll_e);
1523                 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err);
1524                 goto put_padctl;
1525         }
1526
1527         if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
1528                 tegra->host_rst = devm_reset_control_get(&pdev->dev,
1529                                                          "xusb_host");
1530                 if (IS_ERR(tegra->host_rst)) {
1531                         err = PTR_ERR(tegra->host_rst);
1532                         dev_err(&pdev->dev,
1533                                 "failed to get xusb_host reset: %d\n", err);
1534                         goto put_padctl;
1535                 }
1536
1537                 tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss");
1538                 if (IS_ERR(tegra->ss_rst)) {
1539                         err = PTR_ERR(tegra->ss_rst);
1540                         dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n",
1541                                 err);
1542                         goto put_padctl;
1543                 }
1544         } else {
1545                 err = tegra_xusb_powerdomain_init(&pdev->dev, tegra);
1546                 if (err)
1547                         goto put_powerdomains;
1548         }
1549
1550         tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies,
1551                                        sizeof(*tegra->supplies), GFP_KERNEL);
1552         if (!tegra->supplies) {
1553                 err = -ENOMEM;
1554                 goto put_powerdomains;
1555         }
1556
1557         regulator_bulk_set_supply_names(tegra->supplies,
1558                                         tegra->soc->supply_names,
1559                                         tegra->soc->num_supplies);
1560
1561         err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies,
1562                                       tegra->supplies);
1563         if (err) {
1564                 dev_err(&pdev->dev, "failed to get regulators: %d\n", err);
1565                 goto put_powerdomains;
1566         }
1567
1568         for (i = 0; i < tegra->soc->num_types; i++) {
1569                 if (!strncmp(tegra->soc->phy_types[i].name, "usb2", 4))
1570                         tegra->num_usb_phys = tegra->soc->phy_types[i].num;
1571                 tegra->num_phys += tegra->soc->phy_types[i].num;
1572         }
1573
1574         tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys,
1575                                    sizeof(*tegra->phys), GFP_KERNEL);
1576         if (!tegra->phys) {
1577                 err = -ENOMEM;
1578                 goto put_powerdomains;
1579         }
1580
1581         for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
1582                 char prop[8];
1583
1584                 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
1585                         snprintf(prop, sizeof(prop), "%s-%d",
1586                                  tegra->soc->phy_types[i].name, j);
1587
1588                         phy = devm_phy_optional_get(&pdev->dev, prop);
1589                         if (IS_ERR(phy)) {
1590                                 dev_err(&pdev->dev,
1591                                         "failed to get PHY %s: %ld\n", prop,
1592                                         PTR_ERR(phy));
1593                                 err = PTR_ERR(phy);
1594                                 goto put_powerdomains;
1595                         }
1596
1597                         tegra->phys[k++] = phy;
1598                 }
1599         }
1600
1601         tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev,
1602                                     dev_name(&pdev->dev));
1603         if (!tegra->hcd) {
1604                 err = -ENOMEM;
1605                 goto put_powerdomains;
1606         }
1607
1608         tegra->hcd->skip_phy_initialization = 1;
1609         tegra->hcd->regs = tegra->regs;
1610         tegra->hcd->rsrc_start = regs->start;
1611         tegra->hcd->rsrc_len = resource_size(regs);
1612
1613         /*
1614          * This must happen after usb_create_hcd(), because usb_create_hcd()
1615          * will overwrite the drvdata of the device with the hcd it creates.
1616          */
1617         platform_set_drvdata(pdev, tegra);
1618
1619         err = tegra_xusb_clk_enable(tegra);
1620         if (err) {
1621                 dev_err(tegra->dev, "failed to enable clocks: %d\n", err);
1622                 goto put_hcd;
1623         }
1624
1625         err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies);
1626         if (err) {
1627                 dev_err(tegra->dev, "failed to enable regulators: %d\n", err);
1628                 goto disable_clk;
1629         }
1630
1631         err = tegra_xusb_phy_enable(tegra);
1632         if (err < 0) {
1633                 dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err);
1634                 goto disable_regulator;
1635         }
1636
1637         /*
1638          * The XUSB Falcon microcontroller can only address 40 bits, so set
1639          * the DMA mask accordingly.
1640          */
1641         err = dma_set_mask_and_coherent(tegra->dev, DMA_BIT_MASK(40));
1642         if (err < 0) {
1643                 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
1644                 goto disable_phy;
1645         }
1646
1647         err = tegra_xusb_request_firmware(tegra);
1648         if (err < 0) {
1649                 dev_err(&pdev->dev, "failed to request firmware: %d\n", err);
1650                 goto disable_phy;
1651         }
1652
1653         err = tegra_xusb_unpowergate_partitions(tegra);
1654         if (err)
1655                 goto free_firmware;
1656
1657         tegra_xusb_config(tegra);
1658
1659         err = tegra_xusb_load_firmware(tegra);
1660         if (err < 0) {
1661                 dev_err(&pdev->dev, "failed to load firmware: %d\n", err);
1662                 goto powergate;
1663         }
1664
1665         err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED);
1666         if (err < 0) {
1667                 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err);
1668                 goto powergate;
1669         }
1670
1671         device_wakeup_enable(tegra->hcd->self.controller);
1672
1673         xhci = hcd_to_xhci(tegra->hcd);
1674
1675         xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver,
1676                                                  &pdev->dev,
1677                                                  dev_name(&pdev->dev),
1678                                                  tegra->hcd);
1679         if (!xhci->shared_hcd) {
1680                 dev_err(&pdev->dev, "failed to create shared HCD\n");
1681                 err = -ENOMEM;
1682                 goto remove_usb2;
1683         }
1684
1685         err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED);
1686         if (err < 0) {
1687                 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err);
1688                 goto put_usb3;
1689         }
1690
1691         err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq,
1692                                         tegra_xusb_mbox_irq,
1693                                         tegra_xusb_mbox_thread, 0,
1694                                         dev_name(&pdev->dev), tegra);
1695         if (err < 0) {
1696                 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1697                 goto remove_usb3;
1698         }
1699
1700         err = devm_request_threaded_irq(&pdev->dev, tegra->padctl_irq, NULL, tegra_xusb_padctl_irq,
1701                                         IRQF_ONESHOT, dev_name(&pdev->dev), tegra);
1702         if (err < 0) {
1703                 dev_err(&pdev->dev, "failed to request padctl IRQ: %d\n", err);
1704                 goto remove_usb3;
1705         }
1706
1707         err = tegra_xusb_enable_firmware_messages(tegra);
1708         if (err < 0) {
1709                 dev_err(&pdev->dev, "failed to enable messages: %d\n", err);
1710                 goto remove_usb3;
1711         }
1712
1713         err = tegra_xusb_init_usb_phy(tegra);
1714         if (err < 0) {
1715                 dev_err(&pdev->dev, "failed to init USB PHY: %d\n", err);
1716                 goto remove_usb3;
1717         }
1718
1719         /* Enable wake for both USB 2.0 and USB 3.0 roothubs */
1720         device_init_wakeup(&tegra->hcd->self.root_hub->dev, true);
1721         device_init_wakeup(&xhci->shared_hcd->self.root_hub->dev, true);
1722         device_init_wakeup(tegra->dev, true);
1723
1724         pm_runtime_use_autosuspend(tegra->dev);
1725         pm_runtime_set_autosuspend_delay(tegra->dev, 2000);
1726         pm_runtime_mark_last_busy(tegra->dev);
1727         pm_runtime_set_active(tegra->dev);
1728         pm_runtime_enable(tegra->dev);
1729
1730         return 0;
1731
1732 remove_usb3:
1733         usb_remove_hcd(xhci->shared_hcd);
1734 put_usb3:
1735         usb_put_hcd(xhci->shared_hcd);
1736 remove_usb2:
1737         usb_remove_hcd(tegra->hcd);
1738 powergate:
1739         tegra_xusb_powergate_partitions(tegra);
1740 free_firmware:
1741         dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1742                           tegra->fw.phys);
1743 disable_phy:
1744         tegra_xusb_phy_disable(tegra);
1745 disable_regulator:
1746         regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
1747 disable_clk:
1748         tegra_xusb_clk_disable(tegra);
1749 put_hcd:
1750         usb_put_hcd(tegra->hcd);
1751 put_powerdomains:
1752         tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
1753 put_padctl:
1754         tegra_xusb_padctl_put(tegra->padctl);
1755         return err;
1756 }
1757
1758 static int tegra_xusb_remove(struct platform_device *pdev)
1759 {
1760         struct tegra_xusb *tegra = platform_get_drvdata(pdev);
1761         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1762
1763         tegra_xusb_deinit_usb_phy(tegra);
1764
1765         pm_runtime_get_sync(&pdev->dev);
1766         usb_remove_hcd(xhci->shared_hcd);
1767         usb_put_hcd(xhci->shared_hcd);
1768         xhci->shared_hcd = NULL;
1769         usb_remove_hcd(tegra->hcd);
1770         usb_put_hcd(tegra->hcd);
1771
1772         dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1773                           tegra->fw.phys);
1774
1775         pm_runtime_disable(&pdev->dev);
1776         pm_runtime_put(&pdev->dev);
1777
1778         tegra_xusb_powergate_partitions(tegra);
1779
1780         tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
1781
1782         tegra_xusb_phy_disable(tegra);
1783         tegra_xusb_clk_disable(tegra);
1784         regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
1785         tegra_xusb_padctl_put(tegra->padctl);
1786
1787         return 0;
1788 }
1789
1790 #if IS_ENABLED(CONFIG_PM) || IS_ENABLED(CONFIG_PM_SLEEP)
1791 static bool xhci_hub_ports_suspended(struct xhci_hub *hub)
1792 {
1793         struct device *dev = hub->hcd->self.controller;
1794         bool status = true;
1795         unsigned int i;
1796         u32 value;
1797
1798         for (i = 0; i < hub->num_ports; i++) {
1799                 value = readl(hub->ports[i]->addr);
1800                 if ((value & PORT_PE) == 0)
1801                         continue;
1802
1803                 if ((value & PORT_PLS_MASK) != XDEV_U3) {
1804                         dev_info(dev, "%u-%u isn't suspended: %#010x\n",
1805                                  hub->hcd->self.busnum, i + 1, value);
1806                         status = false;
1807                 }
1808         }
1809
1810         return status;
1811 }
1812
1813 static int tegra_xusb_check_ports(struct tegra_xusb *tegra)
1814 {
1815         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1816         struct xhci_bus_state *bus_state = &xhci->usb2_rhub.bus_state;
1817         unsigned long flags;
1818         int err = 0;
1819
1820         if (bus_state->bus_suspended) {
1821                 /* xusb_hub_suspend() has just directed one or more USB2 port(s)
1822                  * to U3 state, it takes 3ms to enter U3.
1823                  */
1824                 usleep_range(3000, 4000);
1825         }
1826
1827         spin_lock_irqsave(&xhci->lock, flags);
1828
1829         if (!xhci_hub_ports_suspended(&xhci->usb2_rhub) ||
1830             !xhci_hub_ports_suspended(&xhci->usb3_rhub))
1831                 err = -EBUSY;
1832
1833         spin_unlock_irqrestore(&xhci->lock, flags);
1834
1835         return err;
1836 }
1837
1838 static void tegra_xusb_save_context(struct tegra_xusb *tegra)
1839 {
1840         const struct tegra_xusb_context_soc *soc = tegra->soc->context;
1841         struct tegra_xusb_context *ctx = &tegra->context;
1842         unsigned int i;
1843
1844         if (soc->ipfs.num_offsets > 0) {
1845                 for (i = 0; i < soc->ipfs.num_offsets; i++)
1846                         ctx->ipfs[i] = ipfs_readl(tegra, soc->ipfs.offsets[i]);
1847         }
1848
1849         if (soc->fpci.num_offsets > 0) {
1850                 for (i = 0; i < soc->fpci.num_offsets; i++)
1851                         ctx->fpci[i] = fpci_readl(tegra, soc->fpci.offsets[i]);
1852         }
1853 }
1854
1855 static void tegra_xusb_restore_context(struct tegra_xusb *tegra)
1856 {
1857         const struct tegra_xusb_context_soc *soc = tegra->soc->context;
1858         struct tegra_xusb_context *ctx = &tegra->context;
1859         unsigned int i;
1860
1861         if (soc->fpci.num_offsets > 0) {
1862                 for (i = 0; i < soc->fpci.num_offsets; i++)
1863                         fpci_writel(tegra, ctx->fpci[i], soc->fpci.offsets[i]);
1864         }
1865
1866         if (soc->ipfs.num_offsets > 0) {
1867                 for (i = 0; i < soc->ipfs.num_offsets; i++)
1868                         ipfs_writel(tegra, ctx->ipfs[i], soc->ipfs.offsets[i]);
1869         }
1870 }
1871
1872 static enum usb_device_speed tegra_xhci_portsc_to_speed(struct tegra_xusb *tegra, u32 portsc)
1873 {
1874         if (DEV_LOWSPEED(portsc))
1875                 return USB_SPEED_LOW;
1876
1877         if (DEV_HIGHSPEED(portsc))
1878                 return USB_SPEED_HIGH;
1879
1880         if (DEV_FULLSPEED(portsc))
1881                 return USB_SPEED_FULL;
1882
1883         if (DEV_SUPERSPEED_ANY(portsc))
1884                 return USB_SPEED_SUPER;
1885
1886         return USB_SPEED_UNKNOWN;
1887 }
1888
1889 static void tegra_xhci_enable_phy_sleepwalk_wake(struct tegra_xusb *tegra)
1890 {
1891         struct tegra_xusb_padctl *padctl = tegra->padctl;
1892         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1893         enum usb_device_speed speed;
1894         struct phy *phy;
1895         unsigned int index, offset;
1896         unsigned int i, j, k;
1897         struct xhci_hub *rhub;
1898         u32 portsc;
1899
1900         for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
1901                 if (strcmp(tegra->soc->phy_types[i].name, "usb3") == 0)
1902                         rhub = &xhci->usb3_rhub;
1903                 else
1904                         rhub = &xhci->usb2_rhub;
1905
1906                 if (strcmp(tegra->soc->phy_types[i].name, "hsic") == 0)
1907                         offset = tegra->soc->ports.usb2.count;
1908                 else
1909                         offset = 0;
1910
1911                 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
1912                         phy = tegra->phys[k++];
1913
1914                         if (!phy)
1915                                 continue;
1916
1917                         index = j + offset;
1918
1919                         if (index >= rhub->num_ports)
1920                                 continue;
1921
1922                         if (!is_host_mode_phy(tegra, i, j))
1923                                 continue;
1924
1925                         portsc = readl(rhub->ports[index]->addr);
1926                         speed = tegra_xhci_portsc_to_speed(tegra, portsc);
1927                         tegra_xusb_padctl_enable_phy_sleepwalk(padctl, phy, speed);
1928                         tegra_xusb_padctl_enable_phy_wake(padctl, phy);
1929                 }
1930         }
1931 }
1932
1933 static void tegra_xhci_disable_phy_wake(struct tegra_xusb *tegra)
1934 {
1935         struct tegra_xusb_padctl *padctl = tegra->padctl;
1936         unsigned int i;
1937
1938         for (i = 0; i < tegra->num_phys; i++) {
1939                 if (!tegra->phys[i])
1940                         continue;
1941
1942                 tegra_xusb_padctl_disable_phy_wake(padctl, tegra->phys[i]);
1943         }
1944 }
1945
1946 static void tegra_xhci_disable_phy_sleepwalk(struct tegra_xusb *tegra)
1947 {
1948         struct tegra_xusb_padctl *padctl = tegra->padctl;
1949         unsigned int i;
1950
1951         for (i = 0; i < tegra->num_phys; i++) {
1952                 if (!tegra->phys[i])
1953                         continue;
1954
1955                 tegra_xusb_padctl_disable_phy_sleepwalk(padctl, tegra->phys[i]);
1956         }
1957 }
1958
1959 static int tegra_xusb_enter_elpg(struct tegra_xusb *tegra, bool runtime)
1960 {
1961         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1962         struct device *dev = tegra->dev;
1963         bool wakeup = runtime ? true : device_may_wakeup(dev);
1964         unsigned int i;
1965         int err;
1966         u32 usbcmd;
1967
1968         dev_dbg(dev, "entering ELPG\n");
1969
1970         usbcmd = readl(&xhci->op_regs->command);
1971         usbcmd &= ~CMD_EIE;
1972         writel(usbcmd, &xhci->op_regs->command);
1973
1974         err = tegra_xusb_check_ports(tegra);
1975         if (err < 0) {
1976                 dev_err(tegra->dev, "not all ports suspended: %d\n", err);
1977                 goto out;
1978         }
1979
1980         err = xhci_suspend(xhci, wakeup);
1981         if (err < 0) {
1982                 dev_err(tegra->dev, "failed to suspend XHCI: %d\n", err);
1983                 goto out;
1984         }
1985
1986         tegra_xusb_save_context(tegra);
1987
1988         if (wakeup)
1989                 tegra_xhci_enable_phy_sleepwalk_wake(tegra);
1990
1991         tegra_xusb_powergate_partitions(tegra);
1992
1993         for (i = 0; i < tegra->num_phys; i++) {
1994                 if (!tegra->phys[i])
1995                         continue;
1996
1997                 phy_power_off(tegra->phys[i]);
1998                 if (!wakeup)
1999                         phy_exit(tegra->phys[i]);
2000         }
2001
2002         tegra_xusb_clk_disable(tegra);
2003
2004 out:
2005         if (!err)
2006                 dev_dbg(tegra->dev, "entering ELPG done\n");
2007         else {
2008                 usbcmd = readl(&xhci->op_regs->command);
2009                 usbcmd |= CMD_EIE;
2010                 writel(usbcmd, &xhci->op_regs->command);
2011
2012                 dev_dbg(tegra->dev, "entering ELPG failed\n");
2013                 pm_runtime_mark_last_busy(tegra->dev);
2014         }
2015
2016         return err;
2017 }
2018
2019 static int tegra_xusb_exit_elpg(struct tegra_xusb *tegra, bool runtime)
2020 {
2021         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
2022         struct device *dev = tegra->dev;
2023         bool wakeup = runtime ? true : device_may_wakeup(dev);
2024         unsigned int i;
2025         u32 usbcmd;
2026         int err;
2027
2028         dev_dbg(dev, "exiting ELPG\n");
2029         pm_runtime_mark_last_busy(tegra->dev);
2030
2031         err = tegra_xusb_clk_enable(tegra);
2032         if (err < 0) {
2033                 dev_err(tegra->dev, "failed to enable clocks: %d\n", err);
2034                 goto out;
2035         }
2036
2037         err = tegra_xusb_unpowergate_partitions(tegra);
2038         if (err)
2039                 goto disable_clks;
2040
2041         if (wakeup)
2042                 tegra_xhci_disable_phy_wake(tegra);
2043
2044         for (i = 0; i < tegra->num_phys; i++) {
2045                 if (!tegra->phys[i])
2046                         continue;
2047
2048                 if (!wakeup)
2049                         phy_init(tegra->phys[i]);
2050
2051                 phy_power_on(tegra->phys[i]);
2052         }
2053
2054         tegra_xusb_config(tegra);
2055         tegra_xusb_restore_context(tegra);
2056
2057         err = tegra_xusb_load_firmware(tegra);
2058         if (err < 0) {
2059                 dev_err(tegra->dev, "failed to load firmware: %d\n", err);
2060                 goto disable_phy;
2061         }
2062
2063         err = __tegra_xusb_enable_firmware_messages(tegra);
2064         if (err < 0) {
2065                 dev_err(tegra->dev, "failed to enable messages: %d\n", err);
2066                 goto disable_phy;
2067         }
2068
2069         if (wakeup)
2070                 tegra_xhci_disable_phy_sleepwalk(tegra);
2071
2072         err = xhci_resume(xhci, 0);
2073         if (err < 0) {
2074                 dev_err(tegra->dev, "failed to resume XHCI: %d\n", err);
2075                 goto disable_phy;
2076         }
2077
2078         usbcmd = readl(&xhci->op_regs->command);
2079         usbcmd |= CMD_EIE;
2080         writel(usbcmd, &xhci->op_regs->command);
2081
2082         goto out;
2083
2084 disable_phy:
2085         for (i = 0; i < tegra->num_phys; i++) {
2086                 if (!tegra->phys[i])
2087                         continue;
2088
2089                 phy_power_off(tegra->phys[i]);
2090                 if (!wakeup)
2091                         phy_exit(tegra->phys[i]);
2092         }
2093         tegra_xusb_powergate_partitions(tegra);
2094 disable_clks:
2095         tegra_xusb_clk_disable(tegra);
2096 out:
2097         if (!err)
2098                 dev_dbg(dev, "exiting ELPG done\n");
2099         else
2100                 dev_dbg(dev, "exiting ELPG failed\n");
2101
2102         return err;
2103 }
2104
2105 static int tegra_xusb_suspend(struct device *dev)
2106 {
2107         struct tegra_xusb *tegra = dev_get_drvdata(dev);
2108         int err;
2109
2110         synchronize_irq(tegra->mbox_irq);
2111
2112         mutex_lock(&tegra->lock);
2113
2114         if (pm_runtime_suspended(dev)) {
2115                 err = tegra_xusb_exit_elpg(tegra, true);
2116                 if (err < 0)
2117                         goto out;
2118         }
2119
2120         err = tegra_xusb_enter_elpg(tegra, false);
2121         if (err < 0) {
2122                 if (pm_runtime_suspended(dev)) {
2123                         pm_runtime_disable(dev);
2124                         pm_runtime_set_active(dev);
2125                         pm_runtime_enable(dev);
2126                 }
2127
2128                 goto out;
2129         }
2130
2131 out:
2132         if (!err) {
2133                 tegra->suspended = true;
2134                 pm_runtime_disable(dev);
2135
2136                 if (device_may_wakeup(dev)) {
2137                         if (enable_irq_wake(tegra->padctl_irq))
2138                                 dev_err(dev, "failed to enable padctl wakes\n");
2139                 }
2140         }
2141
2142         mutex_unlock(&tegra->lock);
2143
2144         return err;
2145 }
2146
2147 static int tegra_xusb_resume(struct device *dev)
2148 {
2149         struct tegra_xusb *tegra = dev_get_drvdata(dev);
2150         int err;
2151
2152         mutex_lock(&tegra->lock);
2153
2154         if (!tegra->suspended) {
2155                 mutex_unlock(&tegra->lock);
2156                 return 0;
2157         }
2158
2159         err = tegra_xusb_exit_elpg(tegra, false);
2160         if (err < 0) {
2161                 mutex_unlock(&tegra->lock);
2162                 return err;
2163         }
2164
2165         if (device_may_wakeup(dev)) {
2166                 if (disable_irq_wake(tegra->padctl_irq))
2167                         dev_err(dev, "failed to disable padctl wakes\n");
2168         }
2169         tegra->suspended = false;
2170         mutex_unlock(&tegra->lock);
2171
2172         pm_runtime_set_active(dev);
2173         pm_runtime_enable(dev);
2174
2175         return 0;
2176 }
2177 #endif
2178
2179 #ifdef CONFIG_PM
2180 static int tegra_xusb_runtime_suspend(struct device *dev)
2181 {
2182         struct tegra_xusb *tegra = dev_get_drvdata(dev);
2183         int ret;
2184
2185         synchronize_irq(tegra->mbox_irq);
2186         mutex_lock(&tegra->lock);
2187         ret = tegra_xusb_enter_elpg(tegra, true);
2188         mutex_unlock(&tegra->lock);
2189
2190         return ret;
2191 }
2192
2193 static int tegra_xusb_runtime_resume(struct device *dev)
2194 {
2195         struct tegra_xusb *tegra = dev_get_drvdata(dev);
2196         int err;
2197
2198         mutex_lock(&tegra->lock);
2199         err = tegra_xusb_exit_elpg(tegra, true);
2200         mutex_unlock(&tegra->lock);
2201
2202         return err;
2203 }
2204 #endif
2205
2206 static const struct dev_pm_ops tegra_xusb_pm_ops = {
2207         SET_RUNTIME_PM_OPS(tegra_xusb_runtime_suspend,
2208                            tegra_xusb_runtime_resume, NULL)
2209         SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume)
2210 };
2211
2212 static const char * const tegra124_supply_names[] = {
2213         "avddio-pex",
2214         "dvddio-pex",
2215         "avdd-usb",
2216         "hvdd-usb-ss",
2217 };
2218
2219 static const struct tegra_xusb_phy_type tegra124_phy_types[] = {
2220         { .name = "usb3", .num = 2, },
2221         { .name = "usb2", .num = 3, },
2222         { .name = "hsic", .num = 2, },
2223 };
2224
2225 static const unsigned int tegra124_xusb_context_ipfs[] = {
2226         IPFS_XUSB_HOST_MSI_BAR_SZ_0,
2227         IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0,
2228         IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0,
2229         IPFS_XUSB_HOST_MSI_VEC0_0,
2230         IPFS_XUSB_HOST_MSI_EN_VEC0_0,
2231         IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0,
2232         IPFS_XUSB_HOST_INTR_MASK_0,
2233         IPFS_XUSB_HOST_INTR_ENABLE_0,
2234         IPFS_XUSB_HOST_UFPCI_CONFIG_0,
2235         IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0,
2236         IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0,
2237 };
2238
2239 static const unsigned int tegra124_xusb_context_fpci[] = {
2240         XUSB_CFG_ARU_CONTEXT_HS_PLS,
2241         XUSB_CFG_ARU_CONTEXT_FS_PLS,
2242         XUSB_CFG_ARU_CONTEXT_HSFS_SPEED,
2243         XUSB_CFG_ARU_CONTEXT_HSFS_PP,
2244         XUSB_CFG_ARU_CONTEXT,
2245         XUSB_CFG_AXI_CFG,
2246         XUSB_CFG_24,
2247         XUSB_CFG_16,
2248 };
2249
2250 static const struct tegra_xusb_context_soc tegra124_xusb_context = {
2251         .ipfs = {
2252                 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_ipfs),
2253                 .offsets = tegra124_xusb_context_ipfs,
2254         },
2255         .fpci = {
2256                 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci),
2257                 .offsets = tegra124_xusb_context_fpci,
2258         },
2259 };
2260
2261 static const struct tegra_xusb_soc tegra124_soc = {
2262         .firmware = "nvidia/tegra124/xusb.bin",
2263         .supply_names = tegra124_supply_names,
2264         .num_supplies = ARRAY_SIZE(tegra124_supply_names),
2265         .phy_types = tegra124_phy_types,
2266         .num_types = ARRAY_SIZE(tegra124_phy_types),
2267         .context = &tegra124_xusb_context,
2268         .ports = {
2269                 .usb2 = { .offset = 4, .count = 4, },
2270                 .hsic = { .offset = 6, .count = 2, },
2271                 .usb3 = { .offset = 0, .count = 2, },
2272         },
2273         .scale_ss_clock = true,
2274         .has_ipfs = true,
2275         .otg_reset_sspi = false,
2276         .mbox = {
2277                 .cmd = 0xe4,
2278                 .data_in = 0xe8,
2279                 .data_out = 0xec,
2280                 .owner = 0xf0,
2281         },
2282 };
2283 MODULE_FIRMWARE("nvidia/tegra124/xusb.bin");
2284
2285 static const char * const tegra210_supply_names[] = {
2286         "dvddio-pex",
2287         "hvddio-pex",
2288         "avdd-usb",
2289 };
2290
2291 static const struct tegra_xusb_phy_type tegra210_phy_types[] = {
2292         { .name = "usb3", .num = 4, },
2293         { .name = "usb2", .num = 4, },
2294         { .name = "hsic", .num = 1, },
2295 };
2296
2297 static const struct tegra_xusb_soc tegra210_soc = {
2298         .firmware = "nvidia/tegra210/xusb.bin",
2299         .supply_names = tegra210_supply_names,
2300         .num_supplies = ARRAY_SIZE(tegra210_supply_names),
2301         .phy_types = tegra210_phy_types,
2302         .num_types = ARRAY_SIZE(tegra210_phy_types),
2303         .context = &tegra124_xusb_context,
2304         .ports = {
2305                 .usb2 = { .offset = 4, .count = 4, },
2306                 .hsic = { .offset = 8, .count = 1, },
2307                 .usb3 = { .offset = 0, .count = 4, },
2308         },
2309         .scale_ss_clock = false,
2310         .has_ipfs = true,
2311         .otg_reset_sspi = true,
2312         .mbox = {
2313                 .cmd = 0xe4,
2314                 .data_in = 0xe8,
2315                 .data_out = 0xec,
2316                 .owner = 0xf0,
2317         },
2318 };
2319 MODULE_FIRMWARE("nvidia/tegra210/xusb.bin");
2320
2321 static const char * const tegra186_supply_names[] = {
2322 };
2323 MODULE_FIRMWARE("nvidia/tegra186/xusb.bin");
2324
2325 static const struct tegra_xusb_phy_type tegra186_phy_types[] = {
2326         { .name = "usb3", .num = 3, },
2327         { .name = "usb2", .num = 3, },
2328         { .name = "hsic", .num = 1, },
2329 };
2330
2331 static const struct tegra_xusb_context_soc tegra186_xusb_context = {
2332         .fpci = {
2333                 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci),
2334                 .offsets = tegra124_xusb_context_fpci,
2335         },
2336 };
2337
2338 static const struct tegra_xusb_soc tegra186_soc = {
2339         .firmware = "nvidia/tegra186/xusb.bin",
2340         .supply_names = tegra186_supply_names,
2341         .num_supplies = ARRAY_SIZE(tegra186_supply_names),
2342         .phy_types = tegra186_phy_types,
2343         .num_types = ARRAY_SIZE(tegra186_phy_types),
2344         .context = &tegra186_xusb_context,
2345         .ports = {
2346                 .usb3 = { .offset = 0, .count = 3, },
2347                 .usb2 = { .offset = 3, .count = 3, },
2348                 .hsic = { .offset = 6, .count = 1, },
2349         },
2350         .scale_ss_clock = false,
2351         .has_ipfs = false,
2352         .otg_reset_sspi = false,
2353         .mbox = {
2354                 .cmd = 0xe4,
2355                 .data_in = 0xe8,
2356                 .data_out = 0xec,
2357                 .owner = 0xf0,
2358         },
2359         .lpm_support = true,
2360 };
2361
2362 static const char * const tegra194_supply_names[] = {
2363 };
2364
2365 static const struct tegra_xusb_phy_type tegra194_phy_types[] = {
2366         { .name = "usb3", .num = 4, },
2367         { .name = "usb2", .num = 4, },
2368 };
2369
2370 static const struct tegra_xusb_soc tegra194_soc = {
2371         .firmware = "nvidia/tegra194/xusb.bin",
2372         .supply_names = tegra194_supply_names,
2373         .num_supplies = ARRAY_SIZE(tegra194_supply_names),
2374         .phy_types = tegra194_phy_types,
2375         .num_types = ARRAY_SIZE(tegra194_phy_types),
2376         .context = &tegra186_xusb_context,
2377         .ports = {
2378                 .usb3 = { .offset = 0, .count = 4, },
2379                 .usb2 = { .offset = 4, .count = 4, },
2380         },
2381         .scale_ss_clock = false,
2382         .has_ipfs = false,
2383         .otg_reset_sspi = false,
2384         .mbox = {
2385                 .cmd = 0x68,
2386                 .data_in = 0x6c,
2387                 .data_out = 0x70,
2388                 .owner = 0x74,
2389         },
2390         .lpm_support = true,
2391 };
2392 MODULE_FIRMWARE("nvidia/tegra194/xusb.bin");
2393
2394 static const struct of_device_id tegra_xusb_of_match[] = {
2395         { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc },
2396         { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc },
2397         { .compatible = "nvidia,tegra186-xusb", .data = &tegra186_soc },
2398         { .compatible = "nvidia,tegra194-xusb", .data = &tegra194_soc },
2399         { },
2400 };
2401 MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
2402
2403 static struct platform_driver tegra_xusb_driver = {
2404         .probe = tegra_xusb_probe,
2405         .remove = tegra_xusb_remove,
2406         .driver = {
2407                 .name = "tegra-xusb",
2408                 .pm = &tegra_xusb_pm_ops,
2409                 .of_match_table = tegra_xusb_of_match,
2410         },
2411 };
2412
2413 static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci)
2414 {
2415         struct tegra_xusb *tegra = dev_get_drvdata(dev);
2416
2417         xhci->quirks |= XHCI_PLAT;
2418         if (tegra && tegra->soc->lpm_support)
2419                 xhci->quirks |= XHCI_LPM_SUPPORT;
2420 }
2421
2422 static int tegra_xhci_setup(struct usb_hcd *hcd)
2423 {
2424         return xhci_gen_setup(hcd, tegra_xhci_quirks);
2425 }
2426
2427 static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = {
2428         .reset = tegra_xhci_setup,
2429 };
2430
2431 static int __init tegra_xusb_init(void)
2432 {
2433         xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides);
2434
2435         return platform_driver_register(&tegra_xusb_driver);
2436 }
2437 module_init(tegra_xusb_init);
2438
2439 static void __exit tegra_xusb_exit(void)
2440 {
2441         platform_driver_unregister(&tegra_xusb_driver);
2442 }
2443 module_exit(tegra_xusb_exit);
2444
2445 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
2446 MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver");
2447 MODULE_LICENSE("GPL v2");