drivers/usb/host/xhci-tegra.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * NVIDIA Tegra xHCI host controller driver
   4  *
   5  * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
   6  * Copyright (C) 2014 Google, Inc.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/firmware.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/of_device.h>
  18 #include <linux/phy/phy.h>
  19 #include <linux/phy/tegra/xusb.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm.h>
  22 #include <linux/pm_domain.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/regulator/consumer.h>
  25 #include <linux/reset.h>
  26 #include <linux/slab.h>
  27 #include <linux/usb/otg.h>
  28 #include <linux/usb/phy.h>
  29 #include <linux/usb/role.h>
  30 #include <soc/tegra/pmc.h>
  31
  32 #include "xhci.h"
  33
  34 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000
  35 #define TEGRA_XHCI_SS_LOW_SPEED   12000000
  36
  37 /* FPCI CFG registers */
  38 #define XUSB_CFG_1                              0x004
  39 #define  XUSB_IO_SPACE_EN                       BIT(0)
  40 #define  XUSB_MEM_SPACE_EN                      BIT(1)
  41 #define  XUSB_BUS_MASTER_EN                     BIT(2)
  42 #define XUSB_CFG_4                              0x010
  43 #define  XUSB_BASE_ADDR_SHIFT                   15
  44 #define  XUSB_BASE_ADDR_MASK                    0x1ffff
  45 #define XUSB_CFG_16                             0x040
  46 #define XUSB_CFG_24                             0x060
  47 #define XUSB_CFG_AXI_CFG                        0x0f8
  48 #define XUSB_CFG_ARU_C11_CSBRANGE               0x41c
  49 #define XUSB_CFG_ARU_CONTEXT                    0x43c
  50 #define XUSB_CFG_ARU_CONTEXT_HS_PLS             0x478
  51 #define XUSB_CFG_ARU_CONTEXT_FS_PLS             0x47c
  52 #define XUSB_CFG_ARU_CONTEXT_HSFS_SPEED         0x480
  53 #define XUSB_CFG_ARU_CONTEXT_HSFS_PP            0x484
  54 #define XUSB_CFG_CSB_BASE_ADDR                  0x800
  55
  56 /* FPCI mailbox registers */
  57 /* XUSB_CFG_ARU_MBOX_CMD */
  58 #define  MBOX_DEST_FALC                         BIT(27)
  59 #define  MBOX_DEST_PME                          BIT(28)
  60 #define  MBOX_DEST_SMI                          BIT(29)
  61 #define  MBOX_DEST_XHCI                         BIT(30)
  62 #define  MBOX_INT_EN                            BIT(31)
  63 /* XUSB_CFG_ARU_MBOX_DATA_IN and XUSB_CFG_ARU_MBOX_DATA_OUT */
  64 #define  CMD_DATA_SHIFT                         0
  65 #define  CMD_DATA_MASK                          0xffffff
  66 #define  CMD_TYPE_SHIFT                         24
  67 #define  CMD_TYPE_MASK                          0xff
  68 /* XUSB_CFG_ARU_MBOX_OWNER */
  69 #define  MBOX_OWNER_NONE                        0
  70 #define  MBOX_OWNER_FW                          1
  71 #define  MBOX_OWNER_SW                          2
  72 #define XUSB_CFG_ARU_SMI_INTR                   0x428
  73 #define  MBOX_SMI_INTR_FW_HANG                  BIT(1)
  74 #define  MBOX_SMI_INTR_EN                       BIT(3)
  75
  76 /* IPFS registers */
  77 #define IPFS_XUSB_HOST_MSI_BAR_SZ_0             0x0c0
  78 #define IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0         0x0c4
  79 #define IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0        0x0c8
  80 #define IPFS_XUSB_HOST_MSI_VEC0_0               0x100
  81 #define IPFS_XUSB_HOST_MSI_EN_VEC0_0            0x140
  82 #define IPFS_XUSB_HOST_CONFIGURATION_0          0x180
  83 #define  IPFS_EN_FPCI                           BIT(0)
  84 #define IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0       0x184
  85 #define IPFS_XUSB_HOST_INTR_MASK_0              0x188
  86 #define  IPFS_IP_INT_MASK                       BIT(16)
  87 #define IPFS_XUSB_HOST_INTR_ENABLE_0            0x198
  88 #define IPFS_XUSB_HOST_UFPCI_CONFIG_0           0x19c
  89 #define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0     0x1bc
  90 #define IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0         0x1dc
  91
  92 #define CSB_PAGE_SELECT_MASK                    0x7fffff
  93 #define CSB_PAGE_SELECT_SHIFT                   9
  94 #define CSB_PAGE_OFFSET_MASK                    0x1ff
  95 #define CSB_PAGE_SELECT(addr)   ((addr) >> (CSB_PAGE_SELECT_SHIFT) &    \
  96                                  CSB_PAGE_SELECT_MASK)
  97 #define CSB_PAGE_OFFSET(addr)   ((addr) & CSB_PAGE_OFFSET_MASK)
  98
  99 /* Falcon CSB registers */
 100 #define XUSB_FALC_CPUCTL                        0x100
 101 #define  CPUCTL_STARTCPU                        BIT(1)
 102 #define  CPUCTL_STATE_HALTED                    BIT(4)
 103 #define  CPUCTL_STATE_STOPPED                   BIT(5)
 104 #define XUSB_FALC_BOOTVEC                       0x104
 105 #define XUSB_FALC_DMACTL                        0x10c
 106 #define XUSB_FALC_IMFILLRNG1                    0x154
 107 #define  IMFILLRNG1_TAG_MASK                    0xffff
 108 #define  IMFILLRNG1_TAG_LO_SHIFT                0
 109 #define  IMFILLRNG1_TAG_HI_SHIFT                16
 110 #define XUSB_FALC_IMFILLCTL                     0x158
 111
 112 /* MP CSB registers */
 113 #define XUSB_CSB_MP_ILOAD_ATTR                  0x101a00
 114 #define XUSB_CSB_MP_ILOAD_BASE_LO               0x101a04
 115 #define XUSB_CSB_MP_ILOAD_BASE_HI               0x101a08
 116 #define XUSB_CSB_MP_L2IMEMOP_SIZE               0x101a10
 117 #define  L2IMEMOP_SIZE_SRC_OFFSET_SHIFT         8
 118 #define  L2IMEMOP_SIZE_SRC_OFFSET_MASK          0x3ff
 119 #define  L2IMEMOP_SIZE_SRC_COUNT_SHIFT          24
 120 #define  L2IMEMOP_SIZE_SRC_COUNT_MASK           0xff
 121 #define XUSB_CSB_MP_L2IMEMOP_TRIG               0x101a14
 122 #define  L2IMEMOP_ACTION_SHIFT                  24
 123 #define  L2IMEMOP_INVALIDATE_ALL                (0x40 << L2IMEMOP_ACTION_SHIFT)
 124 #define  L2IMEMOP_LOAD_LOCKED_RESULT            (0x11 << L2IMEMOP_ACTION_SHIFT)
 125 #define XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT        0x101a18
 126 #define  L2IMEMOP_RESULT_VLD                    BIT(31)
 127 #define XUSB_CSB_MP_APMAP                       0x10181c
 128 #define  APMAP_BOOTPATH                         BIT(31)
 129
 130 #define IMEM_BLOCK_SIZE                         256
 131
 132 struct tegra_xusb_fw_header {
 133         __le32 boot_loadaddr_in_imem;
 134         __le32 boot_codedfi_offset;
 135         __le32 boot_codetag;
 136         __le32 boot_codesize;
 137         __le32 phys_memaddr;
 138         __le16 reqphys_memsize;
 139         __le16 alloc_phys_memsize;
 140         __le32 rodata_img_offset;
 141         __le32 rodata_section_start;
 142         __le32 rodata_section_end;
 143         __le32 main_fnaddr;
 144         __le32 fwimg_cksum;
 145         __le32 fwimg_created_time;
 146         __le32 imem_resident_start;
 147         __le32 imem_resident_end;
 148         __le32 idirect_start;
 149         __le32 idirect_end;
 150         __le32 l2_imem_start;
 151         __le32 l2_imem_end;
 152         __le32 version_id;
 153         u8 init_ddirect;
 154         u8 reserved[3];
 155         __le32 phys_addr_log_buffer;
 156         __le32 total_log_entries;
 157         __le32 dequeue_ptr;
 158         __le32 dummy_var[2];
 159         __le32 fwimg_len;
 160         u8 magic[8];
 161         __le32 ss_low_power_entry_timeout;
 162         u8 num_hsic_port;
 163         u8 padding[139]; /* Pad to 256 bytes */
 164 };
 165
 166 struct tegra_xusb_phy_type {
 167         const char *name;
 168         unsigned int num;
 169 };
 170
 171 struct tegra_xusb_mbox_regs {
 172         u16 cmd;
 173         u16 data_in;
 174         u16 data_out;
 175         u16 owner;
 176 };
 177
 178 struct tegra_xusb_context_soc {
 179         struct {
 180                 const unsigned int *offsets;
 181                 unsigned int num_offsets;
 182         } ipfs;
 183
 184         struct {
 185                 const unsigned int *offsets;
 186                 unsigned int num_offsets;
 187         } fpci;
 188 };
 189
 190 struct tegra_xusb_soc {
 191         const char *firmware;
 192         const char * const *supply_names;
 193         unsigned int num_supplies;
 194         const struct tegra_xusb_phy_type *phy_types;
 195         unsigned int num_types;
 196         const struct tegra_xusb_context_soc *context;
 197
 198         struct {
 199                 struct {
 200                         unsigned int offset;
 201                         unsigned int count;
 202                 } usb2, ulpi, hsic, usb3;
 203         } ports;
 204
 205         struct tegra_xusb_mbox_regs mbox;
 206
 207         bool scale_ss_clock;
 208         bool has_ipfs;
 209         bool lpm_support;
 210         bool otg_reset_sspi;
 211 };
 212
 213 struct tegra_xusb_context {
 214         u32 *ipfs;
 215         u32 *fpci;
 216 };
 217
 218 struct tegra_xusb {
 219         struct device *dev;
 220         void __iomem *regs;
 221         struct usb_hcd *hcd;
 222
 223         struct mutex lock;
 224
 225         int xhci_irq;
 226         int mbox_irq;
 227
 228         void __iomem *ipfs_base;
 229         void __iomem *fpci_base;
 230
 231         const struct tegra_xusb_soc *soc;
 232
 233         struct regulator_bulk_data *supplies;
 234
 235         struct tegra_xusb_padctl *padctl;
 236
 237         struct clk *host_clk;
 238         struct clk *falcon_clk;
 239         struct clk *ss_clk;
 240         struct clk *ss_src_clk;
 241         struct clk *hs_src_clk;
 242         struct clk *fs_src_clk;
 243         struct clk *pll_u_480m;
 244         struct clk *clk_m;
 245         struct clk *pll_e;
 246
 247         struct reset_control *host_rst;
 248         struct reset_control *ss_rst;
 249
 250         struct device *genpd_dev_host;
 251         struct device *genpd_dev_ss;
 252         bool use_genpd;
 253
 254         struct phy **phys;
 255         unsigned int num_phys;
 256
 257         struct usb_phy **usbphy;
 258         unsigned int num_usb_phys;
 259         int otg_usb2_port;
 260         int otg_usb3_port;
 261         bool host_mode;
 262         struct notifier_block id_nb;
 263         struct work_struct id_work;
 264
 265         /* Firmware loading related */
 266         struct {
 267                 size_t size;
 268                 void *virt;
 269                 dma_addr_t phys;
 270         } fw;
 271
 272         struct tegra_xusb_context context;
 273 };
 274
 275 static struct hc_driver __read_mostly tegra_xhci_hc_driver;
 276
 277 static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset)
 278 {
 279         return readl(tegra->fpci_base + offset);
 280 }
 281
 282 static inline void fpci_writel(struct tegra_xusb *tegra, u32 value,
 283                                unsigned int offset)
 284 {
 285         writel(value, tegra->fpci_base + offset);
 286 }
 287
 288 static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset)
 289 {
 290         return readl(tegra->ipfs_base + offset);
 291 }
 292
 293 static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value,
 294                                unsigned int offset)
 295 {
 296         writel(value, tegra->ipfs_base + offset);
 297 }
 298
 299 static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset)
 300 {
 301         u32 page = CSB_PAGE_SELECT(offset);
 302         u32 ofs = CSB_PAGE_OFFSET(offset);
 303
 304         fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
 305
 306         return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs);
 307 }
 308
 309 static void csb_writel(struct tegra_xusb *tegra, u32 value,
 310                        unsigned int offset)
 311 {
 312         u32 page = CSB_PAGE_SELECT(offset);
 313         u32 ofs = CSB_PAGE_OFFSET(offset);
 314
 315         fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
 316         fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs);
 317 }
 318
 319 static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra,
 320                                  unsigned long rate)
 321 {
 322         unsigned long new_parent_rate, old_parent_rate;
 323         struct clk *clk = tegra->ss_src_clk;
 324         unsigned int div;
 325         int err;
 326
 327         if (clk_get_rate(clk) == rate)
 328                 return 0;
 329
 330         switch (rate) {
 331         case TEGRA_XHCI_SS_HIGH_SPEED:
 332                 /*
 333                  * Reparent to PLLU_480M. Set divider first to avoid
 334                  * overclocking.
 335                  */
 336                 old_parent_rate = clk_get_rate(clk_get_parent(clk));
 337                 new_parent_rate = clk_get_rate(tegra->pll_u_480m);
 338                 div = new_parent_rate / rate;
 339
 340                 err = clk_set_rate(clk, old_parent_rate / div);
 341                 if (err)
 342                         return err;
 343
 344                 err = clk_set_parent(clk, tegra->pll_u_480m);
 345                 if (err)
 346                         return err;
 347
 348                 /*
 349                  * The rate should already be correct, but set it again just
 350                  * to be sure.
 351                  */
 352                 err = clk_set_rate(clk, rate);
 353                 if (err)
 354                         return err;
 355
 356                 break;
 357
 358         case TEGRA_XHCI_SS_LOW_SPEED:
 359                 /* Reparent to CLK_M */
 360                 err = clk_set_parent(clk, tegra->clk_m);
 361                 if (err)
 362                         return err;
 363
 364                 err = clk_set_rate(clk, rate);
 365                 if (err)
 366                         return err;
 367
 368                 break;
 369
 370         default:
 371                 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate);
 372                 return -EINVAL;
 373         }
 374
 375         if (clk_get_rate(clk) != rate) {
 376                 dev_err(tegra->dev, "SS clock doesn't match requested rate\n");
 377                 return -EINVAL;
 378         }
 379
 380         return 0;
 381 }
 382
 383 static unsigned long extract_field(u32 value, unsigned int start,
 384                                    unsigned int count)
 385 {
 386         return (value >> start) & ((1 << count) - 1);
 387 }
 388
 389 /* Command requests from the firmware */
 390 enum tegra_xusb_mbox_cmd {
 391         MBOX_CMD_MSG_ENABLED = 1,
 392         MBOX_CMD_INC_FALC_CLOCK,
 393         MBOX_CMD_DEC_FALC_CLOCK,
 394         MBOX_CMD_INC_SSPI_CLOCK,
 395         MBOX_CMD_DEC_SSPI_CLOCK,
 396         MBOX_CMD_SET_BW, /* no ACK/NAK required */
 397         MBOX_CMD_SET_SS_PWR_GATING,
 398         MBOX_CMD_SET_SS_PWR_UNGATING,
 399         MBOX_CMD_SAVE_DFE_CTLE_CTX,
 400         MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
 401         MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */
 402         MBOX_CMD_START_HSIC_IDLE,
 403         MBOX_CMD_STOP_HSIC_IDLE,
 404         MBOX_CMD_DBC_WAKE_STACK, /* unused */
 405         MBOX_CMD_HSIC_PRETEND_CONNECT,
 406         MBOX_CMD_RESET_SSPI,
 407         MBOX_CMD_DISABLE_SS_LFPS_DETECTION,
 408         MBOX_CMD_ENABLE_SS_LFPS_DETECTION,
 409
 410         MBOX_CMD_MAX,
 411
 412         /* Response message to above commands */
 413         MBOX_CMD_ACK = 128,
 414         MBOX_CMD_NAK
 415 };
 416
 417 struct tegra_xusb_mbox_msg {
 418         u32 cmd;
 419         u32 data;
 420 };
 421
 422 static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg)
 423 {
 424         return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT |
 425                (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT;
 426 }
 427 static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg,
 428                                           u32 value)
 429 {
 430         msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
 431         msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
 432 }
 433
 434 static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd)
 435 {
 436         switch (cmd) {
 437         case MBOX_CMD_SET_BW:
 438         case MBOX_CMD_ACK:
 439         case MBOX_CMD_NAK:
 440                 return false;
 441
 442         default:
 443                 return true;
 444         }
 445 }
 446
 447 static int tegra_xusb_mbox_send(struct tegra_xusb *tegra,
 448                                 const struct tegra_xusb_mbox_msg *msg)
 449 {
 450         bool wait_for_idle = false;
 451         u32 value;
 452
 453         /*
 454          * Acquire the mailbox. The firmware still owns the mailbox for
 455          * ACK/NAK messages.
 456          */
 457         if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) {
 458                 value = fpci_readl(tegra, tegra->soc->mbox.owner);
 459                 if (value != MBOX_OWNER_NONE) {
 460                         dev_err(tegra->dev, "mailbox is busy\n");
 461                         return -EBUSY;
 462                 }
 463
 464                 fpci_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner);
 465
 466                 value = fpci_readl(tegra, tegra->soc->mbox.owner);
 467                 if (value != MBOX_OWNER_SW) {
 468                         dev_err(tegra->dev, "failed to acquire mailbox\n");
 469                         return -EBUSY;
 470                 }
 471
 472                 wait_for_idle = true;
 473         }
 474
 475         value = tegra_xusb_mbox_pack(msg);
 476         fpci_writel(tegra, value, tegra->soc->mbox.data_in);
 477
 478         value = fpci_readl(tegra, tegra->soc->mbox.cmd);
 479         value |= MBOX_INT_EN | MBOX_DEST_FALC;
 480         fpci_writel(tegra, value, tegra->soc->mbox.cmd);
 481
 482         if (wait_for_idle) {
 483                 unsigned long timeout = jiffies + msecs_to_jiffies(250);
 484
 485                 while (time_before(jiffies, timeout)) {
 486                         value = fpci_readl(tegra, tegra->soc->mbox.owner);
 487                         if (value == MBOX_OWNER_NONE)
 488                                 break;
 489
 490                         usleep_range(10, 20);
 491                 }
 492
 493                 if (time_after(jiffies, timeout))
 494                         value = fpci_readl(tegra, tegra->soc->mbox.owner);
 495
 496                 if (value != MBOX_OWNER_NONE)
 497                         return -ETIMEDOUT;
 498         }
 499
 500         return 0;
 501 }
 502
 503 static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data)
 504 {
 505         struct tegra_xusb *tegra = data;
 506         u32 value;
 507
 508         /* clear mailbox interrupts */
 509         value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR);
 510         fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR);
 511
 512         if (value & MBOX_SMI_INTR_FW_HANG)
 513                 dev_err(tegra->dev, "controller firmware hang\n");
 514
 515         return IRQ_WAKE_THREAD;
 516 }
 517
 518 static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
 519                                    const struct tegra_xusb_mbox_msg *msg)
 520 {
 521         struct tegra_xusb_padctl *padctl = tegra->padctl;
 522         const struct tegra_xusb_soc *soc = tegra->soc;
 523         struct device *dev = tegra->dev;
 524         struct tegra_xusb_mbox_msg rsp;
 525         unsigned long mask;
 526         unsigned int port;
 527         bool idle, enable;
 528         int err = 0;
 529
 530         memset(&rsp, 0, sizeof(rsp));
 531
 532         switch (msg->cmd) {
 533         case MBOX_CMD_INC_FALC_CLOCK:
 534         case MBOX_CMD_DEC_FALC_CLOCK:
 535                 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000;
 536                 if (rsp.data != msg->data)
 537                         rsp.cmd = MBOX_CMD_NAK;
 538                 else
 539                         rsp.cmd = MBOX_CMD_ACK;
 540
 541                 break;
 542
 543         case MBOX_CMD_INC_SSPI_CLOCK:
 544         case MBOX_CMD_DEC_SSPI_CLOCK:
 545                 if (tegra->soc->scale_ss_clock) {
 546                         err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000);
 547                         if (err < 0)
 548                                 rsp.cmd = MBOX_CMD_NAK;
 549                         else
 550                                 rsp.cmd = MBOX_CMD_ACK;
 551
 552                         rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000;
 553                 } else {
 554                         rsp.cmd = MBOX_CMD_ACK;
 555                         rsp.data = msg->data;
 556                 }
 557
 558                 break;
 559
 560         case MBOX_CMD_SET_BW:
 561                 /*
 562                  * TODO: Request bandwidth once EMC scaling is supported.
 563                  * Ignore for now since ACK/NAK is not required for SET_BW
 564                  * messages.
 565                  */
 566                 break;
 567
 568         case MBOX_CMD_SAVE_DFE_CTLE_CTX:
 569                 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data);
 570                 if (err < 0) {
 571                         dev_err(dev, "failed to save context for USB3#%u: %d\n",
 572                                 msg->data, err);
 573                         rsp.cmd = MBOX_CMD_NAK;
 574                 } else {
 575                         rsp.cmd = MBOX_CMD_ACK;
 576                 }
 577
 578                 rsp.data = msg->data;
 579                 break;
 580
 581         case MBOX_CMD_START_HSIC_IDLE:
 582         case MBOX_CMD_STOP_HSIC_IDLE:
 583                 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE)
 584                         idle = false;
 585                 else
 586                         idle = true;
 587
 588                 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset,
 589                                      soc->ports.hsic.count);
 590
 591                 for_each_set_bit(port, &mask, 32) {
 592                         err = tegra_xusb_padctl_hsic_set_idle(padctl, port,
 593                                                               idle);
 594                         if (err < 0)
 595                                 break;
 596                 }
 597
 598                 if (err < 0) {
 599                         dev_err(dev, "failed to set HSIC#%u %s: %d\n", port,
 600                                 idle ? "idle" : "busy", err);
 601                         rsp.cmd = MBOX_CMD_NAK;
 602                 } else {
 603                         rsp.cmd = MBOX_CMD_ACK;
 604                 }
 605
 606                 rsp.data = msg->data;
 607                 break;
 608
 609         case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
 610         case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
 611                 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION)
 612                         enable = false;
 613                 else
 614                         enable = true;
 615
 616                 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset,
 617                                      soc->ports.usb3.count);
 618
 619                 for_each_set_bit(port, &mask, soc->ports.usb3.count) {
 620                         err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl,
 621                                                                      port,
 622                                                                      enable);
 623                         if (err < 0)
 624                                 break;
 625
 626                         /*
 627                          * wait 500us for LFPS detector to be disabled before
 628                          * sending ACK
 629                          */
 630                         if (!enable)
 631                                 usleep_range(500, 1000);
 632                 }
 633
 634                 if (err < 0) {
 635                         dev_err(dev,
 636                                 "failed to %s LFPS detection on USB3#%u: %d\n",
 637                                 enable ? "enable" : "disable", port, err);
 638                         rsp.cmd = MBOX_CMD_NAK;
 639                 } else {
 640                         rsp.cmd = MBOX_CMD_ACK;
 641                 }
 642
 643                 rsp.data = msg->data;
 644                 break;
 645
 646         default:
 647                 dev_warn(dev, "unknown message: %#x\n", msg->cmd);
 648                 break;
 649         }
 650
 651         if (rsp.cmd) {
 652                 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK";
 653
 654                 err = tegra_xusb_mbox_send(tegra, &rsp);
 655                 if (err < 0)
 656                         dev_err(dev, "failed to send %s: %d\n", cmd, err);
 657         }
 658 }
 659
 660 static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data)
 661 {
 662         struct tegra_xusb *tegra = data;
 663         struct tegra_xusb_mbox_msg msg;
 664         u32 value;
 665
 666         mutex_lock(&tegra->lock);
 667
 668         value = fpci_readl(tegra, tegra->soc->mbox.data_out);
 669         tegra_xusb_mbox_unpack(&msg, value);
 670
 671         value = fpci_readl(tegra, tegra->soc->mbox.cmd);
 672         value &= ~MBOX_DEST_SMI;
 673         fpci_writel(tegra, value, tegra->soc->mbox.cmd);
 674
 675         /* clear mailbox owner if no ACK/NAK is required */
 676         if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd))
 677                 fpci_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner);
 678
 679         tegra_xusb_mbox_handle(tegra, &msg);
 680
 681         mutex_unlock(&tegra->lock);
 682         return IRQ_HANDLED;
 683 }
 684
 685 static void tegra_xusb_config(struct tegra_xusb *tegra)
 686 {
 687         u32 regs = tegra->hcd->rsrc_start;
 688         u32 value;
 689
 690         if (tegra->soc->has_ipfs) {
 691                 value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0);
 692                 value |= IPFS_EN_FPCI;
 693                 ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0);
 694
 695                 usleep_range(10, 20);
 696         }
 697
 698         /* Program BAR0 space */
 699         value = fpci_readl(tegra, XUSB_CFG_4);
 700         value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
 701         value |= regs & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
 702         fpci_writel(tegra, value, XUSB_CFG_4);
 703
 704         usleep_range(100, 200);
 705
 706         /* Enable bus master */
 707         value = fpci_readl(tegra, XUSB_CFG_1);
 708         value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN;
 709         fpci_writel(tegra, value, XUSB_CFG_1);
 710
 711         if (tegra->soc->has_ipfs) {
 712                 /* Enable interrupt assertion */
 713                 value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0);
 714                 value |= IPFS_IP_INT_MASK;
 715                 ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0);
 716
 717                 /* Set hysteresis */
 718                 ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
 719         }
 720 }
 721
 722 static int tegra_xusb_clk_enable(struct tegra_xusb *tegra)
 723 {
 724         int err;
 725
 726         err = clk_prepare_enable(tegra->pll_e);
 727         if (err < 0)
 728                 return err;
 729
 730         err = clk_prepare_enable(tegra->host_clk);
 731         if (err < 0)
 732                 goto disable_plle;
 733
 734         err = clk_prepare_enable(tegra->ss_clk);
 735         if (err < 0)
 736                 goto disable_host;
 737
 738         err = clk_prepare_enable(tegra->falcon_clk);
 739         if (err < 0)
 740                 goto disable_ss;
 741
 742         err = clk_prepare_enable(tegra->fs_src_clk);
 743         if (err < 0)
 744                 goto disable_falc;
 745
 746         err = clk_prepare_enable(tegra->hs_src_clk);
 747         if (err < 0)
 748                 goto disable_fs_src;
 749
 750         if (tegra->soc->scale_ss_clock) {
 751                 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED);
 752                 if (err < 0)
 753                         goto disable_hs_src;
 754         }
 755
 756         return 0;
 757
 758 disable_hs_src:
 759         clk_disable_unprepare(tegra->hs_src_clk);
 760 disable_fs_src:
 761         clk_disable_unprepare(tegra->fs_src_clk);
 762 disable_falc:
 763         clk_disable_unprepare(tegra->falcon_clk);
 764 disable_ss:
 765         clk_disable_unprepare(tegra->ss_clk);
 766 disable_host:
 767         clk_disable_unprepare(tegra->host_clk);
 768 disable_plle:
 769         clk_disable_unprepare(tegra->pll_e);
 770         return err;
 771 }
 772
 773 static void tegra_xusb_clk_disable(struct tegra_xusb *tegra)
 774 {
 775         clk_disable_unprepare(tegra->pll_e);
 776         clk_disable_unprepare(tegra->host_clk);
 777         clk_disable_unprepare(tegra->ss_clk);
 778         clk_disable_unprepare(tegra->falcon_clk);
 779         clk_disable_unprepare(tegra->fs_src_clk);
 780         clk_disable_unprepare(tegra->hs_src_clk);
 781 }
 782
 783 static int tegra_xusb_phy_enable(struct tegra_xusb *tegra)
 784 {
 785         unsigned int i;
 786         int err;
 787
 788         for (i = 0; i < tegra->num_phys; i++) {
 789                 err = phy_init(tegra->phys[i]);
 790                 if (err)
 791                         goto disable_phy;
 792
 793                 err = phy_power_on(tegra->phys[i]);
 794                 if (err) {
 795                         phy_exit(tegra->phys[i]);
 796                         goto disable_phy;
 797                 }
 798         }
 799
 800         return 0;
 801
 802 disable_phy:
 803         while (i--) {
 804                 phy_power_off(tegra->phys[i]);
 805                 phy_exit(tegra->phys[i]);
 806         }
 807
 808         return err;
 809 }
 810
 811 static void tegra_xusb_phy_disable(struct tegra_xusb *tegra)
 812 {
 813         unsigned int i;
 814
 815         for (i = 0; i < tegra->num_phys; i++) {
 816                 phy_power_off(tegra->phys[i]);
 817                 phy_exit(tegra->phys[i]);
 818         }
 819 }
 820
 821 static int tegra_xusb_runtime_suspend(struct device *dev)
 822 {
 823         return 0;
 824 }
 825
 826 static int tegra_xusb_runtime_resume(struct device *dev)
 827 {
 828         return 0;
 829 }
 830
 831 #ifdef CONFIG_PM_SLEEP
 832 static int tegra_xusb_init_context(struct tegra_xusb *tegra)
 833 {
 834         const struct tegra_xusb_context_soc *soc = tegra->soc->context;
 835
 836         tegra->context.ipfs = devm_kcalloc(tegra->dev, soc->ipfs.num_offsets,
 837                                            sizeof(u32), GFP_KERNEL);
 838         if (!tegra->context.ipfs)
 839                 return -ENOMEM;
 840
 841         tegra->context.fpci = devm_kcalloc(tegra->dev, soc->fpci.num_offsets,
 842                                            sizeof(u32), GFP_KERNEL);
 843         if (!tegra->context.fpci)
 844                 return -ENOMEM;
 845
 846         return 0;
 847 }
 848 #else
 849 static inline int tegra_xusb_init_context(struct tegra_xusb *tegra)
 850 {
 851         return 0;
 852 }
 853 #endif
 854
 855 static int tegra_xusb_request_firmware(struct tegra_xusb *tegra)
 856 {
 857         struct tegra_xusb_fw_header *header;
 858         const struct firmware *fw;
 859         int err;
 860
 861         err = request_firmware(&fw, tegra->soc->firmware, tegra->dev);
 862         if (err < 0) {
 863                 dev_err(tegra->dev, "failed to request firmware: %d\n", err);
 864                 return err;
 865         }
 866
 867         /* Load Falcon controller with its firmware. */
 868         header = (struct tegra_xusb_fw_header *)fw->data;
 869         tegra->fw.size = le32_to_cpu(header->fwimg_len);
 870
 871         tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size,
 872                                             &tegra->fw.phys, GFP_KERNEL);
 873         if (!tegra->fw.virt) {
 874                 dev_err(tegra->dev, "failed to allocate memory for firmware\n");
 875                 release_firmware(fw);
 876                 return -ENOMEM;
 877         }
 878
 879         header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
 880         memcpy(tegra->fw.virt, fw->data, tegra->fw.size);
 881         release_firmware(fw);
 882
 883         return 0;
 884 }
 885
 886 static int tegra_xusb_load_firmware(struct tegra_xusb *tegra)
 887 {
 888         unsigned int code_tag_blocks, code_size_blocks, code_blocks;
 889         struct xhci_cap_regs __iomem *cap = tegra->regs;
 890         struct tegra_xusb_fw_header *header;
 891         struct device *dev = tegra->dev;
 892         struct xhci_op_regs __iomem *op;
 893         unsigned long timeout;
 894         time64_t timestamp;
 895         struct tm time;
 896         u64 address;
 897         u32 value;
 898         int err;
 899
 900         header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
 901         op = tegra->regs + HC_LENGTH(readl(&cap->hc_capbase));
 902
 903         if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
 904                 dev_info(dev, "Firmware already loaded, Falcon state %#x\n",
 905                          csb_readl(tegra, XUSB_FALC_CPUCTL));
 906                 return 0;
 907         }
 908
 909         /* Program the size of DFI into ILOAD_ATTR. */
 910         csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR);
 911
 912         /*
 913          * Boot code of the firmware reads the ILOAD_BASE registers
 914          * to get to the start of the DFI in system memory.
 915          */
 916         address = tegra->fw.phys + sizeof(*header);
 917         csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI);
 918         csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO);
 919
 920         /* Set BOOTPATH to 1 in APMAP. */
 921         csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP);
 922
 923         /* Invalidate L2IMEM. */
 924         csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG);
 925
 926         /*
 927          * Initiate fetch of bootcode from system memory into L2IMEM.
 928          * Program bootcode location and size in system memory.
 929          */
 930         code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag),
 931                                        IMEM_BLOCK_SIZE);
 932         code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize),
 933                                         IMEM_BLOCK_SIZE);
 934         code_blocks = code_tag_blocks + code_size_blocks;
 935
 936         value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) <<
 937                         L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) |
 938                 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) <<
 939                         L2IMEMOP_SIZE_SRC_COUNT_SHIFT);
 940         csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE);
 941
 942         /* Trigger L2IMEM load operation. */
 943         csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT,
 944                    XUSB_CSB_MP_L2IMEMOP_TRIG);
 945
 946         /* Setup Falcon auto-fill. */
 947         csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL);
 948
 949         value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) <<
 950                         IMFILLRNG1_TAG_LO_SHIFT) |
 951                 ((code_blocks & IMFILLRNG1_TAG_MASK) <<
 952                         IMFILLRNG1_TAG_HI_SHIFT);
 953         csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1);
 954
 955         csb_writel(tegra, 0, XUSB_FALC_DMACTL);
 956
 957         /* wait for RESULT_VLD to get set */
 958 #define tegra_csb_readl(offset) csb_readl(tegra, offset)
 959         err = readx_poll_timeout(tegra_csb_readl,
 960                                  XUSB_CSB_MEMPOOL_L2IMEMOP_RESULT, value,
 961                                  value & L2IMEMOP_RESULT_VLD, 100, 10000);
 962         if (err < 0) {
 963                 dev_err(dev, "DMA controller not ready %#010x\n", value);
 964                 return err;
 965         }
 966 #undef tegra_csb_readl
 967
 968         csb_writel(tegra, le32_to_cpu(header->boot_codetag),
 969                    XUSB_FALC_BOOTVEC);
 970
 971         /* Boot Falcon CPU and wait for USBSTS_CNR to get cleared. */
 972         csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL);
 973
 974         timeout = jiffies + msecs_to_jiffies(200);
 975
 976         do {
 977                 value = readl(&op->status);
 978                 if ((value & STS_CNR) == 0)
 979                         break;
 980
 981                 usleep_range(1000, 2000);
 982         } while (time_is_after_jiffies(timeout));
 983
 984         value = readl(&op->status);
 985         if (value & STS_CNR) {
 986                 value = csb_readl(tegra, XUSB_FALC_CPUCTL);
 987                 dev_err(dev, "XHCI controller not read: %#010x\n", value);
 988                 return -EIO;
 989         }
 990
 991         timestamp = le32_to_cpu(header->fwimg_created_time);
 992         time64_to_tm(timestamp, 0, &time);
 993
 994         dev_info(dev, "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC\n",
 995                  time.tm_year + 1900, time.tm_mon + 1, time.tm_mday,
 996                  time.tm_hour, time.tm_min, time.tm_sec);
 997
 998         return 0;
 999 }
1000
1001 static void tegra_xusb_powerdomain_remove(struct device *dev,
1002                                           struct tegra_xusb *tegra)
1003 {
1004         if (!tegra->use_genpd)
1005                 return;
1006
1007         if (!IS_ERR_OR_NULL(tegra->genpd_dev_ss))
1008                 dev_pm_domain_detach(tegra->genpd_dev_ss, true);
1009         if (!IS_ERR_OR_NULL(tegra->genpd_dev_host))
1010                 dev_pm_domain_detach(tegra->genpd_dev_host, true);
1011 }
1012
1013 static int tegra_xusb_powerdomain_init(struct device *dev,
1014                                        struct tegra_xusb *tegra)
1015 {
1016         int err;
1017
1018         tegra->genpd_dev_host = dev_pm_domain_attach_by_name(dev, "xusb_host");
1019         if (IS_ERR(tegra->genpd_dev_host)) {
1020                 err = PTR_ERR(tegra->genpd_dev_host);
1021                 dev_err(dev, "failed to get host pm-domain: %d\n", err);
1022                 return err;
1023         }
1024
1025         tegra->genpd_dev_ss = dev_pm_domain_attach_by_name(dev, "xusb_ss");
1026         if (IS_ERR(tegra->genpd_dev_ss)) {
1027                 err = PTR_ERR(tegra->genpd_dev_ss);
1028                 dev_err(dev, "failed to get superspeed pm-domain: %d\n", err);
1029                 return err;
1030         }
1031
1032         tegra->use_genpd = true;
1033
1034         return 0;
1035 }
1036
1037 static int tegra_xusb_unpowergate_partitions(struct tegra_xusb *tegra)
1038 {
1039         struct device *dev = tegra->dev;
1040         int rc;
1041
1042         if (tegra->use_genpd) {
1043                 rc = pm_runtime_get_sync(tegra->genpd_dev_ss);
1044                 if (rc < 0) {
1045                         dev_err(dev, "failed to enable XUSB SS partition\n");
1046                         return rc;
1047                 }
1048
1049                 rc = pm_runtime_get_sync(tegra->genpd_dev_host);
1050                 if (rc < 0) {
1051                         dev_err(dev, "failed to enable XUSB Host partition\n");
1052                         pm_runtime_put_sync(tegra->genpd_dev_ss);
1053                         return rc;
1054                 }
1055         } else {
1056                 rc = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA,
1057                                                         tegra->ss_clk,
1058                                                         tegra->ss_rst);
1059                 if (rc < 0) {
1060                         dev_err(dev, "failed to enable XUSB SS partition\n");
1061                         return rc;
1062                 }
1063
1064                 rc = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
1065                                                         tegra->host_clk,
1066                                                         tegra->host_rst);
1067                 if (rc < 0) {
1068                         dev_err(dev, "failed to enable XUSB Host partition\n");
1069                         tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1070                         return rc;
1071                 }
1072         }
1073
1074         return 0;
1075 }
1076
1077 static int tegra_xusb_powergate_partitions(struct tegra_xusb *tegra)
1078 {
1079         struct device *dev = tegra->dev;
1080         int rc;
1081
1082         if (tegra->use_genpd) {
1083                 rc = pm_runtime_put_sync(tegra->genpd_dev_host);
1084                 if (rc < 0) {
1085                         dev_err(dev, "failed to disable XUSB Host partition\n");
1086                         return rc;
1087                 }
1088
1089                 rc = pm_runtime_put_sync(tegra->genpd_dev_ss);
1090                 if (rc < 0) {
1091                         dev_err(dev, "failed to disable XUSB SS partition\n");
1092                         pm_runtime_get_sync(tegra->genpd_dev_host);
1093                         return rc;
1094                 }
1095         } else {
1096                 rc = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
1097                 if (rc < 0) {
1098                         dev_err(dev, "failed to disable XUSB Host partition\n");
1099                         return rc;
1100                 }
1101
1102                 rc = tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1103                 if (rc < 0) {
1104                         dev_err(dev, "failed to disable XUSB SS partition\n");
1105                         tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
1106                                                           tegra->host_clk,
1107                                                           tegra->host_rst);
1108                         return rc;
1109                 }
1110         }
1111
1112         return 0;
1113 }
1114
1115 static int __tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra)
1116 {
1117         struct tegra_xusb_mbox_msg msg;
1118         int err;
1119
1120         /* Enable firmware messages from controller. */
1121         msg.cmd = MBOX_CMD_MSG_ENABLED;
1122         msg.data = 0;
1123
1124         err = tegra_xusb_mbox_send(tegra, &msg);
1125         if (err < 0)
1126                 dev_err(tegra->dev, "failed to enable messages: %d\n", err);
1127
1128         return err;
1129 }
1130
1131 static int tegra_xusb_enable_firmware_messages(struct tegra_xusb *tegra)
1132 {
1133         int err;
1134
1135         mutex_lock(&tegra->lock);
1136         err = __tegra_xusb_enable_firmware_messages(tegra);
1137         mutex_unlock(&tegra->lock);
1138
1139         return err;
1140 }
1141
1142 static void tegra_xhci_set_port_power(struct tegra_xusb *tegra, bool main,
1143                                                  bool set)
1144 {
1145         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1146         struct usb_hcd *hcd = main ?  xhci->main_hcd : xhci->shared_hcd;
1147         unsigned int wait = (!main && !set) ? 1000 : 10;
1148         u16 typeReq = set ? SetPortFeature : ClearPortFeature;
1149         u16 wIndex = main ? tegra->otg_usb2_port + 1 : tegra->otg_usb3_port + 1;
1150         u32 status;
1151         u32 stat_power = main ? USB_PORT_STAT_POWER : USB_SS_PORT_STAT_POWER;
1152         u32 status_val = set ? stat_power : 0;
1153
1154         dev_dbg(tegra->dev, "%s():%s %s port power\n", __func__,
1155                 set ? "set" : "clear", main ? "HS" : "SS");
1156
1157         hcd->driver->hub_control(hcd, typeReq, USB_PORT_FEAT_POWER, wIndex,
1158                                  NULL, 0);
1159
1160         do {
1161                 tegra_xhci_hc_driver.hub_control(hcd, GetPortStatus, 0, wIndex,
1162                                         (char *) &status, sizeof(status));
1163                 if (status_val == (status & stat_power))
1164                         break;
1165
1166                 if (!main && !set)
1167                         usleep_range(600, 700);
1168                 else
1169                         usleep_range(10, 20);
1170         } while (--wait > 0);
1171
1172         if (status_val != (status & stat_power))
1173                 dev_info(tegra->dev, "failed to %s %s PP %d\n",
1174                                                 set ? "set" : "clear",
1175                                                 main ? "HS" : "SS", status);
1176 }
1177
1178 static struct phy *tegra_xusb_get_phy(struct tegra_xusb *tegra, char *name,
1179                                                                 int port)
1180 {
1181         unsigned int i, phy_count = 0;
1182
1183         for (i = 0; i < tegra->soc->num_types; i++) {
1184                 if (!strncmp(tegra->soc->phy_types[i].name, name,
1185                                                             strlen(name)))
1186                         return tegra->phys[phy_count+port];
1187
1188                 phy_count += tegra->soc->phy_types[i].num;
1189         }
1190
1191         return NULL;
1192 }
1193
1194 static void tegra_xhci_id_work(struct work_struct *work)
1195 {
1196         struct tegra_xusb *tegra = container_of(work, struct tegra_xusb,
1197                                                 id_work);
1198         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1199         struct tegra_xusb_mbox_msg msg;
1200         struct phy *phy = tegra_xusb_get_phy(tegra, "usb2",
1201                                                     tegra->otg_usb2_port);
1202         u32 status;
1203         int ret;
1204
1205         dev_dbg(tegra->dev, "host mode %s\n", tegra->host_mode ? "on" : "off");
1206
1207         mutex_lock(&tegra->lock);
1208
1209         if (tegra->host_mode)
1210                 phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_HOST);
1211         else
1212                 phy_set_mode_ext(phy, PHY_MODE_USB_OTG, USB_ROLE_NONE);
1213
1214         mutex_unlock(&tegra->lock);
1215
1216         if (tegra->host_mode) {
1217                 /* switch to host mode */
1218                 if (tegra->otg_usb3_port >= 0) {
1219                         if (tegra->soc->otg_reset_sspi) {
1220                                 /* set PP=0 */
1221                                 tegra_xhci_hc_driver.hub_control(
1222                                         xhci->shared_hcd, GetPortStatus,
1223                                         0, tegra->otg_usb3_port+1,
1224                                         (char *) &status, sizeof(status));
1225                                 if (status & USB_SS_PORT_STAT_POWER)
1226                                         tegra_xhci_set_port_power(tegra, false,
1227                                                                   false);
1228
1229                                 /* reset OTG port SSPI */
1230                                 msg.cmd = MBOX_CMD_RESET_SSPI;
1231                                 msg.data = tegra->otg_usb3_port+1;
1232
1233                                 ret = tegra_xusb_mbox_send(tegra, &msg);
1234                                 if (ret < 0) {
1235                                         dev_info(tegra->dev,
1236                                                 "failed to RESET_SSPI %d\n",
1237                                                 ret);
1238                                 }
1239                         }
1240
1241                         tegra_xhci_set_port_power(tegra, false, true);
1242                 }
1243
1244                 tegra_xhci_set_port_power(tegra, true, true);
1245
1246         } else {
1247                 if (tegra->otg_usb3_port >= 0)
1248                         tegra_xhci_set_port_power(tegra, false, false);
1249
1250                 tegra_xhci_set_port_power(tegra, true, false);
1251         }
1252 }
1253
1254 static int tegra_xusb_get_usb2_port(struct tegra_xusb *tegra,
1255                                               struct usb_phy *usbphy)
1256 {
1257         unsigned int i;
1258
1259         for (i = 0; i < tegra->num_usb_phys; i++) {
1260                 if (tegra->usbphy[i] && usbphy == tegra->usbphy[i])
1261                         return i;
1262         }
1263
1264         return -1;
1265 }
1266
1267 static int tegra_xhci_id_notify(struct notifier_block *nb,
1268                                          unsigned long action, void *data)
1269 {
1270         struct tegra_xusb *tegra = container_of(nb, struct tegra_xusb,
1271                                                     id_nb);
1272         struct usb_phy *usbphy = (struct usb_phy *)data;
1273
1274         dev_dbg(tegra->dev, "%s(): action is %d", __func__, usbphy->last_event);
1275
1276         if ((tegra->host_mode && usbphy->last_event == USB_EVENT_ID) ||
1277                 (!tegra->host_mode && usbphy->last_event != USB_EVENT_ID)) {
1278                 dev_dbg(tegra->dev, "Same role(%d) received. Ignore",
1279                         tegra->host_mode);
1280                 return NOTIFY_OK;
1281         }
1282
1283         tegra->otg_usb2_port = tegra_xusb_get_usb2_port(tegra, usbphy);
1284         tegra->otg_usb3_port = tegra_xusb_padctl_get_usb3_companion(
1285                                                         tegra->padctl,
1286                                                         tegra->otg_usb2_port);
1287
1288         tegra->host_mode = (usbphy->last_event == USB_EVENT_ID) ? true : false;
1289
1290         schedule_work(&tegra->id_work);
1291
1292         return NOTIFY_OK;
1293 }
1294
1295 static int tegra_xusb_init_usb_phy(struct tegra_xusb *tegra)
1296 {
1297         unsigned int i;
1298
1299         tegra->usbphy = devm_kcalloc(tegra->dev, tegra->num_usb_phys,
1300                                    sizeof(*tegra->usbphy), GFP_KERNEL);
1301         if (!tegra->usbphy)
1302                 return -ENOMEM;
1303
1304         INIT_WORK(&tegra->id_work, tegra_xhci_id_work);
1305         tegra->id_nb.notifier_call = tegra_xhci_id_notify;
1306         tegra->otg_usb2_port = -EINVAL;
1307         tegra->otg_usb3_port = -EINVAL;
1308
1309         for (i = 0; i < tegra->num_usb_phys; i++) {
1310                 struct phy *phy = tegra_xusb_get_phy(tegra, "usb2", i);
1311
1312                 if (!phy)
1313                         continue;
1314
1315                 tegra->usbphy[i] = devm_usb_get_phy_by_node(tegra->dev,
1316                                                         phy->dev.of_node,
1317                                                         &tegra->id_nb);
1318                 if (!IS_ERR(tegra->usbphy[i])) {
1319                         dev_dbg(tegra->dev, "usbphy-%d registered", i);
1320                         otg_set_host(tegra->usbphy[i]->otg, &tegra->hcd->self);
1321                 } else {
1322                         /*
1323                          * usb-phy is optional, continue if its not available.
1324                          */
1325                         tegra->usbphy[i] = NULL;
1326                 }
1327         }
1328
1329         return 0;
1330 }
1331
1332 static void tegra_xusb_deinit_usb_phy(struct tegra_xusb *tegra)
1333 {
1334         unsigned int i;
1335
1336         cancel_work_sync(&tegra->id_work);
1337
1338         for (i = 0; i < tegra->num_usb_phys; i++)
1339                 if (tegra->usbphy[i])
1340                         otg_set_host(tegra->usbphy[i]->otg, NULL);
1341 }
1342
1343 static int tegra_xusb_probe(struct platform_device *pdev)
1344 {
1345         struct tegra_xusb *tegra;
1346         struct resource *regs;
1347         struct xhci_hcd *xhci;
1348         unsigned int i, j, k;
1349         struct phy *phy;
1350         int err;
1351
1352         BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256);
1353
1354         tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
1355         if (!tegra)
1356                 return -ENOMEM;
1357
1358         tegra->soc = of_device_get_match_data(&pdev->dev);
1359         mutex_init(&tegra->lock);
1360         tegra->dev = &pdev->dev;
1361
1362         err = tegra_xusb_init_context(tegra);
1363         if (err < 0)
1364                 return err;
1365
1366         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1367         tegra->regs = devm_ioremap_resource(&pdev->dev, regs);
1368         if (IS_ERR(tegra->regs))
1369                 return PTR_ERR(tegra->regs);
1370
1371         tegra->fpci_base = devm_platform_ioremap_resource(pdev, 1);
1372         if (IS_ERR(tegra->fpci_base))
1373                 return PTR_ERR(tegra->fpci_base);
1374
1375         if (tegra->soc->has_ipfs) {
1376                 tegra->ipfs_base = devm_platform_ioremap_resource(pdev, 2);
1377                 if (IS_ERR(tegra->ipfs_base))
1378                         return PTR_ERR(tegra->ipfs_base);
1379         }
1380
1381         tegra->xhci_irq = platform_get_irq(pdev, 0);
1382         if (tegra->xhci_irq < 0)
1383                 return tegra->xhci_irq;
1384
1385         tegra->mbox_irq = platform_get_irq(pdev, 1);
1386         if (tegra->mbox_irq < 0)
1387                 return tegra->mbox_irq;
1388
1389         tegra->padctl = tegra_xusb_padctl_get(&pdev->dev);
1390         if (IS_ERR(tegra->padctl))
1391                 return PTR_ERR(tegra->padctl);
1392
1393         tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host");
1394         if (IS_ERR(tegra->host_clk)) {
1395                 err = PTR_ERR(tegra->host_clk);
1396                 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err);
1397                 goto put_padctl;
1398         }
1399
1400         tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src");
1401         if (IS_ERR(tegra->falcon_clk)) {
1402                 err = PTR_ERR(tegra->falcon_clk);
1403                 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err);
1404                 goto put_padctl;
1405         }
1406
1407         tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss");
1408         if (IS_ERR(tegra->ss_clk)) {
1409                 err = PTR_ERR(tegra->ss_clk);
1410                 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err);
1411                 goto put_padctl;
1412         }
1413
1414         tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src");
1415         if (IS_ERR(tegra->ss_src_clk)) {
1416                 err = PTR_ERR(tegra->ss_src_clk);
1417                 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err);
1418                 goto put_padctl;
1419         }
1420
1421         tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src");
1422         if (IS_ERR(tegra->hs_src_clk)) {
1423                 err = PTR_ERR(tegra->hs_src_clk);
1424                 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err);
1425                 goto put_padctl;
1426         }
1427
1428         tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src");
1429         if (IS_ERR(tegra->fs_src_clk)) {
1430                 err = PTR_ERR(tegra->fs_src_clk);
1431                 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err);
1432                 goto put_padctl;
1433         }
1434
1435         tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m");
1436         if (IS_ERR(tegra->pll_u_480m)) {
1437                 err = PTR_ERR(tegra->pll_u_480m);
1438                 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err);
1439                 goto put_padctl;
1440         }
1441
1442         tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1443         if (IS_ERR(tegra->clk_m)) {
1444                 err = PTR_ERR(tegra->clk_m);
1445                 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err);
1446                 goto put_padctl;
1447         }
1448
1449         tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e");
1450         if (IS_ERR(tegra->pll_e)) {
1451                 err = PTR_ERR(tegra->pll_e);
1452                 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err);
1453                 goto put_padctl;
1454         }
1455
1456         if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
1457                 tegra->host_rst = devm_reset_control_get(&pdev->dev,
1458                                                          "xusb_host");
1459                 if (IS_ERR(tegra->host_rst)) {
1460                         err = PTR_ERR(tegra->host_rst);
1461                         dev_err(&pdev->dev,
1462                                 "failed to get xusb_host reset: %d\n", err);
1463                         goto put_padctl;
1464                 }
1465
1466                 tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss");
1467                 if (IS_ERR(tegra->ss_rst)) {
1468                         err = PTR_ERR(tegra->ss_rst);
1469                         dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n",
1470                                 err);
1471                         goto put_padctl;
1472                 }
1473         } else {
1474                 err = tegra_xusb_powerdomain_init(&pdev->dev, tegra);
1475                 if (err)
1476                         goto put_powerdomains;
1477         }
1478
1479         tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies,
1480                                        sizeof(*tegra->supplies), GFP_KERNEL);
1481         if (!tegra->supplies) {
1482                 err = -ENOMEM;
1483                 goto put_powerdomains;
1484         }
1485
1486         regulator_bulk_set_supply_names(tegra->supplies,
1487                                         tegra->soc->supply_names,
1488                                         tegra->soc->num_supplies);
1489
1490         err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies,
1491                                       tegra->supplies);
1492         if (err) {
1493                 dev_err(&pdev->dev, "failed to get regulators: %d\n", err);
1494                 goto put_powerdomains;
1495         }
1496
1497         for (i = 0; i < tegra->soc->num_types; i++) {
1498                 if (!strncmp(tegra->soc->phy_types[i].name, "usb2", 4))
1499                         tegra->num_usb_phys = tegra->soc->phy_types[i].num;
1500                 tegra->num_phys += tegra->soc->phy_types[i].num;
1501         }
1502
1503         tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys,
1504                                    sizeof(*tegra->phys), GFP_KERNEL);
1505         if (!tegra->phys) {
1506                 err = -ENOMEM;
1507                 goto put_powerdomains;
1508         }
1509
1510         for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
1511                 char prop[8];
1512
1513                 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
1514                         snprintf(prop, sizeof(prop), "%s-%d",
1515                                  tegra->soc->phy_types[i].name, j);
1516
1517                         phy = devm_phy_optional_get(&pdev->dev, prop);
1518                         if (IS_ERR(phy)) {
1519                                 dev_err(&pdev->dev,
1520                                         "failed to get PHY %s: %ld\n", prop,
1521                                         PTR_ERR(phy));
1522                                 err = PTR_ERR(phy);
1523                                 goto put_powerdomains;
1524                         }
1525
1526                         tegra->phys[k++] = phy;
1527                 }
1528         }
1529
1530         tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev,
1531                                     dev_name(&pdev->dev));
1532         if (!tegra->hcd) {
1533                 err = -ENOMEM;
1534                 goto put_powerdomains;
1535         }
1536
1537         tegra->hcd->regs = tegra->regs;
1538         tegra->hcd->rsrc_start = regs->start;
1539         tegra->hcd->rsrc_len = resource_size(regs);
1540
1541         /*
1542          * This must happen after usb_create_hcd(), because usb_create_hcd()
1543          * will overwrite the drvdata of the device with the hcd it creates.
1544          */
1545         platform_set_drvdata(pdev, tegra);
1546
1547         err = tegra_xusb_clk_enable(tegra);
1548         if (err) {
1549                 dev_err(tegra->dev, "failed to enable clocks: %d\n", err);
1550                 goto put_hcd;
1551         }
1552
1553         err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies);
1554         if (err) {
1555                 dev_err(tegra->dev, "failed to enable regulators: %d\n", err);
1556                 goto disable_clk;
1557         }
1558
1559         err = tegra_xusb_phy_enable(tegra);
1560         if (err < 0) {
1561                 dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err);
1562                 goto disable_regulator;
1563         }
1564
1565         /*
1566          * The XUSB Falcon microcontroller can only address 40 bits, so set
1567          * the DMA mask accordingly.
1568          */
1569         err = dma_set_mask_and_coherent(tegra->dev, DMA_BIT_MASK(40));
1570         if (err < 0) {
1571                 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
1572                 goto disable_phy;
1573         }
1574
1575         err = tegra_xusb_request_firmware(tegra);
1576         if (err < 0) {
1577                 dev_err(&pdev->dev, "failed to request firmware: %d\n", err);
1578                 goto disable_phy;
1579         }
1580
1581         err = tegra_xusb_unpowergate_partitions(tegra);
1582         if (err)
1583                 goto free_firmware;
1584
1585         tegra_xusb_config(tegra);
1586
1587         err = tegra_xusb_load_firmware(tegra);
1588         if (err < 0) {
1589                 dev_err(&pdev->dev, "failed to load firmware: %d\n", err);
1590                 goto powergate;
1591         }
1592
1593         err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED);
1594         if (err < 0) {
1595                 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err);
1596                 goto powergate;
1597         }
1598
1599         device_wakeup_enable(tegra->hcd->self.controller);
1600
1601         xhci = hcd_to_xhci(tegra->hcd);
1602
1603         xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver,
1604                                                  &pdev->dev,
1605                                                  dev_name(&pdev->dev),
1606                                                  tegra->hcd);
1607         if (!xhci->shared_hcd) {
1608                 dev_err(&pdev->dev, "failed to create shared HCD\n");
1609                 err = -ENOMEM;
1610                 goto remove_usb2;
1611         }
1612
1613         err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED);
1614         if (err < 0) {
1615                 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err);
1616                 goto put_usb3;
1617         }
1618
1619         err = tegra_xusb_enable_firmware_messages(tegra);
1620         if (err < 0) {
1621                 dev_err(&pdev->dev, "failed to enable messages: %d\n", err);
1622                 goto remove_usb3;
1623         }
1624
1625         err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq,
1626                                         tegra_xusb_mbox_irq,
1627                                         tegra_xusb_mbox_thread, 0,
1628                                         dev_name(&pdev->dev), tegra);
1629         if (err < 0) {
1630                 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1631                 goto remove_usb3;
1632         }
1633
1634         err = tegra_xusb_init_usb_phy(tegra);
1635         if (err < 0) {
1636                 dev_err(&pdev->dev, "failed to init USB PHY: %d\n", err);
1637                 goto remove_usb3;
1638         }
1639
1640         return 0;
1641
1642 remove_usb3:
1643         usb_remove_hcd(xhci->shared_hcd);
1644 put_usb3:
1645         usb_put_hcd(xhci->shared_hcd);
1646 remove_usb2:
1647         usb_remove_hcd(tegra->hcd);
1648 powergate:
1649         tegra_xusb_powergate_partitions(tegra);
1650 free_firmware:
1651         dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1652                           tegra->fw.phys);
1653 disable_phy:
1654         tegra_xusb_phy_disable(tegra);
1655 disable_regulator:
1656         regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
1657 disable_clk:
1658         tegra_xusb_clk_disable(tegra);
1659 put_hcd:
1660         usb_put_hcd(tegra->hcd);
1661 put_powerdomains:
1662         tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
1663 put_padctl:
1664         tegra_xusb_padctl_put(tegra->padctl);
1665         return err;
1666 }
1667
1668 static int tegra_xusb_remove(struct platform_device *pdev)
1669 {
1670         struct tegra_xusb *tegra = platform_get_drvdata(pdev);
1671         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1672
1673         tegra_xusb_deinit_usb_phy(tegra);
1674
1675         usb_remove_hcd(xhci->shared_hcd);
1676         usb_put_hcd(xhci->shared_hcd);
1677         xhci->shared_hcd = NULL;
1678         usb_remove_hcd(tegra->hcd);
1679         usb_put_hcd(tegra->hcd);
1680
1681         dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1682                           tegra->fw.phys);
1683
1684         pm_runtime_put_sync(&pdev->dev);
1685         pm_runtime_disable(&pdev->dev);
1686
1687         tegra_xusb_powergate_partitions(tegra);
1688
1689         tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
1690
1691         tegra_xusb_phy_disable(tegra);
1692         tegra_xusb_clk_disable(tegra);
1693         regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
1694         tegra_xusb_padctl_put(tegra->padctl);
1695
1696         return 0;
1697 }
1698
1699 #ifdef CONFIG_PM_SLEEP
1700 static bool xhci_hub_ports_suspended(struct xhci_hub *hub)
1701 {
1702         struct device *dev = hub->hcd->self.controller;
1703         bool status = true;
1704         unsigned int i;
1705         u32 value;
1706
1707         for (i = 0; i < hub->num_ports; i++) {
1708                 value = readl(hub->ports[i]->addr);
1709                 if ((value & PORT_PE) == 0)
1710                         continue;
1711
1712                 if ((value & PORT_PLS_MASK) != XDEV_U3) {
1713                         dev_info(dev, "%u-%u isn't suspended: %#010x\n",
1714                                  hub->hcd->self.busnum, i + 1, value);
1715                         status = false;
1716                 }
1717         }
1718
1719         return status;
1720 }
1721
1722 static int tegra_xusb_check_ports(struct tegra_xusb *tegra)
1723 {
1724         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1725         unsigned long flags;
1726         int err = 0;
1727
1728         spin_lock_irqsave(&xhci->lock, flags);
1729
1730         if (!xhci_hub_ports_suspended(&xhci->usb2_rhub) ||
1731             !xhci_hub_ports_suspended(&xhci->usb3_rhub))
1732                 err = -EBUSY;
1733
1734         spin_unlock_irqrestore(&xhci->lock, flags);
1735
1736         return err;
1737 }
1738
1739 static void tegra_xusb_save_context(struct tegra_xusb *tegra)
1740 {
1741         const struct tegra_xusb_context_soc *soc = tegra->soc->context;
1742         struct tegra_xusb_context *ctx = &tegra->context;
1743         unsigned int i;
1744
1745         if (soc->ipfs.num_offsets > 0) {
1746                 for (i = 0; i < soc->ipfs.num_offsets; i++)
1747                         ctx->ipfs[i] = ipfs_readl(tegra, soc->ipfs.offsets[i]);
1748         }
1749
1750         if (soc->fpci.num_offsets > 0) {
1751                 for (i = 0; i < soc->fpci.num_offsets; i++)
1752                         ctx->fpci[i] = fpci_readl(tegra, soc->fpci.offsets[i]);
1753         }
1754 }
1755
1756 static void tegra_xusb_restore_context(struct tegra_xusb *tegra)
1757 {
1758         const struct tegra_xusb_context_soc *soc = tegra->soc->context;
1759         struct tegra_xusb_context *ctx = &tegra->context;
1760         unsigned int i;
1761
1762         if (soc->fpci.num_offsets > 0) {
1763                 for (i = 0; i < soc->fpci.num_offsets; i++)
1764                         fpci_writel(tegra, ctx->fpci[i], soc->fpci.offsets[i]);
1765         }
1766
1767         if (soc->ipfs.num_offsets > 0) {
1768                 for (i = 0; i < soc->ipfs.num_offsets; i++)
1769                         ipfs_writel(tegra, ctx->ipfs[i], soc->ipfs.offsets[i]);
1770         }
1771 }
1772
1773 static int tegra_xusb_enter_elpg(struct tegra_xusb *tegra, bool wakeup)
1774 {
1775         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1776         int err;
1777
1778         err = tegra_xusb_check_ports(tegra);
1779         if (err < 0) {
1780                 dev_err(tegra->dev, "not all ports suspended: %d\n", err);
1781                 return err;
1782         }
1783
1784         err = xhci_suspend(xhci, wakeup);
1785         if (err < 0) {
1786                 dev_err(tegra->dev, "failed to suspend XHCI: %d\n", err);
1787                 return err;
1788         }
1789
1790         tegra_xusb_save_context(tegra);
1791         tegra_xusb_phy_disable(tegra);
1792         tegra_xusb_clk_disable(tegra);
1793
1794         return 0;
1795 }
1796
1797 static int tegra_xusb_exit_elpg(struct tegra_xusb *tegra, bool wakeup)
1798 {
1799         struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1800         int err;
1801
1802         err = tegra_xusb_clk_enable(tegra);
1803         if (err < 0) {
1804                 dev_err(tegra->dev, "failed to enable clocks: %d\n", err);
1805                 return err;
1806         }
1807
1808         err = tegra_xusb_phy_enable(tegra);
1809         if (err < 0) {
1810                 dev_err(tegra->dev, "failed to enable PHYs: %d\n", err);
1811                 goto disable_clk;
1812         }
1813
1814         tegra_xusb_config(tegra);
1815         tegra_xusb_restore_context(tegra);
1816
1817         err = tegra_xusb_load_firmware(tegra);
1818         if (err < 0) {
1819                 dev_err(tegra->dev, "failed to load firmware: %d\n", err);
1820                 goto disable_phy;
1821         }
1822
1823         err = __tegra_xusb_enable_firmware_messages(tegra);
1824         if (err < 0) {
1825                 dev_err(tegra->dev, "failed to enable messages: %d\n", err);
1826                 goto disable_phy;
1827         }
1828
1829         err = xhci_resume(xhci, true);
1830         if (err < 0) {
1831                 dev_err(tegra->dev, "failed to resume XHCI: %d\n", err);
1832                 goto disable_phy;
1833         }
1834
1835         return 0;
1836
1837 disable_phy:
1838         tegra_xusb_phy_disable(tegra);
1839 disable_clk:
1840         tegra_xusb_clk_disable(tegra);
1841         return err;
1842 }
1843
1844 static int tegra_xusb_suspend(struct device *dev)
1845 {
1846         struct tegra_xusb *tegra = dev_get_drvdata(dev);
1847         bool wakeup = device_may_wakeup(dev);
1848         int err;
1849
1850         synchronize_irq(tegra->mbox_irq);
1851
1852         mutex_lock(&tegra->lock);
1853         err = tegra_xusb_enter_elpg(tegra, wakeup);
1854         mutex_unlock(&tegra->lock);
1855
1856         return err;
1857 }
1858
1859 static int tegra_xusb_resume(struct device *dev)
1860 {
1861         struct tegra_xusb *tegra = dev_get_drvdata(dev);
1862         bool wakeup = device_may_wakeup(dev);
1863         int err;
1864
1865         mutex_lock(&tegra->lock);
1866         err = tegra_xusb_exit_elpg(tegra, wakeup);
1867         mutex_unlock(&tegra->lock);
1868
1869         return err;
1870 }
1871 #endif
1872
1873 static const struct dev_pm_ops tegra_xusb_pm_ops = {
1874         SET_RUNTIME_PM_OPS(tegra_xusb_runtime_suspend,
1875                            tegra_xusb_runtime_resume, NULL)
1876         SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume)
1877 };
1878
1879 static const char * const tegra124_supply_names[] = {
1880         "avddio-pex",
1881         "dvddio-pex",
1882         "avdd-usb",
1883         "hvdd-usb-ss",
1884 };
1885
1886 static const struct tegra_xusb_phy_type tegra124_phy_types[] = {
1887         { .name = "usb3", .num = 2, },
1888         { .name = "usb2", .num = 3, },
1889         { .name = "hsic", .num = 2, },
1890 };
1891
1892 static const unsigned int tegra124_xusb_context_ipfs[] = {
1893         IPFS_XUSB_HOST_MSI_BAR_SZ_0,
1894         IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0,
1895         IPFS_XUSB_HOST_MSI_FPCI_BAR_ST_0,
1896         IPFS_XUSB_HOST_MSI_VEC0_0,
1897         IPFS_XUSB_HOST_MSI_EN_VEC0_0,
1898         IPFS_XUSB_HOST_FPCI_ERROR_MASKS_0,
1899         IPFS_XUSB_HOST_INTR_MASK_0,
1900         IPFS_XUSB_HOST_INTR_ENABLE_0,
1901         IPFS_XUSB_HOST_UFPCI_CONFIG_0,
1902         IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0,
1903         IPFS_XUSB_HOST_MCCIF_FIFOCTRL_0,
1904 };
1905
1906 static const unsigned int tegra124_xusb_context_fpci[] = {
1907         XUSB_CFG_ARU_CONTEXT_HS_PLS,
1908         XUSB_CFG_ARU_CONTEXT_FS_PLS,
1909         XUSB_CFG_ARU_CONTEXT_HSFS_SPEED,
1910         XUSB_CFG_ARU_CONTEXT_HSFS_PP,
1911         XUSB_CFG_ARU_CONTEXT,
1912         XUSB_CFG_AXI_CFG,
1913         XUSB_CFG_24,
1914         XUSB_CFG_16,
1915 };
1916
1917 static const struct tegra_xusb_context_soc tegra124_xusb_context = {
1918         .ipfs = {
1919                 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_ipfs),
1920                 .offsets = tegra124_xusb_context_ipfs,
1921         },
1922         .fpci = {
1923                 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci),
1924                 .offsets = tegra124_xusb_context_fpci,
1925         },
1926 };
1927
1928 static const struct tegra_xusb_soc tegra124_soc = {
1929         .firmware = "nvidia/tegra124/xusb.bin",
1930         .supply_names = tegra124_supply_names,
1931         .num_supplies = ARRAY_SIZE(tegra124_supply_names),
1932         .phy_types = tegra124_phy_types,
1933         .num_types = ARRAY_SIZE(tegra124_phy_types),
1934         .context = &tegra124_xusb_context,
1935         .ports = {
1936                 .usb2 = { .offset = 4, .count = 4, },
1937                 .hsic = { .offset = 6, .count = 2, },
1938                 .usb3 = { .offset = 0, .count = 2, },
1939         },
1940         .scale_ss_clock = true,
1941         .has_ipfs = true,
1942         .otg_reset_sspi = false,
1943         .mbox = {
1944                 .cmd = 0xe4,
1945                 .data_in = 0xe8,
1946                 .data_out = 0xec,
1947                 .owner = 0xf0,
1948         },
1949 };
1950 MODULE_FIRMWARE("nvidia/tegra124/xusb.bin");
1951
1952 static const char * const tegra210_supply_names[] = {
1953         "dvddio-pex",
1954         "hvddio-pex",
1955         "avdd-usb",
1956 };
1957
1958 static const struct tegra_xusb_phy_type tegra210_phy_types[] = {
1959         { .name = "usb3", .num = 4, },
1960         { .name = "usb2", .num = 4, },
1961         { .name = "hsic", .num = 1, },
1962 };
1963
1964 static const struct tegra_xusb_soc tegra210_soc = {
1965         .firmware = "nvidia/tegra210/xusb.bin",
1966         .supply_names = tegra210_supply_names,
1967         .num_supplies = ARRAY_SIZE(tegra210_supply_names),
1968         .phy_types = tegra210_phy_types,
1969         .num_types = ARRAY_SIZE(tegra210_phy_types),
1970         .context = &tegra124_xusb_context,
1971         .ports = {
1972                 .usb2 = { .offset = 4, .count = 4, },
1973                 .hsic = { .offset = 8, .count = 1, },
1974                 .usb3 = { .offset = 0, .count = 4, },
1975         },
1976         .scale_ss_clock = false,
1977         .has_ipfs = true,
1978         .otg_reset_sspi = true,
1979         .mbox = {
1980                 .cmd = 0xe4,
1981                 .data_in = 0xe8,
1982                 .data_out = 0xec,
1983                 .owner = 0xf0,
1984         },
1985 };
1986 MODULE_FIRMWARE("nvidia/tegra210/xusb.bin");
1987
1988 static const char * const tegra186_supply_names[] = {
1989 };
1990 MODULE_FIRMWARE("nvidia/tegra186/xusb.bin");
1991
1992 static const struct tegra_xusb_phy_type tegra186_phy_types[] = {
1993         { .name = "usb3", .num = 3, },
1994         { .name = "usb2", .num = 3, },
1995         { .name = "hsic", .num = 1, },
1996 };
1997
1998 static const struct tegra_xusb_context_soc tegra186_xusb_context = {
1999         .fpci = {
2000                 .num_offsets = ARRAY_SIZE(tegra124_xusb_context_fpci),
2001                 .offsets = tegra124_xusb_context_fpci,
2002         },
2003 };
2004
2005 static const struct tegra_xusb_soc tegra186_soc = {
2006         .firmware = "nvidia/tegra186/xusb.bin",
2007         .supply_names = tegra186_supply_names,
2008         .num_supplies = ARRAY_SIZE(tegra186_supply_names),
2009         .phy_types = tegra186_phy_types,
2010         .num_types = ARRAY_SIZE(tegra186_phy_types),
2011         .context = &tegra186_xusb_context,
2012         .ports = {
2013                 .usb3 = { .offset = 0, .count = 3, },
2014                 .usb2 = { .offset = 3, .count = 3, },
2015                 .hsic = { .offset = 6, .count = 1, },
2016         },
2017         .scale_ss_clock = false,
2018         .has_ipfs = false,
2019         .otg_reset_sspi = false,
2020         .mbox = {
2021                 .cmd = 0xe4,
2022                 .data_in = 0xe8,
2023                 .data_out = 0xec,
2024                 .owner = 0xf0,
2025         },
2026         .lpm_support = true,
2027 };
2028
2029 static const char * const tegra194_supply_names[] = {
2030 };
2031
2032 static const struct tegra_xusb_phy_type tegra194_phy_types[] = {
2033         { .name = "usb3", .num = 4, },
2034         { .name = "usb2", .num = 4, },
2035 };
2036
2037 static const struct tegra_xusb_soc tegra194_soc = {
2038         .firmware = "nvidia/tegra194/xusb.bin",
2039         .supply_names = tegra194_supply_names,
2040         .num_supplies = ARRAY_SIZE(tegra194_supply_names),
2041         .phy_types = tegra194_phy_types,
2042         .num_types = ARRAY_SIZE(tegra194_phy_types),
2043         .context = &tegra186_xusb_context,
2044         .ports = {
2045                 .usb3 = { .offset = 0, .count = 4, },
2046                 .usb2 = { .offset = 4, .count = 4, },
2047         },
2048         .scale_ss_clock = false,
2049         .has_ipfs = false,
2050         .otg_reset_sspi = false,
2051         .mbox = {
2052                 .cmd = 0x68,
2053                 .data_in = 0x6c,
2054                 .data_out = 0x70,
2055                 .owner = 0x74,
2056         },
2057         .lpm_support = true,
2058 };
2059 MODULE_FIRMWARE("nvidia/tegra194/xusb.bin");
2060
2061 static const struct of_device_id tegra_xusb_of_match[] = {
2062         { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc },
2063         { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc },
2064         { .compatible = "nvidia,tegra186-xusb", .data = &tegra186_soc },
2065         { .compatible = "nvidia,tegra194-xusb", .data = &tegra194_soc },
2066         { },
2067 };
2068 MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
2069
2070 static struct platform_driver tegra_xusb_driver = {
2071         .probe = tegra_xusb_probe,
2072         .remove = tegra_xusb_remove,
2073         .driver = {
2074                 .name = "tegra-xusb",
2075                 .pm = &tegra_xusb_pm_ops,
2076                 .of_match_table = tegra_xusb_of_match,
2077         },
2078 };
2079
2080 static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci)
2081 {
2082         struct tegra_xusb *tegra = dev_get_drvdata(dev);
2083
2084         xhci->quirks |= XHCI_PLAT;
2085         if (tegra && tegra->soc->lpm_support)
2086                 xhci->quirks |= XHCI_LPM_SUPPORT;
2087 }
2088
2089 static int tegra_xhci_setup(struct usb_hcd *hcd)
2090 {
2091         return xhci_gen_setup(hcd, tegra_xhci_quirks);
2092 }
2093
2094 static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = {
2095         .reset = tegra_xhci_setup,
2096 };
2097
2098 static int __init tegra_xusb_init(void)
2099 {
2100         xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides);
2101
2102         return platform_driver_register(&tegra_xusb_driver);
2103 }
2104 module_init(tegra_xusb_init);
2105
2106 static void __exit tegra_xusb_exit(void)
2107 {
2108         platform_driver_unregister(&tegra_xusb_driver);
2109 }
2110 module_exit(tegra_xusb_exit);
2111
2112 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
2113 MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver");
2114 MODULE_LICENSE("GPL v2");