1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
12 * Ring initialization rules:
13 * 1. Each segment is initialized to zero, except for link TRBs.
14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
15 * Consumer Cycle State (CCS), depending on ring function.
16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
18 * Ring behavior rules:
19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
20 * least one free TRB in the ring. This is useful if you want to turn that
21 * into a link TRB and expand the ring.
22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
23 * link TRB, then load the pointer with the address in the link TRB. If the
24 * link TRB had its toggle bit set, you may need to update the ring cycle
25 * state (see cycle bit rules). You may have to do this multiple times
26 * until you reach a non-link TRB.
27 * 3. A ring is full if enqueue++ (for the definition of increment above)
28 * equals the dequeue pointer.
31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
32 * in a link TRB, it must toggle the ring cycle state.
33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
34 * in a link TRB, it must toggle the ring cycle state.
37 * 1. Check if ring is full before you enqueue.
38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
39 * Update enqueue pointer between each write (which may update the ring
41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
42 * and endpoint rings. If HC is the producer for the event ring,
43 * and it generates an interrupt according to interrupt modulation rules.
46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
47 * the TRB is owned by the consumer.
48 * 2. Update dequeue pointer (which may update the ring cycle state) and
49 * continue processing TRBs until you reach a TRB which is not owned by you.
50 * 3. Notify the producer. SW is the consumer for the event ring, and it
51 * updates event ring dequeue pointer. HC is the consumer for the command and
52 * endpoint rings; it generates events on the event ring for these.
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
57 #include <linux/dma-mapping.h>
59 #include "xhci-trace.h"
61 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
62 u32 field1, u32 field2,
63 u32 field3, u32 field4, bool command_must_succeed);
66 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
69 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
72 unsigned long segment_offset;
74 if (!seg || !trb || trb < seg->trbs)
77 segment_offset = trb - seg->trbs;
78 if (segment_offset >= TRBS_PER_SEGMENT)
80 return seg->dma + (segment_offset * sizeof(*trb));
83 static bool trb_is_noop(union xhci_trb *trb)
85 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
88 static bool trb_is_link(union xhci_trb *trb)
90 return TRB_TYPE_LINK_LE32(trb->link.control);
93 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
95 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
98 static bool last_trb_on_ring(struct xhci_ring *ring,
99 struct xhci_segment *seg, union xhci_trb *trb)
101 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
104 static bool link_trb_toggles_cycle(union xhci_trb *trb)
106 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
109 static bool last_td_in_urb(struct xhci_td *td)
111 struct urb_priv *urb_priv = td->urb->hcpriv;
113 return urb_priv->num_tds_done == urb_priv->num_tds;
116 static void inc_td_cnt(struct urb *urb)
118 struct urb_priv *urb_priv = urb->hcpriv;
120 urb_priv->num_tds_done++;
123 static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
125 if (trb_is_link(trb)) {
126 /* unchain chained link TRBs */
127 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
129 trb->generic.field[0] = 0;
130 trb->generic.field[1] = 0;
131 trb->generic.field[2] = 0;
132 /* Preserve only the cycle bit of this TRB */
133 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
134 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
138 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
139 * TRB is in a new segment. This does not skip over link TRBs, and it does not
140 * effect the ring dequeue or enqueue pointers.
142 static void next_trb(struct xhci_hcd *xhci,
143 struct xhci_ring *ring,
144 struct xhci_segment **seg,
145 union xhci_trb **trb)
147 if (trb_is_link(*trb)) {
149 *trb = ((*seg)->trbs);
156 * See Cycle bit rules. SW is the consumer for the event ring only.
158 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
160 unsigned int link_trb_count = 0;
162 /* event ring doesn't have link trbs, check for last trb */
163 if (ring->type == TYPE_EVENT) {
164 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
168 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
169 ring->cycle_state ^= 1;
170 ring->deq_seg = ring->deq_seg->next;
171 ring->dequeue = ring->deq_seg->trbs;
175 /* All other rings have link trbs */
176 if (!trb_is_link(ring->dequeue)) {
177 if (last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
178 xhci_warn(xhci, "Missing link TRB at end of segment\n");
181 ring->num_trbs_free++;
185 while (trb_is_link(ring->dequeue)) {
186 ring->deq_seg = ring->deq_seg->next;
187 ring->dequeue = ring->deq_seg->trbs;
189 if (link_trb_count++ > ring->num_segs) {
190 xhci_warn(xhci, "Ring is an endless link TRB loop\n");
195 trace_xhci_inc_deq(ring);
201 * See Cycle bit rules. SW is the consumer for the event ring only.
203 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
204 * chain bit is set), then set the chain bit in all the following link TRBs.
205 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
206 * have their chain bit cleared (so that each Link TRB is a separate TD).
208 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
209 * set, but other sections talk about dealing with the chain bit set. This was
210 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
211 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
213 * @more_trbs_coming: Will you enqueue more TRBs before calling
214 * prepare_transfer()?
216 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
217 bool more_trbs_coming)
220 union xhci_trb *next;
221 unsigned int link_trb_count = 0;
223 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
224 /* If this is not event ring, there is one less usable TRB */
225 if (!trb_is_link(ring->enqueue))
226 ring->num_trbs_free--;
228 if (last_trb_on_seg(ring->enq_seg, ring->enqueue)) {
229 xhci_err(xhci, "Tried to move enqueue past ring segment\n");
233 next = ++(ring->enqueue);
235 /* Update the dequeue pointer further if that was a link TRB */
236 while (trb_is_link(next)) {
239 * If the caller doesn't plan on enqueueing more TDs before
240 * ringing the doorbell, then we don't want to give the link TRB
241 * to the hardware just yet. We'll give the link TRB back in
242 * prepare_ring() just before we enqueue the TD at the top of
245 if (!chain && !more_trbs_coming)
248 /* If we're not dealing with 0.95 hardware or isoc rings on
249 * AMD 0.96 host, carry over the chain bit of the previous TRB
250 * (which may mean the chain bit is cleared).
252 if (!(ring->type == TYPE_ISOC &&
253 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
254 !xhci_link_trb_quirk(xhci)) {
255 next->link.control &= cpu_to_le32(~TRB_CHAIN);
256 next->link.control |= cpu_to_le32(chain);
258 /* Give this link TRB to the hardware */
260 next->link.control ^= cpu_to_le32(TRB_CYCLE);
262 /* Toggle the cycle bit after the last ring segment. */
263 if (link_trb_toggles_cycle(next))
264 ring->cycle_state ^= 1;
266 ring->enq_seg = ring->enq_seg->next;
267 ring->enqueue = ring->enq_seg->trbs;
268 next = ring->enqueue;
270 if (link_trb_count++ > ring->num_segs) {
271 xhci_warn(xhci, "%s: Ring link TRB loop\n", __func__);
276 trace_xhci_inc_enq(ring);
280 * Check to see if there's room to enqueue num_trbs on the ring and make sure
281 * enqueue pointer will not advance into dequeue segment. See rules above.
283 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
284 unsigned int num_trbs)
286 int num_trbs_in_deq_seg;
288 if (ring->num_trbs_free < num_trbs)
291 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
292 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
293 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
300 /* Ring the host controller doorbell after placing a command on the ring */
301 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
303 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
306 xhci_dbg(xhci, "// Ding dong!\n");
308 trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST);
310 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
311 /* Flush PCI posted writes */
312 readl(&xhci->dba->doorbell[0]);
315 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
317 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
320 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
322 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
327 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
328 * If there are other commands waiting then restart the ring and kick the timer.
329 * This must be called with command ring stopped and xhci->lock held.
331 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
332 struct xhci_command *cur_cmd)
334 struct xhci_command *i_cmd;
336 /* Turn all aborted commands in list to no-ops, then restart */
337 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
339 if (i_cmd->status != COMP_COMMAND_ABORTED)
342 i_cmd->status = COMP_COMMAND_RING_STOPPED;
344 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
347 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
350 * caller waiting for completion is called when command
351 * completion event is received for these no-op commands
355 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
357 /* ring command ring doorbell to restart the command ring */
358 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
359 !(xhci->xhc_state & XHCI_STATE_DYING)) {
360 xhci->current_cmd = cur_cmd;
361 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
362 xhci_ring_cmd_db(xhci);
366 /* Must be called with xhci->lock held, releases and aquires lock back */
367 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
372 xhci_dbg(xhci, "Abort command ring\n");
374 reinit_completion(&xhci->cmd_ring_stop_completion);
376 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
377 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
378 &xhci->op_regs->cmd_ring);
380 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
381 * completion of the Command Abort operation. If CRR is not negated in 5
382 * seconds then driver handles it as if host died (-ENODEV).
383 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
384 * and try to recover a -ETIMEDOUT with a host controller reset.
386 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
387 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
389 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
395 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
396 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
397 * but the completion event in never sent. Wait 2 secs (arbitrary
398 * number) to handle those cases after negation of CMD_RING_RUNNING.
400 spin_unlock_irqrestore(&xhci->lock, flags);
401 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
402 msecs_to_jiffies(2000));
403 spin_lock_irqsave(&xhci->lock, flags);
405 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
406 xhci_cleanup_command_queue(xhci);
408 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
413 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
414 unsigned int slot_id,
415 unsigned int ep_index,
416 unsigned int stream_id)
418 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
419 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
420 unsigned int ep_state = ep->ep_state;
422 /* Don't ring the doorbell for this endpoint if there are pending
423 * cancellations because we don't want to interrupt processing.
424 * We don't want to restart any stream rings if there's a set dequeue
425 * pointer command pending because the device can choose to start any
426 * stream once the endpoint is on the HW schedule.
428 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
429 (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT))
432 trace_xhci_ring_ep_doorbell(slot_id, DB_VALUE(ep_index, stream_id));
434 writel(DB_VALUE(ep_index, stream_id), db_addr);
435 /* flush the write */
439 /* Ring the doorbell for any rings with pending URBs */
440 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
441 unsigned int slot_id,
442 unsigned int ep_index)
444 unsigned int stream_id;
445 struct xhci_virt_ep *ep;
447 ep = &xhci->devs[slot_id]->eps[ep_index];
449 /* A ring has pending URBs if its TD list is not empty */
450 if (!(ep->ep_state & EP_HAS_STREAMS)) {
451 if (ep->ring && !(list_empty(&ep->ring->td_list)))
452 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
456 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
458 struct xhci_stream_info *stream_info = ep->stream_info;
459 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
460 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
465 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
466 unsigned int slot_id,
467 unsigned int ep_index)
469 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
472 static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci,
473 unsigned int slot_id,
474 unsigned int ep_index)
476 if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) {
477 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
480 if (ep_index >= EP_CTX_PER_DEV) {
481 xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index);
484 if (!xhci->devs[slot_id]) {
485 xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id);
489 return &xhci->devs[slot_id]->eps[ep_index];
492 static struct xhci_ring *xhci_virt_ep_to_ring(struct xhci_hcd *xhci,
493 struct xhci_virt_ep *ep,
494 unsigned int stream_id)
496 /* common case, no streams */
497 if (!(ep->ep_state & EP_HAS_STREAMS))
500 if (!ep->stream_info)
503 if (stream_id == 0 || stream_id >= ep->stream_info->num_streams) {
504 xhci_warn(xhci, "Invalid stream_id %u request for slot_id %u ep_index %u\n",
505 stream_id, ep->vdev->slot_id, ep->ep_index);
509 return ep->stream_info->stream_rings[stream_id];
512 /* Get the right ring for the given slot_id, ep_index and stream_id.
513 * If the endpoint supports streams, boundary check the URB's stream ID.
514 * If the endpoint doesn't support streams, return the singular endpoint ring.
516 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
517 unsigned int slot_id, unsigned int ep_index,
518 unsigned int stream_id)
520 struct xhci_virt_ep *ep;
522 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
526 return xhci_virt_ep_to_ring(xhci, ep, stream_id);
531 * Get the hw dequeue pointer xHC stopped on, either directly from the
532 * endpoint context, or if streams are in use from the stream context.
533 * The returned hw_dequeue contains the lowest four bits with cycle state
534 * and possbile stream context type.
536 static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
537 unsigned int ep_index, unsigned int stream_id)
539 struct xhci_ep_ctx *ep_ctx;
540 struct xhci_stream_ctx *st_ctx;
541 struct xhci_virt_ep *ep;
543 ep = &vdev->eps[ep_index];
545 if (ep->ep_state & EP_HAS_STREAMS) {
546 st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
547 return le64_to_cpu(st_ctx->stream_ring);
549 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
550 return le64_to_cpu(ep_ctx->deq);
553 static int xhci_move_dequeue_past_td(struct xhci_hcd *xhci,
554 unsigned int slot_id, unsigned int ep_index,
555 unsigned int stream_id, struct xhci_td *td)
557 struct xhci_virt_device *dev = xhci->devs[slot_id];
558 struct xhci_virt_ep *ep = &dev->eps[ep_index];
559 struct xhci_ring *ep_ring;
560 struct xhci_command *cmd;
561 struct xhci_segment *new_seg;
562 union xhci_trb *new_deq;
566 bool cycle_found = false;
567 bool td_last_trb_found = false;
571 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
572 ep_index, stream_id);
574 xhci_warn(xhci, "WARN can't find new dequeue, invalid stream ID %u\n",
579 * A cancelled TD can complete with a stall if HW cached the trb.
580 * In this case driver can't find td, but if the ring is empty we
581 * can move the dequeue pointer to the current enqueue position.
582 * We shouldn't hit this anymore as cached cancelled TRBs are given back
583 * after clearing the cache, but be on the safe side and keep it anyway
586 if (list_empty(&ep_ring->td_list)) {
587 new_seg = ep_ring->enq_seg;
588 new_deq = ep_ring->enqueue;
589 new_cycle = ep_ring->cycle_state;
590 xhci_dbg(xhci, "ep ring empty, Set new dequeue = enqueue");
593 xhci_warn(xhci, "Can't find new dequeue state, missing td\n");
598 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
599 new_seg = ep_ring->deq_seg;
600 new_deq = ep_ring->dequeue;
601 new_cycle = hw_dequeue & 0x1;
604 * We want to find the pointer, segment and cycle state of the new trb
605 * (the one after current TD's last_trb). We know the cycle state at
606 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
610 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
611 == (dma_addr_t)(hw_dequeue & ~0xf)) {
613 if (td_last_trb_found)
616 if (new_deq == td->last_trb)
617 td_last_trb_found = true;
619 if (cycle_found && trb_is_link(new_deq) &&
620 link_trb_toggles_cycle(new_deq))
623 next_trb(xhci, ep_ring, &new_seg, &new_deq);
625 /* Search wrapped around, bail out */
626 if (new_deq == ep->ring->dequeue) {
627 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
631 } while (!cycle_found || !td_last_trb_found);
635 /* Don't update the ring cycle state for the producer (us). */
636 addr = xhci_trb_virt_to_dma(new_seg, new_deq);
638 xhci_warn(xhci, "Can't find dma of new dequeue ptr\n");
639 xhci_warn(xhci, "deq seg = %p, deq ptr = %p\n", new_seg, new_deq);
643 if ((ep->ep_state & SET_DEQ_PENDING)) {
644 xhci_warn(xhci, "Set TR Deq already pending, don't submit for 0x%pad\n",
649 /* This function gets called from contexts where it cannot sleep */
650 cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
652 xhci_warn(xhci, "Can't alloc Set TR Deq cmd 0x%pad\n", &addr);
657 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
658 ret = queue_command(xhci, cmd,
659 lower_32_bits(addr) | trb_sct | new_cycle,
661 STREAM_ID_FOR_TRB(stream_id), SLOT_ID_FOR_TRB(slot_id) |
662 EP_ID_FOR_TRB(ep_index) | TRB_TYPE(TRB_SET_DEQ), false);
664 xhci_free_command(xhci, cmd);
667 ep->queued_deq_seg = new_seg;
668 ep->queued_deq_ptr = new_deq;
670 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
671 "Set TR Deq ptr 0x%llx, cycle %u\n", addr, new_cycle);
673 /* Stop the TD queueing code from ringing the doorbell until
674 * this command completes. The HC won't set the dequeue pointer
675 * if the ring is running, and ringing the doorbell starts the
678 ep->ep_state |= SET_DEQ_PENDING;
679 xhci_ring_cmd_db(xhci);
683 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
684 * (The last TRB actually points to the ring enqueue pointer, which is not part
685 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
687 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
688 struct xhci_td *td, bool flip_cycle)
690 struct xhci_segment *seg = td->start_seg;
691 union xhci_trb *trb = td->first_trb;
694 trb_to_noop(trb, TRB_TR_NOOP);
696 /* flip cycle if asked to */
697 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
698 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
700 if (trb == td->last_trb)
703 next_trb(xhci, ep_ring, &seg, &trb);
707 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
708 struct xhci_virt_ep *ep)
710 ep->ep_state &= ~EP_STOP_CMD_PENDING;
711 /* Can't del_timer_sync in interrupt */
712 del_timer(&ep->stop_cmd_timer);
716 * Must be called with xhci->lock held in interrupt context,
717 * releases and re-acquires xhci->lock
719 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
720 struct xhci_td *cur_td, int status)
722 struct urb *urb = cur_td->urb;
723 struct urb_priv *urb_priv = urb->hcpriv;
724 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
726 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
727 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
728 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
729 if (xhci->quirks & XHCI_AMD_PLL_FIX)
730 usb_amd_quirk_pll_enable();
733 xhci_urb_free_priv(urb_priv);
734 usb_hcd_unlink_urb_from_ep(hcd, urb);
735 trace_xhci_urb_giveback(urb);
736 usb_hcd_giveback_urb(hcd, urb, status);
739 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
740 struct xhci_ring *ring, struct xhci_td *td)
742 struct device *dev = xhci_to_hcd(xhci)->self.controller;
743 struct xhci_segment *seg = td->bounce_seg;
744 struct urb *urb = td->urb;
747 if (!ring || !seg || !urb)
750 if (usb_urb_dir_out(urb)) {
751 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
756 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
758 /* for in tranfers we need to copy the data from bounce to sg */
760 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
761 seg->bounce_len, seg->bounce_offs);
762 if (len != seg->bounce_len)
763 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
764 len, seg->bounce_len);
766 memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf,
770 seg->bounce_offs = 0;
773 static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
774 struct xhci_ring *ep_ring, int status)
776 struct urb *urb = NULL;
778 /* Clean up the endpoint's TD list */
781 /* if a bounce buffer was used to align this td then unmap it */
782 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
784 /* Do one last check of the actual transfer length.
785 * If the host controller said we transferred more data than the buffer
786 * length, urb->actual_length will be a very big number (since it's
787 * unsigned). Play it safe and say we didn't transfer anything.
789 if (urb->actual_length > urb->transfer_buffer_length) {
790 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
791 urb->transfer_buffer_length, urb->actual_length);
792 urb->actual_length = 0;
795 /* TD might be removed from td_list if we are giving back a cancelled URB */
796 if (!list_empty(&td->td_list))
797 list_del_init(&td->td_list);
798 /* Giving back a cancelled URB, or if a slated TD completed anyway */
799 if (!list_empty(&td->cancelled_td_list))
800 list_del_init(&td->cancelled_td_list);
803 /* Giveback the urb when all the tds are completed */
804 if (last_td_in_urb(td)) {
805 if ((urb->actual_length != urb->transfer_buffer_length &&
806 (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
807 (status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
808 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
809 urb, urb->actual_length,
810 urb->transfer_buffer_length, status);
812 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
813 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
815 xhci_giveback_urb_in_irq(xhci, td, status);
822 /* Complete the cancelled URBs we unlinked from td_list. */
823 static void xhci_giveback_invalidated_tds(struct xhci_virt_ep *ep)
825 struct xhci_ring *ring;
826 struct xhci_td *td, *tmp_td;
828 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
831 ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
833 if (td->cancel_status == TD_CLEARED)
834 xhci_td_cleanup(ep->xhci, td, ring, td->status);
836 if (ep->xhci->xhc_state & XHCI_STATE_DYING)
841 static int xhci_reset_halted_ep(struct xhci_hcd *xhci, unsigned int slot_id,
842 unsigned int ep_index, enum xhci_ep_reset_type reset_type)
844 struct xhci_command *command;
847 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
853 ret = xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
856 xhci_err(xhci, "ERROR queuing reset endpoint for slot %d ep_index %d, %d\n",
857 slot_id, ep_index, ret);
861 static int xhci_handle_halted_endpoint(struct xhci_hcd *xhci,
862 struct xhci_virt_ep *ep, unsigned int stream_id,
864 enum xhci_ep_reset_type reset_type)
866 unsigned int slot_id = ep->vdev->slot_id;
870 * Avoid resetting endpoint if link is inactive. Can cause host hang.
871 * Device will be reset soon to recover the link so don't do anything
873 if (ep->vdev->flags & VDEV_PORT_ERROR)
876 /* add td to cancelled list and let reset ep handler take care of it */
877 if (reset_type == EP_HARD_RESET) {
878 ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
879 if (td && list_empty(&td->cancelled_td_list)) {
880 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
881 td->cancel_status = TD_HALTED;
885 if (ep->ep_state & EP_HALTED) {
886 xhci_dbg(xhci, "Reset ep command already pending\n");
890 err = xhci_reset_halted_ep(xhci, slot_id, ep->ep_index, reset_type);
894 ep->ep_state |= EP_HALTED;
896 xhci_ring_cmd_db(xhci);
902 * Fix up the ep ring first, so HW stops executing cancelled TDs.
903 * We have the xHCI lock, so nothing can modify this list until we drop it.
904 * We're also in the event handler, so we can't get re-interrupted if another
905 * Stop Endpoint command completes.
907 * only call this when ring is not in a running state
910 static int xhci_invalidate_cancelled_tds(struct xhci_virt_ep *ep)
912 struct xhci_hcd *xhci;
913 struct xhci_td *td = NULL;
914 struct xhci_td *tmp_td = NULL;
915 struct xhci_td *cached_td = NULL;
916 struct xhci_ring *ring;
918 unsigned int slot_id = ep->vdev->slot_id;
923 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
924 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
925 "Removing canceled TD starting at 0x%llx (dma).",
926 (unsigned long long)xhci_trb_virt_to_dma(
927 td->start_seg, td->first_trb));
928 list_del_init(&td->td_list);
929 ring = xhci_urb_to_transfer_ring(xhci, td->urb);
931 xhci_warn(xhci, "WARN Cancelled URB %p has invalid stream ID %u.\n",
932 td->urb, td->urb->stream_id);
936 * If a ring stopped on the TD we need to cancel then we have to
937 * move the xHC endpoint ring dequeue pointer past this TD.
938 * Rings halted due to STALL may show hw_deq is past the stalled
939 * TD, but still require a set TR Deq command to flush xHC cache.
941 hw_deq = xhci_get_hw_deq(xhci, ep->vdev, ep->ep_index,
945 if (td->cancel_status == TD_HALTED) {
947 } else if (trb_in_td(xhci, td->start_seg, td->first_trb,
948 td->last_trb, hw_deq, false)) {
949 switch (td->cancel_status) {
950 case TD_CLEARED: /* TD is already no-op */
951 case TD_CLEARING_CACHE: /* set TR deq command already queued */
953 case TD_DIRTY: /* TD is cached, clear it */
955 /* FIXME stream case, several stopped rings */
960 td_to_noop(xhci, ring, td, false);
961 td->cancel_status = TD_CLEARED;
965 cached_td->cancel_status = TD_CLEARING_CACHE;
967 err = xhci_move_dequeue_past_td(xhci, slot_id, ep->ep_index,
968 cached_td->urb->stream_id,
970 /* Failed to move past cached td, try just setting it noop */
972 td_to_noop(xhci, ring, cached_td, false);
973 cached_td->cancel_status = TD_CLEARED;
981 * Returns the TD the endpoint ring halted on.
982 * Only call for non-running rings without streams.
984 static struct xhci_td *find_halted_td(struct xhci_virt_ep *ep)
989 if (!list_empty(&ep->ring->td_list)) { /* Not streams compatible */
990 hw_deq = xhci_get_hw_deq(ep->xhci, ep->vdev, ep->ep_index, 0);
992 td = list_first_entry(&ep->ring->td_list, struct xhci_td, td_list);
993 if (trb_in_td(ep->xhci, td->start_seg, td->first_trb,
994 td->last_trb, hw_deq, false))
1001 * When we get a command completion for a Stop Endpoint Command, we need to
1002 * unlink any cancelled TDs from the ring. There are two ways to do that:
1004 * 1. If the HW was in the middle of processing the TD that needs to be
1005 * cancelled, then we must move the ring's dequeue pointer past the last TRB
1006 * in the TD with a Set Dequeue Pointer Command.
1007 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
1008 * bit cleared) so that the HW will skip over them.
1010 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
1011 union xhci_trb *trb, u32 comp_code)
1013 unsigned int ep_index;
1014 struct xhci_virt_ep *ep;
1015 struct xhci_ep_ctx *ep_ctx;
1016 struct xhci_td *td = NULL;
1017 enum xhci_ep_reset_type reset_type;
1018 struct xhci_command *command;
1021 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
1022 if (!xhci->devs[slot_id])
1023 xhci_warn(xhci, "Stop endpoint command completion for disabled slot %u\n",
1028 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1029 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1033 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1035 trace_xhci_handle_cmd_stop_ep(ep_ctx);
1037 if (comp_code == COMP_CONTEXT_STATE_ERROR) {
1039 * If stop endpoint command raced with a halting endpoint we need to
1040 * reset the host side endpoint first.
1041 * If the TD we halted on isn't cancelled the TD should be given back
1042 * with a proper error code, and the ring dequeue moved past the TD.
1043 * If streams case we can't find hw_deq, or the TD we halted on so do a
1046 * Proper error code is unknown here, it would be -EPIPE if device side
1047 * of enadpoit halted (aka STALL), and -EPROTO if not (transaction error)
1048 * We use -EPROTO, if device is stalled it should return a stall error on
1049 * next transfer, which then will return -EPIPE, and device side stall is
1050 * noted and cleared by class driver.
1052 switch (GET_EP_CTX_STATE(ep_ctx)) {
1053 case EP_STATE_HALTED:
1054 xhci_dbg(xhci, "Stop ep completion raced with stall, reset ep\n");
1055 if (ep->ep_state & EP_HAS_STREAMS) {
1056 reset_type = EP_SOFT_RESET;
1058 reset_type = EP_HARD_RESET;
1059 td = find_halted_td(ep);
1061 td->status = -EPROTO;
1063 /* reset ep, reset handler cleans up cancelled tds */
1064 err = xhci_handle_halted_endpoint(xhci, ep, 0, td,
1068 xhci_stop_watchdog_timer_in_irq(xhci, ep);
1070 case EP_STATE_RUNNING:
1071 /* Race, HW handled stop ep cmd before ep was running */
1072 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1074 xhci_stop_watchdog_timer_in_irq(xhci, ep);
1076 mod_timer(&ep->stop_cmd_timer,
1077 jiffies + XHCI_STOP_EP_CMD_TIMEOUT * HZ);
1078 xhci_queue_stop_endpoint(xhci, command, slot_id, ep_index, 0);
1079 xhci_ring_cmd_db(xhci);
1086 /* will queue a set TR deq if stopped on a cancelled, uncleared TD */
1087 xhci_invalidate_cancelled_tds(ep);
1088 xhci_stop_watchdog_timer_in_irq(xhci, ep);
1090 /* Otherwise ring the doorbell(s) to restart queued transfers */
1091 xhci_giveback_invalidated_tds(ep);
1092 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1095 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
1097 struct xhci_td *cur_td;
1098 struct xhci_td *tmp;
1100 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
1101 list_del_init(&cur_td->td_list);
1103 if (!list_empty(&cur_td->cancelled_td_list))
1104 list_del_init(&cur_td->cancelled_td_list);
1106 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
1108 inc_td_cnt(cur_td->urb);
1109 if (last_td_in_urb(cur_td))
1110 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1114 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
1115 int slot_id, int ep_index)
1117 struct xhci_td *cur_td;
1118 struct xhci_td *tmp;
1119 struct xhci_virt_ep *ep;
1120 struct xhci_ring *ring;
1122 ep = &xhci->devs[slot_id]->eps[ep_index];
1123 if ((ep->ep_state & EP_HAS_STREAMS) ||
1124 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
1127 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
1129 ring = ep->stream_info->stream_rings[stream_id];
1133 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1134 "Killing URBs for slot ID %u, ep index %u, stream %u",
1135 slot_id, ep_index, stream_id);
1136 xhci_kill_ring_urbs(xhci, ring);
1142 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1143 "Killing URBs for slot ID %u, ep index %u",
1145 xhci_kill_ring_urbs(xhci, ring);
1148 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
1149 cancelled_td_list) {
1150 list_del_init(&cur_td->cancelled_td_list);
1151 inc_td_cnt(cur_td->urb);
1153 if (last_td_in_urb(cur_td))
1154 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1159 * host controller died, register read returns 0xffffffff
1160 * Complete pending commands, mark them ABORTED.
1161 * URBs need to be given back as usb core might be waiting with device locks
1162 * held for the URBs to finish during device disconnect, blocking host remove.
1164 * Call with xhci->lock held.
1165 * lock is relased and re-acquired while giving back urb.
1167 void xhci_hc_died(struct xhci_hcd *xhci)
1171 if (xhci->xhc_state & XHCI_STATE_DYING)
1174 xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
1175 xhci->xhc_state |= XHCI_STATE_DYING;
1177 xhci_cleanup_command_queue(xhci);
1179 /* return any pending urbs, remove may be waiting for them */
1180 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
1183 for (j = 0; j < 31; j++)
1184 xhci_kill_endpoint_urbs(xhci, i, j);
1187 /* inform usb core hc died if PCI remove isn't already handling it */
1188 if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
1189 usb_hc_died(xhci_to_hcd(xhci));
1192 /* Watchdog timer function for when a stop endpoint command fails to complete.
1193 * In this case, we assume the host controller is broken or dying or dead. The
1194 * host may still be completing some other events, so we have to be careful to
1195 * let the event ring handler and the URB dequeueing/enqueueing functions know
1196 * through xhci->state.
1198 * The timer may also fire if the host takes a very long time to respond to the
1199 * command, and the stop endpoint command completion handler cannot delete the
1200 * timer before the timer function is called. Another endpoint cancellation may
1201 * sneak in before the timer function can grab the lock, and that may queue
1202 * another stop endpoint command and add the timer back. So we cannot use a
1203 * simple flag to say whether there is a pending stop endpoint command for a
1204 * particular endpoint.
1206 * Instead we use a combination of that flag and checking if a new timer is
1209 void xhci_stop_endpoint_command_watchdog(struct timer_list *t)
1211 struct xhci_virt_ep *ep = from_timer(ep, t, stop_cmd_timer);
1212 struct xhci_hcd *xhci = ep->xhci;
1213 unsigned long flags;
1215 char str[XHCI_MSG_MAX];
1217 spin_lock_irqsave(&xhci->lock, flags);
1219 /* bail out if cmd completed but raced with stop ep watchdog timer.*/
1220 if (!(ep->ep_state & EP_STOP_CMD_PENDING) ||
1221 timer_pending(&ep->stop_cmd_timer)) {
1222 spin_unlock_irqrestore(&xhci->lock, flags);
1223 xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit");
1226 usbsts = readl(&xhci->op_regs->status);
1228 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
1229 xhci_warn(xhci, "USBSTS:%s\n", xhci_decode_usbsts(str, usbsts));
1231 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1236 * handle a stop endpoint cmd timeout as if host died (-ENODEV).
1237 * In the future we could distinguish between -ENODEV and -ETIMEDOUT
1238 * and try to recover a -ETIMEDOUT with a host controller reset
1242 spin_unlock_irqrestore(&xhci->lock, flags);
1243 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1244 "xHCI host controller is dead.");
1247 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1248 struct xhci_virt_device *dev,
1249 struct xhci_ring *ep_ring,
1250 unsigned int ep_index)
1252 union xhci_trb *dequeue_temp;
1253 int num_trbs_free_temp;
1254 bool revert = false;
1256 num_trbs_free_temp = ep_ring->num_trbs_free;
1257 dequeue_temp = ep_ring->dequeue;
1259 /* If we get two back-to-back stalls, and the first stalled transfer
1260 * ends just before a link TRB, the dequeue pointer will be left on
1261 * the link TRB by the code in the while loop. So we have to update
1262 * the dequeue pointer one segment further, or we'll jump off
1263 * the segment into la-la-land.
1265 if (trb_is_link(ep_ring->dequeue)) {
1266 ep_ring->deq_seg = ep_ring->deq_seg->next;
1267 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1270 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1271 /* We have more usable TRBs */
1272 ep_ring->num_trbs_free++;
1274 if (trb_is_link(ep_ring->dequeue)) {
1275 if (ep_ring->dequeue ==
1276 dev->eps[ep_index].queued_deq_ptr)
1278 ep_ring->deq_seg = ep_ring->deq_seg->next;
1279 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1281 if (ep_ring->dequeue == dequeue_temp) {
1288 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1289 ep_ring->num_trbs_free = num_trbs_free_temp;
1294 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1295 * we need to clear the set deq pending flag in the endpoint ring state, so that
1296 * the TD queueing code can ring the doorbell again. We also need to ring the
1297 * endpoint doorbell to restart the ring, but only if there aren't more
1298 * cancellations pending.
1300 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1301 union xhci_trb *trb, u32 cmd_comp_code)
1303 unsigned int ep_index;
1304 unsigned int stream_id;
1305 struct xhci_ring *ep_ring;
1306 struct xhci_virt_ep *ep;
1307 struct xhci_ep_ctx *ep_ctx;
1308 struct xhci_slot_ctx *slot_ctx;
1309 struct xhci_td *td, *tmp_td;
1311 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1312 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1313 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1317 ep_ring = xhci_virt_ep_to_ring(xhci, ep, stream_id);
1319 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1321 /* XXX: Harmless??? */
1325 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1326 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
1327 trace_xhci_handle_cmd_set_deq(slot_ctx);
1328 trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1330 if (cmd_comp_code != COMP_SUCCESS) {
1331 unsigned int ep_state;
1332 unsigned int slot_state;
1334 switch (cmd_comp_code) {
1335 case COMP_TRB_ERROR:
1336 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1338 case COMP_CONTEXT_STATE_ERROR:
1339 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1340 ep_state = GET_EP_CTX_STATE(ep_ctx);
1341 slot_state = le32_to_cpu(slot_ctx->dev_state);
1342 slot_state = GET_SLOT_STATE(slot_state);
1343 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1344 "Slot state = %u, EP state = %u",
1345 slot_state, ep_state);
1347 case COMP_SLOT_NOT_ENABLED_ERROR:
1348 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1352 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1356 /* OK what do we do now? The endpoint state is hosed, and we
1357 * should never get to this point if the synchronization between
1358 * queueing, and endpoint state are correct. This might happen
1359 * if the device gets disconnected after we've finished
1360 * cancelling URBs, which might not be an error...
1364 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1365 if (ep->ep_state & EP_HAS_STREAMS) {
1366 struct xhci_stream_ctx *ctx =
1367 &ep->stream_info->stream_ctx_array[stream_id];
1368 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1370 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1372 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1373 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1374 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1375 ep->queued_deq_ptr) == deq) {
1376 /* Update the ring's dequeue segment and dequeue pointer
1377 * to reflect the new position.
1379 update_ring_for_set_deq_completion(xhci, ep->vdev,
1382 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1383 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1384 ep->queued_deq_seg, ep->queued_deq_ptr);
1387 /* HW cached TDs cleared from cache, give them back */
1388 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
1389 cancelled_td_list) {
1390 ep_ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
1391 if (td->cancel_status == TD_CLEARING_CACHE) {
1392 td->cancel_status = TD_CLEARED;
1393 xhci_td_cleanup(ep->xhci, td, ep_ring, td->status);
1397 ep->ep_state &= ~SET_DEQ_PENDING;
1398 ep->queued_deq_seg = NULL;
1399 ep->queued_deq_ptr = NULL;
1400 /* Restart any rings with pending URBs */
1401 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1404 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1405 union xhci_trb *trb, u32 cmd_comp_code)
1407 struct xhci_virt_ep *ep;
1408 struct xhci_ep_ctx *ep_ctx;
1409 unsigned int ep_index;
1411 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1412 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1416 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1417 trace_xhci_handle_cmd_reset_ep(ep_ctx);
1419 /* This command will only fail if the endpoint wasn't halted,
1420 * but we don't care.
1422 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1423 "Ignoring reset ep completion code of %u", cmd_comp_code);
1425 /* Cleanup cancelled TDs as ep is stopped. May queue a Set TR Deq cmd */
1426 xhci_invalidate_cancelled_tds(ep);
1428 if (xhci->quirks & XHCI_RESET_EP_QUIRK)
1429 xhci_dbg(xhci, "Note: Removed workaround to queue config ep for this hw");
1430 /* Clear our internal halted state */
1431 ep->ep_state &= ~EP_HALTED;
1433 xhci_giveback_invalidated_tds(ep);
1435 /* if this was a soft reset, then restart */
1436 if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP)
1437 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1440 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1441 struct xhci_command *command, u32 cmd_comp_code)
1443 if (cmd_comp_code == COMP_SUCCESS)
1444 command->slot_id = slot_id;
1446 command->slot_id = 0;
1449 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1451 struct xhci_virt_device *virt_dev;
1452 struct xhci_slot_ctx *slot_ctx;
1454 virt_dev = xhci->devs[slot_id];
1458 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1459 trace_xhci_handle_cmd_disable_slot(slot_ctx);
1461 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1462 /* Delete default control endpoint resources */
1463 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1464 xhci_free_virt_device(xhci, slot_id);
1467 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1470 struct xhci_virt_device *virt_dev;
1471 struct xhci_input_control_ctx *ctrl_ctx;
1472 struct xhci_ep_ctx *ep_ctx;
1473 unsigned int ep_index;
1474 unsigned int ep_state;
1475 u32 add_flags, drop_flags;
1478 * Configure endpoint commands can come from the USB core
1479 * configuration or alt setting changes, or because the HW
1480 * needed an extra configure endpoint command after a reset
1481 * endpoint command or streams were being configured.
1482 * If the command was for a halted endpoint, the xHCI driver
1483 * is not waiting on the configure endpoint command.
1485 virt_dev = xhci->devs[slot_id];
1488 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1490 xhci_warn(xhci, "Could not get input context, bad type.\n");
1494 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1495 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1496 /* Input ctx add_flags are the endpoint index plus one */
1497 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1499 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1500 trace_xhci_handle_cmd_config_ep(ep_ctx);
1502 /* A usb_set_interface() call directly after clearing a halted
1503 * condition may race on this quirky hardware. Not worth
1504 * worrying about, since this is prototype hardware. Not sure
1505 * if this will work for streams, but streams support was
1506 * untested on this prototype.
1508 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1509 ep_index != (unsigned int) -1 &&
1510 add_flags - SLOT_FLAG == drop_flags) {
1511 ep_state = virt_dev->eps[ep_index].ep_state;
1512 if (!(ep_state & EP_HALTED))
1514 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1515 "Completed config ep cmd - "
1516 "last ep index = %d, state = %d",
1517 ep_index, ep_state);
1518 /* Clear internal halted state and restart ring(s) */
1519 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1520 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1526 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1528 struct xhci_virt_device *vdev;
1529 struct xhci_slot_ctx *slot_ctx;
1531 vdev = xhci->devs[slot_id];
1534 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1535 trace_xhci_handle_cmd_addr_dev(slot_ctx);
1538 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id)
1540 struct xhci_virt_device *vdev;
1541 struct xhci_slot_ctx *slot_ctx;
1543 vdev = xhci->devs[slot_id];
1545 xhci_warn(xhci, "Reset device command completion for disabled slot %u\n",
1549 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1550 trace_xhci_handle_cmd_reset_dev(slot_ctx);
1552 xhci_dbg(xhci, "Completed reset device command.\n");
1555 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1556 struct xhci_event_cmd *event)
1558 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1559 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1562 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1563 "NEC firmware version %2x.%02x",
1564 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1565 NEC_FW_MINOR(le32_to_cpu(event->status)));
1568 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1570 list_del(&cmd->cmd_list);
1572 if (cmd->completion) {
1573 cmd->status = status;
1574 complete(cmd->completion);
1580 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1582 struct xhci_command *cur_cmd, *tmp_cmd;
1583 xhci->current_cmd = NULL;
1584 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1585 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1588 void xhci_handle_command_timeout(struct work_struct *work)
1590 struct xhci_hcd *xhci;
1591 unsigned long flags;
1594 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1596 spin_lock_irqsave(&xhci->lock, flags);
1599 * If timeout work is pending, or current_cmd is NULL, it means we
1600 * raced with command completion. Command is handled so just return.
1602 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1603 spin_unlock_irqrestore(&xhci->lock, flags);
1606 /* mark this command to be cancelled */
1607 xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1609 /* Make sure command ring is running before aborting it */
1610 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1611 if (hw_ring_state == ~(u64)0) {
1613 goto time_out_completed;
1616 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1617 (hw_ring_state & CMD_RING_RUNNING)) {
1618 /* Prevent new doorbell, and start command abort */
1619 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1620 xhci_dbg(xhci, "Command timeout\n");
1621 xhci_abort_cmd_ring(xhci, flags);
1622 goto time_out_completed;
1625 /* host removed. Bail out */
1626 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1627 xhci_dbg(xhci, "host removed, ring start fail?\n");
1628 xhci_cleanup_command_queue(xhci);
1630 goto time_out_completed;
1633 /* command timeout on stopped ring, ring can't be aborted */
1634 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1635 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1638 spin_unlock_irqrestore(&xhci->lock, flags);
1642 static void handle_cmd_completion(struct xhci_hcd *xhci,
1643 struct xhci_event_cmd *event)
1645 unsigned int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1647 dma_addr_t cmd_dequeue_dma;
1649 union xhci_trb *cmd_trb;
1650 struct xhci_command *cmd;
1653 if (slot_id >= MAX_HC_SLOTS) {
1654 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
1658 cmd_dma = le64_to_cpu(event->cmd_trb);
1659 cmd_trb = xhci->cmd_ring->dequeue;
1661 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1663 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1666 * Check whether the completion event is for our internal kept
1669 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1671 "ERROR mismatched command completion event\n");
1675 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1677 cancel_delayed_work(&xhci->cmd_timer);
1679 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1681 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1682 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1683 complete_all(&xhci->cmd_ring_stop_completion);
1687 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1689 "Command completion event does not match command\n");
1694 * Host aborted the command ring, check if the current command was
1695 * supposed to be aborted, otherwise continue normally.
1696 * The command ring is stopped now, but the xHC will issue a Command
1697 * Ring Stopped event which will cause us to restart it.
1699 if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1700 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1701 if (cmd->status == COMP_COMMAND_ABORTED) {
1702 if (xhci->current_cmd == cmd)
1703 xhci->current_cmd = NULL;
1708 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1710 case TRB_ENABLE_SLOT:
1711 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1713 case TRB_DISABLE_SLOT:
1714 xhci_handle_cmd_disable_slot(xhci, slot_id);
1717 if (!cmd->completion)
1718 xhci_handle_cmd_config_ep(xhci, slot_id, cmd_comp_code);
1720 case TRB_EVAL_CONTEXT:
1723 xhci_handle_cmd_addr_dev(xhci, slot_id);
1726 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1727 le32_to_cpu(cmd_trb->generic.field[3])));
1728 if (!cmd->completion)
1729 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb,
1733 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1734 le32_to_cpu(cmd_trb->generic.field[3])));
1735 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1738 /* Is this an aborted command turned to NO-OP? */
1739 if (cmd->status == COMP_COMMAND_RING_STOPPED)
1740 cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1743 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1744 le32_to_cpu(cmd_trb->generic.field[3])));
1745 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1748 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1749 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1751 slot_id = TRB_TO_SLOT_ID(
1752 le32_to_cpu(cmd_trb->generic.field[3]));
1753 xhci_handle_cmd_reset_dev(xhci, slot_id);
1755 case TRB_NEC_GET_FW:
1756 xhci_handle_cmd_nec_get_fw(xhci, event);
1759 /* Skip over unknown commands on the event ring */
1760 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1764 /* restart timer if this wasn't the last command */
1765 if (!list_is_singular(&xhci->cmd_list)) {
1766 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1767 struct xhci_command, cmd_list);
1768 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1769 } else if (xhci->current_cmd == cmd) {
1770 xhci->current_cmd = NULL;
1774 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1776 inc_deq(xhci, xhci->cmd_ring);
1779 static void handle_vendor_event(struct xhci_hcd *xhci,
1780 union xhci_trb *event, u32 trb_type)
1782 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1783 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1784 handle_cmd_completion(xhci, &event->event_cmd);
1787 static void handle_device_notification(struct xhci_hcd *xhci,
1788 union xhci_trb *event)
1791 struct usb_device *udev;
1793 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1794 if (!xhci->devs[slot_id]) {
1795 xhci_warn(xhci, "Device Notification event for "
1796 "unused slot %u\n", slot_id);
1800 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1802 udev = xhci->devs[slot_id]->udev;
1803 if (udev && udev->parent)
1804 usb_wakeup_notification(udev->parent, udev->portnum);
1808 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1810 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1811 * If a connection to a USB 1 device is followed by another connection
1812 * to a USB 2 device.
1814 * Reset the PHY after the USB device is disconnected if device speed
1815 * is less than HCD_USB3.
1816 * Retry the reset sequence max of 4 times checking the PLL lock status.
1819 static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1821 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1823 u32 retry_count = 4;
1826 /* Assert PHY reset */
1827 writel(0x6F, hcd->regs + 0x1048);
1829 /* De-assert the PHY reset */
1830 writel(0x7F, hcd->regs + 0x1048);
1832 pll_lock_check = readl(hcd->regs + 0x1070);
1833 } while (!(pll_lock_check & 0x1) && --retry_count);
1836 static void handle_port_status(struct xhci_hcd *xhci,
1837 union xhci_trb *event)
1839 struct usb_hcd *hcd;
1841 u32 portsc, cmd_reg;
1844 unsigned int hcd_portnum;
1845 struct xhci_bus_state *bus_state;
1846 bool bogus_port_status = false;
1847 struct xhci_port *port;
1849 /* Port status change events always have a successful completion code */
1850 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1852 "WARN: xHC returned failed port status event\n");
1854 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1855 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1857 if ((port_id <= 0) || (port_id > max_ports)) {
1858 xhci_warn(xhci, "Port change event with invalid port ID %d\n",
1860 inc_deq(xhci, xhci->event_ring);
1864 port = &xhci->hw_ports[port_id - 1];
1865 if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
1866 xhci_warn(xhci, "Port change event, no port for port ID %u\n",
1868 bogus_port_status = true;
1872 /* We might get interrupts after shared_hcd is removed */
1873 if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
1874 xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
1875 bogus_port_status = true;
1879 hcd = port->rhub->hcd;
1880 bus_state = &port->rhub->bus_state;
1881 hcd_portnum = port->hcd_portnum;
1882 portsc = readl(port->addr);
1884 xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n",
1885 hcd->self.busnum, hcd_portnum + 1, port_id, portsc);
1887 trace_xhci_handle_port_status(hcd_portnum, portsc);
1889 if (hcd->state == HC_STATE_SUSPENDED) {
1890 xhci_dbg(xhci, "resume root hub\n");
1891 usb_hcd_resume_root_hub(hcd);
1894 if (hcd->speed >= HCD_USB3 &&
1895 (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
1896 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1897 if (slot_id && xhci->devs[slot_id])
1898 xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR;
1901 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1902 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1904 cmd_reg = readl(&xhci->op_regs->command);
1905 if (!(cmd_reg & CMD_RUN)) {
1906 xhci_warn(xhci, "xHC is not running.\n");
1910 if (DEV_SUPERSPEED_ANY(portsc)) {
1911 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1912 /* Set a flag to say the port signaled remote wakeup,
1913 * so we can tell the difference between the end of
1914 * device and host initiated resume.
1916 bus_state->port_remote_wakeup |= 1 << hcd_portnum;
1917 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1918 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1919 xhci_set_link_state(xhci, port, XDEV_U0);
1920 /* Need to wait until the next link state change
1921 * indicates the device is actually in U0.
1923 bogus_port_status = true;
1925 } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
1926 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1927 bus_state->resume_done[hcd_portnum] = jiffies +
1928 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1929 set_bit(hcd_portnum, &bus_state->resuming_ports);
1930 /* Do the rest in GetPortStatus after resume time delay.
1931 * Avoid polling roothub status before that so that a
1932 * usb device auto-resume latency around ~40ms.
1934 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1935 mod_timer(&hcd->rh_timer,
1936 bus_state->resume_done[hcd_portnum]);
1937 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1938 bogus_port_status = true;
1942 if ((portsc & PORT_PLC) &&
1943 DEV_SUPERSPEED_ANY(portsc) &&
1944 ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
1945 (portsc & PORT_PLS_MASK) == XDEV_U1 ||
1946 (portsc & PORT_PLS_MASK) == XDEV_U2)) {
1947 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1948 complete(&bus_state->u3exit_done[hcd_portnum]);
1949 /* We've just brought the device into U0/1/2 through either the
1950 * Resume state after a device remote wakeup, or through the
1951 * U3Exit state after a host-initiated resume. If it's a device
1952 * initiated remote wake, don't pass up the link state change,
1953 * so the roothub behavior is consistent with external
1954 * USB 3.0 hub behavior.
1956 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1957 if (slot_id && xhci->devs[slot_id])
1958 xhci_ring_device(xhci, slot_id);
1959 if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
1960 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1961 usb_wakeup_notification(hcd->self.root_hub,
1963 bogus_port_status = true;
1969 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1970 * RExit to a disconnect state). If so, let the the driver know it's
1971 * out of the RExit state.
1973 if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 &&
1974 test_and_clear_bit(hcd_portnum,
1975 &bus_state->rexit_ports)) {
1976 complete(&bus_state->rexit_done[hcd_portnum]);
1977 bogus_port_status = true;
1981 if (hcd->speed < HCD_USB3) {
1982 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1983 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
1984 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
1985 xhci_cavium_reset_phy_quirk(xhci);
1989 /* Update event ring dequeue pointer before dropping the lock */
1990 inc_deq(xhci, xhci->event_ring);
1992 /* Don't make the USB core poll the roothub if we got a bad port status
1993 * change event. Besides, at that point we can't tell which roothub
1994 * (USB 2.0 or USB 3.0) to kick.
1996 if (bogus_port_status)
2000 * xHCI port-status-change events occur when the "or" of all the
2001 * status-change bits in the portsc register changes from 0 to 1.
2002 * New status changes won't cause an event if any other change
2003 * bits are still set. When an event occurs, switch over to
2004 * polling to avoid losing status changes.
2006 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
2007 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
2008 spin_unlock(&xhci->lock);
2009 /* Pass this up to the core */
2010 usb_hcd_poll_rh_status(hcd);
2011 spin_lock(&xhci->lock);
2015 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
2016 * at end_trb, which may be in another segment. If the suspect DMA address is a
2017 * TRB in this TD, this function returns that TRB's segment. Otherwise it
2020 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2021 struct xhci_segment *start_seg,
2022 union xhci_trb *start_trb,
2023 union xhci_trb *end_trb,
2024 dma_addr_t suspect_dma,
2027 dma_addr_t start_dma;
2028 dma_addr_t end_seg_dma;
2029 dma_addr_t end_trb_dma;
2030 struct xhci_segment *cur_seg;
2032 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
2033 cur_seg = start_seg;
2038 /* We may get an event for a Link TRB in the middle of a TD */
2039 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
2040 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
2041 /* If the end TRB isn't in this segment, this is set to 0 */
2042 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
2046 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
2047 (unsigned long long)suspect_dma,
2048 (unsigned long long)start_dma,
2049 (unsigned long long)end_trb_dma,
2050 (unsigned long long)cur_seg->dma,
2051 (unsigned long long)end_seg_dma);
2053 if (end_trb_dma > 0) {
2054 /* The end TRB is in this segment, so suspect should be here */
2055 if (start_dma <= end_trb_dma) {
2056 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
2059 /* Case for one segment with
2060 * a TD wrapped around to the top
2062 if ((suspect_dma >= start_dma &&
2063 suspect_dma <= end_seg_dma) ||
2064 (suspect_dma >= cur_seg->dma &&
2065 suspect_dma <= end_trb_dma))
2070 /* Might still be somewhere in this segment */
2071 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
2074 cur_seg = cur_seg->next;
2075 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
2076 } while (cur_seg != start_seg);
2081 static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td,
2082 struct xhci_virt_ep *ep)
2085 * As part of low/full-speed endpoint-halt processing
2086 * we must clear the TT buffer (USB 2.0 specification 11.17.5).
2088 if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) &&
2089 (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) &&
2090 !(ep->ep_state & EP_CLEARING_TT)) {
2091 ep->ep_state |= EP_CLEARING_TT;
2092 td->urb->ep->hcpriv = td->urb->dev;
2093 if (usb_hub_clear_tt_buffer(td->urb))
2094 ep->ep_state &= ~EP_CLEARING_TT;
2098 /* Check if an error has halted the endpoint ring. The class driver will
2099 * cleanup the halt for a non-default control endpoint if we indicate a stall.
2100 * However, a babble and other errors also halt the endpoint ring, and the class
2101 * driver won't clear the halt in that case, so we need to issue a Set Transfer
2102 * Ring Dequeue Pointer command manually.
2104 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
2105 struct xhci_ep_ctx *ep_ctx,
2106 unsigned int trb_comp_code)
2108 /* TRB completion codes that may require a manual halt cleanup */
2109 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
2110 trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
2111 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
2112 /* The 0.95 spec says a babbling control endpoint
2113 * is not halted. The 0.96 spec says it is. Some HW
2114 * claims to be 0.95 compliant, but it halts the control
2115 * endpoint anyway. Check if a babble halted the
2118 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
2124 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
2126 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
2127 /* Vendor defined "informational" completion code,
2128 * treat as not-an-error.
2130 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
2132 xhci_dbg(xhci, "Treating code as success.\n");
2138 static int finish_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2139 struct xhci_ring *ep_ring, struct xhci_td *td,
2142 struct xhci_ep_ctx *ep_ctx;
2144 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2146 switch (trb_comp_code) {
2147 case COMP_STOPPED_LENGTH_INVALID:
2148 case COMP_STOPPED_SHORT_PACKET:
2151 * The "Stop Endpoint" completion will take care of any
2152 * stopped TDs. A stopped TD may be restarted, so don't update
2153 * the ring dequeue pointer or take this TD off any lists yet.
2156 case COMP_USB_TRANSACTION_ERROR:
2157 case COMP_BABBLE_DETECTED_ERROR:
2158 case COMP_SPLIT_TRANSACTION_ERROR:
2160 * If endpoint context state is not halted we might be
2161 * racing with a reset endpoint command issued by a unsuccessful
2162 * stop endpoint completion (context error). In that case the
2163 * td should be on the cancelled list, and EP_HALTED flag set.
2165 * Or then it's not halted due to the 0.95 spec stating that a
2166 * babbling control endpoint should not halt. The 0.96 spec
2167 * again says it should. Some HW claims to be 0.95 compliant,
2168 * but it halts the control endpoint anyway.
2170 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_HALTED) {
2172 * If EP_HALTED is set and TD is on the cancelled list
2173 * the TD and dequeue pointer will be handled by reset
2174 * ep command completion
2176 if ((ep->ep_state & EP_HALTED) &&
2177 !list_empty(&td->cancelled_td_list)) {
2178 xhci_dbg(xhci, "Already resolving halted ep for 0x%llx\n",
2179 (unsigned long long)xhci_trb_virt_to_dma(
2180 td->start_seg, td->first_trb));
2183 /* endpoint not halted, don't reset it */
2186 /* Almost same procedure as for STALL_ERROR below */
2187 xhci_clear_hub_tt_buffer(xhci, td, ep);
2188 xhci_handle_halted_endpoint(xhci, ep, ep_ring->stream_id, td,
2191 case COMP_STALL_ERROR:
2193 * xhci internal endpoint state will go to a "halt" state for
2194 * any stall, including default control pipe protocol stall.
2195 * To clear the host side halt we need to issue a reset endpoint
2196 * command, followed by a set dequeue command to move past the
2198 * Class drivers clear the device side halt from a functional
2199 * stall later. Hub TT buffer should only be cleared for FS/LS
2200 * devices behind HS hubs for functional stalls.
2202 if (ep->ep_index != 0)
2203 xhci_clear_hub_tt_buffer(xhci, td, ep);
2205 xhci_handle_halted_endpoint(xhci, ep, ep_ring->stream_id, td,
2208 return 0; /* xhci_handle_halted_endpoint marked td cancelled */
2213 /* Update ring dequeue pointer */
2214 ep_ring->dequeue = td->last_trb;
2215 ep_ring->deq_seg = td->last_trb_seg;
2216 ep_ring->num_trbs_free += td->num_trbs - 1;
2217 inc_deq(xhci, ep_ring);
2219 return xhci_td_cleanup(xhci, td, ep_ring, td->status);
2222 /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
2223 static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
2224 union xhci_trb *stop_trb)
2227 union xhci_trb *trb = ring->dequeue;
2228 struct xhci_segment *seg = ring->deq_seg;
2230 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
2231 if (!trb_is_noop(trb) && !trb_is_link(trb))
2232 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
2238 * Process control tds, update urb status and actual_length.
2240 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2241 struct xhci_ring *ep_ring, struct xhci_td *td,
2242 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2244 struct xhci_ep_ctx *ep_ctx;
2246 u32 remaining, requested;
2249 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2250 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2251 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2252 requested = td->urb->transfer_buffer_length;
2253 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2255 switch (trb_comp_code) {
2257 if (trb_type != TRB_STATUS) {
2258 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2259 (trb_type == TRB_DATA) ? "data" : "setup");
2260 td->status = -ESHUTDOWN;
2265 case COMP_SHORT_PACKET:
2268 case COMP_STOPPED_SHORT_PACKET:
2269 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2270 td->urb->actual_length = remaining;
2272 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2277 td->urb->actual_length = 0;
2281 td->urb->actual_length = requested - remaining;
2284 td->urb->actual_length = requested;
2287 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2291 case COMP_STOPPED_LENGTH_INVALID:
2294 if (!xhci_requires_manual_halt_cleanup(xhci,
2295 ep_ctx, trb_comp_code))
2297 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2298 trb_comp_code, ep->ep_index);
2300 case COMP_STALL_ERROR:
2301 /* Did we transfer part of the data (middle) phase? */
2302 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2303 td->urb->actual_length = requested - remaining;
2304 else if (!td->urb_length_set)
2305 td->urb->actual_length = 0;
2309 /* stopped at setup stage, no data transferred */
2310 if (trb_type == TRB_SETUP)
2314 * if on data stage then update the actual_length of the URB and flag it
2315 * as set, so it won't be overwritten in the event for the last TRB.
2317 if (trb_type == TRB_DATA ||
2318 trb_type == TRB_NORMAL) {
2319 td->urb_length_set = true;
2320 td->urb->actual_length = requested - remaining;
2321 xhci_dbg(xhci, "Waiting for status stage event\n");
2325 /* at status stage */
2326 if (!td->urb_length_set)
2327 td->urb->actual_length = requested;
2330 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2334 * Process isochronous tds, update urb packet status and actual_length.
2336 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2337 struct xhci_ring *ep_ring, struct xhci_td *td,
2338 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2340 struct urb_priv *urb_priv;
2342 struct usb_iso_packet_descriptor *frame;
2344 bool sum_trbs_for_length = false;
2345 u32 remaining, requested, ep_trb_len;
2346 int short_framestatus;
2348 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2349 urb_priv = td->urb->hcpriv;
2350 idx = urb_priv->num_tds_done;
2351 frame = &td->urb->iso_frame_desc[idx];
2352 requested = frame->length;
2353 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2354 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2355 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2358 /* handle completion code */
2359 switch (trb_comp_code) {
2362 frame->status = short_framestatus;
2363 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2364 sum_trbs_for_length = true;
2369 case COMP_SHORT_PACKET:
2370 frame->status = short_framestatus;
2371 sum_trbs_for_length = true;
2373 case COMP_BANDWIDTH_OVERRUN_ERROR:
2374 frame->status = -ECOMM;
2376 case COMP_ISOCH_BUFFER_OVERRUN:
2377 case COMP_BABBLE_DETECTED_ERROR:
2378 frame->status = -EOVERFLOW;
2380 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2381 case COMP_STALL_ERROR:
2382 frame->status = -EPROTO;
2384 case COMP_USB_TRANSACTION_ERROR:
2385 frame->status = -EPROTO;
2386 if (ep_trb != td->last_trb)
2390 sum_trbs_for_length = true;
2392 case COMP_STOPPED_SHORT_PACKET:
2393 /* field normally containing residue now contains tranferred */
2394 frame->status = short_framestatus;
2395 requested = remaining;
2397 case COMP_STOPPED_LENGTH_INVALID:
2402 sum_trbs_for_length = true;
2407 if (sum_trbs_for_length)
2408 frame->actual_length = sum_trb_lengths(xhci, ep->ring, ep_trb) +
2409 ep_trb_len - remaining;
2411 frame->actual_length = requested;
2413 td->urb->actual_length += frame->actual_length;
2415 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2418 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2419 struct xhci_virt_ep *ep, int status)
2421 struct urb_priv *urb_priv;
2422 struct usb_iso_packet_descriptor *frame;
2425 urb_priv = td->urb->hcpriv;
2426 idx = urb_priv->num_tds_done;
2427 frame = &td->urb->iso_frame_desc[idx];
2429 /* The transfer is partly done. */
2430 frame->status = -EXDEV;
2432 /* calc actual length */
2433 frame->actual_length = 0;
2435 /* Update ring dequeue pointer */
2436 ep->ring->dequeue = td->last_trb;
2437 ep->ring->deq_seg = td->last_trb_seg;
2438 ep->ring->num_trbs_free += td->num_trbs - 1;
2439 inc_deq(xhci, ep->ring);
2441 return xhci_td_cleanup(xhci, td, ep->ring, status);
2445 * Process bulk and interrupt tds, update urb status and actual_length.
2447 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2448 struct xhci_ring *ep_ring, struct xhci_td *td,
2449 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2451 struct xhci_slot_ctx *slot_ctx;
2453 u32 remaining, requested, ep_trb_len;
2455 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
2456 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2457 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2458 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2459 requested = td->urb->transfer_buffer_length;
2461 switch (trb_comp_code) {
2463 ep_ring->err_count = 0;
2464 /* handle success with untransferred data as short packet */
2465 if (ep_trb != td->last_trb || remaining) {
2466 xhci_warn(xhci, "WARN Successful completion on short TX\n");
2467 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2468 td->urb->ep->desc.bEndpointAddress,
2469 requested, remaining);
2473 case COMP_SHORT_PACKET:
2474 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2475 td->urb->ep->desc.bEndpointAddress,
2476 requested, remaining);
2479 case COMP_STOPPED_SHORT_PACKET:
2480 td->urb->actual_length = remaining;
2482 case COMP_STOPPED_LENGTH_INVALID:
2483 /* stopped on ep trb with invalid length, exclude it */
2487 case COMP_USB_TRANSACTION_ERROR:
2488 if (xhci->quirks & XHCI_NO_SOFT_RETRY ||
2489 (ep_ring->err_count++ > MAX_SOFT_RETRY) ||
2490 le32_to_cpu(slot_ctx->tt_info) & TT_SLOT)
2495 xhci_handle_halted_endpoint(xhci, ep, ep_ring->stream_id, td,
2503 if (ep_trb == td->last_trb)
2504 td->urb->actual_length = requested - remaining;
2506 td->urb->actual_length =
2507 sum_trb_lengths(xhci, ep_ring, ep_trb) +
2508 ep_trb_len - remaining;
2510 if (remaining > requested) {
2511 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2513 td->urb->actual_length = 0;
2516 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2520 * If this function returns an error condition, it means it got a Transfer
2521 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2522 * At this point, the host controller is probably hosed and should be reset.
2524 static int handle_tx_event(struct xhci_hcd *xhci,
2525 struct xhci_transfer_event *event)
2527 struct xhci_virt_ep *ep;
2528 struct xhci_ring *ep_ring;
2529 unsigned int slot_id;
2531 struct xhci_td *td = NULL;
2532 dma_addr_t ep_trb_dma;
2533 struct xhci_segment *ep_seg;
2534 union xhci_trb *ep_trb;
2535 int status = -EINPROGRESS;
2536 struct xhci_ep_ctx *ep_ctx;
2537 struct list_head *tmp;
2540 bool handling_skipped_tds = false;
2542 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2543 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2544 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2545 ep_trb_dma = le64_to_cpu(event->buffer);
2547 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
2549 xhci_err(xhci, "ERROR Invalid Transfer event\n");
2553 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2554 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
2556 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2558 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2563 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2565 switch (trb_comp_code) {
2566 case COMP_STALL_ERROR:
2567 case COMP_USB_TRANSACTION_ERROR:
2568 case COMP_INVALID_STREAM_TYPE_ERROR:
2569 case COMP_INVALID_STREAM_ID_ERROR:
2570 xhci_handle_halted_endpoint(xhci, ep, 0, NULL,
2573 case COMP_RING_UNDERRUN:
2574 case COMP_RING_OVERRUN:
2575 case COMP_STOPPED_LENGTH_INVALID:
2578 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2584 /* Count current td numbers if ep->skip is set */
2586 list_for_each(tmp, &ep_ring->td_list)
2590 /* Look for common error cases */
2591 switch (trb_comp_code) {
2592 /* Skip codes that require special handling depending on
2596 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2598 if (xhci->quirks & XHCI_TRUST_TX_LENGTH ||
2599 ep_ring->last_td_was_short)
2600 trb_comp_code = COMP_SHORT_PACKET;
2602 xhci_warn_ratelimited(xhci,
2603 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2606 case COMP_SHORT_PACKET:
2608 /* Completion codes for endpoint stopped state */
2610 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2613 case COMP_STOPPED_LENGTH_INVALID:
2615 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2618 case COMP_STOPPED_SHORT_PACKET:
2620 "Stopped with short packet transfer detected for slot %u ep %u\n",
2623 /* Completion codes for endpoint halted state */
2624 case COMP_STALL_ERROR:
2625 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2629 case COMP_SPLIT_TRANSACTION_ERROR:
2630 xhci_dbg(xhci, "Split transaction error for slot %u ep %u\n",
2634 case COMP_USB_TRANSACTION_ERROR:
2635 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2639 case COMP_BABBLE_DETECTED_ERROR:
2640 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2642 status = -EOVERFLOW;
2644 /* Completion codes for endpoint error state */
2645 case COMP_TRB_ERROR:
2647 "WARN: TRB error for slot %u ep %u on endpoint\n",
2651 /* completion codes not indicating endpoint state change */
2652 case COMP_DATA_BUFFER_ERROR:
2654 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2658 case COMP_BANDWIDTH_OVERRUN_ERROR:
2660 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2663 case COMP_ISOCH_BUFFER_OVERRUN:
2665 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2668 case COMP_RING_UNDERRUN:
2670 * When the Isoch ring is empty, the xHC will generate
2671 * a Ring Overrun Event for IN Isoch endpoint or Ring
2672 * Underrun Event for OUT Isoch endpoint.
2674 xhci_dbg(xhci, "underrun event on endpoint\n");
2675 if (!list_empty(&ep_ring->td_list))
2676 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2677 "still with TDs queued?\n",
2678 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2681 case COMP_RING_OVERRUN:
2682 xhci_dbg(xhci, "overrun event on endpoint\n");
2683 if (!list_empty(&ep_ring->td_list))
2684 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2685 "still with TDs queued?\n",
2686 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2689 case COMP_MISSED_SERVICE_ERROR:
2691 * When encounter missed service error, one or more isoc tds
2692 * may be missed by xHC.
2693 * Set skip flag of the ep_ring; Complete the missed tds as
2694 * short transfer when process the ep_ring next time.
2698 "Miss service interval error for slot %u ep %u, set skip flag\n",
2701 case COMP_NO_PING_RESPONSE_ERROR:
2704 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2708 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2709 /* needs disable slot command to recover */
2711 "WARN: detect an incompatible device for slot %u ep %u",
2716 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2721 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2722 trb_comp_code, slot_id, ep_index);
2727 /* This TRB should be in the TD at the head of this ring's
2730 if (list_empty(&ep_ring->td_list)) {
2732 * Don't print wanings if it's due to a stopped endpoint
2733 * generating an extra completion event if the device
2734 * was suspended. Or, a event for the last TRB of a
2735 * short TD we already got a short event for.
2736 * The short TD is already removed from the TD list.
2739 if (!(trb_comp_code == COMP_STOPPED ||
2740 trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2741 ep_ring->last_td_was_short)) {
2742 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2743 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2748 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2751 if (trb_comp_code == COMP_STALL_ERROR ||
2752 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2754 xhci_handle_halted_endpoint(xhci, ep,
2762 /* We've skipped all the TDs on the ep ring when ep->skip set */
2763 if (ep->skip && td_num == 0) {
2765 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2770 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2775 /* Is this a TRB in the currently executing TD? */
2776 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2777 td->last_trb, ep_trb_dma, false);
2780 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2781 * is not in the current TD pointed by ep_ring->dequeue because
2782 * that the hardware dequeue pointer still at the previous TRB
2783 * of the current TD. The previous TRB maybe a Link TD or the
2784 * last TRB of the previous TD. The command completion handle
2785 * will take care the rest.
2787 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2788 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2794 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2795 /* Some host controllers give a spurious
2796 * successful event after a short transfer.
2799 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2800 ep_ring->last_td_was_short) {
2801 ep_ring->last_td_was_short = false;
2804 /* HC is busted, give up! */
2806 "ERROR Transfer event TRB DMA ptr not "
2807 "part of current TD ep_index %d "
2808 "comp_code %u\n", ep_index,
2810 trb_in_td(xhci, ep_ring->deq_seg,
2811 ep_ring->dequeue, td->last_trb,
2816 skip_isoc_td(xhci, td, ep, status);
2819 if (trb_comp_code == COMP_SHORT_PACKET)
2820 ep_ring->last_td_was_short = true;
2822 ep_ring->last_td_was_short = false;
2826 "Found td. Clear skip flag for slot %u ep %u.\n",
2831 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2834 trace_xhci_handle_transfer(ep_ring,
2835 (struct xhci_generic_trb *) ep_trb);
2838 * No-op TRB could trigger interrupts in a case where
2839 * a URB was killed and a STALL_ERROR happens right
2840 * after the endpoint ring stopped. Reset the halted
2841 * endpoint. Otherwise, the endpoint remains stalled
2845 if (trb_is_noop(ep_trb)) {
2846 if (trb_comp_code == COMP_STALL_ERROR ||
2847 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2849 xhci_handle_halted_endpoint(xhci, ep,
2855 td->status = status;
2857 /* update the urb's actual_length and give back to the core */
2858 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2859 process_ctrl_td(xhci, ep, ep_ring, td, ep_trb, event);
2860 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2861 process_isoc_td(xhci, ep, ep_ring, td, ep_trb, event);
2863 process_bulk_intr_td(xhci, ep, ep_ring, td, ep_trb, event);
2865 handling_skipped_tds = ep->skip &&
2866 trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2867 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2870 * Do not update event ring dequeue pointer if we're in a loop
2871 * processing missed tds.
2873 if (!handling_skipped_tds)
2874 inc_deq(xhci, xhci->event_ring);
2877 * If ep->skip is set, it means there are missed tds on the
2878 * endpoint ring need to take care of.
2879 * Process them as short transfer until reach the td pointed by
2882 } while (handling_skipped_tds);
2887 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2888 (unsigned long long) xhci_trb_virt_to_dma(
2889 xhci->event_ring->deq_seg,
2890 xhci->event_ring->dequeue),
2891 lower_32_bits(le64_to_cpu(event->buffer)),
2892 upper_32_bits(le64_to_cpu(event->buffer)),
2893 le32_to_cpu(event->transfer_len),
2894 le32_to_cpu(event->flags));
2899 * This function handles all OS-owned events on the event ring. It may drop
2900 * xhci->lock between event processing (e.g. to pass up port status changes).
2901 * Returns >0 for "possibly more events to process" (caller should call again),
2902 * otherwise 0 if done. In future, <0 returns should indicate error code.
2904 static int xhci_handle_event(struct xhci_hcd *xhci)
2906 union xhci_trb *event;
2907 int update_ptrs = 1;
2911 /* Event ring hasn't been allocated yet. */
2912 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2913 xhci_err(xhci, "ERROR event ring not ready\n");
2917 event = xhci->event_ring->dequeue;
2918 /* Does the HC or OS own the TRB? */
2919 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2920 xhci->event_ring->cycle_state)
2923 trace_xhci_handle_event(xhci->event_ring, &event->generic);
2926 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2927 * speculative reads of the event's flags/data below.
2930 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
2931 /* FIXME: Handle more event types. */
2934 case TRB_COMPLETION:
2935 handle_cmd_completion(xhci, &event->event_cmd);
2937 case TRB_PORT_STATUS:
2938 handle_port_status(xhci, event);
2942 ret = handle_tx_event(xhci, &event->trans_event);
2947 handle_device_notification(xhci, event);
2950 if (trb_type >= TRB_VENDOR_DEFINED_LOW)
2951 handle_vendor_event(xhci, event, trb_type);
2953 xhci_warn(xhci, "ERROR unknown event type %d\n", trb_type);
2955 /* Any of the above functions may drop and re-acquire the lock, so check
2956 * to make sure a watchdog timer didn't mark the host as non-responsive.
2958 if (xhci->xhc_state & XHCI_STATE_DYING) {
2959 xhci_dbg(xhci, "xHCI host dying, returning from "
2960 "event handler.\n");
2965 /* Update SW event ring dequeue pointer */
2966 inc_deq(xhci, xhci->event_ring);
2968 /* Are there more items on the event ring? Caller will call us again to
2975 * Update Event Ring Dequeue Pointer:
2976 * - When all events have finished
2977 * - To avoid "Event Ring Full Error" condition
2979 static void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
2980 union xhci_trb *event_ring_deq)
2985 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2986 /* If necessary, update the HW's version of the event ring deq ptr. */
2987 if (event_ring_deq != xhci->event_ring->dequeue) {
2988 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2989 xhci->event_ring->dequeue);
2991 xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n");
2993 * Per 4.9.4, Software writes to the ERDP register shall
2994 * always advance the Event Ring Dequeue Pointer value.
2996 if ((temp_64 & (u64) ~ERST_PTR_MASK) ==
2997 ((u64) deq & (u64) ~ERST_PTR_MASK))
3000 /* Update HC event ring dequeue pointer */
3001 temp_64 &= ERST_PTR_MASK;
3002 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
3005 /* Clear the event handler busy flag (RW1C) */
3006 temp_64 |= ERST_EHB;
3007 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
3011 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
3012 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
3013 * indicators of an event TRB error, but we check the status *first* to be safe.
3015 irqreturn_t xhci_irq(struct usb_hcd *hcd)
3017 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3018 union xhci_trb *event_ring_deq;
3019 irqreturn_t ret = IRQ_NONE;
3024 spin_lock(&xhci->lock);
3025 /* Check if the xHC generated the interrupt, or the irq is shared */
3026 status = readl(&xhci->op_regs->status);
3027 if (status == ~(u32)0) {
3033 if (!(status & STS_EINT))
3036 if (status & STS_FATAL) {
3037 xhci_warn(xhci, "WARNING: Host System Error\n");
3044 * Clear the op reg interrupt status first,
3045 * so we can receive interrupts from other MSI-X interrupters.
3046 * Write 1 to clear the interrupt status.
3049 writel(status, &xhci->op_regs->status);
3051 if (!hcd->msi_enabled) {
3053 irq_pending = readl(&xhci->ir_set->irq_pending);
3054 irq_pending |= IMAN_IP;
3055 writel(irq_pending, &xhci->ir_set->irq_pending);
3058 if (xhci->xhc_state & XHCI_STATE_DYING ||
3059 xhci->xhc_state & XHCI_STATE_HALTED) {
3060 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
3061 "Shouldn't IRQs be disabled?\n");
3062 /* Clear the event handler busy flag (RW1C);
3063 * the event ring should be empty.
3065 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
3066 xhci_write_64(xhci, temp_64 | ERST_EHB,
3067 &xhci->ir_set->erst_dequeue);
3072 event_ring_deq = xhci->event_ring->dequeue;
3073 /* FIXME this should be a delayed service routine
3074 * that clears the EHB.
3076 while (xhci_handle_event(xhci) > 0) {
3077 if (event_loop++ < TRBS_PER_SEGMENT / 2)
3079 xhci_update_erst_dequeue(xhci, event_ring_deq);
3081 /* ring is half-full, force isoc trbs to interrupt more often */
3082 if (xhci->isoc_bei_interval > AVOID_BEI_INTERVAL_MIN)
3083 xhci->isoc_bei_interval = xhci->isoc_bei_interval / 2;
3088 xhci_update_erst_dequeue(xhci, event_ring_deq);
3092 spin_unlock(&xhci->lock);
3097 irqreturn_t xhci_msi_irq(int irq, void *hcd)
3099 return xhci_irq(hcd);
3102 /**** Endpoint Ring Operations ****/
3105 * Generic function for queueing a TRB on a ring.
3106 * The caller must have checked to make sure there's room on the ring.
3108 * @more_trbs_coming: Will you enqueue more TRBs before calling
3109 * prepare_transfer()?
3111 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
3112 bool more_trbs_coming,
3113 u32 field1, u32 field2, u32 field3, u32 field4)
3115 struct xhci_generic_trb *trb;
3117 trb = &ring->enqueue->generic;
3118 trb->field[0] = cpu_to_le32(field1);
3119 trb->field[1] = cpu_to_le32(field2);
3120 trb->field[2] = cpu_to_le32(field3);
3121 /* make sure TRB is fully written before giving it to the controller */
3123 trb->field[3] = cpu_to_le32(field4);
3125 trace_xhci_queue_trb(ring, trb);
3127 inc_enq(xhci, ring, more_trbs_coming);
3131 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
3132 * FIXME allocate segments if the ring is full.
3134 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
3135 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
3137 unsigned int num_trbs_needed;
3138 unsigned int link_trb_count = 0;
3140 /* Make sure the endpoint has been added to xHC schedule */
3142 case EP_STATE_DISABLED:
3144 * USB core changed config/interfaces without notifying us,
3145 * or hardware is reporting the wrong state.
3147 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
3149 case EP_STATE_ERROR:
3150 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
3151 /* FIXME event handling code for error needs to clear it */
3152 /* XXX not sure if this should be -ENOENT or not */
3154 case EP_STATE_HALTED:
3155 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
3157 case EP_STATE_STOPPED:
3158 case EP_STATE_RUNNING:
3161 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
3163 * FIXME issue Configure Endpoint command to try to get the HC
3164 * back into a known state.
3170 if (room_on_ring(xhci, ep_ring, num_trbs))
3173 if (ep_ring == xhci->cmd_ring) {
3174 xhci_err(xhci, "Do not support expand command ring\n");
3178 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
3179 "ERROR no room on ep ring, try ring expansion");
3180 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
3181 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
3183 xhci_err(xhci, "Ring expansion failed\n");
3188 while (trb_is_link(ep_ring->enqueue)) {
3189 /* If we're not dealing with 0.95 hardware or isoc rings
3190 * on AMD 0.96 host, clear the chain bit.
3192 if (!xhci_link_trb_quirk(xhci) &&
3193 !(ep_ring->type == TYPE_ISOC &&
3194 (xhci->quirks & XHCI_AMD_0x96_HOST)))
3195 ep_ring->enqueue->link.control &=
3196 cpu_to_le32(~TRB_CHAIN);
3198 ep_ring->enqueue->link.control |=
3199 cpu_to_le32(TRB_CHAIN);
3202 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
3204 /* Toggle the cycle bit after the last ring segment. */
3205 if (link_trb_toggles_cycle(ep_ring->enqueue))
3206 ep_ring->cycle_state ^= 1;
3208 ep_ring->enq_seg = ep_ring->enq_seg->next;
3209 ep_ring->enqueue = ep_ring->enq_seg->trbs;
3211 /* prevent infinite loop if all first trbs are link trbs */
3212 if (link_trb_count++ > ep_ring->num_segs) {
3213 xhci_warn(xhci, "Ring is an endless link TRB loop\n");
3218 if (last_trb_on_seg(ep_ring->enq_seg, ep_ring->enqueue)) {
3219 xhci_warn(xhci, "Missing link TRB at end of ring segment\n");
3226 static int prepare_transfer(struct xhci_hcd *xhci,
3227 struct xhci_virt_device *xdev,
3228 unsigned int ep_index,
3229 unsigned int stream_id,
3230 unsigned int num_trbs,
3232 unsigned int td_index,
3236 struct urb_priv *urb_priv;
3238 struct xhci_ring *ep_ring;
3239 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3241 ep_ring = xhci_triad_to_transfer_ring(xhci, xdev->slot_id, ep_index,
3244 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3249 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3250 num_trbs, mem_flags);
3254 urb_priv = urb->hcpriv;
3255 td = &urb_priv->td[td_index];
3257 INIT_LIST_HEAD(&td->td_list);
3258 INIT_LIST_HEAD(&td->cancelled_td_list);
3260 if (td_index == 0) {
3261 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3267 /* Add this TD to the tail of the endpoint ring's TD list */
3268 list_add_tail(&td->td_list, &ep_ring->td_list);
3269 td->start_seg = ep_ring->enq_seg;
3270 td->first_trb = ep_ring->enqueue;
3275 unsigned int count_trbs(u64 addr, u64 len)
3277 unsigned int num_trbs;
3279 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3287 static inline unsigned int count_trbs_needed(struct urb *urb)
3289 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3292 static unsigned int count_sg_trbs_needed(struct urb *urb)
3294 struct scatterlist *sg;
3295 unsigned int i, len, full_len, num_trbs = 0;
3297 full_len = urb->transfer_buffer_length;
3299 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3300 len = sg_dma_len(sg);
3301 num_trbs += count_trbs(sg_dma_address(sg), len);
3302 len = min_t(unsigned int, len, full_len);
3311 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3315 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3316 len = urb->iso_frame_desc[i].length;
3318 return count_trbs(addr, len);
3321 static void check_trb_math(struct urb *urb, int running_total)
3323 if (unlikely(running_total != urb->transfer_buffer_length))
3324 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3325 "queued %#x (%d), asked for %#x (%d)\n",
3327 urb->ep->desc.bEndpointAddress,
3328 running_total, running_total,
3329 urb->transfer_buffer_length,
3330 urb->transfer_buffer_length);
3333 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3334 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3335 struct xhci_generic_trb *start_trb)
3338 * Pass all the TRBs to the hardware at once and make sure this write
3343 start_trb->field[3] |= cpu_to_le32(start_cycle);
3345 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3346 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3349 static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3350 struct xhci_ep_ctx *ep_ctx)
3355 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3356 ep_interval = urb->interval;
3358 /* Convert to microframes */
3359 if (urb->dev->speed == USB_SPEED_LOW ||
3360 urb->dev->speed == USB_SPEED_FULL)
3363 /* FIXME change this to a warning and a suggestion to use the new API
3364 * to set the polling interval (once the API is added).
3366 if (xhci_interval != ep_interval) {
3367 dev_dbg_ratelimited(&urb->dev->dev,
3368 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3369 ep_interval, ep_interval == 1 ? "" : "s",
3370 xhci_interval, xhci_interval == 1 ? "" : "s");
3371 urb->interval = xhci_interval;
3372 /* Convert back to frames for LS/FS devices */
3373 if (urb->dev->speed == USB_SPEED_LOW ||
3374 urb->dev->speed == USB_SPEED_FULL)
3380 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3381 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3382 * (comprised of sg list entries) can take several service intervals to
3385 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3386 struct urb *urb, int slot_id, unsigned int ep_index)
3388 struct xhci_ep_ctx *ep_ctx;
3390 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3391 check_interval(xhci, urb, ep_ctx);
3393 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3397 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3398 * packets remaining in the TD (*not* including this TRB).
3400 * Total TD packet count = total_packet_count =
3401 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3403 * Packets transferred up to and including this TRB = packets_transferred =
3404 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3406 * TD size = total_packet_count - packets_transferred
3408 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3409 * including this TRB, right shifted by 10
3411 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3412 * This is taken care of in the TRB_TD_SIZE() macro
3414 * The last TRB in a TD must have the TD size set to zero.
3416 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3417 int trb_buff_len, unsigned int td_total_len,
3418 struct urb *urb, bool more_trbs_coming)
3420 u32 maxp, total_packet_count;
3422 /* MTK xHCI 0.96 contains some features from 1.0 */
3423 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3424 return ((td_total_len - transferred) >> 10);
3426 /* One TRB with a zero-length data packet. */
3427 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3428 trb_buff_len == td_total_len)
3431 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3432 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3435 maxp = usb_endpoint_maxp(&urb->ep->desc);
3436 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3438 /* Queueing functions don't count the current TRB into transferred */
3439 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3443 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3444 u32 *trb_buff_len, struct xhci_segment *seg)
3446 struct device *dev = xhci_to_hcd(xhci)->self.controller;
3447 unsigned int unalign;
3448 unsigned int max_pkt;
3452 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3453 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3455 /* we got lucky, last normal TRB data on segment is packet aligned */
3459 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3460 unalign, *trb_buff_len);
3462 /* is the last nornal TRB alignable by splitting it */
3463 if (*trb_buff_len > unalign) {
3464 *trb_buff_len -= unalign;
3465 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3470 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3471 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3472 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3474 new_buff_len = max_pkt - (enqd_len % max_pkt);
3476 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3477 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3479 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3480 if (usb_urb_dir_out(urb)) {
3482 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3483 seg->bounce_buf, new_buff_len, enqd_len);
3484 if (len != new_buff_len)
3485 xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n",
3488 memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len);
3491 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3492 max_pkt, DMA_TO_DEVICE);
3494 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3495 max_pkt, DMA_FROM_DEVICE);
3498 if (dma_mapping_error(dev, seg->bounce_dma)) {
3499 /* try without aligning. Some host controllers survive */
3500 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3503 *trb_buff_len = new_buff_len;
3504 seg->bounce_len = new_buff_len;
3505 seg->bounce_offs = enqd_len;
3507 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3512 /* This is very similar to what ehci-q.c qtd_fill() does */
3513 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3514 struct urb *urb, int slot_id, unsigned int ep_index)
3516 struct xhci_ring *ring;
3517 struct urb_priv *urb_priv;
3519 struct xhci_generic_trb *start_trb;
3520 struct scatterlist *sg = NULL;
3521 bool more_trbs_coming = true;
3522 bool need_zero_pkt = false;
3523 bool first_trb = true;
3524 unsigned int num_trbs;
3525 unsigned int start_cycle, num_sgs = 0;
3526 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3528 u32 field, length_field, remainder;
3529 u64 addr, send_addr;
3531 ring = xhci_urb_to_transfer_ring(xhci, urb);
3535 full_len = urb->transfer_buffer_length;
3536 /* If we have scatter/gather list, we use it. */
3537 if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) {
3538 num_sgs = urb->num_mapped_sgs;
3540 addr = (u64) sg_dma_address(sg);
3541 block_len = sg_dma_len(sg);
3542 num_trbs = count_sg_trbs_needed(urb);
3544 num_trbs = count_trbs_needed(urb);
3545 addr = (u64) urb->transfer_dma;
3546 block_len = full_len;
3548 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3549 ep_index, urb->stream_id,
3550 num_trbs, urb, 0, mem_flags);
3551 if (unlikely(ret < 0))
3554 urb_priv = urb->hcpriv;
3556 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3557 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3558 need_zero_pkt = true;
3560 td = &urb_priv->td[0];
3563 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3564 * until we've finished creating all the other TRBs. The ring's cycle
3565 * state may change as we enqueue the other TRBs, so save it too.
3567 start_trb = &ring->enqueue->generic;
3568 start_cycle = ring->cycle_state;
3571 /* Queue the TRBs, even if they are zero-length */
3572 for (enqd_len = 0; first_trb || enqd_len < full_len;
3573 enqd_len += trb_buff_len) {
3574 field = TRB_TYPE(TRB_NORMAL);
3576 /* TRB buffer should not cross 64KB boundaries */
3577 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3578 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3580 if (enqd_len + trb_buff_len > full_len)
3581 trb_buff_len = full_len - enqd_len;
3583 /* Don't change the cycle bit of the first TRB until later */
3586 if (start_cycle == 0)
3589 field |= ring->cycle_state;
3591 /* Chain all the TRBs together; clear the chain bit in the last
3592 * TRB to indicate it's the last TRB in the chain.
3594 if (enqd_len + trb_buff_len < full_len) {
3596 if (trb_is_link(ring->enqueue + 1)) {
3597 if (xhci_align_td(xhci, urb, enqd_len,
3600 send_addr = ring->enq_seg->bounce_dma;
3601 /* assuming TD won't span 2 segs */
3602 td->bounce_seg = ring->enq_seg;
3606 if (enqd_len + trb_buff_len >= full_len) {
3607 field &= ~TRB_CHAIN;
3609 more_trbs_coming = false;
3610 td->last_trb = ring->enqueue;
3611 td->last_trb_seg = ring->enq_seg;
3612 if (xhci_urb_suitable_for_idt(urb)) {
3613 memcpy(&send_addr, urb->transfer_buffer,
3615 le64_to_cpus(&send_addr);
3620 /* Only set interrupt on short packet for IN endpoints */
3621 if (usb_urb_dir_in(urb))
3624 /* Set the TRB length, TD size, and interrupter fields. */
3625 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3626 full_len, urb, more_trbs_coming);
3628 length_field = TRB_LEN(trb_buff_len) |
3629 TRB_TD_SIZE(remainder) |
3632 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3633 lower_32_bits(send_addr),
3634 upper_32_bits(send_addr),
3638 addr += trb_buff_len;
3639 sent_len = trb_buff_len;
3641 while (sg && sent_len >= block_len) {
3644 sent_len -= block_len;
3646 if (num_sgs != 0 && sg) {
3647 block_len = sg_dma_len(sg);
3648 addr = (u64) sg_dma_address(sg);
3652 block_len -= sent_len;
3656 if (need_zero_pkt) {
3657 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3658 ep_index, urb->stream_id,
3659 1, urb, 1, mem_flags);
3660 urb_priv->td[1].last_trb = ring->enqueue;
3661 urb_priv->td[1].last_trb_seg = ring->enq_seg;
3662 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3663 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3664 urb_priv->td[1].num_trbs++;
3667 check_trb_math(urb, enqd_len);
3668 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3669 start_cycle, start_trb);
3673 /* Caller must have locked xhci->lock */
3674 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3675 struct urb *urb, int slot_id, unsigned int ep_index)
3677 struct xhci_ring *ep_ring;
3680 struct usb_ctrlrequest *setup;
3681 struct xhci_generic_trb *start_trb;
3684 struct urb_priv *urb_priv;
3687 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3692 * Need to copy setup packet into setup TRB, so we can't use the setup
3695 if (!urb->setup_packet)
3698 /* 1 TRB for setup, 1 for status */
3701 * Don't need to check if we need additional event data and normal TRBs,
3702 * since data in control transfers will never get bigger than 16MB
3703 * XXX: can we get a buffer that crosses 64KB boundaries?
3705 if (urb->transfer_buffer_length > 0)
3707 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3708 ep_index, urb->stream_id,
3709 num_trbs, urb, 0, mem_flags);
3713 urb_priv = urb->hcpriv;
3714 td = &urb_priv->td[0];
3715 td->num_trbs = num_trbs;
3718 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3719 * until we've finished creating all the other TRBs. The ring's cycle
3720 * state may change as we enqueue the other TRBs, so save it too.
3722 start_trb = &ep_ring->enqueue->generic;
3723 start_cycle = ep_ring->cycle_state;
3725 /* Queue setup TRB - see section 6.4.1.2.1 */
3726 /* FIXME better way to translate setup_packet into two u32 fields? */
3727 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3729 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3730 if (start_cycle == 0)
3733 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3734 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3735 if (urb->transfer_buffer_length > 0) {
3736 if (setup->bRequestType & USB_DIR_IN)
3737 field |= TRB_TX_TYPE(TRB_DATA_IN);
3739 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3743 queue_trb(xhci, ep_ring, true,
3744 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3745 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3746 TRB_LEN(8) | TRB_INTR_TARGET(0),
3747 /* Immediate data in pointer */
3750 /* If there's data, queue data TRBs */
3751 /* Only set interrupt on short packet for IN endpoints */
3752 if (usb_urb_dir_in(urb))
3753 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3755 field = TRB_TYPE(TRB_DATA);
3757 if (urb->transfer_buffer_length > 0) {
3758 u32 length_field, remainder;
3761 if (xhci_urb_suitable_for_idt(urb)) {
3762 memcpy(&addr, urb->transfer_buffer,
3763 urb->transfer_buffer_length);
3764 le64_to_cpus(&addr);
3767 addr = (u64) urb->transfer_dma;
3770 remainder = xhci_td_remainder(xhci, 0,
3771 urb->transfer_buffer_length,
3772 urb->transfer_buffer_length,
3774 length_field = TRB_LEN(urb->transfer_buffer_length) |
3775 TRB_TD_SIZE(remainder) |
3777 if (setup->bRequestType & USB_DIR_IN)
3778 field |= TRB_DIR_IN;
3779 queue_trb(xhci, ep_ring, true,
3780 lower_32_bits(addr),
3781 upper_32_bits(addr),
3783 field | ep_ring->cycle_state);
3786 /* Save the DMA address of the last TRB in the TD */
3787 td->last_trb = ep_ring->enqueue;
3788 td->last_trb_seg = ep_ring->enq_seg;
3790 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3791 /* If the device sent data, the status stage is an OUT transfer */
3792 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3796 queue_trb(xhci, ep_ring, false,
3800 /* Event on completion */
3801 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3803 giveback_first_trb(xhci, slot_id, ep_index, 0,
3804 start_cycle, start_trb);
3809 * The transfer burst count field of the isochronous TRB defines the number of
3810 * bursts that are required to move all packets in this TD. Only SuperSpeed
3811 * devices can burst up to bMaxBurst number of packets per service interval.
3812 * This field is zero based, meaning a value of zero in the field means one
3813 * burst. Basically, for everything but SuperSpeed devices, this field will be
3814 * zero. Only xHCI 1.0 host controllers support this field.
3816 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3817 struct urb *urb, unsigned int total_packet_count)
3819 unsigned int max_burst;
3821 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3824 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3825 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3829 * Returns the number of packets in the last "burst" of packets. This field is
3830 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3831 * the last burst packet count is equal to the total number of packets in the
3832 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3833 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3834 * contain 1 to (bMaxBurst + 1) packets.
3836 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3837 struct urb *urb, unsigned int total_packet_count)
3839 unsigned int max_burst;
3840 unsigned int residue;
3842 if (xhci->hci_version < 0x100)
3845 if (urb->dev->speed >= USB_SPEED_SUPER) {
3846 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3847 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3848 residue = total_packet_count % (max_burst + 1);
3849 /* If residue is zero, the last burst contains (max_burst + 1)
3850 * number of packets, but the TLBPC field is zero-based.
3856 if (total_packet_count == 0)
3858 return total_packet_count - 1;
3862 * Calculates Frame ID field of the isochronous TRB identifies the
3863 * target frame that the Interval associated with this Isochronous
3864 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3866 * Returns actual frame id on success, negative value on error.
3868 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3869 struct urb *urb, int index)
3871 int start_frame, ist, ret = 0;
3872 int start_frame_id, end_frame_id, current_frame_id;
3874 if (urb->dev->speed == USB_SPEED_LOW ||
3875 urb->dev->speed == USB_SPEED_FULL)
3876 start_frame = urb->start_frame + index * urb->interval;
3878 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3880 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3882 * If bit [3] of IST is cleared to '0', software can add a TRB no
3883 * later than IST[2:0] Microframes before that TRB is scheduled to
3885 * If bit [3] of IST is set to '1', software can add a TRB no later
3886 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3888 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3889 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3892 /* Software shall not schedule an Isoch TD with a Frame ID value that
3893 * is less than the Start Frame ID or greater than the End Frame ID,
3896 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3897 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3899 * Both the End Frame ID and Start Frame ID values are calculated
3900 * in microframes. When software determines the valid Frame ID value;
3901 * The End Frame ID value should be rounded down to the nearest Frame
3902 * boundary, and the Start Frame ID value should be rounded up to the
3903 * nearest Frame boundary.
3905 current_frame_id = readl(&xhci->run_regs->microframe_index);
3906 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3907 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3909 start_frame &= 0x7ff;
3910 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3911 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3913 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3914 __func__, index, readl(&xhci->run_regs->microframe_index),
3915 start_frame_id, end_frame_id, start_frame);
3917 if (start_frame_id < end_frame_id) {
3918 if (start_frame > end_frame_id ||
3919 start_frame < start_frame_id)
3921 } else if (start_frame_id > end_frame_id) {
3922 if ((start_frame > end_frame_id &&
3923 start_frame < start_frame_id))
3930 if (ret == -EINVAL || start_frame == start_frame_id) {
3931 start_frame = start_frame_id + 1;
3932 if (urb->dev->speed == USB_SPEED_LOW ||
3933 urb->dev->speed == USB_SPEED_FULL)
3934 urb->start_frame = start_frame;
3936 urb->start_frame = start_frame << 3;
3942 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3943 start_frame, current_frame_id, index,
3944 start_frame_id, end_frame_id);
3945 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3952 /* Check if we should generate event interrupt for a TD in an isoc URB */
3953 static bool trb_block_event_intr(struct xhci_hcd *xhci, int num_tds, int i)
3955 if (xhci->hci_version < 0x100)
3957 /* always generate an event interrupt for the last TD */
3958 if (i == num_tds - 1)
3961 * If AVOID_BEI is set the host handles full event rings poorly,
3962 * generate an event at least every 8th TD to clear the event ring
3964 if (i && xhci->quirks & XHCI_AVOID_BEI)
3965 return !!(i % xhci->isoc_bei_interval);
3970 /* This is for isoc transfer */
3971 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3972 struct urb *urb, int slot_id, unsigned int ep_index)
3974 struct xhci_ring *ep_ring;
3975 struct urb_priv *urb_priv;
3977 int num_tds, trbs_per_td;
3978 struct xhci_generic_trb *start_trb;
3981 u32 field, length_field;
3982 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3983 u64 start_addr, addr;
3985 bool more_trbs_coming;
3986 struct xhci_virt_ep *xep;
3989 xep = &xhci->devs[slot_id]->eps[ep_index];
3990 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3992 num_tds = urb->number_of_packets;
3994 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3997 start_addr = (u64) urb->transfer_dma;
3998 start_trb = &ep_ring->enqueue->generic;
3999 start_cycle = ep_ring->cycle_state;
4001 urb_priv = urb->hcpriv;
4002 /* Queue the TRBs for each TD, even if they are zero-length */
4003 for (i = 0; i < num_tds; i++) {
4004 unsigned int total_pkt_count, max_pkt;
4005 unsigned int burst_count, last_burst_pkt_count;
4010 addr = start_addr + urb->iso_frame_desc[i].offset;
4011 td_len = urb->iso_frame_desc[i].length;
4012 td_remain_len = td_len;
4013 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
4014 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
4016 /* A zero-length transfer still involves at least one packet. */
4017 if (total_pkt_count == 0)
4019 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
4020 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
4021 urb, total_pkt_count);
4023 trbs_per_td = count_isoc_trbs_needed(urb, i);
4025 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
4026 urb->stream_id, trbs_per_td, urb, i, mem_flags);
4032 td = &urb_priv->td[i];
4033 td->num_trbs = trbs_per_td;
4034 /* use SIA as default, if frame id is used overwrite it */
4035 sia_frame_id = TRB_SIA;
4036 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
4037 HCC_CFC(xhci->hcc_params)) {
4038 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
4040 sia_frame_id = TRB_FRAME_ID(frame_id);
4043 * Set isoc specific data for the first TRB in a TD.
4044 * Prevent HW from getting the TRBs by keeping the cycle state
4045 * inverted in the first TDs isoc TRB.
4047 field = TRB_TYPE(TRB_ISOC) |
4048 TRB_TLBPC(last_burst_pkt_count) |
4050 (i ? ep_ring->cycle_state : !start_cycle);
4052 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
4053 if (!xep->use_extended_tbc)
4054 field |= TRB_TBC(burst_count);
4056 /* fill the rest of the TRB fields, and remaining normal TRBs */
4057 for (j = 0; j < trbs_per_td; j++) {
4060 /* only first TRB is isoc, overwrite otherwise */
4062 field = TRB_TYPE(TRB_NORMAL) |
4063 ep_ring->cycle_state;
4065 /* Only set interrupt on short packet for IN EPs */
4066 if (usb_urb_dir_in(urb))
4069 /* Set the chain bit for all except the last TRB */
4070 if (j < trbs_per_td - 1) {
4071 more_trbs_coming = true;
4074 more_trbs_coming = false;
4075 td->last_trb = ep_ring->enqueue;
4076 td->last_trb_seg = ep_ring->enq_seg;
4078 if (trb_block_event_intr(xhci, num_tds, i))
4081 /* Calculate TRB length */
4082 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
4083 if (trb_buff_len > td_remain_len)
4084 trb_buff_len = td_remain_len;
4086 /* Set the TRB length, TD size, & interrupter fields. */
4087 remainder = xhci_td_remainder(xhci, running_total,
4088 trb_buff_len, td_len,
4089 urb, more_trbs_coming);
4091 length_field = TRB_LEN(trb_buff_len) |
4094 /* xhci 1.1 with ETE uses TD Size field for TBC */
4095 if (first_trb && xep->use_extended_tbc)
4096 length_field |= TRB_TD_SIZE_TBC(burst_count);
4098 length_field |= TRB_TD_SIZE(remainder);
4101 queue_trb(xhci, ep_ring, more_trbs_coming,
4102 lower_32_bits(addr),
4103 upper_32_bits(addr),
4106 running_total += trb_buff_len;
4108 addr += trb_buff_len;
4109 td_remain_len -= trb_buff_len;
4112 /* Check TD length */
4113 if (running_total != td_len) {
4114 xhci_err(xhci, "ISOC TD length unmatch\n");
4120 /* store the next frame id */
4121 if (HCC_CFC(xhci->hcc_params))
4122 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
4124 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
4125 if (xhci->quirks & XHCI_AMD_PLL_FIX)
4126 usb_amd_quirk_pll_disable();
4128 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
4130 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
4131 start_cycle, start_trb);
4134 /* Clean up a partially enqueued isoc transfer. */
4136 for (i--; i >= 0; i--)
4137 list_del_init(&urb_priv->td[i].td_list);
4139 /* Use the first TD as a temporary variable to turn the TDs we've queued
4140 * into No-ops with a software-owned cycle bit. That way the hardware
4141 * won't accidentally start executing bogus TDs when we partially
4142 * overwrite them. td->first_trb and td->start_seg are already set.
4144 urb_priv->td[0].last_trb = ep_ring->enqueue;
4145 /* Every TRB except the first & last will have its cycle bit flipped. */
4146 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
4148 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
4149 ep_ring->enqueue = urb_priv->td[0].first_trb;
4150 ep_ring->enq_seg = urb_priv->td[0].start_seg;
4151 ep_ring->cycle_state = start_cycle;
4152 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
4153 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
4158 * Check transfer ring to guarantee there is enough room for the urb.
4159 * Update ISO URB start_frame and interval.
4160 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
4161 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
4162 * Contiguous Frame ID is not supported by HC.
4164 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
4165 struct urb *urb, int slot_id, unsigned int ep_index)
4167 struct xhci_virt_device *xdev;
4168 struct xhci_ring *ep_ring;
4169 struct xhci_ep_ctx *ep_ctx;
4171 int num_tds, num_trbs, i;
4173 struct xhci_virt_ep *xep;
4176 xdev = xhci->devs[slot_id];
4177 xep = &xhci->devs[slot_id]->eps[ep_index];
4178 ep_ring = xdev->eps[ep_index].ring;
4179 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
4182 num_tds = urb->number_of_packets;
4183 for (i = 0; i < num_tds; i++)
4184 num_trbs += count_isoc_trbs_needed(urb, i);
4186 /* Check the ring to guarantee there is enough room for the whole urb.
4187 * Do not insert any td of the urb to the ring if the check failed.
4189 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
4190 num_trbs, mem_flags);
4195 * Check interval value. This should be done before we start to
4196 * calculate the start frame value.
4198 check_interval(xhci, urb, ep_ctx);
4200 /* Calculate the start frame and put it in urb->start_frame. */
4201 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
4202 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
4203 urb->start_frame = xep->next_frame_id;
4204 goto skip_start_over;
4208 start_frame = readl(&xhci->run_regs->microframe_index);
4209 start_frame &= 0x3fff;
4211 * Round up to the next frame and consider the time before trb really
4212 * gets scheduled by hardare.
4214 ist = HCS_IST(xhci->hcs_params2) & 0x7;
4215 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
4217 start_frame += ist + XHCI_CFC_DELAY;
4218 start_frame = roundup(start_frame, 8);
4221 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
4222 * is greate than 8 microframes.
4224 if (urb->dev->speed == USB_SPEED_LOW ||
4225 urb->dev->speed == USB_SPEED_FULL) {
4226 start_frame = roundup(start_frame, urb->interval << 3);
4227 urb->start_frame = start_frame >> 3;
4229 start_frame = roundup(start_frame, urb->interval);
4230 urb->start_frame = start_frame;
4234 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
4236 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4239 /**** Command Ring Operations ****/
4241 /* Generic function for queueing a command TRB on the command ring.
4242 * Check to make sure there's room on the command ring for one command TRB.
4243 * Also check that there's room reserved for commands that must not fail.
4244 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4245 * then only check for the number of reserved spots.
4246 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4247 * because the command event handler may want to resubmit a failed command.
4249 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4250 u32 field1, u32 field2,
4251 u32 field3, u32 field4, bool command_must_succeed)
4253 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4256 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
4257 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4258 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
4262 if (!command_must_succeed)
4265 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4266 reserved_trbs, GFP_ATOMIC);
4268 xhci_err(xhci, "ERR: No room for command on command ring\n");
4269 if (command_must_succeed)
4270 xhci_err(xhci, "ERR: Reserved TRB counting for "
4271 "unfailable commands failed.\n");
4275 cmd->command_trb = xhci->cmd_ring->enqueue;
4277 /* if there are no other commands queued we start the timeout timer */
4278 if (list_empty(&xhci->cmd_list)) {
4279 xhci->current_cmd = cmd;
4280 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
4283 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4285 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4286 field4 | xhci->cmd_ring->cycle_state);
4290 /* Queue a slot enable or disable request on the command ring */
4291 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4292 u32 trb_type, u32 slot_id)
4294 return queue_command(xhci, cmd, 0, 0, 0,
4295 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4298 /* Queue an address device command TRB */
4299 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4300 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4302 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4303 upper_32_bits(in_ctx_ptr), 0,
4304 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4305 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4308 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4309 u32 field1, u32 field2, u32 field3, u32 field4)
4311 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4314 /* Queue a reset device command TRB */
4315 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4318 return queue_command(xhci, cmd, 0, 0, 0,
4319 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4323 /* Queue a configure endpoint command TRB */
4324 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4325 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4326 u32 slot_id, bool command_must_succeed)
4328 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4329 upper_32_bits(in_ctx_ptr), 0,
4330 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4331 command_must_succeed);
4334 /* Queue an evaluate context command TRB */
4335 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4336 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4338 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4339 upper_32_bits(in_ctx_ptr), 0,
4340 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4341 command_must_succeed);
4345 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4346 * activity on an endpoint that is about to be suspended.
4348 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4349 int slot_id, unsigned int ep_index, int suspend)
4351 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4352 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4353 u32 type = TRB_TYPE(TRB_STOP_RING);
4354 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4356 return queue_command(xhci, cmd, 0, 0, 0,
4357 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4360 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4361 int slot_id, unsigned int ep_index,
4362 enum xhci_ep_reset_type reset_type)
4364 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4365 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4366 u32 type = TRB_TYPE(TRB_RESET_EP);
4368 if (reset_type == EP_SOFT_RESET)
4371 return queue_command(xhci, cmd, 0, 0, 0,
4372 trb_slot_id | trb_ep_index | type, false);