1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
12 * Ring initialization rules:
13 * 1. Each segment is initialized to zero, except for link TRBs.
14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
15 * Consumer Cycle State (CCS), depending on ring function.
16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
18 * Ring behavior rules:
19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
20 * least one free TRB in the ring. This is useful if you want to turn that
21 * into a link TRB and expand the ring.
22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
23 * link TRB, then load the pointer with the address in the link TRB. If the
24 * link TRB had its toggle bit set, you may need to update the ring cycle
25 * state (see cycle bit rules). You may have to do this multiple times
26 * until you reach a non-link TRB.
27 * 3. A ring is full if enqueue++ (for the definition of increment above)
28 * equals the dequeue pointer.
31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
32 * in a link TRB, it must toggle the ring cycle state.
33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
34 * in a link TRB, it must toggle the ring cycle state.
37 * 1. Check if ring is full before you enqueue.
38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
39 * Update enqueue pointer between each write (which may update the ring
41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
42 * and endpoint rings. If HC is the producer for the event ring,
43 * and it generates an interrupt according to interrupt modulation rules.
46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
47 * the TRB is owned by the consumer.
48 * 2. Update dequeue pointer (which may update the ring cycle state) and
49 * continue processing TRBs until you reach a TRB which is not owned by you.
50 * 3. Notify the producer. SW is the consumer for the event ring, and it
51 * updates event ring dequeue pointer. HC is the consumer for the command and
52 * endpoint rings; it generates events on the event ring for these.
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
57 #include <linux/dma-mapping.h>
59 #include "xhci-trace.h"
63 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
66 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
69 unsigned long segment_offset;
71 if (!seg || !trb || trb < seg->trbs)
74 segment_offset = trb - seg->trbs;
75 if (segment_offset >= TRBS_PER_SEGMENT)
77 return seg->dma + (segment_offset * sizeof(*trb));
80 static bool trb_is_noop(union xhci_trb *trb)
82 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
85 static bool trb_is_link(union xhci_trb *trb)
87 return TRB_TYPE_LINK_LE32(trb->link.control);
90 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
92 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
95 static bool last_trb_on_ring(struct xhci_ring *ring,
96 struct xhci_segment *seg, union xhci_trb *trb)
98 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
101 static bool link_trb_toggles_cycle(union xhci_trb *trb)
103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
106 static bool last_td_in_urb(struct xhci_td *td)
108 struct urb_priv *urb_priv = td->urb->hcpriv;
110 return urb_priv->num_tds_done == urb_priv->num_tds;
113 static void inc_td_cnt(struct urb *urb)
115 struct urb_priv *urb_priv = urb->hcpriv;
117 urb_priv->num_tds_done++;
120 static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
122 if (trb_is_link(trb)) {
123 /* unchain chained link TRBs */
124 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
126 trb->generic.field[0] = 0;
127 trb->generic.field[1] = 0;
128 trb->generic.field[2] = 0;
129 /* Preserve only the cycle bit of this TRB */
130 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
131 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
135 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
136 * TRB is in a new segment. This does not skip over link TRBs, and it does not
137 * effect the ring dequeue or enqueue pointers.
139 static void next_trb(struct xhci_hcd *xhci,
140 struct xhci_ring *ring,
141 struct xhci_segment **seg,
142 union xhci_trb **trb)
144 if (trb_is_link(*trb)) {
146 *trb = ((*seg)->trbs);
153 * See Cycle bit rules. SW is the consumer for the event ring only.
154 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
156 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
158 /* event ring doesn't have link trbs, check for last trb */
159 if (ring->type == TYPE_EVENT) {
160 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
164 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
165 ring->cycle_state ^= 1;
166 ring->deq_seg = ring->deq_seg->next;
167 ring->dequeue = ring->deq_seg->trbs;
171 /* All other rings have link trbs */
172 if (!trb_is_link(ring->dequeue)) {
174 ring->num_trbs_free++;
176 while (trb_is_link(ring->dequeue)) {
177 ring->deq_seg = ring->deq_seg->next;
178 ring->dequeue = ring->deq_seg->trbs;
182 trace_xhci_inc_deq(ring);
188 * See Cycle bit rules. SW is the consumer for the event ring only.
189 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
191 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
192 * chain bit is set), then set the chain bit in all the following link TRBs.
193 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
194 * have their chain bit cleared (so that each Link TRB is a separate TD).
196 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
197 * set, but other sections talk about dealing with the chain bit set. This was
198 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
199 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
201 * @more_trbs_coming: Will you enqueue more TRBs before calling
202 * prepare_transfer()?
204 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
205 bool more_trbs_coming)
208 union xhci_trb *next;
210 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
211 /* If this is not event ring, there is one less usable TRB */
212 if (!trb_is_link(ring->enqueue))
213 ring->num_trbs_free--;
214 next = ++(ring->enqueue);
216 /* Update the dequeue pointer further if that was a link TRB */
217 while (trb_is_link(next)) {
220 * If the caller doesn't plan on enqueueing more TDs before
221 * ringing the doorbell, then we don't want to give the link TRB
222 * to the hardware just yet. We'll give the link TRB back in
223 * prepare_ring() just before we enqueue the TD at the top of
226 if (!chain && !more_trbs_coming)
229 /* If we're not dealing with 0.95 hardware or isoc rings on
230 * AMD 0.96 host, carry over the chain bit of the previous TRB
231 * (which may mean the chain bit is cleared).
233 if (!(ring->type == TYPE_ISOC &&
234 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
235 !xhci_link_trb_quirk(xhci)) {
236 next->link.control &= cpu_to_le32(~TRB_CHAIN);
237 next->link.control |= cpu_to_le32(chain);
239 /* Give this link TRB to the hardware */
241 next->link.control ^= cpu_to_le32(TRB_CYCLE);
243 /* Toggle the cycle bit after the last ring segment. */
244 if (link_trb_toggles_cycle(next))
245 ring->cycle_state ^= 1;
247 ring->enq_seg = ring->enq_seg->next;
248 ring->enqueue = ring->enq_seg->trbs;
249 next = ring->enqueue;
252 trace_xhci_inc_enq(ring);
256 * Check to see if there's room to enqueue num_trbs on the ring and make sure
257 * enqueue pointer will not advance into dequeue segment. See rules above.
259 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
260 unsigned int num_trbs)
262 int num_trbs_in_deq_seg;
264 if (ring->num_trbs_free < num_trbs)
267 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
268 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
269 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
276 /* Ring the host controller doorbell after placing a command on the ring */
277 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
279 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
282 xhci_dbg(xhci, "// Ding dong!\n");
284 trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST);
286 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
287 /* Flush PCI posted writes */
288 readl(&xhci->dba->doorbell[0]);
291 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
293 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
296 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
298 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
303 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
304 * If there are other commands waiting then restart the ring and kick the timer.
305 * This must be called with command ring stopped and xhci->lock held.
307 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
308 struct xhci_command *cur_cmd)
310 struct xhci_command *i_cmd;
312 /* Turn all aborted commands in list to no-ops, then restart */
313 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
315 if (i_cmd->status != COMP_COMMAND_ABORTED)
318 i_cmd->status = COMP_COMMAND_RING_STOPPED;
320 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
323 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
326 * caller waiting for completion is called when command
327 * completion event is received for these no-op commands
331 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
333 /* ring command ring doorbell to restart the command ring */
334 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
335 !(xhci->xhc_state & XHCI_STATE_DYING)) {
336 xhci->current_cmd = cur_cmd;
337 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
338 xhci_ring_cmd_db(xhci);
342 /* Must be called with xhci->lock held, releases and aquires lock back */
343 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
348 xhci_dbg(xhci, "Abort command ring\n");
350 reinit_completion(&xhci->cmd_ring_stop_completion);
352 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
353 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
354 &xhci->op_regs->cmd_ring);
356 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
357 * completion of the Command Abort operation. If CRR is not negated in 5
358 * seconds then driver handles it as if host died (-ENODEV).
359 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
360 * and try to recover a -ETIMEDOUT with a host controller reset.
362 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
363 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
365 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
371 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
372 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
373 * but the completion event in never sent. Wait 2 secs (arbitrary
374 * number) to handle those cases after negation of CMD_RING_RUNNING.
376 spin_unlock_irqrestore(&xhci->lock, flags);
377 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
378 msecs_to_jiffies(2000));
379 spin_lock_irqsave(&xhci->lock, flags);
381 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
382 xhci_cleanup_command_queue(xhci);
384 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
389 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
390 unsigned int slot_id,
391 unsigned int ep_index,
392 unsigned int stream_id)
394 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
395 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
396 unsigned int ep_state = ep->ep_state;
398 /* Don't ring the doorbell for this endpoint if there are pending
399 * cancellations because we don't want to interrupt processing.
400 * We don't want to restart any stream rings if there's a set dequeue
401 * pointer command pending because the device can choose to start any
402 * stream once the endpoint is on the HW schedule.
404 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
405 (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT))
408 trace_xhci_ring_ep_doorbell(slot_id, DB_VALUE(ep_index, stream_id));
410 writel(DB_VALUE(ep_index, stream_id), db_addr);
411 /* The CPU has better things to do at this point than wait for a
412 * write-posting flush. It'll get there soon enough.
416 /* Ring the doorbell for any rings with pending URBs */
417 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
418 unsigned int slot_id,
419 unsigned int ep_index)
421 unsigned int stream_id;
422 struct xhci_virt_ep *ep;
424 ep = &xhci->devs[slot_id]->eps[ep_index];
426 /* A ring has pending URBs if its TD list is not empty */
427 if (!(ep->ep_state & EP_HAS_STREAMS)) {
428 if (ep->ring && !(list_empty(&ep->ring->td_list)))
429 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
433 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
435 struct xhci_stream_info *stream_info = ep->stream_info;
436 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
437 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
442 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
443 unsigned int slot_id,
444 unsigned int ep_index)
446 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
449 /* Get the right ring for the given slot_id, ep_index and stream_id.
450 * If the endpoint supports streams, boundary check the URB's stream ID.
451 * If the endpoint doesn't support streams, return the singular endpoint ring.
453 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
454 unsigned int slot_id, unsigned int ep_index,
455 unsigned int stream_id)
457 struct xhci_virt_ep *ep;
459 ep = &xhci->devs[slot_id]->eps[ep_index];
460 /* Common case: no streams */
461 if (!(ep->ep_state & EP_HAS_STREAMS))
464 if (stream_id == 0) {
466 "WARN: Slot ID %u, ep index %u has streams, "
467 "but URB has no stream ID.\n",
472 if (stream_id < ep->stream_info->num_streams)
473 return ep->stream_info->stream_rings[stream_id];
476 "WARN: Slot ID %u, ep index %u has "
477 "stream IDs 1 to %u allocated, "
478 "but stream ID %u is requested.\n",
480 ep->stream_info->num_streams - 1,
487 * Get the hw dequeue pointer xHC stopped on, either directly from the
488 * endpoint context, or if streams are in use from the stream context.
489 * The returned hw_dequeue contains the lowest four bits with cycle state
490 * and possbile stream context type.
492 static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
493 unsigned int ep_index, unsigned int stream_id)
495 struct xhci_ep_ctx *ep_ctx;
496 struct xhci_stream_ctx *st_ctx;
497 struct xhci_virt_ep *ep;
499 ep = &vdev->eps[ep_index];
501 if (ep->ep_state & EP_HAS_STREAMS) {
502 st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
503 return le64_to_cpu(st_ctx->stream_ring);
505 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
506 return le64_to_cpu(ep_ctx->deq);
510 * Move the xHC's endpoint ring dequeue pointer past cur_td.
511 * Record the new state of the xHC's endpoint ring dequeue segment,
512 * dequeue pointer, stream id, and new consumer cycle state in state.
513 * Update our internal representation of the ring's dequeue pointer.
515 * We do this in three jumps:
516 * - First we update our new ring state to be the same as when the xHC stopped.
517 * - Then we traverse the ring to find the segment that contains
518 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
519 * any link TRBs with the toggle cycle bit set.
520 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
521 * if we've moved it past a link TRB with the toggle cycle bit set.
523 * Some of the uses of xhci_generic_trb are grotty, but if they're done
524 * with correct __le32 accesses they should work fine. Only users of this are
527 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
528 unsigned int slot_id, unsigned int ep_index,
529 unsigned int stream_id, struct xhci_td *cur_td,
530 struct xhci_dequeue_state *state)
532 struct xhci_virt_device *dev = xhci->devs[slot_id];
533 struct xhci_virt_ep *ep = &dev->eps[ep_index];
534 struct xhci_ring *ep_ring;
535 struct xhci_segment *new_seg;
536 union xhci_trb *new_deq;
539 bool cycle_found = false;
540 bool td_last_trb_found = false;
542 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
543 ep_index, stream_id);
545 xhci_warn(xhci, "WARN can't find new dequeue state "
546 "for invalid stream ID %u.\n",
551 * A cancelled TD can complete with a stall if HW cached the trb.
552 * In this case driver can't find cur_td, but if the ring is empty we
553 * can move the dequeue pointer to the current enqueue position.
556 if (list_empty(&ep_ring->td_list)) {
557 state->new_deq_seg = ep_ring->enq_seg;
558 state->new_deq_ptr = ep_ring->enqueue;
559 state->new_cycle_state = ep_ring->cycle_state;
562 xhci_warn(xhci, "Can't find new dequeue state, missing cur_td\n");
567 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
568 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
569 "Finding endpoint context");
571 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
572 new_seg = ep_ring->deq_seg;
573 new_deq = ep_ring->dequeue;
574 state->new_cycle_state = hw_dequeue & 0x1;
575 state->stream_id = stream_id;
578 * We want to find the pointer, segment and cycle state of the new trb
579 * (the one after current TD's last_trb). We know the cycle state at
580 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
584 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
585 == (dma_addr_t)(hw_dequeue & ~0xf)) {
587 if (td_last_trb_found)
590 if (new_deq == cur_td->last_trb)
591 td_last_trb_found = true;
593 if (cycle_found && trb_is_link(new_deq) &&
594 link_trb_toggles_cycle(new_deq))
595 state->new_cycle_state ^= 0x1;
597 next_trb(xhci, ep_ring, &new_seg, &new_deq);
599 /* Search wrapped around, bail out */
600 if (new_deq == ep->ring->dequeue) {
601 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
602 state->new_deq_seg = NULL;
603 state->new_deq_ptr = NULL;
607 } while (!cycle_found || !td_last_trb_found);
609 state->new_deq_seg = new_seg;
610 state->new_deq_ptr = new_deq;
613 /* Don't update the ring cycle state for the producer (us). */
614 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
615 "Cycle state = 0x%x", state->new_cycle_state);
617 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
618 "New dequeue segment = %p (virtual)",
620 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
621 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
622 "New dequeue pointer = 0x%llx (DMA)",
623 (unsigned long long) addr);
626 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
627 * (The last TRB actually points to the ring enqueue pointer, which is not part
628 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
630 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
631 struct xhci_td *td, bool flip_cycle)
633 struct xhci_segment *seg = td->start_seg;
634 union xhci_trb *trb = td->first_trb;
637 trb_to_noop(trb, TRB_TR_NOOP);
639 /* flip cycle if asked to */
640 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
641 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
643 if (trb == td->last_trb)
646 next_trb(xhci, ep_ring, &seg, &trb);
650 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
651 struct xhci_virt_ep *ep)
653 ep->ep_state &= ~EP_STOP_CMD_PENDING;
654 /* Can't del_timer_sync in interrupt */
655 del_timer(&ep->stop_cmd_timer);
659 * Must be called with xhci->lock held in interrupt context,
660 * releases and re-acquires xhci->lock
662 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
663 struct xhci_td *cur_td, int status)
665 struct urb *urb = cur_td->urb;
666 struct urb_priv *urb_priv = urb->hcpriv;
667 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
669 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
670 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
671 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
672 if (xhci->quirks & XHCI_AMD_PLL_FIX)
673 usb_amd_quirk_pll_enable();
676 xhci_urb_free_priv(urb_priv);
677 usb_hcd_unlink_urb_from_ep(hcd, urb);
678 trace_xhci_urb_giveback(urb);
679 usb_hcd_giveback_urb(hcd, urb, status);
682 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
683 struct xhci_ring *ring, struct xhci_td *td)
685 struct device *dev = xhci_to_hcd(xhci)->self.controller;
686 struct xhci_segment *seg = td->bounce_seg;
687 struct urb *urb = td->urb;
690 if (!ring || !seg || !urb)
693 if (usb_urb_dir_out(urb)) {
694 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
699 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
701 /* for in tranfers we need to copy the data from bounce to sg */
703 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
704 seg->bounce_len, seg->bounce_offs);
705 if (len != seg->bounce_len)
706 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
707 len, seg->bounce_len);
709 memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf,
713 seg->bounce_offs = 0;
717 * When we get a command completion for a Stop Endpoint Command, we need to
718 * unlink any cancelled TDs from the ring. There are two ways to do that:
720 * 1. If the HW was in the middle of processing the TD that needs to be
721 * cancelled, then we must move the ring's dequeue pointer past the last TRB
722 * in the TD with a Set Dequeue Pointer Command.
723 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
724 * bit cleared) so that the HW will skip over them.
726 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
727 union xhci_trb *trb, struct xhci_event_cmd *event)
729 unsigned int ep_index;
730 struct xhci_ring *ep_ring;
731 struct xhci_virt_ep *ep;
732 struct xhci_td *cur_td = NULL;
733 struct xhci_td *last_unlinked_td;
734 struct xhci_ep_ctx *ep_ctx;
735 struct xhci_virt_device *vdev;
737 struct xhci_dequeue_state deq_state;
739 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
740 if (!xhci->devs[slot_id])
741 xhci_warn(xhci, "Stop endpoint command "
742 "completion for disabled slot %u\n",
747 memset(&deq_state, 0, sizeof(deq_state));
748 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
750 vdev = xhci->devs[slot_id];
751 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
752 trace_xhci_handle_cmd_stop_ep(ep_ctx);
754 ep = &xhci->devs[slot_id]->eps[ep_index];
755 last_unlinked_td = list_last_entry(&ep->cancelled_td_list,
756 struct xhci_td, cancelled_td_list);
758 if (list_empty(&ep->cancelled_td_list)) {
759 xhci_stop_watchdog_timer_in_irq(xhci, ep);
760 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
764 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
765 * We have the xHCI lock, so nothing can modify this list until we drop
766 * it. We're also in the event handler, so we can't get re-interrupted
767 * if another Stop Endpoint command completes
769 list_for_each_entry(cur_td, &ep->cancelled_td_list, cancelled_td_list) {
770 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
771 "Removing canceled TD starting at 0x%llx (dma).",
772 (unsigned long long)xhci_trb_virt_to_dma(
773 cur_td->start_seg, cur_td->first_trb));
774 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
776 /* This shouldn't happen unless a driver is mucking
777 * with the stream ID after submission. This will
778 * leave the TD on the hardware ring, and the hardware
779 * will try to execute it, and may access a buffer
780 * that has already been freed. In the best case, the
781 * hardware will execute it, and the event handler will
782 * ignore the completion event for that TD, since it was
783 * removed from the td_list for that endpoint. In
784 * short, don't muck with the stream ID after
787 xhci_warn(xhci, "WARN Cancelled URB %p "
788 "has invalid stream ID %u.\n",
790 cur_td->urb->stream_id);
791 goto remove_finished_td;
794 * If we stopped on the TD we need to cancel, then we have to
795 * move the xHC endpoint ring dequeue pointer past this TD.
797 hw_deq = xhci_get_hw_deq(xhci, vdev, ep_index,
798 cur_td->urb->stream_id);
801 if (trb_in_td(xhci, cur_td->start_seg, cur_td->first_trb,
802 cur_td->last_trb, hw_deq, false)) {
803 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
804 cur_td->urb->stream_id,
807 td_to_noop(xhci, ep_ring, cur_td, false);
812 * The event handler won't see a completion for this TD anymore,
813 * so remove it from the endpoint ring's TD list. Keep it in
814 * the cancelled TD list for URB completion later.
816 list_del_init(&cur_td->td_list);
819 xhci_stop_watchdog_timer_in_irq(xhci, ep);
821 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
822 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
823 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
825 xhci_ring_cmd_db(xhci);
827 /* Otherwise ring the doorbell(s) to restart queued transfers */
828 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
832 * Drop the lock and complete the URBs in the cancelled TD list.
833 * New TDs to be cancelled might be added to the end of the list before
834 * we can complete all the URBs for the TDs we already unlinked.
835 * So stop when we've completed the URB for the last TD we unlinked.
838 cur_td = list_first_entry(&ep->cancelled_td_list,
839 struct xhci_td, cancelled_td_list);
840 list_del_init(&cur_td->cancelled_td_list);
842 /* Clean up the cancelled URB */
843 /* Doesn't matter what we pass for status, since the core will
844 * just overwrite it (because the URB has been unlinked).
846 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
847 xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td);
848 inc_td_cnt(cur_td->urb);
849 if (last_td_in_urb(cur_td))
850 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
852 /* Stop processing the cancelled list if the watchdog timer is
855 if (xhci->xhc_state & XHCI_STATE_DYING)
857 } while (cur_td != last_unlinked_td);
859 /* Return to the event handler with xhci->lock re-acquired */
862 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
864 struct xhci_td *cur_td;
867 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
868 list_del_init(&cur_td->td_list);
870 if (!list_empty(&cur_td->cancelled_td_list))
871 list_del_init(&cur_td->cancelled_td_list);
873 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
875 inc_td_cnt(cur_td->urb);
876 if (last_td_in_urb(cur_td))
877 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
881 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
882 int slot_id, int ep_index)
884 struct xhci_td *cur_td;
886 struct xhci_virt_ep *ep;
887 struct xhci_ring *ring;
889 ep = &xhci->devs[slot_id]->eps[ep_index];
890 if ((ep->ep_state & EP_HAS_STREAMS) ||
891 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
894 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
896 ring = ep->stream_info->stream_rings[stream_id];
900 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
901 "Killing URBs for slot ID %u, ep index %u, stream %u",
902 slot_id, ep_index, stream_id);
903 xhci_kill_ring_urbs(xhci, ring);
909 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
910 "Killing URBs for slot ID %u, ep index %u",
912 xhci_kill_ring_urbs(xhci, ring);
915 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
917 list_del_init(&cur_td->cancelled_td_list);
918 inc_td_cnt(cur_td->urb);
920 if (last_td_in_urb(cur_td))
921 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
926 * host controller died, register read returns 0xffffffff
927 * Complete pending commands, mark them ABORTED.
928 * URBs need to be given back as usb core might be waiting with device locks
929 * held for the URBs to finish during device disconnect, blocking host remove.
931 * Call with xhci->lock held.
932 * lock is relased and re-acquired while giving back urb.
934 void xhci_hc_died(struct xhci_hcd *xhci)
938 if (xhci->xhc_state & XHCI_STATE_DYING)
941 xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
942 xhci->xhc_state |= XHCI_STATE_DYING;
944 xhci_cleanup_command_queue(xhci);
946 /* return any pending urbs, remove may be waiting for them */
947 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
950 for (j = 0; j < 31; j++)
951 xhci_kill_endpoint_urbs(xhci, i, j);
954 /* inform usb core hc died if PCI remove isn't already handling it */
955 if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
956 usb_hc_died(xhci_to_hcd(xhci));
959 /* Watchdog timer function for when a stop endpoint command fails to complete.
960 * In this case, we assume the host controller is broken or dying or dead. The
961 * host may still be completing some other events, so we have to be careful to
962 * let the event ring handler and the URB dequeueing/enqueueing functions know
963 * through xhci->state.
965 * The timer may also fire if the host takes a very long time to respond to the
966 * command, and the stop endpoint command completion handler cannot delete the
967 * timer before the timer function is called. Another endpoint cancellation may
968 * sneak in before the timer function can grab the lock, and that may queue
969 * another stop endpoint command and add the timer back. So we cannot use a
970 * simple flag to say whether there is a pending stop endpoint command for a
971 * particular endpoint.
973 * Instead we use a combination of that flag and checking if a new timer is
976 void xhci_stop_endpoint_command_watchdog(struct timer_list *t)
978 struct xhci_virt_ep *ep = from_timer(ep, t, stop_cmd_timer);
979 struct xhci_hcd *xhci = ep->xhci;
983 spin_lock_irqsave(&xhci->lock, flags);
985 /* bail out if cmd completed but raced with stop ep watchdog timer.*/
986 if (!(ep->ep_state & EP_STOP_CMD_PENDING) ||
987 timer_pending(&ep->stop_cmd_timer)) {
988 spin_unlock_irqrestore(&xhci->lock, flags);
989 xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit");
992 usbsts = readl(&xhci->op_regs->status);
994 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
995 xhci_warn(xhci, "USBSTS:%s\n", xhci_decode_usbsts(usbsts));
997 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1002 * handle a stop endpoint cmd timeout as if host died (-ENODEV).
1003 * In the future we could distinguish between -ENODEV and -ETIMEDOUT
1004 * and try to recover a -ETIMEDOUT with a host controller reset
1008 spin_unlock_irqrestore(&xhci->lock, flags);
1009 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1010 "xHCI host controller is dead.");
1013 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1014 struct xhci_virt_device *dev,
1015 struct xhci_ring *ep_ring,
1016 unsigned int ep_index)
1018 union xhci_trb *dequeue_temp;
1019 int num_trbs_free_temp;
1020 bool revert = false;
1022 num_trbs_free_temp = ep_ring->num_trbs_free;
1023 dequeue_temp = ep_ring->dequeue;
1025 /* If we get two back-to-back stalls, and the first stalled transfer
1026 * ends just before a link TRB, the dequeue pointer will be left on
1027 * the link TRB by the code in the while loop. So we have to update
1028 * the dequeue pointer one segment further, or we'll jump off
1029 * the segment into la-la-land.
1031 if (trb_is_link(ep_ring->dequeue)) {
1032 ep_ring->deq_seg = ep_ring->deq_seg->next;
1033 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1036 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1037 /* We have more usable TRBs */
1038 ep_ring->num_trbs_free++;
1040 if (trb_is_link(ep_ring->dequeue)) {
1041 if (ep_ring->dequeue ==
1042 dev->eps[ep_index].queued_deq_ptr)
1044 ep_ring->deq_seg = ep_ring->deq_seg->next;
1045 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1047 if (ep_ring->dequeue == dequeue_temp) {
1054 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1055 ep_ring->num_trbs_free = num_trbs_free_temp;
1060 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1061 * we need to clear the set deq pending flag in the endpoint ring state, so that
1062 * the TD queueing code can ring the doorbell again. We also need to ring the
1063 * endpoint doorbell to restart the ring, but only if there aren't more
1064 * cancellations pending.
1066 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1067 union xhci_trb *trb, u32 cmd_comp_code)
1069 unsigned int ep_index;
1070 unsigned int stream_id;
1071 struct xhci_ring *ep_ring;
1072 struct xhci_virt_device *dev;
1073 struct xhci_virt_ep *ep;
1074 struct xhci_ep_ctx *ep_ctx;
1075 struct xhci_slot_ctx *slot_ctx;
1077 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1078 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1079 dev = xhci->devs[slot_id];
1080 ep = &dev->eps[ep_index];
1082 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1084 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1086 /* XXX: Harmless??? */
1090 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1091 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1092 trace_xhci_handle_cmd_set_deq(slot_ctx);
1093 trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1095 if (cmd_comp_code != COMP_SUCCESS) {
1096 unsigned int ep_state;
1097 unsigned int slot_state;
1099 switch (cmd_comp_code) {
1100 case COMP_TRB_ERROR:
1101 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1103 case COMP_CONTEXT_STATE_ERROR:
1104 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1105 ep_state = GET_EP_CTX_STATE(ep_ctx);
1106 slot_state = le32_to_cpu(slot_ctx->dev_state);
1107 slot_state = GET_SLOT_STATE(slot_state);
1108 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1109 "Slot state = %u, EP state = %u",
1110 slot_state, ep_state);
1112 case COMP_SLOT_NOT_ENABLED_ERROR:
1113 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1117 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1121 /* OK what do we do now? The endpoint state is hosed, and we
1122 * should never get to this point if the synchronization between
1123 * queueing, and endpoint state are correct. This might happen
1124 * if the device gets disconnected after we've finished
1125 * cancelling URBs, which might not be an error...
1129 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1130 if (ep->ep_state & EP_HAS_STREAMS) {
1131 struct xhci_stream_ctx *ctx =
1132 &ep->stream_info->stream_ctx_array[stream_id];
1133 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1135 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1137 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1138 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1139 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1140 ep->queued_deq_ptr) == deq) {
1141 /* Update the ring's dequeue segment and dequeue pointer
1142 * to reflect the new position.
1144 update_ring_for_set_deq_completion(xhci, dev,
1147 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1148 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1149 ep->queued_deq_seg, ep->queued_deq_ptr);
1154 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1155 dev->eps[ep_index].queued_deq_seg = NULL;
1156 dev->eps[ep_index].queued_deq_ptr = NULL;
1157 /* Restart any rings with pending URBs */
1158 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1161 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1162 union xhci_trb *trb, u32 cmd_comp_code)
1164 struct xhci_virt_device *vdev;
1165 struct xhci_ep_ctx *ep_ctx;
1166 unsigned int ep_index;
1168 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1169 vdev = xhci->devs[slot_id];
1170 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
1171 trace_xhci_handle_cmd_reset_ep(ep_ctx);
1173 /* This command will only fail if the endpoint wasn't halted,
1174 * but we don't care.
1176 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1177 "Ignoring reset ep completion code of %u", cmd_comp_code);
1179 /* HW with the reset endpoint quirk needs to have a configure endpoint
1180 * command complete before the endpoint can be used. Queue that here
1181 * because the HW can't handle two commands being queued in a row.
1183 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1184 struct xhci_command *command;
1186 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1190 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1191 "Queueing configure endpoint command");
1192 xhci_queue_configure_endpoint(xhci, command,
1193 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1195 xhci_ring_cmd_db(xhci);
1197 /* Clear our internal halted state */
1198 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1201 /* if this was a soft reset, then restart */
1202 if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP)
1203 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1206 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1207 struct xhci_command *command, u32 cmd_comp_code)
1209 if (cmd_comp_code == COMP_SUCCESS)
1210 command->slot_id = slot_id;
1212 command->slot_id = 0;
1215 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1217 struct xhci_virt_device *virt_dev;
1218 struct xhci_slot_ctx *slot_ctx;
1220 virt_dev = xhci->devs[slot_id];
1224 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1225 trace_xhci_handle_cmd_disable_slot(slot_ctx);
1227 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1228 /* Delete default control endpoint resources */
1229 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1230 xhci_free_virt_device(xhci, slot_id);
1233 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1234 struct xhci_event_cmd *event, u32 cmd_comp_code)
1236 struct xhci_virt_device *virt_dev;
1237 struct xhci_input_control_ctx *ctrl_ctx;
1238 struct xhci_ep_ctx *ep_ctx;
1239 unsigned int ep_index;
1240 unsigned int ep_state;
1241 u32 add_flags, drop_flags;
1244 * Configure endpoint commands can come from the USB core
1245 * configuration or alt setting changes, or because the HW
1246 * needed an extra configure endpoint command after a reset
1247 * endpoint command or streams were being configured.
1248 * If the command was for a halted endpoint, the xHCI driver
1249 * is not waiting on the configure endpoint command.
1251 virt_dev = xhci->devs[slot_id];
1252 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1254 xhci_warn(xhci, "Could not get input context, bad type.\n");
1258 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1259 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1260 /* Input ctx add_flags are the endpoint index plus one */
1261 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1263 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1264 trace_xhci_handle_cmd_config_ep(ep_ctx);
1266 /* A usb_set_interface() call directly after clearing a halted
1267 * condition may race on this quirky hardware. Not worth
1268 * worrying about, since this is prototype hardware. Not sure
1269 * if this will work for streams, but streams support was
1270 * untested on this prototype.
1272 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1273 ep_index != (unsigned int) -1 &&
1274 add_flags - SLOT_FLAG == drop_flags) {
1275 ep_state = virt_dev->eps[ep_index].ep_state;
1276 if (!(ep_state & EP_HALTED))
1278 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1279 "Completed config ep cmd - "
1280 "last ep index = %d, state = %d",
1281 ep_index, ep_state);
1282 /* Clear internal halted state and restart ring(s) */
1283 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1284 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1290 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1292 struct xhci_virt_device *vdev;
1293 struct xhci_slot_ctx *slot_ctx;
1295 vdev = xhci->devs[slot_id];
1296 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1297 trace_xhci_handle_cmd_addr_dev(slot_ctx);
1300 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1301 struct xhci_event_cmd *event)
1303 struct xhci_virt_device *vdev;
1304 struct xhci_slot_ctx *slot_ctx;
1306 vdev = xhci->devs[slot_id];
1307 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1308 trace_xhci_handle_cmd_reset_dev(slot_ctx);
1310 xhci_dbg(xhci, "Completed reset device command.\n");
1311 if (!xhci->devs[slot_id])
1312 xhci_warn(xhci, "Reset device command completion "
1313 "for disabled slot %u\n", slot_id);
1316 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1317 struct xhci_event_cmd *event)
1319 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1320 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1323 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1324 "NEC firmware version %2x.%02x",
1325 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1326 NEC_FW_MINOR(le32_to_cpu(event->status)));
1329 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1331 list_del(&cmd->cmd_list);
1333 if (cmd->completion) {
1334 cmd->status = status;
1335 complete(cmd->completion);
1341 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1343 struct xhci_command *cur_cmd, *tmp_cmd;
1344 xhci->current_cmd = NULL;
1345 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1346 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1349 void xhci_handle_command_timeout(struct work_struct *work)
1351 struct xhci_hcd *xhci;
1352 unsigned long flags;
1355 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1357 spin_lock_irqsave(&xhci->lock, flags);
1360 * If timeout work is pending, or current_cmd is NULL, it means we
1361 * raced with command completion. Command is handled so just return.
1363 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1364 spin_unlock_irqrestore(&xhci->lock, flags);
1367 /* mark this command to be cancelled */
1368 xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1370 /* Make sure command ring is running before aborting it */
1371 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1372 if (hw_ring_state == ~(u64)0) {
1374 goto time_out_completed;
1377 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1378 (hw_ring_state & CMD_RING_RUNNING)) {
1379 /* Prevent new doorbell, and start command abort */
1380 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1381 xhci_dbg(xhci, "Command timeout\n");
1382 xhci_abort_cmd_ring(xhci, flags);
1383 goto time_out_completed;
1386 /* host removed. Bail out */
1387 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1388 xhci_dbg(xhci, "host removed, ring start fail?\n");
1389 xhci_cleanup_command_queue(xhci);
1391 goto time_out_completed;
1394 /* command timeout on stopped ring, ring can't be aborted */
1395 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1396 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1399 spin_unlock_irqrestore(&xhci->lock, flags);
1403 static void handle_cmd_completion(struct xhci_hcd *xhci,
1404 struct xhci_event_cmd *event)
1406 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1408 dma_addr_t cmd_dequeue_dma;
1410 union xhci_trb *cmd_trb;
1411 struct xhci_command *cmd;
1414 cmd_dma = le64_to_cpu(event->cmd_trb);
1415 cmd_trb = xhci->cmd_ring->dequeue;
1417 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1419 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1422 * Check whether the completion event is for our internal kept
1425 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1427 "ERROR mismatched command completion event\n");
1431 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1433 cancel_delayed_work(&xhci->cmd_timer);
1435 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1437 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1438 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1439 complete_all(&xhci->cmd_ring_stop_completion);
1443 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1445 "Command completion event does not match command\n");
1450 * Host aborted the command ring, check if the current command was
1451 * supposed to be aborted, otherwise continue normally.
1452 * The command ring is stopped now, but the xHC will issue a Command
1453 * Ring Stopped event which will cause us to restart it.
1455 if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1456 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1457 if (cmd->status == COMP_COMMAND_ABORTED) {
1458 if (xhci->current_cmd == cmd)
1459 xhci->current_cmd = NULL;
1464 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1466 case TRB_ENABLE_SLOT:
1467 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1469 case TRB_DISABLE_SLOT:
1470 xhci_handle_cmd_disable_slot(xhci, slot_id);
1473 if (!cmd->completion)
1474 xhci_handle_cmd_config_ep(xhci, slot_id, event,
1477 case TRB_EVAL_CONTEXT:
1480 xhci_handle_cmd_addr_dev(xhci, slot_id);
1483 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1484 le32_to_cpu(cmd_trb->generic.field[3])));
1485 if (!cmd->completion)
1486 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1489 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1490 le32_to_cpu(cmd_trb->generic.field[3])));
1491 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1494 /* Is this an aborted command turned to NO-OP? */
1495 if (cmd->status == COMP_COMMAND_RING_STOPPED)
1496 cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1499 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1500 le32_to_cpu(cmd_trb->generic.field[3])));
1501 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1504 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1505 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1507 slot_id = TRB_TO_SLOT_ID(
1508 le32_to_cpu(cmd_trb->generic.field[3]));
1509 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1511 case TRB_NEC_GET_FW:
1512 xhci_handle_cmd_nec_get_fw(xhci, event);
1515 /* Skip over unknown commands on the event ring */
1516 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1520 /* restart timer if this wasn't the last command */
1521 if (!list_is_singular(&xhci->cmd_list)) {
1522 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1523 struct xhci_command, cmd_list);
1524 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1525 } else if (xhci->current_cmd == cmd) {
1526 xhci->current_cmd = NULL;
1530 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1532 inc_deq(xhci, xhci->cmd_ring);
1535 static void handle_vendor_event(struct xhci_hcd *xhci,
1536 union xhci_trb *event)
1540 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1541 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1542 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1543 handle_cmd_completion(xhci, &event->event_cmd);
1546 static void handle_device_notification(struct xhci_hcd *xhci,
1547 union xhci_trb *event)
1550 struct usb_device *udev;
1552 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1553 if (!xhci->devs[slot_id]) {
1554 xhci_warn(xhci, "Device Notification event for "
1555 "unused slot %u\n", slot_id);
1559 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1561 udev = xhci->devs[slot_id]->udev;
1562 if (udev && udev->parent)
1563 usb_wakeup_notification(udev->parent, udev->portnum);
1567 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1569 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1570 * If a connection to a USB 1 device is followed by another connection
1571 * to a USB 2 device.
1573 * Reset the PHY after the USB device is disconnected if device speed
1574 * is less than HCD_USB3.
1575 * Retry the reset sequence max of 4 times checking the PLL lock status.
1578 static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1580 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1582 u32 retry_count = 4;
1585 /* Assert PHY reset */
1586 writel(0x6F, hcd->regs + 0x1048);
1588 /* De-assert the PHY reset */
1589 writel(0x7F, hcd->regs + 0x1048);
1591 pll_lock_check = readl(hcd->regs + 0x1070);
1592 } while (!(pll_lock_check & 0x1) && --retry_count);
1595 static void handle_port_status(struct xhci_hcd *xhci,
1596 union xhci_trb *event)
1598 struct usb_hcd *hcd;
1600 u32 portsc, cmd_reg;
1603 unsigned int hcd_portnum;
1604 struct xhci_bus_state *bus_state;
1605 bool bogus_port_status = false;
1606 struct xhci_port *port;
1608 /* Port status change events always have a successful completion code */
1609 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1611 "WARN: xHC returned failed port status event\n");
1613 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1614 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1616 if ((port_id <= 0) || (port_id > max_ports)) {
1617 xhci_warn(xhci, "Port change event with invalid port ID %d\n",
1619 inc_deq(xhci, xhci->event_ring);
1623 port = &xhci->hw_ports[port_id - 1];
1624 if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
1625 xhci_warn(xhci, "Port change event, no port for port ID %u\n",
1627 bogus_port_status = true;
1631 /* We might get interrupts after shared_hcd is removed */
1632 if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
1633 xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
1634 bogus_port_status = true;
1638 hcd = port->rhub->hcd;
1639 bus_state = &port->rhub->bus_state;
1640 hcd_portnum = port->hcd_portnum;
1641 portsc = readl(port->addr);
1643 xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n",
1644 hcd->self.busnum, hcd_portnum + 1, port_id, portsc);
1646 trace_xhci_handle_port_status(hcd_portnum, portsc);
1648 if (hcd->state == HC_STATE_SUSPENDED) {
1649 xhci_dbg(xhci, "resume root hub\n");
1650 usb_hcd_resume_root_hub(hcd);
1653 if (hcd->speed >= HCD_USB3 &&
1654 (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
1655 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1656 if (slot_id && xhci->devs[slot_id])
1657 xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR;
1660 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1661 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1663 cmd_reg = readl(&xhci->op_regs->command);
1664 if (!(cmd_reg & CMD_RUN)) {
1665 xhci_warn(xhci, "xHC is not running.\n");
1669 if (DEV_SUPERSPEED_ANY(portsc)) {
1670 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1671 /* Set a flag to say the port signaled remote wakeup,
1672 * so we can tell the difference between the end of
1673 * device and host initiated resume.
1675 bus_state->port_remote_wakeup |= 1 << hcd_portnum;
1676 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1677 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1678 xhci_set_link_state(xhci, port, XDEV_U0);
1679 /* Need to wait until the next link state change
1680 * indicates the device is actually in U0.
1682 bogus_port_status = true;
1684 } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
1685 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1686 bus_state->resume_done[hcd_portnum] = jiffies +
1687 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1688 set_bit(hcd_portnum, &bus_state->resuming_ports);
1689 /* Do the rest in GetPortStatus after resume time delay.
1690 * Avoid polling roothub status before that so that a
1691 * usb device auto-resume latency around ~40ms.
1693 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1694 mod_timer(&hcd->rh_timer,
1695 bus_state->resume_done[hcd_portnum]);
1696 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1697 bogus_port_status = true;
1701 if ((portsc & PORT_PLC) &&
1702 DEV_SUPERSPEED_ANY(portsc) &&
1703 ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
1704 (portsc & PORT_PLS_MASK) == XDEV_U1 ||
1705 (portsc & PORT_PLS_MASK) == XDEV_U2)) {
1706 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1707 complete(&bus_state->u3exit_done[hcd_portnum]);
1708 /* We've just brought the device into U0/1/2 through either the
1709 * Resume state after a device remote wakeup, or through the
1710 * U3Exit state after a host-initiated resume. If it's a device
1711 * initiated remote wake, don't pass up the link state change,
1712 * so the roothub behavior is consistent with external
1713 * USB 3.0 hub behavior.
1715 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1716 if (slot_id && xhci->devs[slot_id])
1717 xhci_ring_device(xhci, slot_id);
1718 if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
1719 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1720 usb_wakeup_notification(hcd->self.root_hub,
1722 bogus_port_status = true;
1728 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1729 * RExit to a disconnect state). If so, let the the driver know it's
1730 * out of the RExit state.
1732 if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 &&
1733 test_and_clear_bit(hcd_portnum,
1734 &bus_state->rexit_ports)) {
1735 complete(&bus_state->rexit_done[hcd_portnum]);
1736 bogus_port_status = true;
1740 if (hcd->speed < HCD_USB3) {
1741 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1742 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
1743 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
1744 xhci_cavium_reset_phy_quirk(xhci);
1748 /* Update event ring dequeue pointer before dropping the lock */
1749 inc_deq(xhci, xhci->event_ring);
1751 /* Don't make the USB core poll the roothub if we got a bad port status
1752 * change event. Besides, at that point we can't tell which roothub
1753 * (USB 2.0 or USB 3.0) to kick.
1755 if (bogus_port_status)
1759 * xHCI port-status-change events occur when the "or" of all the
1760 * status-change bits in the portsc register changes from 0 to 1.
1761 * New status changes won't cause an event if any other change
1762 * bits are still set. When an event occurs, switch over to
1763 * polling to avoid losing status changes.
1765 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1766 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1767 spin_unlock(&xhci->lock);
1768 /* Pass this up to the core */
1769 usb_hcd_poll_rh_status(hcd);
1770 spin_lock(&xhci->lock);
1774 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1775 * at end_trb, which may be in another segment. If the suspect DMA address is a
1776 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1779 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1780 struct xhci_segment *start_seg,
1781 union xhci_trb *start_trb,
1782 union xhci_trb *end_trb,
1783 dma_addr_t suspect_dma,
1786 dma_addr_t start_dma;
1787 dma_addr_t end_seg_dma;
1788 dma_addr_t end_trb_dma;
1789 struct xhci_segment *cur_seg;
1791 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1792 cur_seg = start_seg;
1797 /* We may get an event for a Link TRB in the middle of a TD */
1798 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1799 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1800 /* If the end TRB isn't in this segment, this is set to 0 */
1801 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1805 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1806 (unsigned long long)suspect_dma,
1807 (unsigned long long)start_dma,
1808 (unsigned long long)end_trb_dma,
1809 (unsigned long long)cur_seg->dma,
1810 (unsigned long long)end_seg_dma);
1812 if (end_trb_dma > 0) {
1813 /* The end TRB is in this segment, so suspect should be here */
1814 if (start_dma <= end_trb_dma) {
1815 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1818 /* Case for one segment with
1819 * a TD wrapped around to the top
1821 if ((suspect_dma >= start_dma &&
1822 suspect_dma <= end_seg_dma) ||
1823 (suspect_dma >= cur_seg->dma &&
1824 suspect_dma <= end_trb_dma))
1829 /* Might still be somewhere in this segment */
1830 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1833 cur_seg = cur_seg->next;
1834 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1835 } while (cur_seg != start_seg);
1840 static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td,
1841 struct xhci_virt_ep *ep)
1844 * As part of low/full-speed endpoint-halt processing
1845 * we must clear the TT buffer (USB 2.0 specification 11.17.5).
1847 if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) &&
1848 (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) &&
1849 !(ep->ep_state & EP_CLEARING_TT)) {
1850 ep->ep_state |= EP_CLEARING_TT;
1851 td->urb->ep->hcpriv = td->urb->dev;
1852 if (usb_hub_clear_tt_buffer(td->urb))
1853 ep->ep_state &= ~EP_CLEARING_TT;
1857 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1858 unsigned int slot_id, unsigned int ep_index,
1859 unsigned int stream_id, struct xhci_td *td,
1860 enum xhci_ep_reset_type reset_type)
1862 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1863 struct xhci_command *command;
1866 * Avoid resetting endpoint if link is inactive. Can cause host hang.
1867 * Device will be reset soon to recover the link so don't do anything
1869 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR)
1872 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1876 ep->ep_state |= EP_HALTED;
1878 xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
1880 if (reset_type == EP_HARD_RESET) {
1881 ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
1882 xhci_cleanup_stalled_ring(xhci, slot_id, ep_index, stream_id,
1885 xhci_ring_cmd_db(xhci);
1888 /* Check if an error has halted the endpoint ring. The class driver will
1889 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1890 * However, a babble and other errors also halt the endpoint ring, and the class
1891 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1892 * Ring Dequeue Pointer command manually.
1894 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1895 struct xhci_ep_ctx *ep_ctx,
1896 unsigned int trb_comp_code)
1898 /* TRB completion codes that may require a manual halt cleanup */
1899 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
1900 trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
1901 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
1902 /* The 0.95 spec says a babbling control endpoint
1903 * is not halted. The 0.96 spec says it is. Some HW
1904 * claims to be 0.95 compliant, but it halts the control
1905 * endpoint anyway. Check if a babble halted the
1908 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
1914 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1916 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1917 /* Vendor defined "informational" completion code,
1918 * treat as not-an-error.
1920 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1922 xhci_dbg(xhci, "Treating code as success.\n");
1928 static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
1929 struct xhci_ring *ep_ring, int *status)
1931 struct urb *urb = NULL;
1933 /* Clean up the endpoint's TD list */
1936 /* if a bounce buffer was used to align this td then unmap it */
1937 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
1939 /* Do one last check of the actual transfer length.
1940 * If the host controller said we transferred more data than the buffer
1941 * length, urb->actual_length will be a very big number (since it's
1942 * unsigned). Play it safe and say we didn't transfer anything.
1944 if (urb->actual_length > urb->transfer_buffer_length) {
1945 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
1946 urb->transfer_buffer_length, urb->actual_length);
1947 urb->actual_length = 0;
1950 list_del_init(&td->td_list);
1951 /* Was this TD slated to be cancelled but completed anyway? */
1952 if (!list_empty(&td->cancelled_td_list))
1953 list_del_init(&td->cancelled_td_list);
1956 /* Giveback the urb when all the tds are completed */
1957 if (last_td_in_urb(td)) {
1958 if ((urb->actual_length != urb->transfer_buffer_length &&
1959 (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
1960 (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
1961 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
1962 urb, urb->actual_length,
1963 urb->transfer_buffer_length, *status);
1965 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
1966 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
1968 xhci_giveback_urb_in_irq(xhci, td, *status);
1974 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1975 struct xhci_transfer_event *event,
1976 struct xhci_virt_ep *ep, int *status)
1978 struct xhci_virt_device *xdev;
1979 struct xhci_ep_ctx *ep_ctx;
1980 struct xhci_ring *ep_ring;
1981 unsigned int slot_id;
1985 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1986 xdev = xhci->devs[slot_id];
1987 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1988 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1989 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1990 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1992 if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
1993 trb_comp_code == COMP_STOPPED ||
1994 trb_comp_code == COMP_STOPPED_SHORT_PACKET) {
1995 /* The Endpoint Stop Command completion will take care of any
1996 * stopped TDs. A stopped TD may be restarted, so don't update
1997 * the ring dequeue pointer or take this TD off any lists yet.
2001 if (trb_comp_code == COMP_STALL_ERROR ||
2002 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2005 * xhci internal endpoint state will go to a "halt" state for
2006 * any stall, including default control pipe protocol stall.
2007 * To clear the host side halt we need to issue a reset endpoint
2008 * command, followed by a set dequeue command to move past the
2010 * Class drivers clear the device side halt from a functional
2011 * stall later. Hub TT buffer should only be cleared for FS/LS
2012 * devices behind HS hubs for functional stalls.
2014 if ((ep_index != 0) || (trb_comp_code != COMP_STALL_ERROR))
2015 xhci_clear_hub_tt_buffer(xhci, td, ep);
2016 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
2017 ep_ring->stream_id, td, EP_HARD_RESET);
2019 /* Update ring dequeue pointer */
2020 while (ep_ring->dequeue != td->last_trb)
2021 inc_deq(xhci, ep_ring);
2022 inc_deq(xhci, ep_ring);
2025 return xhci_td_cleanup(xhci, td, ep_ring, status);
2028 /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
2029 static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
2030 union xhci_trb *stop_trb)
2033 union xhci_trb *trb = ring->dequeue;
2034 struct xhci_segment *seg = ring->deq_seg;
2036 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
2037 if (!trb_is_noop(trb) && !trb_is_link(trb))
2038 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
2044 * Process control tds, update urb status and actual_length.
2046 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
2047 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2048 struct xhci_virt_ep *ep, int *status)
2050 struct xhci_virt_device *xdev;
2051 unsigned int slot_id;
2053 struct xhci_ep_ctx *ep_ctx;
2055 u32 remaining, requested;
2058 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2059 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2060 xdev = xhci->devs[slot_id];
2061 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2062 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2063 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2064 requested = td->urb->transfer_buffer_length;
2065 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2067 switch (trb_comp_code) {
2069 if (trb_type != TRB_STATUS) {
2070 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2071 (trb_type == TRB_DATA) ? "data" : "setup");
2072 *status = -ESHUTDOWN;
2077 case COMP_SHORT_PACKET:
2080 case COMP_STOPPED_SHORT_PACKET:
2081 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2082 td->urb->actual_length = remaining;
2084 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2089 td->urb->actual_length = 0;
2093 td->urb->actual_length = requested - remaining;
2096 td->urb->actual_length = requested;
2099 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2103 case COMP_STOPPED_LENGTH_INVALID:
2106 if (!xhci_requires_manual_halt_cleanup(xhci,
2107 ep_ctx, trb_comp_code))
2109 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2110 trb_comp_code, ep_index);
2112 case COMP_STALL_ERROR:
2113 /* Did we transfer part of the data (middle) phase? */
2114 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2115 td->urb->actual_length = requested - remaining;
2116 else if (!td->urb_length_set)
2117 td->urb->actual_length = 0;
2121 /* stopped at setup stage, no data transferred */
2122 if (trb_type == TRB_SETUP)
2126 * if on data stage then update the actual_length of the URB and flag it
2127 * as set, so it won't be overwritten in the event for the last TRB.
2129 if (trb_type == TRB_DATA ||
2130 trb_type == TRB_NORMAL) {
2131 td->urb_length_set = true;
2132 td->urb->actual_length = requested - remaining;
2133 xhci_dbg(xhci, "Waiting for status stage event\n");
2137 /* at status stage */
2138 if (!td->urb_length_set)
2139 td->urb->actual_length = requested;
2142 return finish_td(xhci, td, event, ep, status);
2146 * Process isochronous tds, update urb packet status and actual_length.
2148 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2149 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2150 struct xhci_virt_ep *ep, int *status)
2152 struct xhci_ring *ep_ring;
2153 struct urb_priv *urb_priv;
2155 struct usb_iso_packet_descriptor *frame;
2157 bool sum_trbs_for_length = false;
2158 u32 remaining, requested, ep_trb_len;
2159 int short_framestatus;
2161 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2162 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2163 urb_priv = td->urb->hcpriv;
2164 idx = urb_priv->num_tds_done;
2165 frame = &td->urb->iso_frame_desc[idx];
2166 requested = frame->length;
2167 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2168 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2169 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2172 /* handle completion code */
2173 switch (trb_comp_code) {
2176 frame->status = short_framestatus;
2177 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2178 sum_trbs_for_length = true;
2183 case COMP_SHORT_PACKET:
2184 frame->status = short_framestatus;
2185 sum_trbs_for_length = true;
2187 case COMP_BANDWIDTH_OVERRUN_ERROR:
2188 frame->status = -ECOMM;
2190 case COMP_ISOCH_BUFFER_OVERRUN:
2191 case COMP_BABBLE_DETECTED_ERROR:
2192 frame->status = -EOVERFLOW;
2194 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2195 case COMP_STALL_ERROR:
2196 frame->status = -EPROTO;
2198 case COMP_USB_TRANSACTION_ERROR:
2199 frame->status = -EPROTO;
2200 if (ep_trb != td->last_trb)
2204 sum_trbs_for_length = true;
2206 case COMP_STOPPED_SHORT_PACKET:
2207 /* field normally containing residue now contains tranferred */
2208 frame->status = short_framestatus;
2209 requested = remaining;
2211 case COMP_STOPPED_LENGTH_INVALID:
2216 sum_trbs_for_length = true;
2221 if (sum_trbs_for_length)
2222 frame->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb) +
2223 ep_trb_len - remaining;
2225 frame->actual_length = requested;
2227 td->urb->actual_length += frame->actual_length;
2229 return finish_td(xhci, td, event, ep, status);
2232 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2233 struct xhci_transfer_event *event,
2234 struct xhci_virt_ep *ep, int *status)
2236 struct xhci_ring *ep_ring;
2237 struct urb_priv *urb_priv;
2238 struct usb_iso_packet_descriptor *frame;
2241 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2242 urb_priv = td->urb->hcpriv;
2243 idx = urb_priv->num_tds_done;
2244 frame = &td->urb->iso_frame_desc[idx];
2246 /* The transfer is partly done. */
2247 frame->status = -EXDEV;
2249 /* calc actual length */
2250 frame->actual_length = 0;
2252 /* Update ring dequeue pointer */
2253 while (ep_ring->dequeue != td->last_trb)
2254 inc_deq(xhci, ep_ring);
2255 inc_deq(xhci, ep_ring);
2257 return xhci_td_cleanup(xhci, td, ep_ring, status);
2261 * Process bulk and interrupt tds, update urb status and actual_length.
2263 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2264 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2265 struct xhci_virt_ep *ep, int *status)
2267 struct xhci_slot_ctx *slot_ctx;
2268 struct xhci_ring *ep_ring;
2270 u32 remaining, requested, ep_trb_len;
2271 unsigned int slot_id;
2274 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2275 slot_ctx = xhci_get_slot_ctx(xhci, xhci->devs[slot_id]->out_ctx);
2276 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2277 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2278 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2279 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2280 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2281 requested = td->urb->transfer_buffer_length;
2283 switch (trb_comp_code) {
2285 ep_ring->err_count = 0;
2286 /* handle success with untransferred data as short packet */
2287 if (ep_trb != td->last_trb || remaining) {
2288 xhci_warn(xhci, "WARN Successful completion on short TX\n");
2289 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2290 td->urb->ep->desc.bEndpointAddress,
2291 requested, remaining);
2295 case COMP_SHORT_PACKET:
2296 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2297 td->urb->ep->desc.bEndpointAddress,
2298 requested, remaining);
2301 case COMP_STOPPED_SHORT_PACKET:
2302 td->urb->actual_length = remaining;
2304 case COMP_STOPPED_LENGTH_INVALID:
2305 /* stopped on ep trb with invalid length, exclude it */
2309 case COMP_USB_TRANSACTION_ERROR:
2310 if ((ep_ring->err_count++ > MAX_SOFT_RETRY) ||
2311 le32_to_cpu(slot_ctx->tt_info) & TT_SLOT)
2314 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
2315 ep_ring->stream_id, td, EP_SOFT_RESET);
2322 if (ep_trb == td->last_trb)
2323 td->urb->actual_length = requested - remaining;
2325 td->urb->actual_length =
2326 sum_trb_lengths(xhci, ep_ring, ep_trb) +
2327 ep_trb_len - remaining;
2329 if (remaining > requested) {
2330 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2332 td->urb->actual_length = 0;
2334 return finish_td(xhci, td, event, ep, status);
2338 * If this function returns an error condition, it means it got a Transfer
2339 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2340 * At this point, the host controller is probably hosed and should be reset.
2342 static int handle_tx_event(struct xhci_hcd *xhci,
2343 struct xhci_transfer_event *event)
2345 struct xhci_virt_device *xdev;
2346 struct xhci_virt_ep *ep;
2347 struct xhci_ring *ep_ring;
2348 unsigned int slot_id;
2350 struct xhci_td *td = NULL;
2351 dma_addr_t ep_trb_dma;
2352 struct xhci_segment *ep_seg;
2353 union xhci_trb *ep_trb;
2354 int status = -EINPROGRESS;
2355 struct xhci_ep_ctx *ep_ctx;
2356 struct list_head *tmp;
2359 bool handling_skipped_tds = false;
2361 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2362 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2363 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2364 ep_trb_dma = le64_to_cpu(event->buffer);
2366 xdev = xhci->devs[slot_id];
2368 xhci_err(xhci, "ERROR Transfer event pointed to bad slot %u\n",
2373 ep = &xdev->eps[ep_index];
2374 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2375 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2377 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2379 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2384 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2386 switch (trb_comp_code) {
2387 case COMP_STALL_ERROR:
2388 case COMP_USB_TRANSACTION_ERROR:
2389 case COMP_INVALID_STREAM_TYPE_ERROR:
2390 case COMP_INVALID_STREAM_ID_ERROR:
2391 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, 0,
2392 NULL, EP_SOFT_RESET);
2394 case COMP_RING_UNDERRUN:
2395 case COMP_RING_OVERRUN:
2396 case COMP_STOPPED_LENGTH_INVALID:
2399 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2405 /* Count current td numbers if ep->skip is set */
2407 list_for_each(tmp, &ep_ring->td_list)
2411 /* Look for common error cases */
2412 switch (trb_comp_code) {
2413 /* Skip codes that require special handling depending on
2417 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2419 if (xhci->quirks & XHCI_TRUST_TX_LENGTH ||
2420 ep_ring->last_td_was_short)
2421 trb_comp_code = COMP_SHORT_PACKET;
2423 xhci_warn_ratelimited(xhci,
2424 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2427 case COMP_SHORT_PACKET:
2429 /* Completion codes for endpoint stopped state */
2431 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2434 case COMP_STOPPED_LENGTH_INVALID:
2436 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2439 case COMP_STOPPED_SHORT_PACKET:
2441 "Stopped with short packet transfer detected for slot %u ep %u\n",
2444 /* Completion codes for endpoint halted state */
2445 case COMP_STALL_ERROR:
2446 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2448 ep->ep_state |= EP_HALTED;
2451 case COMP_SPLIT_TRANSACTION_ERROR:
2452 xhci_dbg(xhci, "Split transaction error for slot %u ep %u\n",
2456 case COMP_USB_TRANSACTION_ERROR:
2457 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2461 case COMP_BABBLE_DETECTED_ERROR:
2462 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2464 status = -EOVERFLOW;
2466 /* Completion codes for endpoint error state */
2467 case COMP_TRB_ERROR:
2469 "WARN: TRB error for slot %u ep %u on endpoint\n",
2473 /* completion codes not indicating endpoint state change */
2474 case COMP_DATA_BUFFER_ERROR:
2476 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2480 case COMP_BANDWIDTH_OVERRUN_ERROR:
2482 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2485 case COMP_ISOCH_BUFFER_OVERRUN:
2487 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2490 case COMP_RING_UNDERRUN:
2492 * When the Isoch ring is empty, the xHC will generate
2493 * a Ring Overrun Event for IN Isoch endpoint or Ring
2494 * Underrun Event for OUT Isoch endpoint.
2496 xhci_dbg(xhci, "underrun event on endpoint\n");
2497 if (!list_empty(&ep_ring->td_list))
2498 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2499 "still with TDs queued?\n",
2500 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2503 case COMP_RING_OVERRUN:
2504 xhci_dbg(xhci, "overrun event on endpoint\n");
2505 if (!list_empty(&ep_ring->td_list))
2506 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2507 "still with TDs queued?\n",
2508 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2511 case COMP_MISSED_SERVICE_ERROR:
2513 * When encounter missed service error, one or more isoc tds
2514 * may be missed by xHC.
2515 * Set skip flag of the ep_ring; Complete the missed tds as
2516 * short transfer when process the ep_ring next time.
2520 "Miss service interval error for slot %u ep %u, set skip flag\n",
2523 case COMP_NO_PING_RESPONSE_ERROR:
2526 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2530 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2531 /* needs disable slot command to recover */
2533 "WARN: detect an incompatible device for slot %u ep %u",
2538 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2543 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2544 trb_comp_code, slot_id, ep_index);
2549 /* This TRB should be in the TD at the head of this ring's
2552 if (list_empty(&ep_ring->td_list)) {
2554 * Don't print wanings if it's due to a stopped endpoint
2555 * generating an extra completion event if the device
2556 * was suspended. Or, a event for the last TRB of a
2557 * short TD we already got a short event for.
2558 * The short TD is already removed from the TD list.
2561 if (!(trb_comp_code == COMP_STOPPED ||
2562 trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2563 ep_ring->last_td_was_short)) {
2564 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2565 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2570 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2573 if (trb_comp_code == COMP_STALL_ERROR ||
2574 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2576 xhci_cleanup_halted_endpoint(xhci, slot_id,
2585 /* We've skipped all the TDs on the ep ring when ep->skip set */
2586 if (ep->skip && td_num == 0) {
2588 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2593 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2598 /* Is this a TRB in the currently executing TD? */
2599 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2600 td->last_trb, ep_trb_dma, false);
2603 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2604 * is not in the current TD pointed by ep_ring->dequeue because
2605 * that the hardware dequeue pointer still at the previous TRB
2606 * of the current TD. The previous TRB maybe a Link TD or the
2607 * last TRB of the previous TD. The command completion handle
2608 * will take care the rest.
2610 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2611 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2617 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2618 /* Some host controllers give a spurious
2619 * successful event after a short transfer.
2622 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2623 ep_ring->last_td_was_short) {
2624 ep_ring->last_td_was_short = false;
2627 /* HC is busted, give up! */
2629 "ERROR Transfer event TRB DMA ptr not "
2630 "part of current TD ep_index %d "
2631 "comp_code %u\n", ep_index,
2633 trb_in_td(xhci, ep_ring->deq_seg,
2634 ep_ring->dequeue, td->last_trb,
2639 skip_isoc_td(xhci, td, event, ep, &status);
2642 if (trb_comp_code == COMP_SHORT_PACKET)
2643 ep_ring->last_td_was_short = true;
2645 ep_ring->last_td_was_short = false;
2649 "Found td. Clear skip flag for slot %u ep %u.\n",
2654 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2657 trace_xhci_handle_transfer(ep_ring,
2658 (struct xhci_generic_trb *) ep_trb);
2661 * No-op TRB could trigger interrupts in a case where
2662 * a URB was killed and a STALL_ERROR happens right
2663 * after the endpoint ring stopped. Reset the halted
2664 * endpoint. Otherwise, the endpoint remains stalled
2667 if (trb_is_noop(ep_trb)) {
2668 if (trb_comp_code == COMP_STALL_ERROR ||
2669 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2671 xhci_cleanup_halted_endpoint(xhci, slot_id,
2678 /* update the urb's actual_length and give back to the core */
2679 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2680 process_ctrl_td(xhci, td, ep_trb, event, ep, &status);
2681 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2682 process_isoc_td(xhci, td, ep_trb, event, ep, &status);
2684 process_bulk_intr_td(xhci, td, ep_trb, event, ep,
2687 handling_skipped_tds = ep->skip &&
2688 trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2689 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2692 * Do not update event ring dequeue pointer if we're in a loop
2693 * processing missed tds.
2695 if (!handling_skipped_tds)
2696 inc_deq(xhci, xhci->event_ring);
2699 * If ep->skip is set, it means there are missed tds on the
2700 * endpoint ring need to take care of.
2701 * Process them as short transfer until reach the td pointed by
2704 } while (handling_skipped_tds);
2709 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2710 (unsigned long long) xhci_trb_virt_to_dma(
2711 xhci->event_ring->deq_seg,
2712 xhci->event_ring->dequeue),
2713 lower_32_bits(le64_to_cpu(event->buffer)),
2714 upper_32_bits(le64_to_cpu(event->buffer)),
2715 le32_to_cpu(event->transfer_len),
2716 le32_to_cpu(event->flags));
2721 * This function handles all OS-owned events on the event ring. It may drop
2722 * xhci->lock between event processing (e.g. to pass up port status changes).
2723 * Returns >0 for "possibly more events to process" (caller should call again),
2724 * otherwise 0 if done. In future, <0 returns should indicate error code.
2726 static int xhci_handle_event(struct xhci_hcd *xhci)
2728 union xhci_trb *event;
2729 int update_ptrs = 1;
2732 /* Event ring hasn't been allocated yet. */
2733 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2734 xhci_err(xhci, "ERROR event ring not ready\n");
2738 event = xhci->event_ring->dequeue;
2739 /* Does the HC or OS own the TRB? */
2740 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2741 xhci->event_ring->cycle_state)
2744 trace_xhci_handle_event(xhci->event_ring, &event->generic);
2747 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2748 * speculative reads of the event's flags/data below.
2751 /* FIXME: Handle more event types. */
2752 switch (le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) {
2753 case TRB_TYPE(TRB_COMPLETION):
2754 handle_cmd_completion(xhci, &event->event_cmd);
2756 case TRB_TYPE(TRB_PORT_STATUS):
2757 handle_port_status(xhci, event);
2760 case TRB_TYPE(TRB_TRANSFER):
2761 ret = handle_tx_event(xhci, &event->trans_event);
2765 case TRB_TYPE(TRB_DEV_NOTE):
2766 handle_device_notification(xhci, event);
2769 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2771 handle_vendor_event(xhci, event);
2773 xhci_warn(xhci, "ERROR unknown event type %d\n",
2775 le32_to_cpu(event->event_cmd.flags)));
2777 /* Any of the above functions may drop and re-acquire the lock, so check
2778 * to make sure a watchdog timer didn't mark the host as non-responsive.
2780 if (xhci->xhc_state & XHCI_STATE_DYING) {
2781 xhci_dbg(xhci, "xHCI host dying, returning from "
2782 "event handler.\n");
2787 /* Update SW event ring dequeue pointer */
2788 inc_deq(xhci, xhci->event_ring);
2790 /* Are there more items on the event ring? Caller will call us again to
2797 * Update Event Ring Dequeue Pointer:
2798 * - When all events have finished
2799 * - To avoid "Event Ring Full Error" condition
2801 static void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
2802 union xhci_trb *event_ring_deq)
2807 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2808 /* If necessary, update the HW's version of the event ring deq ptr. */
2809 if (event_ring_deq != xhci->event_ring->dequeue) {
2810 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2811 xhci->event_ring->dequeue);
2813 xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n");
2815 * Per 4.9.4, Software writes to the ERDP register shall
2816 * always advance the Event Ring Dequeue Pointer value.
2818 if ((temp_64 & (u64) ~ERST_PTR_MASK) ==
2819 ((u64) deq & (u64) ~ERST_PTR_MASK))
2822 /* Update HC event ring dequeue pointer */
2823 temp_64 &= ERST_PTR_MASK;
2824 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2827 /* Clear the event handler busy flag (RW1C) */
2828 temp_64 |= ERST_EHB;
2829 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2833 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2834 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2835 * indicators of an event TRB error, but we check the status *first* to be safe.
2837 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2839 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2840 union xhci_trb *event_ring_deq;
2841 irqreturn_t ret = IRQ_NONE;
2842 unsigned long flags;
2847 spin_lock_irqsave(&xhci->lock, flags);
2848 /* Check if the xHC generated the interrupt, or the irq is shared */
2849 status = readl(&xhci->op_regs->status);
2850 if (status == ~(u32)0) {
2856 if (!(status & STS_EINT))
2859 if (status & STS_FATAL) {
2860 xhci_warn(xhci, "WARNING: Host System Error\n");
2867 * Clear the op reg interrupt status first,
2868 * so we can receive interrupts from other MSI-X interrupters.
2869 * Write 1 to clear the interrupt status.
2872 writel(status, &xhci->op_regs->status);
2874 if (!hcd->msi_enabled) {
2876 irq_pending = readl(&xhci->ir_set->irq_pending);
2877 irq_pending |= IMAN_IP;
2878 writel(irq_pending, &xhci->ir_set->irq_pending);
2881 if (xhci->xhc_state & XHCI_STATE_DYING ||
2882 xhci->xhc_state & XHCI_STATE_HALTED) {
2883 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2884 "Shouldn't IRQs be disabled?\n");
2885 /* Clear the event handler busy flag (RW1C);
2886 * the event ring should be empty.
2888 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2889 xhci_write_64(xhci, temp_64 | ERST_EHB,
2890 &xhci->ir_set->erst_dequeue);
2895 event_ring_deq = xhci->event_ring->dequeue;
2896 /* FIXME this should be a delayed service routine
2897 * that clears the EHB.
2899 while (xhci_handle_event(xhci) > 0) {
2900 if (event_loop++ < TRBS_PER_SEGMENT / 2)
2902 xhci_update_erst_dequeue(xhci, event_ring_deq);
2906 xhci_update_erst_dequeue(xhci, event_ring_deq);
2910 spin_unlock_irqrestore(&xhci->lock, flags);
2915 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2917 return xhci_irq(hcd);
2920 /**** Endpoint Ring Operations ****/
2923 * Generic function for queueing a TRB on a ring.
2924 * The caller must have checked to make sure there's room on the ring.
2926 * @more_trbs_coming: Will you enqueue more TRBs before calling
2927 * prepare_transfer()?
2929 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2930 bool more_trbs_coming,
2931 u32 field1, u32 field2, u32 field3, u32 field4)
2933 struct xhci_generic_trb *trb;
2935 trb = &ring->enqueue->generic;
2936 trb->field[0] = cpu_to_le32(field1);
2937 trb->field[1] = cpu_to_le32(field2);
2938 trb->field[2] = cpu_to_le32(field3);
2939 /* make sure TRB is fully written before giving it to the controller */
2941 trb->field[3] = cpu_to_le32(field4);
2943 trace_xhci_queue_trb(ring, trb);
2945 inc_enq(xhci, ring, more_trbs_coming);
2949 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2950 * FIXME allocate segments if the ring is full.
2952 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2953 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2955 unsigned int num_trbs_needed;
2957 /* Make sure the endpoint has been added to xHC schedule */
2959 case EP_STATE_DISABLED:
2961 * USB core changed config/interfaces without notifying us,
2962 * or hardware is reporting the wrong state.
2964 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2966 case EP_STATE_ERROR:
2967 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2968 /* FIXME event handling code for error needs to clear it */
2969 /* XXX not sure if this should be -ENOENT or not */
2971 case EP_STATE_HALTED:
2972 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2974 case EP_STATE_STOPPED:
2975 case EP_STATE_RUNNING:
2978 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2980 * FIXME issue Configure Endpoint command to try to get the HC
2981 * back into a known state.
2987 if (room_on_ring(xhci, ep_ring, num_trbs))
2990 if (ep_ring == xhci->cmd_ring) {
2991 xhci_err(xhci, "Do not support expand command ring\n");
2995 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2996 "ERROR no room on ep ring, try ring expansion");
2997 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2998 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
3000 xhci_err(xhci, "Ring expansion failed\n");
3005 while (trb_is_link(ep_ring->enqueue)) {
3006 /* If we're not dealing with 0.95 hardware or isoc rings
3007 * on AMD 0.96 host, clear the chain bit.
3009 if (!xhci_link_trb_quirk(xhci) &&
3010 !(ep_ring->type == TYPE_ISOC &&
3011 (xhci->quirks & XHCI_AMD_0x96_HOST)))
3012 ep_ring->enqueue->link.control &=
3013 cpu_to_le32(~TRB_CHAIN);
3015 ep_ring->enqueue->link.control |=
3016 cpu_to_le32(TRB_CHAIN);
3019 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
3021 /* Toggle the cycle bit after the last ring segment. */
3022 if (link_trb_toggles_cycle(ep_ring->enqueue))
3023 ep_ring->cycle_state ^= 1;
3025 ep_ring->enq_seg = ep_ring->enq_seg->next;
3026 ep_ring->enqueue = ep_ring->enq_seg->trbs;
3031 static int prepare_transfer(struct xhci_hcd *xhci,
3032 struct xhci_virt_device *xdev,
3033 unsigned int ep_index,
3034 unsigned int stream_id,
3035 unsigned int num_trbs,
3037 unsigned int td_index,
3041 struct urb_priv *urb_priv;
3043 struct xhci_ring *ep_ring;
3044 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3046 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
3048 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3053 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3054 num_trbs, mem_flags);
3058 urb_priv = urb->hcpriv;
3059 td = &urb_priv->td[td_index];
3061 INIT_LIST_HEAD(&td->td_list);
3062 INIT_LIST_HEAD(&td->cancelled_td_list);
3064 if (td_index == 0) {
3065 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3071 /* Add this TD to the tail of the endpoint ring's TD list */
3072 list_add_tail(&td->td_list, &ep_ring->td_list);
3073 td->start_seg = ep_ring->enq_seg;
3074 td->first_trb = ep_ring->enqueue;
3079 unsigned int count_trbs(u64 addr, u64 len)
3081 unsigned int num_trbs;
3083 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3091 static inline unsigned int count_trbs_needed(struct urb *urb)
3093 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3096 static unsigned int count_sg_trbs_needed(struct urb *urb)
3098 struct scatterlist *sg;
3099 unsigned int i, len, full_len, num_trbs = 0;
3101 full_len = urb->transfer_buffer_length;
3103 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3104 len = sg_dma_len(sg);
3105 num_trbs += count_trbs(sg_dma_address(sg), len);
3106 len = min_t(unsigned int, len, full_len);
3115 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3119 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3120 len = urb->iso_frame_desc[i].length;
3122 return count_trbs(addr, len);
3125 static void check_trb_math(struct urb *urb, int running_total)
3127 if (unlikely(running_total != urb->transfer_buffer_length))
3128 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3129 "queued %#x (%d), asked for %#x (%d)\n",
3131 urb->ep->desc.bEndpointAddress,
3132 running_total, running_total,
3133 urb->transfer_buffer_length,
3134 urb->transfer_buffer_length);
3137 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3138 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3139 struct xhci_generic_trb *start_trb)
3142 * Pass all the TRBs to the hardware at once and make sure this write
3147 start_trb->field[3] |= cpu_to_le32(start_cycle);
3149 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3150 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3153 static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3154 struct xhci_ep_ctx *ep_ctx)
3159 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3160 ep_interval = urb->interval;
3162 /* Convert to microframes */
3163 if (urb->dev->speed == USB_SPEED_LOW ||
3164 urb->dev->speed == USB_SPEED_FULL)
3167 /* FIXME change this to a warning and a suggestion to use the new API
3168 * to set the polling interval (once the API is added).
3170 if (xhci_interval != ep_interval) {
3171 dev_dbg_ratelimited(&urb->dev->dev,
3172 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3173 ep_interval, ep_interval == 1 ? "" : "s",
3174 xhci_interval, xhci_interval == 1 ? "" : "s");
3175 urb->interval = xhci_interval;
3176 /* Convert back to frames for LS/FS devices */
3177 if (urb->dev->speed == USB_SPEED_LOW ||
3178 urb->dev->speed == USB_SPEED_FULL)
3184 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3185 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3186 * (comprised of sg list entries) can take several service intervals to
3189 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3190 struct urb *urb, int slot_id, unsigned int ep_index)
3192 struct xhci_ep_ctx *ep_ctx;
3194 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3195 check_interval(xhci, urb, ep_ctx);
3197 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3201 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3202 * packets remaining in the TD (*not* including this TRB).
3204 * Total TD packet count = total_packet_count =
3205 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3207 * Packets transferred up to and including this TRB = packets_transferred =
3208 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3210 * TD size = total_packet_count - packets_transferred
3212 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3213 * including this TRB, right shifted by 10
3215 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3216 * This is taken care of in the TRB_TD_SIZE() macro
3218 * The last TRB in a TD must have the TD size set to zero.
3220 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3221 int trb_buff_len, unsigned int td_total_len,
3222 struct urb *urb, bool more_trbs_coming)
3224 u32 maxp, total_packet_count;
3226 /* MTK xHCI 0.96 contains some features from 1.0 */
3227 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3228 return ((td_total_len - transferred) >> 10);
3230 /* One TRB with a zero-length data packet. */
3231 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3232 trb_buff_len == td_total_len)
3235 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3236 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3239 maxp = usb_endpoint_maxp(&urb->ep->desc);
3240 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3242 /* Queueing functions don't count the current TRB into transferred */
3243 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3247 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3248 u32 *trb_buff_len, struct xhci_segment *seg)
3250 struct device *dev = xhci_to_hcd(xhci)->self.controller;
3251 unsigned int unalign;
3252 unsigned int max_pkt;
3256 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3257 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3259 /* we got lucky, last normal TRB data on segment is packet aligned */
3263 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3264 unalign, *trb_buff_len);
3266 /* is the last nornal TRB alignable by splitting it */
3267 if (*trb_buff_len > unalign) {
3268 *trb_buff_len -= unalign;
3269 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3274 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3275 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3276 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3278 new_buff_len = max_pkt - (enqd_len % max_pkt);
3280 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3281 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3283 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3284 if (usb_urb_dir_out(urb)) {
3286 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3287 seg->bounce_buf, new_buff_len, enqd_len);
3288 if (len != new_buff_len)
3289 xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n",
3292 memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len);
3295 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3296 max_pkt, DMA_TO_DEVICE);
3298 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3299 max_pkt, DMA_FROM_DEVICE);
3302 if (dma_mapping_error(dev, seg->bounce_dma)) {
3303 /* try without aligning. Some host controllers survive */
3304 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3307 *trb_buff_len = new_buff_len;
3308 seg->bounce_len = new_buff_len;
3309 seg->bounce_offs = enqd_len;
3311 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3316 /* This is very similar to what ehci-q.c qtd_fill() does */
3317 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3318 struct urb *urb, int slot_id, unsigned int ep_index)
3320 struct xhci_ring *ring;
3321 struct urb_priv *urb_priv;
3323 struct xhci_generic_trb *start_trb;
3324 struct scatterlist *sg = NULL;
3325 bool more_trbs_coming = true;
3326 bool need_zero_pkt = false;
3327 bool first_trb = true;
3328 unsigned int num_trbs;
3329 unsigned int start_cycle, num_sgs = 0;
3330 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3332 u32 field, length_field, remainder;
3333 u64 addr, send_addr;
3335 ring = xhci_urb_to_transfer_ring(xhci, urb);
3339 full_len = urb->transfer_buffer_length;
3340 /* If we have scatter/gather list, we use it. */
3341 if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) {
3342 num_sgs = urb->num_mapped_sgs;
3344 addr = (u64) sg_dma_address(sg);
3345 block_len = sg_dma_len(sg);
3346 num_trbs = count_sg_trbs_needed(urb);
3348 num_trbs = count_trbs_needed(urb);
3349 addr = (u64) urb->transfer_dma;
3350 block_len = full_len;
3352 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3353 ep_index, urb->stream_id,
3354 num_trbs, urb, 0, mem_flags);
3355 if (unlikely(ret < 0))
3358 urb_priv = urb->hcpriv;
3360 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3361 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3362 need_zero_pkt = true;
3364 td = &urb_priv->td[0];
3367 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3368 * until we've finished creating all the other TRBs. The ring's cycle
3369 * state may change as we enqueue the other TRBs, so save it too.
3371 start_trb = &ring->enqueue->generic;
3372 start_cycle = ring->cycle_state;
3375 /* Queue the TRBs, even if they are zero-length */
3376 for (enqd_len = 0; first_trb || enqd_len < full_len;
3377 enqd_len += trb_buff_len) {
3378 field = TRB_TYPE(TRB_NORMAL);
3380 /* TRB buffer should not cross 64KB boundaries */
3381 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3382 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3384 if (enqd_len + trb_buff_len > full_len)
3385 trb_buff_len = full_len - enqd_len;
3387 /* Don't change the cycle bit of the first TRB until later */
3390 if (start_cycle == 0)
3393 field |= ring->cycle_state;
3395 /* Chain all the TRBs together; clear the chain bit in the last
3396 * TRB to indicate it's the last TRB in the chain.
3398 if (enqd_len + trb_buff_len < full_len) {
3400 if (trb_is_link(ring->enqueue + 1)) {
3401 if (xhci_align_td(xhci, urb, enqd_len,
3404 send_addr = ring->enq_seg->bounce_dma;
3405 /* assuming TD won't span 2 segs */
3406 td->bounce_seg = ring->enq_seg;
3410 if (enqd_len + trb_buff_len >= full_len) {
3411 field &= ~TRB_CHAIN;
3413 more_trbs_coming = false;
3414 td->last_trb = ring->enqueue;
3416 if (xhci_urb_suitable_for_idt(urb)) {
3417 memcpy(&send_addr, urb->transfer_buffer,
3419 le64_to_cpus(&send_addr);
3424 /* Only set interrupt on short packet for IN endpoints */
3425 if (usb_urb_dir_in(urb))
3428 /* Set the TRB length, TD size, and interrupter fields. */
3429 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3430 full_len, urb, more_trbs_coming);
3432 length_field = TRB_LEN(trb_buff_len) |
3433 TRB_TD_SIZE(remainder) |
3436 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3437 lower_32_bits(send_addr),
3438 upper_32_bits(send_addr),
3442 addr += trb_buff_len;
3443 sent_len = trb_buff_len;
3445 while (sg && sent_len >= block_len) {
3448 sent_len -= block_len;
3450 if (num_sgs != 0 && sg) {
3451 block_len = sg_dma_len(sg);
3452 addr = (u64) sg_dma_address(sg);
3456 block_len -= sent_len;
3460 if (need_zero_pkt) {
3461 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3462 ep_index, urb->stream_id,
3463 1, urb, 1, mem_flags);
3464 urb_priv->td[1].last_trb = ring->enqueue;
3465 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3466 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3469 check_trb_math(urb, enqd_len);
3470 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3471 start_cycle, start_trb);
3475 /* Caller must have locked xhci->lock */
3476 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3477 struct urb *urb, int slot_id, unsigned int ep_index)
3479 struct xhci_ring *ep_ring;
3482 struct usb_ctrlrequest *setup;
3483 struct xhci_generic_trb *start_trb;
3486 struct urb_priv *urb_priv;
3489 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3494 * Need to copy setup packet into setup TRB, so we can't use the setup
3497 if (!urb->setup_packet)
3500 /* 1 TRB for setup, 1 for status */
3503 * Don't need to check if we need additional event data and normal TRBs,
3504 * since data in control transfers will never get bigger than 16MB
3505 * XXX: can we get a buffer that crosses 64KB boundaries?
3507 if (urb->transfer_buffer_length > 0)
3509 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3510 ep_index, urb->stream_id,
3511 num_trbs, urb, 0, mem_flags);
3515 urb_priv = urb->hcpriv;
3516 td = &urb_priv->td[0];
3519 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3520 * until we've finished creating all the other TRBs. The ring's cycle
3521 * state may change as we enqueue the other TRBs, so save it too.
3523 start_trb = &ep_ring->enqueue->generic;
3524 start_cycle = ep_ring->cycle_state;
3526 /* Queue setup TRB - see section 6.4.1.2.1 */
3527 /* FIXME better way to translate setup_packet into two u32 fields? */
3528 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3530 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3531 if (start_cycle == 0)
3534 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3535 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3536 if (urb->transfer_buffer_length > 0) {
3537 if (setup->bRequestType & USB_DIR_IN)
3538 field |= TRB_TX_TYPE(TRB_DATA_IN);
3540 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3544 queue_trb(xhci, ep_ring, true,
3545 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3546 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3547 TRB_LEN(8) | TRB_INTR_TARGET(0),
3548 /* Immediate data in pointer */
3551 /* If there's data, queue data TRBs */
3552 /* Only set interrupt on short packet for IN endpoints */
3553 if (usb_urb_dir_in(urb))
3554 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3556 field = TRB_TYPE(TRB_DATA);
3558 if (urb->transfer_buffer_length > 0) {
3559 u32 length_field, remainder;
3562 if (xhci_urb_suitable_for_idt(urb)) {
3563 memcpy(&addr, urb->transfer_buffer,
3564 urb->transfer_buffer_length);
3565 le64_to_cpus(&addr);
3568 addr = (u64) urb->transfer_dma;
3571 remainder = xhci_td_remainder(xhci, 0,
3572 urb->transfer_buffer_length,
3573 urb->transfer_buffer_length,
3575 length_field = TRB_LEN(urb->transfer_buffer_length) |
3576 TRB_TD_SIZE(remainder) |
3578 if (setup->bRequestType & USB_DIR_IN)
3579 field |= TRB_DIR_IN;
3580 queue_trb(xhci, ep_ring, true,
3581 lower_32_bits(addr),
3582 upper_32_bits(addr),
3584 field | ep_ring->cycle_state);
3587 /* Save the DMA address of the last TRB in the TD */
3588 td->last_trb = ep_ring->enqueue;
3590 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3591 /* If the device sent data, the status stage is an OUT transfer */
3592 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3596 queue_trb(xhci, ep_ring, false,
3600 /* Event on completion */
3601 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3603 giveback_first_trb(xhci, slot_id, ep_index, 0,
3604 start_cycle, start_trb);
3609 * The transfer burst count field of the isochronous TRB defines the number of
3610 * bursts that are required to move all packets in this TD. Only SuperSpeed
3611 * devices can burst up to bMaxBurst number of packets per service interval.
3612 * This field is zero based, meaning a value of zero in the field means one
3613 * burst. Basically, for everything but SuperSpeed devices, this field will be
3614 * zero. Only xHCI 1.0 host controllers support this field.
3616 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3617 struct urb *urb, unsigned int total_packet_count)
3619 unsigned int max_burst;
3621 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3624 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3625 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3629 * Returns the number of packets in the last "burst" of packets. This field is
3630 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3631 * the last burst packet count is equal to the total number of packets in the
3632 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3633 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3634 * contain 1 to (bMaxBurst + 1) packets.
3636 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3637 struct urb *urb, unsigned int total_packet_count)
3639 unsigned int max_burst;
3640 unsigned int residue;
3642 if (xhci->hci_version < 0x100)
3645 if (urb->dev->speed >= USB_SPEED_SUPER) {
3646 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3647 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3648 residue = total_packet_count % (max_burst + 1);
3649 /* If residue is zero, the last burst contains (max_burst + 1)
3650 * number of packets, but the TLBPC field is zero-based.
3656 if (total_packet_count == 0)
3658 return total_packet_count - 1;
3662 * Calculates Frame ID field of the isochronous TRB identifies the
3663 * target frame that the Interval associated with this Isochronous
3664 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3666 * Returns actual frame id on success, negative value on error.
3668 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3669 struct urb *urb, int index)
3671 int start_frame, ist, ret = 0;
3672 int start_frame_id, end_frame_id, current_frame_id;
3674 if (urb->dev->speed == USB_SPEED_LOW ||
3675 urb->dev->speed == USB_SPEED_FULL)
3676 start_frame = urb->start_frame + index * urb->interval;
3678 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3680 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3682 * If bit [3] of IST is cleared to '0', software can add a TRB no
3683 * later than IST[2:0] Microframes before that TRB is scheduled to
3685 * If bit [3] of IST is set to '1', software can add a TRB no later
3686 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3688 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3689 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3692 /* Software shall not schedule an Isoch TD with a Frame ID value that
3693 * is less than the Start Frame ID or greater than the End Frame ID,
3696 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3697 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3699 * Both the End Frame ID and Start Frame ID values are calculated
3700 * in microframes. When software determines the valid Frame ID value;
3701 * The End Frame ID value should be rounded down to the nearest Frame
3702 * boundary, and the Start Frame ID value should be rounded up to the
3703 * nearest Frame boundary.
3705 current_frame_id = readl(&xhci->run_regs->microframe_index);
3706 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3707 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3709 start_frame &= 0x7ff;
3710 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3711 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3713 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3714 __func__, index, readl(&xhci->run_regs->microframe_index),
3715 start_frame_id, end_frame_id, start_frame);
3717 if (start_frame_id < end_frame_id) {
3718 if (start_frame > end_frame_id ||
3719 start_frame < start_frame_id)
3721 } else if (start_frame_id > end_frame_id) {
3722 if ((start_frame > end_frame_id &&
3723 start_frame < start_frame_id))
3730 if (ret == -EINVAL || start_frame == start_frame_id) {
3731 start_frame = start_frame_id + 1;
3732 if (urb->dev->speed == USB_SPEED_LOW ||
3733 urb->dev->speed == USB_SPEED_FULL)
3734 urb->start_frame = start_frame;
3736 urb->start_frame = start_frame << 3;
3742 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3743 start_frame, current_frame_id, index,
3744 start_frame_id, end_frame_id);
3745 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3752 /* Check if we should generate event interrupt for a TD in an isoc URB */
3753 static bool trb_block_event_intr(struct xhci_hcd *xhci, int num_tds, int i)
3755 if (xhci->hci_version < 0x100)
3757 /* always generate an event interrupt for the last TD */
3758 if (i == num_tds - 1)
3761 * If AVOID_BEI is set the host handles full event rings poorly,
3762 * generate an event at least every 8th TD to clear the event ring
3764 if (i && xhci->quirks & XHCI_AVOID_BEI)
3770 /* This is for isoc transfer */
3771 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3772 struct urb *urb, int slot_id, unsigned int ep_index)
3774 struct xhci_ring *ep_ring;
3775 struct urb_priv *urb_priv;
3777 int num_tds, trbs_per_td;
3778 struct xhci_generic_trb *start_trb;
3781 u32 field, length_field;
3782 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3783 u64 start_addr, addr;
3785 bool more_trbs_coming;
3786 struct xhci_virt_ep *xep;
3789 xep = &xhci->devs[slot_id]->eps[ep_index];
3790 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3792 num_tds = urb->number_of_packets;
3794 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3797 start_addr = (u64) urb->transfer_dma;
3798 start_trb = &ep_ring->enqueue->generic;
3799 start_cycle = ep_ring->cycle_state;
3801 urb_priv = urb->hcpriv;
3802 /* Queue the TRBs for each TD, even if they are zero-length */
3803 for (i = 0; i < num_tds; i++) {
3804 unsigned int total_pkt_count, max_pkt;
3805 unsigned int burst_count, last_burst_pkt_count;
3810 addr = start_addr + urb->iso_frame_desc[i].offset;
3811 td_len = urb->iso_frame_desc[i].length;
3812 td_remain_len = td_len;
3813 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3814 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
3816 /* A zero-length transfer still involves at least one packet. */
3817 if (total_pkt_count == 0)
3819 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
3820 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
3821 urb, total_pkt_count);
3823 trbs_per_td = count_isoc_trbs_needed(urb, i);
3825 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3826 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3832 td = &urb_priv->td[i];
3834 /* use SIA as default, if frame id is used overwrite it */
3835 sia_frame_id = TRB_SIA;
3836 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
3837 HCC_CFC(xhci->hcc_params)) {
3838 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
3840 sia_frame_id = TRB_FRAME_ID(frame_id);
3843 * Set isoc specific data for the first TRB in a TD.
3844 * Prevent HW from getting the TRBs by keeping the cycle state
3845 * inverted in the first TDs isoc TRB.
3847 field = TRB_TYPE(TRB_ISOC) |
3848 TRB_TLBPC(last_burst_pkt_count) |
3850 (i ? ep_ring->cycle_state : !start_cycle);
3852 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
3853 if (!xep->use_extended_tbc)
3854 field |= TRB_TBC(burst_count);
3856 /* fill the rest of the TRB fields, and remaining normal TRBs */
3857 for (j = 0; j < trbs_per_td; j++) {
3860 /* only first TRB is isoc, overwrite otherwise */
3862 field = TRB_TYPE(TRB_NORMAL) |
3863 ep_ring->cycle_state;
3865 /* Only set interrupt on short packet for IN EPs */
3866 if (usb_urb_dir_in(urb))
3869 /* Set the chain bit for all except the last TRB */
3870 if (j < trbs_per_td - 1) {
3871 more_trbs_coming = true;
3874 more_trbs_coming = false;
3875 td->last_trb = ep_ring->enqueue;
3877 if (trb_block_event_intr(xhci, num_tds, i))
3880 /* Calculate TRB length */
3881 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3882 if (trb_buff_len > td_remain_len)
3883 trb_buff_len = td_remain_len;
3885 /* Set the TRB length, TD size, & interrupter fields. */
3886 remainder = xhci_td_remainder(xhci, running_total,
3887 trb_buff_len, td_len,
3888 urb, more_trbs_coming);
3890 length_field = TRB_LEN(trb_buff_len) |
3893 /* xhci 1.1 with ETE uses TD Size field for TBC */
3894 if (first_trb && xep->use_extended_tbc)
3895 length_field |= TRB_TD_SIZE_TBC(burst_count);
3897 length_field |= TRB_TD_SIZE(remainder);
3900 queue_trb(xhci, ep_ring, more_trbs_coming,
3901 lower_32_bits(addr),
3902 upper_32_bits(addr),
3905 running_total += trb_buff_len;
3907 addr += trb_buff_len;
3908 td_remain_len -= trb_buff_len;
3911 /* Check TD length */
3912 if (running_total != td_len) {
3913 xhci_err(xhci, "ISOC TD length unmatch\n");
3919 /* store the next frame id */
3920 if (HCC_CFC(xhci->hcc_params))
3921 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
3923 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3924 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3925 usb_amd_quirk_pll_disable();
3927 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3929 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3930 start_cycle, start_trb);
3933 /* Clean up a partially enqueued isoc transfer. */
3935 for (i--; i >= 0; i--)
3936 list_del_init(&urb_priv->td[i].td_list);
3938 /* Use the first TD as a temporary variable to turn the TDs we've queued
3939 * into No-ops with a software-owned cycle bit. That way the hardware
3940 * won't accidentally start executing bogus TDs when we partially
3941 * overwrite them. td->first_trb and td->start_seg are already set.
3943 urb_priv->td[0].last_trb = ep_ring->enqueue;
3944 /* Every TRB except the first & last will have its cycle bit flipped. */
3945 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
3947 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3948 ep_ring->enqueue = urb_priv->td[0].first_trb;
3949 ep_ring->enq_seg = urb_priv->td[0].start_seg;
3950 ep_ring->cycle_state = start_cycle;
3951 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3952 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3957 * Check transfer ring to guarantee there is enough room for the urb.
3958 * Update ISO URB start_frame and interval.
3959 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
3960 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
3961 * Contiguous Frame ID is not supported by HC.
3963 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3964 struct urb *urb, int slot_id, unsigned int ep_index)
3966 struct xhci_virt_device *xdev;
3967 struct xhci_ring *ep_ring;
3968 struct xhci_ep_ctx *ep_ctx;
3970 int num_tds, num_trbs, i;
3972 struct xhci_virt_ep *xep;
3975 xdev = xhci->devs[slot_id];
3976 xep = &xhci->devs[slot_id]->eps[ep_index];
3977 ep_ring = xdev->eps[ep_index].ring;
3978 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3981 num_tds = urb->number_of_packets;
3982 for (i = 0; i < num_tds; i++)
3983 num_trbs += count_isoc_trbs_needed(urb, i);
3985 /* Check the ring to guarantee there is enough room for the whole urb.
3986 * Do not insert any td of the urb to the ring if the check failed.
3988 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3989 num_trbs, mem_flags);
3994 * Check interval value. This should be done before we start to
3995 * calculate the start frame value.
3997 check_interval(xhci, urb, ep_ctx);
3999 /* Calculate the start frame and put it in urb->start_frame. */
4000 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
4001 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
4002 urb->start_frame = xep->next_frame_id;
4003 goto skip_start_over;
4007 start_frame = readl(&xhci->run_regs->microframe_index);
4008 start_frame &= 0x3fff;
4010 * Round up to the next frame and consider the time before trb really
4011 * gets scheduled by hardare.
4013 ist = HCS_IST(xhci->hcs_params2) & 0x7;
4014 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
4016 start_frame += ist + XHCI_CFC_DELAY;
4017 start_frame = roundup(start_frame, 8);
4020 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
4021 * is greate than 8 microframes.
4023 if (urb->dev->speed == USB_SPEED_LOW ||
4024 urb->dev->speed == USB_SPEED_FULL) {
4025 start_frame = roundup(start_frame, urb->interval << 3);
4026 urb->start_frame = start_frame >> 3;
4028 start_frame = roundup(start_frame, urb->interval);
4029 urb->start_frame = start_frame;
4033 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
4035 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4038 /**** Command Ring Operations ****/
4040 /* Generic function for queueing a command TRB on the command ring.
4041 * Check to make sure there's room on the command ring for one command TRB.
4042 * Also check that there's room reserved for commands that must not fail.
4043 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4044 * then only check for the number of reserved spots.
4045 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4046 * because the command event handler may want to resubmit a failed command.
4048 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4049 u32 field1, u32 field2,
4050 u32 field3, u32 field4, bool command_must_succeed)
4052 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4055 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
4056 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4057 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
4061 if (!command_must_succeed)
4064 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4065 reserved_trbs, GFP_ATOMIC);
4067 xhci_err(xhci, "ERR: No room for command on command ring\n");
4068 if (command_must_succeed)
4069 xhci_err(xhci, "ERR: Reserved TRB counting for "
4070 "unfailable commands failed.\n");
4074 cmd->command_trb = xhci->cmd_ring->enqueue;
4076 /* if there are no other commands queued we start the timeout timer */
4077 if (list_empty(&xhci->cmd_list)) {
4078 xhci->current_cmd = cmd;
4079 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
4082 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4084 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4085 field4 | xhci->cmd_ring->cycle_state);
4089 /* Queue a slot enable or disable request on the command ring */
4090 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4091 u32 trb_type, u32 slot_id)
4093 return queue_command(xhci, cmd, 0, 0, 0,
4094 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4097 /* Queue an address device command TRB */
4098 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4099 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4101 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4102 upper_32_bits(in_ctx_ptr), 0,
4103 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4104 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4107 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4108 u32 field1, u32 field2, u32 field3, u32 field4)
4110 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4113 /* Queue a reset device command TRB */
4114 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4117 return queue_command(xhci, cmd, 0, 0, 0,
4118 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4122 /* Queue a configure endpoint command TRB */
4123 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4124 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4125 u32 slot_id, bool command_must_succeed)
4127 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4128 upper_32_bits(in_ctx_ptr), 0,
4129 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4130 command_must_succeed);
4133 /* Queue an evaluate context command TRB */
4134 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4135 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4137 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4138 upper_32_bits(in_ctx_ptr), 0,
4139 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4140 command_must_succeed);
4144 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4145 * activity on an endpoint that is about to be suspended.
4147 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4148 int slot_id, unsigned int ep_index, int suspend)
4150 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4151 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4152 u32 type = TRB_TYPE(TRB_STOP_RING);
4153 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4155 return queue_command(xhci, cmd, 0, 0, 0,
4156 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4159 /* Set Transfer Ring Dequeue Pointer command */
4160 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
4161 unsigned int slot_id, unsigned int ep_index,
4162 struct xhci_dequeue_state *deq_state)
4165 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4166 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4167 u32 trb_stream_id = STREAM_ID_FOR_TRB(deq_state->stream_id);
4169 u32 type = TRB_TYPE(TRB_SET_DEQ);
4170 struct xhci_virt_ep *ep;
4171 struct xhci_command *cmd;
4174 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
4175 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
4176 deq_state->new_deq_seg,
4177 (unsigned long long)deq_state->new_deq_seg->dma,
4178 deq_state->new_deq_ptr,
4179 (unsigned long long)xhci_trb_virt_to_dma(
4180 deq_state->new_deq_seg, deq_state->new_deq_ptr),
4181 deq_state->new_cycle_state);
4183 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
4184 deq_state->new_deq_ptr);
4186 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4187 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4188 deq_state->new_deq_seg, deq_state->new_deq_ptr);
4191 ep = &xhci->devs[slot_id]->eps[ep_index];
4192 if ((ep->ep_state & SET_DEQ_PENDING)) {
4193 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4194 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4198 /* This function gets called from contexts where it cannot sleep */
4199 cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
4203 ep->queued_deq_seg = deq_state->new_deq_seg;
4204 ep->queued_deq_ptr = deq_state->new_deq_ptr;
4205 if (deq_state->stream_id)
4206 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4207 ret = queue_command(xhci, cmd,
4208 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
4209 upper_32_bits(addr), trb_stream_id,
4210 trb_slot_id | trb_ep_index | type, false);
4212 xhci_free_command(xhci, cmd);
4216 /* Stop the TD queueing code from ringing the doorbell until
4217 * this command completes. The HC won't set the dequeue pointer
4218 * if the ring is running, and ringing the doorbell starts the
4221 ep->ep_state |= SET_DEQ_PENDING;
4224 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4225 int slot_id, unsigned int ep_index,
4226 enum xhci_ep_reset_type reset_type)
4228 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4229 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4230 u32 type = TRB_TYPE(TRB_RESET_EP);
4232 if (reset_type == EP_SOFT_RESET)
4235 return queue_command(xhci, cmd, 0, 0, 0,
4236 trb_slot_id | trb_ep_index | type, false);