1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
12 * Ring initialization rules:
13 * 1. Each segment is initialized to zero, except for link TRBs.
14 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
15 * Consumer Cycle State (CCS), depending on ring function.
16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
18 * Ring behavior rules:
19 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
20 * least one free TRB in the ring. This is useful if you want to turn that
21 * into a link TRB and expand the ring.
22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
23 * link TRB, then load the pointer with the address in the link TRB. If the
24 * link TRB had its toggle bit set, you may need to update the ring cycle
25 * state (see cycle bit rules). You may have to do this multiple times
26 * until you reach a non-link TRB.
27 * 3. A ring is full if enqueue++ (for the definition of increment above)
28 * equals the dequeue pointer.
31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
32 * in a link TRB, it must toggle the ring cycle state.
33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
34 * in a link TRB, it must toggle the ring cycle state.
37 * 1. Check if ring is full before you enqueue.
38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
39 * Update enqueue pointer between each write (which may update the ring
41 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
42 * and endpoint rings. If HC is the producer for the event ring,
43 * and it generates an interrupt according to interrupt modulation rules.
46 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
47 * the TRB is owned by the consumer.
48 * 2. Update dequeue pointer (which may update the ring cycle state) and
49 * continue processing TRBs until you reach a TRB which is not owned by you.
50 * 3. Notify the producer. SW is the consumer for the event ring, and it
51 * updates event ring dequeue pointer. HC is the consumer for the command and
52 * endpoint rings; it generates events on the event ring for these.
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
57 #include <linux/dma-mapping.h>
59 #include "xhci-trace.h"
61 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
62 u32 field1, u32 field2,
63 u32 field3, u32 field4, bool command_must_succeed);
66 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
69 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
72 unsigned long segment_offset;
74 if (!seg || !trb || trb < seg->trbs)
77 segment_offset = trb - seg->trbs;
78 if (segment_offset >= TRBS_PER_SEGMENT)
80 return seg->dma + (segment_offset * sizeof(*trb));
83 static bool trb_is_noop(union xhci_trb *trb)
85 return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
88 static bool trb_is_link(union xhci_trb *trb)
90 return TRB_TYPE_LINK_LE32(trb->link.control);
93 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
95 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
98 static bool last_trb_on_ring(struct xhci_ring *ring,
99 struct xhci_segment *seg, union xhci_trb *trb)
101 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
104 static bool link_trb_toggles_cycle(union xhci_trb *trb)
106 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
109 static bool last_td_in_urb(struct xhci_td *td)
111 struct urb_priv *urb_priv = td->urb->hcpriv;
113 return urb_priv->num_tds_done == urb_priv->num_tds;
116 static void inc_td_cnt(struct urb *urb)
118 struct urb_priv *urb_priv = urb->hcpriv;
120 urb_priv->num_tds_done++;
123 static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
125 if (trb_is_link(trb)) {
126 /* unchain chained link TRBs */
127 trb->link.control &= cpu_to_le32(~TRB_CHAIN);
129 trb->generic.field[0] = 0;
130 trb->generic.field[1] = 0;
131 trb->generic.field[2] = 0;
132 /* Preserve only the cycle bit of this TRB */
133 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
134 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
138 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
139 * TRB is in a new segment. This does not skip over link TRBs, and it does not
140 * effect the ring dequeue or enqueue pointers.
142 static void next_trb(struct xhci_hcd *xhci,
143 struct xhci_ring *ring,
144 struct xhci_segment **seg,
145 union xhci_trb **trb)
147 if (trb_is_link(*trb)) {
149 *trb = ((*seg)->trbs);
156 * See Cycle bit rules. SW is the consumer for the event ring only.
158 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
160 unsigned int link_trb_count = 0;
162 /* event ring doesn't have link trbs, check for last trb */
163 if (ring->type == TYPE_EVENT) {
164 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
168 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
169 ring->cycle_state ^= 1;
170 ring->deq_seg = ring->deq_seg->next;
171 ring->dequeue = ring->deq_seg->trbs;
175 /* All other rings have link trbs */
176 if (!trb_is_link(ring->dequeue)) {
177 if (last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
178 xhci_warn(xhci, "Missing link TRB at end of segment\n");
181 ring->num_trbs_free++;
185 while (trb_is_link(ring->dequeue)) {
186 ring->deq_seg = ring->deq_seg->next;
187 ring->dequeue = ring->deq_seg->trbs;
189 if (link_trb_count++ > ring->num_segs) {
190 xhci_warn(xhci, "Ring is an endless link TRB loop\n");
195 trace_xhci_inc_deq(ring);
201 * See Cycle bit rules. SW is the consumer for the event ring only.
203 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
204 * chain bit is set), then set the chain bit in all the following link TRBs.
205 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
206 * have their chain bit cleared (so that each Link TRB is a separate TD).
208 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
209 * set, but other sections talk about dealing with the chain bit set. This was
210 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
211 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
213 * @more_trbs_coming: Will you enqueue more TRBs before calling
214 * prepare_transfer()?
216 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
217 bool more_trbs_coming)
220 union xhci_trb *next;
221 unsigned int link_trb_count = 0;
223 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
224 /* If this is not event ring, there is one less usable TRB */
225 if (!trb_is_link(ring->enqueue))
226 ring->num_trbs_free--;
228 if (last_trb_on_seg(ring->enq_seg, ring->enqueue)) {
229 xhci_err(xhci, "Tried to move enqueue past ring segment\n");
233 next = ++(ring->enqueue);
235 /* Update the dequeue pointer further if that was a link TRB */
236 while (trb_is_link(next)) {
239 * If the caller doesn't plan on enqueueing more TDs before
240 * ringing the doorbell, then we don't want to give the link TRB
241 * to the hardware just yet. We'll give the link TRB back in
242 * prepare_ring() just before we enqueue the TD at the top of
245 if (!chain && !more_trbs_coming)
248 /* If we're not dealing with 0.95 hardware or isoc rings on
249 * AMD 0.96 host, carry over the chain bit of the previous TRB
250 * (which may mean the chain bit is cleared).
252 if (!(ring->type == TYPE_ISOC &&
253 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
254 !xhci_link_trb_quirk(xhci)) {
255 next->link.control &= cpu_to_le32(~TRB_CHAIN);
256 next->link.control |= cpu_to_le32(chain);
258 /* Give this link TRB to the hardware */
260 next->link.control ^= cpu_to_le32(TRB_CYCLE);
262 /* Toggle the cycle bit after the last ring segment. */
263 if (link_trb_toggles_cycle(next))
264 ring->cycle_state ^= 1;
266 ring->enq_seg = ring->enq_seg->next;
267 ring->enqueue = ring->enq_seg->trbs;
268 next = ring->enqueue;
270 if (link_trb_count++ > ring->num_segs) {
271 xhci_warn(xhci, "%s: Ring link TRB loop\n", __func__);
276 trace_xhci_inc_enq(ring);
280 * Check to see if there's room to enqueue num_trbs on the ring and make sure
281 * enqueue pointer will not advance into dequeue segment. See rules above.
283 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
284 unsigned int num_trbs)
286 int num_trbs_in_deq_seg;
288 if (ring->num_trbs_free < num_trbs)
291 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
292 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
293 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
300 /* Ring the host controller doorbell after placing a command on the ring */
301 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
303 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
306 xhci_dbg(xhci, "// Ding dong!\n");
308 trace_xhci_ring_host_doorbell(0, DB_VALUE_HOST);
310 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
311 /* Flush PCI posted writes */
312 readl(&xhci->dba->doorbell[0]);
315 static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
317 return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
320 static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
322 return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
327 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
328 * If there are other commands waiting then restart the ring and kick the timer.
329 * This must be called with command ring stopped and xhci->lock held.
331 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
332 struct xhci_command *cur_cmd)
334 struct xhci_command *i_cmd;
336 /* Turn all aborted commands in list to no-ops, then restart */
337 list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
339 if (i_cmd->status != COMP_COMMAND_ABORTED)
342 i_cmd->status = COMP_COMMAND_RING_STOPPED;
344 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
347 trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
350 * caller waiting for completion is called when command
351 * completion event is received for these no-op commands
355 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
357 /* ring command ring doorbell to restart the command ring */
358 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
359 !(xhci->xhc_state & XHCI_STATE_DYING)) {
360 xhci->current_cmd = cur_cmd;
361 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
362 xhci_ring_cmd_db(xhci);
366 /* Must be called with xhci->lock held, releases and aquires lock back */
367 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
372 xhci_dbg(xhci, "Abort command ring\n");
374 reinit_completion(&xhci->cmd_ring_stop_completion);
376 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
377 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
378 &xhci->op_regs->cmd_ring);
380 /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
381 * completion of the Command Abort operation. If CRR is not negated in 5
382 * seconds then driver handles it as if host died (-ENODEV).
383 * In the future we should distinguish between -ENODEV and -ETIMEDOUT
384 * and try to recover a -ETIMEDOUT with a host controller reset.
386 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
387 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
389 xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
395 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
396 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
397 * but the completion event in never sent. Wait 2 secs (arbitrary
398 * number) to handle those cases after negation of CMD_RING_RUNNING.
400 spin_unlock_irqrestore(&xhci->lock, flags);
401 ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
402 msecs_to_jiffies(2000));
403 spin_lock_irqsave(&xhci->lock, flags);
405 xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
406 xhci_cleanup_command_queue(xhci);
408 xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
413 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
414 unsigned int slot_id,
415 unsigned int ep_index,
416 unsigned int stream_id)
418 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
419 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
420 unsigned int ep_state = ep->ep_state;
422 /* Don't ring the doorbell for this endpoint if there are pending
423 * cancellations because we don't want to interrupt processing.
424 * We don't want to restart any stream rings if there's a set dequeue
425 * pointer command pending because the device can choose to start any
426 * stream once the endpoint is on the HW schedule.
428 if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
429 (ep_state & EP_HALTED) || (ep_state & EP_CLEARING_TT))
432 trace_xhci_ring_ep_doorbell(slot_id, DB_VALUE(ep_index, stream_id));
434 writel(DB_VALUE(ep_index, stream_id), db_addr);
435 /* flush the write */
439 /* Ring the doorbell for any rings with pending URBs */
440 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
441 unsigned int slot_id,
442 unsigned int ep_index)
444 unsigned int stream_id;
445 struct xhci_virt_ep *ep;
447 ep = &xhci->devs[slot_id]->eps[ep_index];
449 /* A ring has pending URBs if its TD list is not empty */
450 if (!(ep->ep_state & EP_HAS_STREAMS)) {
451 if (ep->ring && !(list_empty(&ep->ring->td_list)))
452 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
456 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
458 struct xhci_stream_info *stream_info = ep->stream_info;
459 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
460 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
465 void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
466 unsigned int slot_id,
467 unsigned int ep_index)
469 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
472 static struct xhci_virt_ep *xhci_get_virt_ep(struct xhci_hcd *xhci,
473 unsigned int slot_id,
474 unsigned int ep_index)
476 if (slot_id == 0 || slot_id >= MAX_HC_SLOTS) {
477 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
480 if (ep_index >= EP_CTX_PER_DEV) {
481 xhci_warn(xhci, "Invalid endpoint index %u\n", ep_index);
484 if (!xhci->devs[slot_id]) {
485 xhci_warn(xhci, "No xhci virt device for slot_id %u\n", slot_id);
489 return &xhci->devs[slot_id]->eps[ep_index];
492 static struct xhci_ring *xhci_virt_ep_to_ring(struct xhci_hcd *xhci,
493 struct xhci_virt_ep *ep,
494 unsigned int stream_id)
496 /* common case, no streams */
497 if (!(ep->ep_state & EP_HAS_STREAMS))
500 if (!ep->stream_info)
503 if (stream_id == 0 || stream_id >= ep->stream_info->num_streams) {
504 xhci_warn(xhci, "Invalid stream_id %u request for slot_id %u ep_index %u\n",
505 stream_id, ep->vdev->slot_id, ep->ep_index);
509 return ep->stream_info->stream_rings[stream_id];
512 /* Get the right ring for the given slot_id, ep_index and stream_id.
513 * If the endpoint supports streams, boundary check the URB's stream ID.
514 * If the endpoint doesn't support streams, return the singular endpoint ring.
516 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
517 unsigned int slot_id, unsigned int ep_index,
518 unsigned int stream_id)
520 struct xhci_virt_ep *ep;
522 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
526 return xhci_virt_ep_to_ring(xhci, ep, stream_id);
531 * Get the hw dequeue pointer xHC stopped on, either directly from the
532 * endpoint context, or if streams are in use from the stream context.
533 * The returned hw_dequeue contains the lowest four bits with cycle state
534 * and possbile stream context type.
536 static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
537 unsigned int ep_index, unsigned int stream_id)
539 struct xhci_ep_ctx *ep_ctx;
540 struct xhci_stream_ctx *st_ctx;
541 struct xhci_virt_ep *ep;
543 ep = &vdev->eps[ep_index];
545 if (ep->ep_state & EP_HAS_STREAMS) {
546 st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
547 return le64_to_cpu(st_ctx->stream_ring);
549 ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
550 return le64_to_cpu(ep_ctx->deq);
553 static int xhci_move_dequeue_past_td(struct xhci_hcd *xhci,
554 unsigned int slot_id, unsigned int ep_index,
555 unsigned int stream_id, struct xhci_td *td)
557 struct xhci_virt_device *dev = xhci->devs[slot_id];
558 struct xhci_virt_ep *ep = &dev->eps[ep_index];
559 struct xhci_ring *ep_ring;
560 struct xhci_command *cmd;
561 struct xhci_segment *new_seg;
562 union xhci_trb *new_deq;
566 bool cycle_found = false;
567 bool td_last_trb_found = false;
571 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
572 ep_index, stream_id);
574 xhci_warn(xhci, "WARN can't find new dequeue, invalid stream ID %u\n",
579 * A cancelled TD can complete with a stall if HW cached the trb.
580 * In this case driver can't find td, but if the ring is empty we
581 * can move the dequeue pointer to the current enqueue position.
582 * We shouldn't hit this anymore as cached cancelled TRBs are given back
583 * after clearing the cache, but be on the safe side and keep it anyway
586 if (list_empty(&ep_ring->td_list)) {
587 new_seg = ep_ring->enq_seg;
588 new_deq = ep_ring->enqueue;
589 new_cycle = ep_ring->cycle_state;
590 xhci_dbg(xhci, "ep ring empty, Set new dequeue = enqueue");
593 xhci_warn(xhci, "Can't find new dequeue state, missing td\n");
598 hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
599 new_seg = ep_ring->deq_seg;
600 new_deq = ep_ring->dequeue;
601 new_cycle = hw_dequeue & 0x1;
604 * We want to find the pointer, segment and cycle state of the new trb
605 * (the one after current TD's last_trb). We know the cycle state at
606 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
610 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
611 == (dma_addr_t)(hw_dequeue & ~0xf)) {
613 if (td_last_trb_found)
616 if (new_deq == td->last_trb)
617 td_last_trb_found = true;
619 if (cycle_found && trb_is_link(new_deq) &&
620 link_trb_toggles_cycle(new_deq))
623 next_trb(xhci, ep_ring, &new_seg, &new_deq);
625 /* Search wrapped around, bail out */
626 if (new_deq == ep->ring->dequeue) {
627 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
631 } while (!cycle_found || !td_last_trb_found);
635 /* Don't update the ring cycle state for the producer (us). */
636 addr = xhci_trb_virt_to_dma(new_seg, new_deq);
638 xhci_warn(xhci, "Can't find dma of new dequeue ptr\n");
639 xhci_warn(xhci, "deq seg = %p, deq ptr = %p\n", new_seg, new_deq);
643 if ((ep->ep_state & SET_DEQ_PENDING)) {
644 xhci_warn(xhci, "Set TR Deq already pending, don't submit for 0x%pad\n",
649 /* This function gets called from contexts where it cannot sleep */
650 cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
652 xhci_warn(xhci, "Can't alloc Set TR Deq cmd 0x%pad\n", &addr);
657 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
658 ret = queue_command(xhci, cmd,
659 lower_32_bits(addr) | trb_sct | new_cycle,
661 STREAM_ID_FOR_TRB(stream_id), SLOT_ID_FOR_TRB(slot_id) |
662 EP_ID_FOR_TRB(ep_index) | TRB_TYPE(TRB_SET_DEQ), false);
664 xhci_free_command(xhci, cmd);
667 ep->queued_deq_seg = new_seg;
668 ep->queued_deq_ptr = new_deq;
670 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
671 "Set TR Deq ptr 0x%llx, cycle %u\n", addr, new_cycle);
673 /* Stop the TD queueing code from ringing the doorbell until
674 * this command completes. The HC won't set the dequeue pointer
675 * if the ring is running, and ringing the doorbell starts the
678 ep->ep_state |= SET_DEQ_PENDING;
679 xhci_ring_cmd_db(xhci);
683 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
684 * (The last TRB actually points to the ring enqueue pointer, which is not part
685 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
687 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
688 struct xhci_td *td, bool flip_cycle)
690 struct xhci_segment *seg = td->start_seg;
691 union xhci_trb *trb = td->first_trb;
694 trb_to_noop(trb, TRB_TR_NOOP);
696 /* flip cycle if asked to */
697 if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
698 trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
700 if (trb == td->last_trb)
703 next_trb(xhci, ep_ring, &seg, &trb);
707 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
708 struct xhci_virt_ep *ep)
710 ep->ep_state &= ~EP_STOP_CMD_PENDING;
711 /* Can't del_timer_sync in interrupt */
712 del_timer(&ep->stop_cmd_timer);
716 * Must be called with xhci->lock held in interrupt context,
717 * releases and re-acquires xhci->lock
719 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
720 struct xhci_td *cur_td, int status)
722 struct urb *urb = cur_td->urb;
723 struct urb_priv *urb_priv = urb->hcpriv;
724 struct usb_hcd *hcd = bus_to_hcd(urb->dev->bus);
726 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
727 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
728 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
729 if (xhci->quirks & XHCI_AMD_PLL_FIX)
730 usb_amd_quirk_pll_enable();
733 xhci_urb_free_priv(urb_priv);
734 usb_hcd_unlink_urb_from_ep(hcd, urb);
735 trace_xhci_urb_giveback(urb);
736 usb_hcd_giveback_urb(hcd, urb, status);
739 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
740 struct xhci_ring *ring, struct xhci_td *td)
742 struct device *dev = xhci_to_hcd(xhci)->self.controller;
743 struct xhci_segment *seg = td->bounce_seg;
744 struct urb *urb = td->urb;
747 if (!ring || !seg || !urb)
750 if (usb_urb_dir_out(urb)) {
751 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
756 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
758 /* for in tranfers we need to copy the data from bounce to sg */
760 len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs, seg->bounce_buf,
761 seg->bounce_len, seg->bounce_offs);
762 if (len != seg->bounce_len)
763 xhci_warn(xhci, "WARN Wrong bounce buffer read length: %zu != %d\n",
764 len, seg->bounce_len);
766 memcpy(urb->transfer_buffer + seg->bounce_offs, seg->bounce_buf,
770 seg->bounce_offs = 0;
773 static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
774 struct xhci_ring *ep_ring, int status)
776 struct urb *urb = NULL;
778 /* Clean up the endpoint's TD list */
781 /* if a bounce buffer was used to align this td then unmap it */
782 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
784 /* Do one last check of the actual transfer length.
785 * If the host controller said we transferred more data than the buffer
786 * length, urb->actual_length will be a very big number (since it's
787 * unsigned). Play it safe and say we didn't transfer anything.
789 if (urb->actual_length > urb->transfer_buffer_length) {
790 xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
791 urb->transfer_buffer_length, urb->actual_length);
792 urb->actual_length = 0;
795 /* TD might be removed from td_list if we are giving back a cancelled URB */
796 if (!list_empty(&td->td_list))
797 list_del_init(&td->td_list);
798 /* Giving back a cancelled URB, or if a slated TD completed anyway */
799 if (!list_empty(&td->cancelled_td_list))
800 list_del_init(&td->cancelled_td_list);
803 /* Giveback the urb when all the tds are completed */
804 if (last_td_in_urb(td)) {
805 if ((urb->actual_length != urb->transfer_buffer_length &&
806 (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
807 (status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
808 xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
809 urb, urb->actual_length,
810 urb->transfer_buffer_length, status);
812 /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
813 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
815 xhci_giveback_urb_in_irq(xhci, td, status);
822 /* Complete the cancelled URBs we unlinked from td_list. */
823 static void xhci_giveback_invalidated_tds(struct xhci_virt_ep *ep)
825 struct xhci_ring *ring;
826 struct xhci_td *td, *tmp_td;
828 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
832 * Doesn't matter what we pass for status, since the core will
833 * just overwrite it (because the URB has been unlinked).
835 ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
837 if (td->cancel_status == TD_CLEARED)
838 xhci_td_cleanup(ep->xhci, td, ring, 0);
840 if (ep->xhci->xhc_state & XHCI_STATE_DYING)
845 static int xhci_reset_halted_ep(struct xhci_hcd *xhci, unsigned int slot_id,
846 unsigned int ep_index, enum xhci_ep_reset_type reset_type)
848 struct xhci_command *command;
851 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
857 ret = xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
860 xhci_err(xhci, "ERROR queuing reset endpoint for slot %d ep_index %d, %d\n",
861 slot_id, ep_index, ret);
865 static void xhci_handle_halted_endpoint(struct xhci_hcd *xhci,
866 struct xhci_virt_ep *ep, unsigned int stream_id,
868 enum xhci_ep_reset_type reset_type)
870 unsigned int slot_id = ep->vdev->slot_id;
874 * Avoid resetting endpoint if link is inactive. Can cause host hang.
875 * Device will be reset soon to recover the link so don't do anything
877 if (ep->vdev->flags & VDEV_PORT_ERROR)
880 /* add td to cancelled list and let reset ep handler take care of it */
881 if (reset_type == EP_HARD_RESET) {
882 ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
883 if (td && list_empty(&td->cancelled_td_list)) {
884 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
885 td->cancel_status = TD_HALTED;
889 if (ep->ep_state & EP_HALTED) {
890 xhci_dbg(xhci, "Reset ep command already pending\n");
894 err = xhci_reset_halted_ep(xhci, slot_id, ep->ep_index, reset_type);
898 ep->ep_state |= EP_HALTED;
900 xhci_ring_cmd_db(xhci);
904 * Fix up the ep ring first, so HW stops executing cancelled TDs.
905 * We have the xHCI lock, so nothing can modify this list until we drop it.
906 * We're also in the event handler, so we can't get re-interrupted if another
907 * Stop Endpoint command completes.
909 * only call this when ring is not in a running state
912 static int xhci_invalidate_cancelled_tds(struct xhci_virt_ep *ep)
914 struct xhci_hcd *xhci;
915 struct xhci_td *td = NULL;
916 struct xhci_td *tmp_td = NULL;
917 struct xhci_td *cached_td = NULL;
918 struct xhci_ring *ring;
920 unsigned int slot_id = ep->vdev->slot_id;
925 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list, cancelled_td_list) {
926 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
927 "Removing canceled TD starting at 0x%llx (dma).",
928 (unsigned long long)xhci_trb_virt_to_dma(
929 td->start_seg, td->first_trb));
930 list_del_init(&td->td_list);
931 ring = xhci_urb_to_transfer_ring(xhci, td->urb);
933 xhci_warn(xhci, "WARN Cancelled URB %p has invalid stream ID %u.\n",
934 td->urb, td->urb->stream_id);
938 * If ring stopped on the TD we need to cancel, then we have to
939 * move the xHC endpoint ring dequeue pointer past this TD.
941 hw_deq = xhci_get_hw_deq(xhci, ep->vdev, ep->ep_index,
945 if (trb_in_td(xhci, td->start_seg, td->first_trb,
946 td->last_trb, hw_deq, false)) {
947 switch (td->cancel_status) {
948 case TD_CLEARED: /* TD is already no-op */
949 case TD_CLEARING_CACHE: /* set TR deq command already queued */
951 case TD_DIRTY: /* TD is cached, clear it */
953 /* FIXME stream case, several stopped rings */
958 td_to_noop(xhci, ring, td, false);
959 td->cancel_status = TD_CLEARED;
963 cached_td->cancel_status = TD_CLEARING_CACHE;
965 err = xhci_move_dequeue_past_td(xhci, slot_id, ep->ep_index,
966 cached_td->urb->stream_id,
968 /* Failed to move past cached td, try just setting it noop */
970 td_to_noop(xhci, ring, cached_td, false);
971 cached_td->cancel_status = TD_CLEARED;
979 * Returns the TD the endpoint ring halted on.
980 * Only call for non-running rings without streams.
982 static struct xhci_td *find_halted_td(struct xhci_virt_ep *ep)
987 if (!list_empty(&ep->ring->td_list)) { /* Not streams compatible */
988 hw_deq = xhci_get_hw_deq(ep->xhci, ep->vdev, ep->ep_index, 0);
990 td = list_first_entry(&ep->ring->td_list, struct xhci_td, td_list);
991 if (trb_in_td(ep->xhci, td->start_seg, td->first_trb,
992 td->last_trb, hw_deq, false))
999 * When we get a command completion for a Stop Endpoint Command, we need to
1000 * unlink any cancelled TDs from the ring. There are two ways to do that:
1002 * 1. If the HW was in the middle of processing the TD that needs to be
1003 * cancelled, then we must move the ring's dequeue pointer past the last TRB
1004 * in the TD with a Set Dequeue Pointer Command.
1005 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
1006 * bit cleared) so that the HW will skip over them.
1008 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
1009 union xhci_trb *trb, u32 comp_code)
1011 unsigned int ep_index;
1012 struct xhci_virt_ep *ep;
1013 struct xhci_ep_ctx *ep_ctx;
1014 struct xhci_td *td = NULL;
1015 enum xhci_ep_reset_type reset_type;
1016 struct xhci_command *command;
1018 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
1019 if (!xhci->devs[slot_id])
1020 xhci_warn(xhci, "Stop endpoint command completion for disabled slot %u\n",
1025 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1026 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1030 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1032 trace_xhci_handle_cmd_stop_ep(ep_ctx);
1034 if (comp_code == COMP_CONTEXT_STATE_ERROR) {
1036 * If stop endpoint command raced with a halting endpoint we need to
1037 * reset the host side endpoint first.
1038 * If the TD we halted on isn't cancelled the TD should be given back
1039 * with a proper error code, and the ring dequeue moved past the TD.
1040 * If streams case we can't find hw_deq, or the TD we halted on so do a
1043 * Proper error code is unknown here, it would be -EPIPE if device side
1044 * of enadpoit halted (aka STALL), and -EPROTO if not (transaction error)
1045 * We use -EPROTO, if device is stalled it should return a stall error on
1046 * next transfer, which then will return -EPIPE, and device side stall is
1047 * noted and cleared by class driver.
1049 switch (GET_EP_CTX_STATE(ep_ctx)) {
1050 case EP_STATE_HALTED:
1051 xhci_dbg(xhci, "Stop ep completion raced with stall, reset ep\n");
1052 if (ep->ep_state & EP_HAS_STREAMS) {
1053 reset_type = EP_SOFT_RESET;
1055 reset_type = EP_HARD_RESET;
1056 td = find_halted_td(ep);
1058 td->status = -EPROTO;
1060 /* reset ep, reset handler cleans up cancelled tds */
1061 xhci_handle_halted_endpoint(xhci, ep, 0, td, reset_type);
1062 xhci_stop_watchdog_timer_in_irq(xhci, ep);
1064 case EP_STATE_RUNNING:
1065 /* Race, HW handled stop ep cmd before ep was running */
1066 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1068 xhci_stop_watchdog_timer_in_irq(xhci, ep);
1070 mod_timer(&ep->stop_cmd_timer,
1071 jiffies + XHCI_STOP_EP_CMD_TIMEOUT * HZ);
1072 xhci_queue_stop_endpoint(xhci, command, slot_id, ep_index, 0);
1073 xhci_ring_cmd_db(xhci);
1080 /* will queue a set TR deq if stopped on a cancelled, uncleared TD */
1081 xhci_invalidate_cancelled_tds(ep);
1082 xhci_stop_watchdog_timer_in_irq(xhci, ep);
1084 /* Otherwise ring the doorbell(s) to restart queued transfers */
1085 xhci_giveback_invalidated_tds(ep);
1086 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1089 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
1091 struct xhci_td *cur_td;
1092 struct xhci_td *tmp;
1094 list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
1095 list_del_init(&cur_td->td_list);
1097 if (!list_empty(&cur_td->cancelled_td_list))
1098 list_del_init(&cur_td->cancelled_td_list);
1100 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
1102 inc_td_cnt(cur_td->urb);
1103 if (last_td_in_urb(cur_td))
1104 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1108 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
1109 int slot_id, int ep_index)
1111 struct xhci_td *cur_td;
1112 struct xhci_td *tmp;
1113 struct xhci_virt_ep *ep;
1114 struct xhci_ring *ring;
1116 ep = &xhci->devs[slot_id]->eps[ep_index];
1117 if ((ep->ep_state & EP_HAS_STREAMS) ||
1118 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
1121 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
1123 ring = ep->stream_info->stream_rings[stream_id];
1127 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1128 "Killing URBs for slot ID %u, ep index %u, stream %u",
1129 slot_id, ep_index, stream_id);
1130 xhci_kill_ring_urbs(xhci, ring);
1136 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1137 "Killing URBs for slot ID %u, ep index %u",
1139 xhci_kill_ring_urbs(xhci, ring);
1142 list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
1143 cancelled_td_list) {
1144 list_del_init(&cur_td->cancelled_td_list);
1145 inc_td_cnt(cur_td->urb);
1147 if (last_td_in_urb(cur_td))
1148 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
1153 * host controller died, register read returns 0xffffffff
1154 * Complete pending commands, mark them ABORTED.
1155 * URBs need to be given back as usb core might be waiting with device locks
1156 * held for the URBs to finish during device disconnect, blocking host remove.
1158 * Call with xhci->lock held.
1159 * lock is relased and re-acquired while giving back urb.
1161 void xhci_hc_died(struct xhci_hcd *xhci)
1165 if (xhci->xhc_state & XHCI_STATE_DYING)
1168 xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
1169 xhci->xhc_state |= XHCI_STATE_DYING;
1171 xhci_cleanup_command_queue(xhci);
1173 /* return any pending urbs, remove may be waiting for them */
1174 for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
1177 for (j = 0; j < 31; j++)
1178 xhci_kill_endpoint_urbs(xhci, i, j);
1181 /* inform usb core hc died if PCI remove isn't already handling it */
1182 if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
1183 usb_hc_died(xhci_to_hcd(xhci));
1186 /* Watchdog timer function for when a stop endpoint command fails to complete.
1187 * In this case, we assume the host controller is broken or dying or dead. The
1188 * host may still be completing some other events, so we have to be careful to
1189 * let the event ring handler and the URB dequeueing/enqueueing functions know
1190 * through xhci->state.
1192 * The timer may also fire if the host takes a very long time to respond to the
1193 * command, and the stop endpoint command completion handler cannot delete the
1194 * timer before the timer function is called. Another endpoint cancellation may
1195 * sneak in before the timer function can grab the lock, and that may queue
1196 * another stop endpoint command and add the timer back. So we cannot use a
1197 * simple flag to say whether there is a pending stop endpoint command for a
1198 * particular endpoint.
1200 * Instead we use a combination of that flag and checking if a new timer is
1203 void xhci_stop_endpoint_command_watchdog(struct timer_list *t)
1205 struct xhci_virt_ep *ep = from_timer(ep, t, stop_cmd_timer);
1206 struct xhci_hcd *xhci = ep->xhci;
1207 unsigned long flags;
1210 spin_lock_irqsave(&xhci->lock, flags);
1212 /* bail out if cmd completed but raced with stop ep watchdog timer.*/
1213 if (!(ep->ep_state & EP_STOP_CMD_PENDING) ||
1214 timer_pending(&ep->stop_cmd_timer)) {
1215 spin_unlock_irqrestore(&xhci->lock, flags);
1216 xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit");
1219 usbsts = readl(&xhci->op_regs->status);
1221 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
1222 xhci_warn(xhci, "USBSTS:%s\n", xhci_decode_usbsts(usbsts));
1224 ep->ep_state &= ~EP_STOP_CMD_PENDING;
1229 * handle a stop endpoint cmd timeout as if host died (-ENODEV).
1230 * In the future we could distinguish between -ENODEV and -ETIMEDOUT
1231 * and try to recover a -ETIMEDOUT with a host controller reset
1235 spin_unlock_irqrestore(&xhci->lock, flags);
1236 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1237 "xHCI host controller is dead.");
1240 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
1241 struct xhci_virt_device *dev,
1242 struct xhci_ring *ep_ring,
1243 unsigned int ep_index)
1245 union xhci_trb *dequeue_temp;
1246 int num_trbs_free_temp;
1247 bool revert = false;
1249 num_trbs_free_temp = ep_ring->num_trbs_free;
1250 dequeue_temp = ep_ring->dequeue;
1252 /* If we get two back-to-back stalls, and the first stalled transfer
1253 * ends just before a link TRB, the dequeue pointer will be left on
1254 * the link TRB by the code in the while loop. So we have to update
1255 * the dequeue pointer one segment further, or we'll jump off
1256 * the segment into la-la-land.
1258 if (trb_is_link(ep_ring->dequeue)) {
1259 ep_ring->deq_seg = ep_ring->deq_seg->next;
1260 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1263 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1264 /* We have more usable TRBs */
1265 ep_ring->num_trbs_free++;
1267 if (trb_is_link(ep_ring->dequeue)) {
1268 if (ep_ring->dequeue ==
1269 dev->eps[ep_index].queued_deq_ptr)
1271 ep_ring->deq_seg = ep_ring->deq_seg->next;
1272 ep_ring->dequeue = ep_ring->deq_seg->trbs;
1274 if (ep_ring->dequeue == dequeue_temp) {
1281 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1282 ep_ring->num_trbs_free = num_trbs_free_temp;
1287 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1288 * we need to clear the set deq pending flag in the endpoint ring state, so that
1289 * the TD queueing code can ring the doorbell again. We also need to ring the
1290 * endpoint doorbell to restart the ring, but only if there aren't more
1291 * cancellations pending.
1293 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1294 union xhci_trb *trb, u32 cmd_comp_code)
1296 unsigned int ep_index;
1297 unsigned int stream_id;
1298 struct xhci_ring *ep_ring;
1299 struct xhci_virt_ep *ep;
1300 struct xhci_ep_ctx *ep_ctx;
1301 struct xhci_slot_ctx *slot_ctx;
1302 struct xhci_td *td, *tmp_td;
1304 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1305 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1306 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1310 ep_ring = xhci_virt_ep_to_ring(xhci, ep, stream_id);
1312 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1314 /* XXX: Harmless??? */
1318 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1319 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
1320 trace_xhci_handle_cmd_set_deq(slot_ctx);
1321 trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1323 if (cmd_comp_code != COMP_SUCCESS) {
1324 unsigned int ep_state;
1325 unsigned int slot_state;
1327 switch (cmd_comp_code) {
1328 case COMP_TRB_ERROR:
1329 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1331 case COMP_CONTEXT_STATE_ERROR:
1332 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1333 ep_state = GET_EP_CTX_STATE(ep_ctx);
1334 slot_state = le32_to_cpu(slot_ctx->dev_state);
1335 slot_state = GET_SLOT_STATE(slot_state);
1336 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1337 "Slot state = %u, EP state = %u",
1338 slot_state, ep_state);
1340 case COMP_SLOT_NOT_ENABLED_ERROR:
1341 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1345 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1349 /* OK what do we do now? The endpoint state is hosed, and we
1350 * should never get to this point if the synchronization between
1351 * queueing, and endpoint state are correct. This might happen
1352 * if the device gets disconnected after we've finished
1353 * cancelling URBs, which might not be an error...
1357 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1358 if (ep->ep_state & EP_HAS_STREAMS) {
1359 struct xhci_stream_ctx *ctx =
1360 &ep->stream_info->stream_ctx_array[stream_id];
1361 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1363 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1365 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1366 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1367 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1368 ep->queued_deq_ptr) == deq) {
1369 /* Update the ring's dequeue segment and dequeue pointer
1370 * to reflect the new position.
1372 update_ring_for_set_deq_completion(xhci, ep->vdev,
1375 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1376 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1377 ep->queued_deq_seg, ep->queued_deq_ptr);
1380 /* HW cached TDs cleared from cache, give them back */
1381 list_for_each_entry_safe(td, tmp_td, &ep->cancelled_td_list,
1382 cancelled_td_list) {
1383 ep_ring = xhci_urb_to_transfer_ring(ep->xhci, td->urb);
1384 if (td->cancel_status == TD_CLEARING_CACHE) {
1385 td->cancel_status = TD_CLEARED;
1386 xhci_td_cleanup(ep->xhci, td, ep_ring, td->status);
1390 ep->ep_state &= ~SET_DEQ_PENDING;
1391 ep->queued_deq_seg = NULL;
1392 ep->queued_deq_ptr = NULL;
1393 /* Restart any rings with pending URBs */
1394 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1397 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1398 union xhci_trb *trb, u32 cmd_comp_code)
1400 struct xhci_virt_ep *ep;
1401 struct xhci_ep_ctx *ep_ctx;
1402 unsigned int ep_index;
1404 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1405 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
1409 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
1410 trace_xhci_handle_cmd_reset_ep(ep_ctx);
1412 /* This command will only fail if the endpoint wasn't halted,
1413 * but we don't care.
1415 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1416 "Ignoring reset ep completion code of %u", cmd_comp_code);
1418 /* Cleanup cancelled TDs as ep is stopped. May queue a Set TR Deq cmd */
1419 xhci_invalidate_cancelled_tds(ep);
1421 if (xhci->quirks & XHCI_RESET_EP_QUIRK)
1422 xhci_dbg(xhci, "Note: Removed workaround to queue config ep for this hw");
1423 /* Clear our internal halted state */
1424 ep->ep_state &= ~EP_HALTED;
1426 xhci_giveback_invalidated_tds(ep);
1428 /* if this was a soft reset, then restart */
1429 if ((le32_to_cpu(trb->generic.field[3])) & TRB_TSP)
1430 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1433 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1434 struct xhci_command *command, u32 cmd_comp_code)
1436 if (cmd_comp_code == COMP_SUCCESS)
1437 command->slot_id = slot_id;
1439 command->slot_id = 0;
1442 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1444 struct xhci_virt_device *virt_dev;
1445 struct xhci_slot_ctx *slot_ctx;
1447 virt_dev = xhci->devs[slot_id];
1451 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1452 trace_xhci_handle_cmd_disable_slot(slot_ctx);
1454 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1455 /* Delete default control endpoint resources */
1456 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1457 xhci_free_virt_device(xhci, slot_id);
1460 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1463 struct xhci_virt_device *virt_dev;
1464 struct xhci_input_control_ctx *ctrl_ctx;
1465 struct xhci_ep_ctx *ep_ctx;
1466 unsigned int ep_index;
1467 unsigned int ep_state;
1468 u32 add_flags, drop_flags;
1471 * Configure endpoint commands can come from the USB core
1472 * configuration or alt setting changes, or because the HW
1473 * needed an extra configure endpoint command after a reset
1474 * endpoint command or streams were being configured.
1475 * If the command was for a halted endpoint, the xHCI driver
1476 * is not waiting on the configure endpoint command.
1478 virt_dev = xhci->devs[slot_id];
1481 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1483 xhci_warn(xhci, "Could not get input context, bad type.\n");
1487 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1488 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1489 /* Input ctx add_flags are the endpoint index plus one */
1490 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1492 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1493 trace_xhci_handle_cmd_config_ep(ep_ctx);
1495 /* A usb_set_interface() call directly after clearing a halted
1496 * condition may race on this quirky hardware. Not worth
1497 * worrying about, since this is prototype hardware. Not sure
1498 * if this will work for streams, but streams support was
1499 * untested on this prototype.
1501 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1502 ep_index != (unsigned int) -1 &&
1503 add_flags - SLOT_FLAG == drop_flags) {
1504 ep_state = virt_dev->eps[ep_index].ep_state;
1505 if (!(ep_state & EP_HALTED))
1507 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1508 "Completed config ep cmd - "
1509 "last ep index = %d, state = %d",
1510 ep_index, ep_state);
1511 /* Clear internal halted state and restart ring(s) */
1512 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1513 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1519 static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1521 struct xhci_virt_device *vdev;
1522 struct xhci_slot_ctx *slot_ctx;
1524 vdev = xhci->devs[slot_id];
1527 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1528 trace_xhci_handle_cmd_addr_dev(slot_ctx);
1531 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id)
1533 struct xhci_virt_device *vdev;
1534 struct xhci_slot_ctx *slot_ctx;
1536 vdev = xhci->devs[slot_id];
1538 xhci_warn(xhci, "Reset device command completion for disabled slot %u\n",
1542 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1543 trace_xhci_handle_cmd_reset_dev(slot_ctx);
1545 xhci_dbg(xhci, "Completed reset device command.\n");
1548 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1549 struct xhci_event_cmd *event)
1551 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1552 xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1555 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1556 "NEC firmware version %2x.%02x",
1557 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1558 NEC_FW_MINOR(le32_to_cpu(event->status)));
1561 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1563 list_del(&cmd->cmd_list);
1565 if (cmd->completion) {
1566 cmd->status = status;
1567 complete(cmd->completion);
1573 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1575 struct xhci_command *cur_cmd, *tmp_cmd;
1576 xhci->current_cmd = NULL;
1577 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1578 xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1581 void xhci_handle_command_timeout(struct work_struct *work)
1583 struct xhci_hcd *xhci;
1584 unsigned long flags;
1587 xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1589 spin_lock_irqsave(&xhci->lock, flags);
1592 * If timeout work is pending, or current_cmd is NULL, it means we
1593 * raced with command completion. Command is handled so just return.
1595 if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1596 spin_unlock_irqrestore(&xhci->lock, flags);
1599 /* mark this command to be cancelled */
1600 xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1602 /* Make sure command ring is running before aborting it */
1603 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1604 if (hw_ring_state == ~(u64)0) {
1606 goto time_out_completed;
1609 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1610 (hw_ring_state & CMD_RING_RUNNING)) {
1611 /* Prevent new doorbell, and start command abort */
1612 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1613 xhci_dbg(xhci, "Command timeout\n");
1614 xhci_abort_cmd_ring(xhci, flags);
1615 goto time_out_completed;
1618 /* host removed. Bail out */
1619 if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1620 xhci_dbg(xhci, "host removed, ring start fail?\n");
1621 xhci_cleanup_command_queue(xhci);
1623 goto time_out_completed;
1626 /* command timeout on stopped ring, ring can't be aborted */
1627 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1628 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1631 spin_unlock_irqrestore(&xhci->lock, flags);
1635 static void handle_cmd_completion(struct xhci_hcd *xhci,
1636 struct xhci_event_cmd *event)
1638 unsigned int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1640 dma_addr_t cmd_dequeue_dma;
1642 union xhci_trb *cmd_trb;
1643 struct xhci_command *cmd;
1646 if (slot_id >= MAX_HC_SLOTS) {
1647 xhci_warn(xhci, "Invalid slot_id %u\n", slot_id);
1651 cmd_dma = le64_to_cpu(event->cmd_trb);
1652 cmd_trb = xhci->cmd_ring->dequeue;
1654 trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1656 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1659 * Check whether the completion event is for our internal kept
1662 if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1664 "ERROR mismatched command completion event\n");
1668 cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1670 cancel_delayed_work(&xhci->cmd_timer);
1672 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1674 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1675 if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1676 complete_all(&xhci->cmd_ring_stop_completion);
1680 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1682 "Command completion event does not match command\n");
1687 * Host aborted the command ring, check if the current command was
1688 * supposed to be aborted, otherwise continue normally.
1689 * The command ring is stopped now, but the xHC will issue a Command
1690 * Ring Stopped event which will cause us to restart it.
1692 if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1693 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1694 if (cmd->status == COMP_COMMAND_ABORTED) {
1695 if (xhci->current_cmd == cmd)
1696 xhci->current_cmd = NULL;
1701 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1703 case TRB_ENABLE_SLOT:
1704 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1706 case TRB_DISABLE_SLOT:
1707 xhci_handle_cmd_disable_slot(xhci, slot_id);
1710 if (!cmd->completion)
1711 xhci_handle_cmd_config_ep(xhci, slot_id, cmd_comp_code);
1713 case TRB_EVAL_CONTEXT:
1716 xhci_handle_cmd_addr_dev(xhci, slot_id);
1719 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1720 le32_to_cpu(cmd_trb->generic.field[3])));
1721 if (!cmd->completion)
1722 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb,
1726 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1727 le32_to_cpu(cmd_trb->generic.field[3])));
1728 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1731 /* Is this an aborted command turned to NO-OP? */
1732 if (cmd->status == COMP_COMMAND_RING_STOPPED)
1733 cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1736 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1737 le32_to_cpu(cmd_trb->generic.field[3])));
1738 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1741 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1742 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1744 slot_id = TRB_TO_SLOT_ID(
1745 le32_to_cpu(cmd_trb->generic.field[3]));
1746 xhci_handle_cmd_reset_dev(xhci, slot_id);
1748 case TRB_NEC_GET_FW:
1749 xhci_handle_cmd_nec_get_fw(xhci, event);
1752 /* Skip over unknown commands on the event ring */
1753 xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1757 /* restart timer if this wasn't the last command */
1758 if (!list_is_singular(&xhci->cmd_list)) {
1759 xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1760 struct xhci_command, cmd_list);
1761 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1762 } else if (xhci->current_cmd == cmd) {
1763 xhci->current_cmd = NULL;
1767 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1769 inc_deq(xhci, xhci->cmd_ring);
1772 static void handle_vendor_event(struct xhci_hcd *xhci,
1773 union xhci_trb *event, u32 trb_type)
1775 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1776 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1777 handle_cmd_completion(xhci, &event->event_cmd);
1780 static void handle_device_notification(struct xhci_hcd *xhci,
1781 union xhci_trb *event)
1784 struct usb_device *udev;
1786 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1787 if (!xhci->devs[slot_id]) {
1788 xhci_warn(xhci, "Device Notification event for "
1789 "unused slot %u\n", slot_id);
1793 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1795 udev = xhci->devs[slot_id]->udev;
1796 if (udev && udev->parent)
1797 usb_wakeup_notification(udev->parent, udev->portnum);
1801 * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI
1803 * As per ThunderX2errata-129 USB 2 device may come up as USB 1
1804 * If a connection to a USB 1 device is followed by another connection
1805 * to a USB 2 device.
1807 * Reset the PHY after the USB device is disconnected if device speed
1808 * is less than HCD_USB3.
1809 * Retry the reset sequence max of 4 times checking the PLL lock status.
1812 static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci)
1814 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1816 u32 retry_count = 4;
1819 /* Assert PHY reset */
1820 writel(0x6F, hcd->regs + 0x1048);
1822 /* De-assert the PHY reset */
1823 writel(0x7F, hcd->regs + 0x1048);
1825 pll_lock_check = readl(hcd->regs + 0x1070);
1826 } while (!(pll_lock_check & 0x1) && --retry_count);
1829 static void handle_port_status(struct xhci_hcd *xhci,
1830 union xhci_trb *event)
1832 struct usb_hcd *hcd;
1834 u32 portsc, cmd_reg;
1837 unsigned int hcd_portnum;
1838 struct xhci_bus_state *bus_state;
1839 bool bogus_port_status = false;
1840 struct xhci_port *port;
1842 /* Port status change events always have a successful completion code */
1843 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1845 "WARN: xHC returned failed port status event\n");
1847 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1848 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1850 if ((port_id <= 0) || (port_id > max_ports)) {
1851 xhci_warn(xhci, "Port change event with invalid port ID %d\n",
1853 inc_deq(xhci, xhci->event_ring);
1857 port = &xhci->hw_ports[port_id - 1];
1858 if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
1859 xhci_warn(xhci, "Port change event, no port for port ID %u\n",
1861 bogus_port_status = true;
1865 /* We might get interrupts after shared_hcd is removed */
1866 if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) {
1867 xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n");
1868 bogus_port_status = true;
1872 hcd = port->rhub->hcd;
1873 bus_state = &port->rhub->bus_state;
1874 hcd_portnum = port->hcd_portnum;
1875 portsc = readl(port->addr);
1877 xhci_dbg(xhci, "Port change event, %d-%d, id %d, portsc: 0x%x\n",
1878 hcd->self.busnum, hcd_portnum + 1, port_id, portsc);
1880 trace_xhci_handle_port_status(hcd_portnum, portsc);
1882 if (hcd->state == HC_STATE_SUSPENDED) {
1883 xhci_dbg(xhci, "resume root hub\n");
1884 usb_hcd_resume_root_hub(hcd);
1887 if (hcd->speed >= HCD_USB3 &&
1888 (portsc & PORT_PLS_MASK) == XDEV_INACTIVE) {
1889 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1890 if (slot_id && xhci->devs[slot_id])
1891 xhci->devs[slot_id]->flags |= VDEV_PORT_ERROR;
1894 if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1895 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1897 cmd_reg = readl(&xhci->op_regs->command);
1898 if (!(cmd_reg & CMD_RUN)) {
1899 xhci_warn(xhci, "xHC is not running.\n");
1903 if (DEV_SUPERSPEED_ANY(portsc)) {
1904 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1905 /* Set a flag to say the port signaled remote wakeup,
1906 * so we can tell the difference between the end of
1907 * device and host initiated resume.
1909 bus_state->port_remote_wakeup |= 1 << hcd_portnum;
1910 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1911 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1912 xhci_set_link_state(xhci, port, XDEV_U0);
1913 /* Need to wait until the next link state change
1914 * indicates the device is actually in U0.
1916 bogus_port_status = true;
1918 } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
1919 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1920 bus_state->resume_done[hcd_portnum] = jiffies +
1921 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1922 set_bit(hcd_portnum, &bus_state->resuming_ports);
1923 /* Do the rest in GetPortStatus after resume time delay.
1924 * Avoid polling roothub status before that so that a
1925 * usb device auto-resume latency around ~40ms.
1927 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1928 mod_timer(&hcd->rh_timer,
1929 bus_state->resume_done[hcd_portnum]);
1930 usb_hcd_start_port_resume(&hcd->self, hcd_portnum);
1931 bogus_port_status = true;
1935 if ((portsc & PORT_PLC) &&
1936 DEV_SUPERSPEED_ANY(portsc) &&
1937 ((portsc & PORT_PLS_MASK) == XDEV_U0 ||
1938 (portsc & PORT_PLS_MASK) == XDEV_U1 ||
1939 (portsc & PORT_PLS_MASK) == XDEV_U2)) {
1940 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1941 complete(&bus_state->u3exit_done[hcd_portnum]);
1942 /* We've just brought the device into U0/1/2 through either the
1943 * Resume state after a device remote wakeup, or through the
1944 * U3Exit state after a host-initiated resume. If it's a device
1945 * initiated remote wake, don't pass up the link state change,
1946 * so the roothub behavior is consistent with external
1947 * USB 3.0 hub behavior.
1949 slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1950 if (slot_id && xhci->devs[slot_id])
1951 xhci_ring_device(xhci, slot_id);
1952 if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
1953 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1954 usb_wakeup_notification(hcd->self.root_hub,
1956 bogus_port_status = true;
1962 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1963 * RExit to a disconnect state). If so, let the the driver know it's
1964 * out of the RExit state.
1966 if (!DEV_SUPERSPEED_ANY(portsc) && hcd->speed < HCD_USB3 &&
1967 test_and_clear_bit(hcd_portnum,
1968 &bus_state->rexit_ports)) {
1969 complete(&bus_state->rexit_done[hcd_portnum]);
1970 bogus_port_status = true;
1974 if (hcd->speed < HCD_USB3) {
1975 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1976 if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) &&
1977 (portsc & PORT_CSC) && !(portsc & PORT_CONNECT))
1978 xhci_cavium_reset_phy_quirk(xhci);
1982 /* Update event ring dequeue pointer before dropping the lock */
1983 inc_deq(xhci, xhci->event_ring);
1985 /* Don't make the USB core poll the roothub if we got a bad port status
1986 * change event. Besides, at that point we can't tell which roothub
1987 * (USB 2.0 or USB 3.0) to kick.
1989 if (bogus_port_status)
1993 * xHCI port-status-change events occur when the "or" of all the
1994 * status-change bits in the portsc register changes from 0 to 1.
1995 * New status changes won't cause an event if any other change
1996 * bits are still set. When an event occurs, switch over to
1997 * polling to avoid losing status changes.
1999 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
2000 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
2001 spin_unlock(&xhci->lock);
2002 /* Pass this up to the core */
2003 usb_hcd_poll_rh_status(hcd);
2004 spin_lock(&xhci->lock);
2008 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
2009 * at end_trb, which may be in another segment. If the suspect DMA address is a
2010 * TRB in this TD, this function returns that TRB's segment. Otherwise it
2013 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2014 struct xhci_segment *start_seg,
2015 union xhci_trb *start_trb,
2016 union xhci_trb *end_trb,
2017 dma_addr_t suspect_dma,
2020 dma_addr_t start_dma;
2021 dma_addr_t end_seg_dma;
2022 dma_addr_t end_trb_dma;
2023 struct xhci_segment *cur_seg;
2025 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
2026 cur_seg = start_seg;
2031 /* We may get an event for a Link TRB in the middle of a TD */
2032 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
2033 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
2034 /* If the end TRB isn't in this segment, this is set to 0 */
2035 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
2039 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
2040 (unsigned long long)suspect_dma,
2041 (unsigned long long)start_dma,
2042 (unsigned long long)end_trb_dma,
2043 (unsigned long long)cur_seg->dma,
2044 (unsigned long long)end_seg_dma);
2046 if (end_trb_dma > 0) {
2047 /* The end TRB is in this segment, so suspect should be here */
2048 if (start_dma <= end_trb_dma) {
2049 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
2052 /* Case for one segment with
2053 * a TD wrapped around to the top
2055 if ((suspect_dma >= start_dma &&
2056 suspect_dma <= end_seg_dma) ||
2057 (suspect_dma >= cur_seg->dma &&
2058 suspect_dma <= end_trb_dma))
2063 /* Might still be somewhere in this segment */
2064 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
2067 cur_seg = cur_seg->next;
2068 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
2069 } while (cur_seg != start_seg);
2074 static void xhci_clear_hub_tt_buffer(struct xhci_hcd *xhci, struct xhci_td *td,
2075 struct xhci_virt_ep *ep)
2078 * As part of low/full-speed endpoint-halt processing
2079 * we must clear the TT buffer (USB 2.0 specification 11.17.5).
2081 if (td->urb->dev->tt && !usb_pipeint(td->urb->pipe) &&
2082 (td->urb->dev->tt->hub != xhci_to_hcd(xhci)->self.root_hub) &&
2083 !(ep->ep_state & EP_CLEARING_TT)) {
2084 ep->ep_state |= EP_CLEARING_TT;
2085 td->urb->ep->hcpriv = td->urb->dev;
2086 if (usb_hub_clear_tt_buffer(td->urb))
2087 ep->ep_state &= ~EP_CLEARING_TT;
2091 /* Check if an error has halted the endpoint ring. The class driver will
2092 * cleanup the halt for a non-default control endpoint if we indicate a stall.
2093 * However, a babble and other errors also halt the endpoint ring, and the class
2094 * driver won't clear the halt in that case, so we need to issue a Set Transfer
2095 * Ring Dequeue Pointer command manually.
2097 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
2098 struct xhci_ep_ctx *ep_ctx,
2099 unsigned int trb_comp_code)
2101 /* TRB completion codes that may require a manual halt cleanup */
2102 if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
2103 trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
2104 trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
2105 /* The 0.95 spec says a babbling control endpoint
2106 * is not halted. The 0.96 spec says it is. Some HW
2107 * claims to be 0.95 compliant, but it halts the control
2108 * endpoint anyway. Check if a babble halted the
2111 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
2117 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
2119 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
2120 /* Vendor defined "informational" completion code,
2121 * treat as not-an-error.
2123 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
2125 xhci_dbg(xhci, "Treating code as success.\n");
2131 static int finish_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2132 struct xhci_ring *ep_ring, struct xhci_td *td,
2135 struct xhci_ep_ctx *ep_ctx;
2137 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2139 switch (trb_comp_code) {
2140 case COMP_STOPPED_LENGTH_INVALID:
2141 case COMP_STOPPED_SHORT_PACKET:
2144 * The "Stop Endpoint" completion will take care of any
2145 * stopped TDs. A stopped TD may be restarted, so don't update
2146 * the ring dequeue pointer or take this TD off any lists yet.
2149 case COMP_USB_TRANSACTION_ERROR:
2150 case COMP_BABBLE_DETECTED_ERROR:
2151 case COMP_SPLIT_TRANSACTION_ERROR:
2153 * If endpoint context state is not halted we might be
2154 * racing with a reset endpoint command issued by a unsuccessful
2155 * stop endpoint completion (context error). In that case the
2156 * td should be on the cancelled list, and EP_HALTED flag set.
2158 * Or then it's not halted due to the 0.95 spec stating that a
2159 * babbling control endpoint should not halt. The 0.96 spec
2160 * again says it should. Some HW claims to be 0.95 compliant,
2161 * but it halts the control endpoint anyway.
2163 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_HALTED) {
2165 * If EP_HALTED is set and TD is on the cancelled list
2166 * the TD and dequeue pointer will be handled by reset
2167 * ep command completion
2169 if ((ep->ep_state & EP_HALTED) &&
2170 !list_empty(&td->cancelled_td_list)) {
2171 xhci_dbg(xhci, "Already resolving halted ep for 0x%llx\n",
2172 (unsigned long long)xhci_trb_virt_to_dma(
2173 td->start_seg, td->first_trb));
2176 /* endpoint not halted, don't reset it */
2179 /* Almost same procedure as for STALL_ERROR below */
2180 xhci_clear_hub_tt_buffer(xhci, td, ep);
2181 xhci_handle_halted_endpoint(xhci, ep, ep_ring->stream_id, td,
2184 case COMP_STALL_ERROR:
2186 * xhci internal endpoint state will go to a "halt" state for
2187 * any stall, including default control pipe protocol stall.
2188 * To clear the host side halt we need to issue a reset endpoint
2189 * command, followed by a set dequeue command to move past the
2191 * Class drivers clear the device side halt from a functional
2192 * stall later. Hub TT buffer should only be cleared for FS/LS
2193 * devices behind HS hubs for functional stalls.
2195 if (ep->ep_index != 0)
2196 xhci_clear_hub_tt_buffer(xhci, td, ep);
2198 xhci_handle_halted_endpoint(xhci, ep, ep_ring->stream_id, td,
2201 return 0; /* xhci_handle_halted_endpoint marked td cancelled */
2206 /* Update ring dequeue pointer */
2207 ep_ring->dequeue = td->last_trb;
2208 ep_ring->deq_seg = td->last_trb_seg;
2209 ep_ring->num_trbs_free += td->num_trbs - 1;
2210 inc_deq(xhci, ep_ring);
2212 return xhci_td_cleanup(xhci, td, ep_ring, td->status);
2215 /* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
2216 static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
2217 union xhci_trb *stop_trb)
2220 union xhci_trb *trb = ring->dequeue;
2221 struct xhci_segment *seg = ring->deq_seg;
2223 for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
2224 if (!trb_is_noop(trb) && !trb_is_link(trb))
2225 sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
2231 * Process control tds, update urb status and actual_length.
2233 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2234 struct xhci_ring *ep_ring, struct xhci_td *td,
2235 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2237 struct xhci_ep_ctx *ep_ctx;
2239 u32 remaining, requested;
2242 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
2243 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep->ep_index);
2244 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2245 requested = td->urb->transfer_buffer_length;
2246 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2248 switch (trb_comp_code) {
2250 if (trb_type != TRB_STATUS) {
2251 xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
2252 (trb_type == TRB_DATA) ? "data" : "setup");
2253 td->status = -ESHUTDOWN;
2258 case COMP_SHORT_PACKET:
2261 case COMP_STOPPED_SHORT_PACKET:
2262 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2263 td->urb->actual_length = remaining;
2265 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
2270 td->urb->actual_length = 0;
2274 td->urb->actual_length = requested - remaining;
2277 td->urb->actual_length = requested;
2280 xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
2284 case COMP_STOPPED_LENGTH_INVALID:
2287 if (!xhci_requires_manual_halt_cleanup(xhci,
2288 ep_ctx, trb_comp_code))
2290 xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
2291 trb_comp_code, ep->ep_index);
2293 case COMP_STALL_ERROR:
2294 /* Did we transfer part of the data (middle) phase? */
2295 if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
2296 td->urb->actual_length = requested - remaining;
2297 else if (!td->urb_length_set)
2298 td->urb->actual_length = 0;
2302 /* stopped at setup stage, no data transferred */
2303 if (trb_type == TRB_SETUP)
2307 * if on data stage then update the actual_length of the URB and flag it
2308 * as set, so it won't be overwritten in the event for the last TRB.
2310 if (trb_type == TRB_DATA ||
2311 trb_type == TRB_NORMAL) {
2312 td->urb_length_set = true;
2313 td->urb->actual_length = requested - remaining;
2314 xhci_dbg(xhci, "Waiting for status stage event\n");
2318 /* at status stage */
2319 if (!td->urb_length_set)
2320 td->urb->actual_length = requested;
2323 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2327 * Process isochronous tds, update urb packet status and actual_length.
2329 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2330 struct xhci_ring *ep_ring, struct xhci_td *td,
2331 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2333 struct urb_priv *urb_priv;
2335 struct usb_iso_packet_descriptor *frame;
2337 bool sum_trbs_for_length = false;
2338 u32 remaining, requested, ep_trb_len;
2339 int short_framestatus;
2341 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2342 urb_priv = td->urb->hcpriv;
2343 idx = urb_priv->num_tds_done;
2344 frame = &td->urb->iso_frame_desc[idx];
2345 requested = frame->length;
2346 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2347 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2348 short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2351 /* handle completion code */
2352 switch (trb_comp_code) {
2355 frame->status = short_framestatus;
2356 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2357 sum_trbs_for_length = true;
2362 case COMP_SHORT_PACKET:
2363 frame->status = short_framestatus;
2364 sum_trbs_for_length = true;
2366 case COMP_BANDWIDTH_OVERRUN_ERROR:
2367 frame->status = -ECOMM;
2369 case COMP_ISOCH_BUFFER_OVERRUN:
2370 case COMP_BABBLE_DETECTED_ERROR:
2371 frame->status = -EOVERFLOW;
2373 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2374 case COMP_STALL_ERROR:
2375 frame->status = -EPROTO;
2377 case COMP_USB_TRANSACTION_ERROR:
2378 frame->status = -EPROTO;
2379 if (ep_trb != td->last_trb)
2383 sum_trbs_for_length = true;
2385 case COMP_STOPPED_SHORT_PACKET:
2386 /* field normally containing residue now contains tranferred */
2387 frame->status = short_framestatus;
2388 requested = remaining;
2390 case COMP_STOPPED_LENGTH_INVALID:
2395 sum_trbs_for_length = true;
2400 if (sum_trbs_for_length)
2401 frame->actual_length = sum_trb_lengths(xhci, ep->ring, ep_trb) +
2402 ep_trb_len - remaining;
2404 frame->actual_length = requested;
2406 td->urb->actual_length += frame->actual_length;
2408 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2411 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2412 struct xhci_virt_ep *ep, int status)
2414 struct urb_priv *urb_priv;
2415 struct usb_iso_packet_descriptor *frame;
2418 urb_priv = td->urb->hcpriv;
2419 idx = urb_priv->num_tds_done;
2420 frame = &td->urb->iso_frame_desc[idx];
2422 /* The transfer is partly done. */
2423 frame->status = -EXDEV;
2425 /* calc actual length */
2426 frame->actual_length = 0;
2428 /* Update ring dequeue pointer */
2429 ep->ring->dequeue = td->last_trb;
2430 ep->ring->deq_seg = td->last_trb_seg;
2431 ep->ring->num_trbs_free += td->num_trbs - 1;
2432 inc_deq(xhci, ep->ring);
2434 return xhci_td_cleanup(xhci, td, ep->ring, status);
2438 * Process bulk and interrupt tds, update urb status and actual_length.
2440 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_virt_ep *ep,
2441 struct xhci_ring *ep_ring, struct xhci_td *td,
2442 union xhci_trb *ep_trb, struct xhci_transfer_event *event)
2444 struct xhci_slot_ctx *slot_ctx;
2446 u32 remaining, requested, ep_trb_len;
2448 slot_ctx = xhci_get_slot_ctx(xhci, ep->vdev->out_ctx);
2449 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2450 remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2451 ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2452 requested = td->urb->transfer_buffer_length;
2454 switch (trb_comp_code) {
2456 ep_ring->err_count = 0;
2457 /* handle success with untransferred data as short packet */
2458 if (ep_trb != td->last_trb || remaining) {
2459 xhci_warn(xhci, "WARN Successful completion on short TX\n");
2460 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2461 td->urb->ep->desc.bEndpointAddress,
2462 requested, remaining);
2466 case COMP_SHORT_PACKET:
2467 xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2468 td->urb->ep->desc.bEndpointAddress,
2469 requested, remaining);
2472 case COMP_STOPPED_SHORT_PACKET:
2473 td->urb->actual_length = remaining;
2475 case COMP_STOPPED_LENGTH_INVALID:
2476 /* stopped on ep trb with invalid length, exclude it */
2480 case COMP_USB_TRANSACTION_ERROR:
2481 if (xhci->quirks & XHCI_NO_SOFT_RETRY ||
2482 (ep_ring->err_count++ > MAX_SOFT_RETRY) ||
2483 le32_to_cpu(slot_ctx->tt_info) & TT_SLOT)
2488 xhci_handle_halted_endpoint(xhci, ep, ep_ring->stream_id, td,
2496 if (ep_trb == td->last_trb)
2497 td->urb->actual_length = requested - remaining;
2499 td->urb->actual_length =
2500 sum_trb_lengths(xhci, ep_ring, ep_trb) +
2501 ep_trb_len - remaining;
2503 if (remaining > requested) {
2504 xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2506 td->urb->actual_length = 0;
2509 return finish_td(xhci, ep, ep_ring, td, trb_comp_code);
2513 * If this function returns an error condition, it means it got a Transfer
2514 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2515 * At this point, the host controller is probably hosed and should be reset.
2517 static int handle_tx_event(struct xhci_hcd *xhci,
2518 struct xhci_transfer_event *event)
2520 struct xhci_virt_ep *ep;
2521 struct xhci_ring *ep_ring;
2522 unsigned int slot_id;
2524 struct xhci_td *td = NULL;
2525 dma_addr_t ep_trb_dma;
2526 struct xhci_segment *ep_seg;
2527 union xhci_trb *ep_trb;
2528 int status = -EINPROGRESS;
2529 struct xhci_ep_ctx *ep_ctx;
2530 struct list_head *tmp;
2533 bool handling_skipped_tds = false;
2535 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2536 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2537 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2538 ep_trb_dma = le64_to_cpu(event->buffer);
2540 ep = xhci_get_virt_ep(xhci, slot_id, ep_index);
2542 xhci_err(xhci, "ERROR Invalid Transfer event\n");
2546 ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2547 ep_ctx = xhci_get_ep_ctx(xhci, ep->vdev->out_ctx, ep_index);
2549 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2551 "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2556 /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2558 switch (trb_comp_code) {
2559 case COMP_STALL_ERROR:
2560 case COMP_USB_TRANSACTION_ERROR:
2561 case COMP_INVALID_STREAM_TYPE_ERROR:
2562 case COMP_INVALID_STREAM_ID_ERROR:
2563 xhci_handle_halted_endpoint(xhci, ep, 0, NULL,
2566 case COMP_RING_UNDERRUN:
2567 case COMP_RING_OVERRUN:
2568 case COMP_STOPPED_LENGTH_INVALID:
2571 xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2577 /* Count current td numbers if ep->skip is set */
2579 list_for_each(tmp, &ep_ring->td_list)
2583 /* Look for common error cases */
2584 switch (trb_comp_code) {
2585 /* Skip codes that require special handling depending on
2589 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2591 if (xhci->quirks & XHCI_TRUST_TX_LENGTH ||
2592 ep_ring->last_td_was_short)
2593 trb_comp_code = COMP_SHORT_PACKET;
2595 xhci_warn_ratelimited(xhci,
2596 "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2599 case COMP_SHORT_PACKET:
2601 /* Completion codes for endpoint stopped state */
2603 xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2606 case COMP_STOPPED_LENGTH_INVALID:
2608 "Stopped on No-op or Link TRB for slot %u ep %u\n",
2611 case COMP_STOPPED_SHORT_PACKET:
2613 "Stopped with short packet transfer detected for slot %u ep %u\n",
2616 /* Completion codes for endpoint halted state */
2617 case COMP_STALL_ERROR:
2618 xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2622 case COMP_SPLIT_TRANSACTION_ERROR:
2623 xhci_dbg(xhci, "Split transaction error for slot %u ep %u\n",
2627 case COMP_USB_TRANSACTION_ERROR:
2628 xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2632 case COMP_BABBLE_DETECTED_ERROR:
2633 xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2635 status = -EOVERFLOW;
2637 /* Completion codes for endpoint error state */
2638 case COMP_TRB_ERROR:
2640 "WARN: TRB error for slot %u ep %u on endpoint\n",
2644 /* completion codes not indicating endpoint state change */
2645 case COMP_DATA_BUFFER_ERROR:
2647 "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2651 case COMP_BANDWIDTH_OVERRUN_ERROR:
2653 "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2656 case COMP_ISOCH_BUFFER_OVERRUN:
2658 "WARN: buffer overrun event for slot %u ep %u on endpoint",
2661 case COMP_RING_UNDERRUN:
2663 * When the Isoch ring is empty, the xHC will generate
2664 * a Ring Overrun Event for IN Isoch endpoint or Ring
2665 * Underrun Event for OUT Isoch endpoint.
2667 xhci_dbg(xhci, "underrun event on endpoint\n");
2668 if (!list_empty(&ep_ring->td_list))
2669 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2670 "still with TDs queued?\n",
2671 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2674 case COMP_RING_OVERRUN:
2675 xhci_dbg(xhci, "overrun event on endpoint\n");
2676 if (!list_empty(&ep_ring->td_list))
2677 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2678 "still with TDs queued?\n",
2679 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2682 case COMP_MISSED_SERVICE_ERROR:
2684 * When encounter missed service error, one or more isoc tds
2685 * may be missed by xHC.
2686 * Set skip flag of the ep_ring; Complete the missed tds as
2687 * short transfer when process the ep_ring next time.
2691 "Miss service interval error for slot %u ep %u, set skip flag\n",
2694 case COMP_NO_PING_RESPONSE_ERROR:
2697 "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2701 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2702 /* needs disable slot command to recover */
2704 "WARN: detect an incompatible device for slot %u ep %u",
2709 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2714 "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2715 trb_comp_code, slot_id, ep_index);
2720 /* This TRB should be in the TD at the head of this ring's
2723 if (list_empty(&ep_ring->td_list)) {
2725 * Don't print wanings if it's due to a stopped endpoint
2726 * generating an extra completion event if the device
2727 * was suspended. Or, a event for the last TRB of a
2728 * short TD we already got a short event for.
2729 * The short TD is already removed from the TD list.
2732 if (!(trb_comp_code == COMP_STOPPED ||
2733 trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2734 ep_ring->last_td_was_short)) {
2735 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2736 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2741 xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2744 if (trb_comp_code == COMP_STALL_ERROR ||
2745 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2747 xhci_handle_halted_endpoint(xhci, ep,
2755 /* We've skipped all the TDs on the ep ring when ep->skip set */
2756 if (ep->skip && td_num == 0) {
2758 xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2763 td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2768 /* Is this a TRB in the currently executing TD? */
2769 ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2770 td->last_trb, ep_trb_dma, false);
2773 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2774 * is not in the current TD pointed by ep_ring->dequeue because
2775 * that the hardware dequeue pointer still at the previous TRB
2776 * of the current TD. The previous TRB maybe a Link TD or the
2777 * last TRB of the previous TD. The command completion handle
2778 * will take care the rest.
2780 if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2781 trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2787 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2788 /* Some host controllers give a spurious
2789 * successful event after a short transfer.
2792 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2793 ep_ring->last_td_was_short) {
2794 ep_ring->last_td_was_short = false;
2797 /* HC is busted, give up! */
2799 "ERROR Transfer event TRB DMA ptr not "
2800 "part of current TD ep_index %d "
2801 "comp_code %u\n", ep_index,
2803 trb_in_td(xhci, ep_ring->deq_seg,
2804 ep_ring->dequeue, td->last_trb,
2809 skip_isoc_td(xhci, td, ep, status);
2812 if (trb_comp_code == COMP_SHORT_PACKET)
2813 ep_ring->last_td_was_short = true;
2815 ep_ring->last_td_was_short = false;
2819 "Found td. Clear skip flag for slot %u ep %u.\n",
2824 ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2827 trace_xhci_handle_transfer(ep_ring,
2828 (struct xhci_generic_trb *) ep_trb);
2831 * No-op TRB could trigger interrupts in a case where
2832 * a URB was killed and a STALL_ERROR happens right
2833 * after the endpoint ring stopped. Reset the halted
2834 * endpoint. Otherwise, the endpoint remains stalled
2838 if (trb_is_noop(ep_trb)) {
2839 if (trb_comp_code == COMP_STALL_ERROR ||
2840 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2842 xhci_handle_halted_endpoint(xhci, ep,
2848 td->status = status;
2850 /* update the urb's actual_length and give back to the core */
2851 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2852 process_ctrl_td(xhci, ep, ep_ring, td, ep_trb, event);
2853 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2854 process_isoc_td(xhci, ep, ep_ring, td, ep_trb, event);
2856 process_bulk_intr_td(xhci, ep, ep_ring, td, ep_trb, event);
2858 handling_skipped_tds = ep->skip &&
2859 trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2860 trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2863 * Do not update event ring dequeue pointer if we're in a loop
2864 * processing missed tds.
2866 if (!handling_skipped_tds)
2867 inc_deq(xhci, xhci->event_ring);
2870 * If ep->skip is set, it means there are missed tds on the
2871 * endpoint ring need to take care of.
2872 * Process them as short transfer until reach the td pointed by
2875 } while (handling_skipped_tds);
2880 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2881 (unsigned long long) xhci_trb_virt_to_dma(
2882 xhci->event_ring->deq_seg,
2883 xhci->event_ring->dequeue),
2884 lower_32_bits(le64_to_cpu(event->buffer)),
2885 upper_32_bits(le64_to_cpu(event->buffer)),
2886 le32_to_cpu(event->transfer_len),
2887 le32_to_cpu(event->flags));
2892 * This function handles all OS-owned events on the event ring. It may drop
2893 * xhci->lock between event processing (e.g. to pass up port status changes).
2894 * Returns >0 for "possibly more events to process" (caller should call again),
2895 * otherwise 0 if done. In future, <0 returns should indicate error code.
2897 static int xhci_handle_event(struct xhci_hcd *xhci)
2899 union xhci_trb *event;
2900 int update_ptrs = 1;
2904 /* Event ring hasn't been allocated yet. */
2905 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2906 xhci_err(xhci, "ERROR event ring not ready\n");
2910 event = xhci->event_ring->dequeue;
2911 /* Does the HC or OS own the TRB? */
2912 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2913 xhci->event_ring->cycle_state)
2916 trace_xhci_handle_event(xhci->event_ring, &event->generic);
2919 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2920 * speculative reads of the event's flags/data below.
2923 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->event_cmd.flags));
2924 /* FIXME: Handle more event types. */
2927 case TRB_COMPLETION:
2928 handle_cmd_completion(xhci, &event->event_cmd);
2930 case TRB_PORT_STATUS:
2931 handle_port_status(xhci, event);
2935 ret = handle_tx_event(xhci, &event->trans_event);
2940 handle_device_notification(xhci, event);
2943 if (trb_type >= TRB_VENDOR_DEFINED_LOW)
2944 handle_vendor_event(xhci, event, trb_type);
2946 xhci_warn(xhci, "ERROR unknown event type %d\n", trb_type);
2948 /* Any of the above functions may drop and re-acquire the lock, so check
2949 * to make sure a watchdog timer didn't mark the host as non-responsive.
2951 if (xhci->xhc_state & XHCI_STATE_DYING) {
2952 xhci_dbg(xhci, "xHCI host dying, returning from "
2953 "event handler.\n");
2958 /* Update SW event ring dequeue pointer */
2959 inc_deq(xhci, xhci->event_ring);
2961 /* Are there more items on the event ring? Caller will call us again to
2968 * Update Event Ring Dequeue Pointer:
2969 * - When all events have finished
2970 * - To avoid "Event Ring Full Error" condition
2972 static void xhci_update_erst_dequeue(struct xhci_hcd *xhci,
2973 union xhci_trb *event_ring_deq)
2978 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2979 /* If necessary, update the HW's version of the event ring deq ptr. */
2980 if (event_ring_deq != xhci->event_ring->dequeue) {
2981 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2982 xhci->event_ring->dequeue);
2984 xhci_warn(xhci, "WARN something wrong with SW event ring dequeue ptr\n");
2986 * Per 4.9.4, Software writes to the ERDP register shall
2987 * always advance the Event Ring Dequeue Pointer value.
2989 if ((temp_64 & (u64) ~ERST_PTR_MASK) ==
2990 ((u64) deq & (u64) ~ERST_PTR_MASK))
2993 /* Update HC event ring dequeue pointer */
2994 temp_64 &= ERST_PTR_MASK;
2995 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2998 /* Clear the event handler busy flag (RW1C) */
2999 temp_64 |= ERST_EHB;
3000 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
3004 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
3005 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
3006 * indicators of an event TRB error, but we check the status *first* to be safe.
3008 irqreturn_t xhci_irq(struct usb_hcd *hcd)
3010 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3011 union xhci_trb *event_ring_deq;
3012 irqreturn_t ret = IRQ_NONE;
3017 spin_lock(&xhci->lock);
3018 /* Check if the xHC generated the interrupt, or the irq is shared */
3019 status = readl(&xhci->op_regs->status);
3020 if (status == ~(u32)0) {
3026 if (!(status & STS_EINT))
3029 if (status & STS_FATAL) {
3030 xhci_warn(xhci, "WARNING: Host System Error\n");
3037 * Clear the op reg interrupt status first,
3038 * so we can receive interrupts from other MSI-X interrupters.
3039 * Write 1 to clear the interrupt status.
3042 writel(status, &xhci->op_regs->status);
3044 if (!hcd->msi_enabled) {
3046 irq_pending = readl(&xhci->ir_set->irq_pending);
3047 irq_pending |= IMAN_IP;
3048 writel(irq_pending, &xhci->ir_set->irq_pending);
3051 if (xhci->xhc_state & XHCI_STATE_DYING ||
3052 xhci->xhc_state & XHCI_STATE_HALTED) {
3053 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
3054 "Shouldn't IRQs be disabled?\n");
3055 /* Clear the event handler busy flag (RW1C);
3056 * the event ring should be empty.
3058 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
3059 xhci_write_64(xhci, temp_64 | ERST_EHB,
3060 &xhci->ir_set->erst_dequeue);
3065 event_ring_deq = xhci->event_ring->dequeue;
3066 /* FIXME this should be a delayed service routine
3067 * that clears the EHB.
3069 while (xhci_handle_event(xhci) > 0) {
3070 if (event_loop++ < TRBS_PER_SEGMENT / 2)
3072 xhci_update_erst_dequeue(xhci, event_ring_deq);
3076 xhci_update_erst_dequeue(xhci, event_ring_deq);
3080 spin_unlock(&xhci->lock);
3085 irqreturn_t xhci_msi_irq(int irq, void *hcd)
3087 return xhci_irq(hcd);
3090 /**** Endpoint Ring Operations ****/
3093 * Generic function for queueing a TRB on a ring.
3094 * The caller must have checked to make sure there's room on the ring.
3096 * @more_trbs_coming: Will you enqueue more TRBs before calling
3097 * prepare_transfer()?
3099 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
3100 bool more_trbs_coming,
3101 u32 field1, u32 field2, u32 field3, u32 field4)
3103 struct xhci_generic_trb *trb;
3105 trb = &ring->enqueue->generic;
3106 trb->field[0] = cpu_to_le32(field1);
3107 trb->field[1] = cpu_to_le32(field2);
3108 trb->field[2] = cpu_to_le32(field3);
3109 /* make sure TRB is fully written before giving it to the controller */
3111 trb->field[3] = cpu_to_le32(field4);
3113 trace_xhci_queue_trb(ring, trb);
3115 inc_enq(xhci, ring, more_trbs_coming);
3119 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
3120 * FIXME allocate segments if the ring is full.
3122 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
3123 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
3125 unsigned int num_trbs_needed;
3126 unsigned int link_trb_count = 0;
3128 /* Make sure the endpoint has been added to xHC schedule */
3130 case EP_STATE_DISABLED:
3132 * USB core changed config/interfaces without notifying us,
3133 * or hardware is reporting the wrong state.
3135 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
3137 case EP_STATE_ERROR:
3138 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
3139 /* FIXME event handling code for error needs to clear it */
3140 /* XXX not sure if this should be -ENOENT or not */
3142 case EP_STATE_HALTED:
3143 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
3145 case EP_STATE_STOPPED:
3146 case EP_STATE_RUNNING:
3149 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
3151 * FIXME issue Configure Endpoint command to try to get the HC
3152 * back into a known state.
3158 if (room_on_ring(xhci, ep_ring, num_trbs))
3161 if (ep_ring == xhci->cmd_ring) {
3162 xhci_err(xhci, "Do not support expand command ring\n");
3166 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
3167 "ERROR no room on ep ring, try ring expansion");
3168 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
3169 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
3171 xhci_err(xhci, "Ring expansion failed\n");
3176 while (trb_is_link(ep_ring->enqueue)) {
3177 /* If we're not dealing with 0.95 hardware or isoc rings
3178 * on AMD 0.96 host, clear the chain bit.
3180 if (!xhci_link_trb_quirk(xhci) &&
3181 !(ep_ring->type == TYPE_ISOC &&
3182 (xhci->quirks & XHCI_AMD_0x96_HOST)))
3183 ep_ring->enqueue->link.control &=
3184 cpu_to_le32(~TRB_CHAIN);
3186 ep_ring->enqueue->link.control |=
3187 cpu_to_le32(TRB_CHAIN);
3190 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
3192 /* Toggle the cycle bit after the last ring segment. */
3193 if (link_trb_toggles_cycle(ep_ring->enqueue))
3194 ep_ring->cycle_state ^= 1;
3196 ep_ring->enq_seg = ep_ring->enq_seg->next;
3197 ep_ring->enqueue = ep_ring->enq_seg->trbs;
3199 /* prevent infinite loop if all first trbs are link trbs */
3200 if (link_trb_count++ > ep_ring->num_segs) {
3201 xhci_warn(xhci, "Ring is an endless link TRB loop\n");
3206 if (last_trb_on_seg(ep_ring->enq_seg, ep_ring->enqueue)) {
3207 xhci_warn(xhci, "Missing link TRB at end of ring segment\n");
3214 static int prepare_transfer(struct xhci_hcd *xhci,
3215 struct xhci_virt_device *xdev,
3216 unsigned int ep_index,
3217 unsigned int stream_id,
3218 unsigned int num_trbs,
3220 unsigned int td_index,
3224 struct urb_priv *urb_priv;
3226 struct xhci_ring *ep_ring;
3227 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3229 ep_ring = xhci_triad_to_transfer_ring(xhci, xdev->slot_id, ep_index,
3232 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
3237 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3238 num_trbs, mem_flags);
3242 urb_priv = urb->hcpriv;
3243 td = &urb_priv->td[td_index];
3245 INIT_LIST_HEAD(&td->td_list);
3246 INIT_LIST_HEAD(&td->cancelled_td_list);
3248 if (td_index == 0) {
3249 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
3255 /* Add this TD to the tail of the endpoint ring's TD list */
3256 list_add_tail(&td->td_list, &ep_ring->td_list);
3257 td->start_seg = ep_ring->enq_seg;
3258 td->first_trb = ep_ring->enqueue;
3263 unsigned int count_trbs(u64 addr, u64 len)
3265 unsigned int num_trbs;
3267 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3275 static inline unsigned int count_trbs_needed(struct urb *urb)
3277 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
3280 static unsigned int count_sg_trbs_needed(struct urb *urb)
3282 struct scatterlist *sg;
3283 unsigned int i, len, full_len, num_trbs = 0;
3285 full_len = urb->transfer_buffer_length;
3287 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
3288 len = sg_dma_len(sg);
3289 num_trbs += count_trbs(sg_dma_address(sg), len);
3290 len = min_t(unsigned int, len, full_len);
3299 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
3303 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3304 len = urb->iso_frame_desc[i].length;
3306 return count_trbs(addr, len);
3309 static void check_trb_math(struct urb *urb, int running_total)
3311 if (unlikely(running_total != urb->transfer_buffer_length))
3312 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3313 "queued %#x (%d), asked for %#x (%d)\n",
3315 urb->ep->desc.bEndpointAddress,
3316 running_total, running_total,
3317 urb->transfer_buffer_length,
3318 urb->transfer_buffer_length);
3321 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3322 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3323 struct xhci_generic_trb *start_trb)
3326 * Pass all the TRBs to the hardware at once and make sure this write
3331 start_trb->field[3] |= cpu_to_le32(start_cycle);
3333 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3334 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3337 static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3338 struct xhci_ep_ctx *ep_ctx)
3343 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3344 ep_interval = urb->interval;
3346 /* Convert to microframes */
3347 if (urb->dev->speed == USB_SPEED_LOW ||
3348 urb->dev->speed == USB_SPEED_FULL)
3351 /* FIXME change this to a warning and a suggestion to use the new API
3352 * to set the polling interval (once the API is added).
3354 if (xhci_interval != ep_interval) {
3355 dev_dbg_ratelimited(&urb->dev->dev,
3356 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3357 ep_interval, ep_interval == 1 ? "" : "s",
3358 xhci_interval, xhci_interval == 1 ? "" : "s");
3359 urb->interval = xhci_interval;
3360 /* Convert back to frames for LS/FS devices */
3361 if (urb->dev->speed == USB_SPEED_LOW ||
3362 urb->dev->speed == USB_SPEED_FULL)
3368 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3369 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3370 * (comprised of sg list entries) can take several service intervals to
3373 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3374 struct urb *urb, int slot_id, unsigned int ep_index)
3376 struct xhci_ep_ctx *ep_ctx;
3378 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3379 check_interval(xhci, urb, ep_ctx);
3381 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3385 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3386 * packets remaining in the TD (*not* including this TRB).
3388 * Total TD packet count = total_packet_count =
3389 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3391 * Packets transferred up to and including this TRB = packets_transferred =
3392 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3394 * TD size = total_packet_count - packets_transferred
3396 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3397 * including this TRB, right shifted by 10
3399 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3400 * This is taken care of in the TRB_TD_SIZE() macro
3402 * The last TRB in a TD must have the TD size set to zero.
3404 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3405 int trb_buff_len, unsigned int td_total_len,
3406 struct urb *urb, bool more_trbs_coming)
3408 u32 maxp, total_packet_count;
3410 /* MTK xHCI 0.96 contains some features from 1.0 */
3411 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3412 return ((td_total_len - transferred) >> 10);
3414 /* One TRB with a zero-length data packet. */
3415 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3416 trb_buff_len == td_total_len)
3419 /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3420 if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3423 maxp = usb_endpoint_maxp(&urb->ep->desc);
3424 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3426 /* Queueing functions don't count the current TRB into transferred */
3427 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3431 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3432 u32 *trb_buff_len, struct xhci_segment *seg)
3434 struct device *dev = xhci_to_hcd(xhci)->self.controller;
3435 unsigned int unalign;
3436 unsigned int max_pkt;
3440 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3441 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3443 /* we got lucky, last normal TRB data on segment is packet aligned */
3447 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3448 unalign, *trb_buff_len);
3450 /* is the last nornal TRB alignable by splitting it */
3451 if (*trb_buff_len > unalign) {
3452 *trb_buff_len -= unalign;
3453 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3458 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3459 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3460 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3462 new_buff_len = max_pkt - (enqd_len % max_pkt);
3464 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3465 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3467 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3468 if (usb_urb_dir_out(urb)) {
3470 len = sg_pcopy_to_buffer(urb->sg, urb->num_sgs,
3471 seg->bounce_buf, new_buff_len, enqd_len);
3472 if (len != new_buff_len)
3473 xhci_warn(xhci, "WARN Wrong bounce buffer write length: %zu != %d\n",
3476 memcpy(seg->bounce_buf, urb->transfer_buffer + enqd_len, new_buff_len);
3479 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3480 max_pkt, DMA_TO_DEVICE);
3482 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3483 max_pkt, DMA_FROM_DEVICE);
3486 if (dma_mapping_error(dev, seg->bounce_dma)) {
3487 /* try without aligning. Some host controllers survive */
3488 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3491 *trb_buff_len = new_buff_len;
3492 seg->bounce_len = new_buff_len;
3493 seg->bounce_offs = enqd_len;
3495 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3500 /* This is very similar to what ehci-q.c qtd_fill() does */
3501 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3502 struct urb *urb, int slot_id, unsigned int ep_index)
3504 struct xhci_ring *ring;
3505 struct urb_priv *urb_priv;
3507 struct xhci_generic_trb *start_trb;
3508 struct scatterlist *sg = NULL;
3509 bool more_trbs_coming = true;
3510 bool need_zero_pkt = false;
3511 bool first_trb = true;
3512 unsigned int num_trbs;
3513 unsigned int start_cycle, num_sgs = 0;
3514 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3516 u32 field, length_field, remainder;
3517 u64 addr, send_addr;
3519 ring = xhci_urb_to_transfer_ring(xhci, urb);
3523 full_len = urb->transfer_buffer_length;
3524 /* If we have scatter/gather list, we use it. */
3525 if (urb->num_sgs && !(urb->transfer_flags & URB_DMA_MAP_SINGLE)) {
3526 num_sgs = urb->num_mapped_sgs;
3528 addr = (u64) sg_dma_address(sg);
3529 block_len = sg_dma_len(sg);
3530 num_trbs = count_sg_trbs_needed(urb);
3532 num_trbs = count_trbs_needed(urb);
3533 addr = (u64) urb->transfer_dma;
3534 block_len = full_len;
3536 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3537 ep_index, urb->stream_id,
3538 num_trbs, urb, 0, mem_flags);
3539 if (unlikely(ret < 0))
3542 urb_priv = urb->hcpriv;
3544 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3545 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3546 need_zero_pkt = true;
3548 td = &urb_priv->td[0];
3551 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3552 * until we've finished creating all the other TRBs. The ring's cycle
3553 * state may change as we enqueue the other TRBs, so save it too.
3555 start_trb = &ring->enqueue->generic;
3556 start_cycle = ring->cycle_state;
3559 /* Queue the TRBs, even if they are zero-length */
3560 for (enqd_len = 0; first_trb || enqd_len < full_len;
3561 enqd_len += trb_buff_len) {
3562 field = TRB_TYPE(TRB_NORMAL);
3564 /* TRB buffer should not cross 64KB boundaries */
3565 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3566 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3568 if (enqd_len + trb_buff_len > full_len)
3569 trb_buff_len = full_len - enqd_len;
3571 /* Don't change the cycle bit of the first TRB until later */
3574 if (start_cycle == 0)
3577 field |= ring->cycle_state;
3579 /* Chain all the TRBs together; clear the chain bit in the last
3580 * TRB to indicate it's the last TRB in the chain.
3582 if (enqd_len + trb_buff_len < full_len) {
3584 if (trb_is_link(ring->enqueue + 1)) {
3585 if (xhci_align_td(xhci, urb, enqd_len,
3588 send_addr = ring->enq_seg->bounce_dma;
3589 /* assuming TD won't span 2 segs */
3590 td->bounce_seg = ring->enq_seg;
3594 if (enqd_len + trb_buff_len >= full_len) {
3595 field &= ~TRB_CHAIN;
3597 more_trbs_coming = false;
3598 td->last_trb = ring->enqueue;
3599 td->last_trb_seg = ring->enq_seg;
3600 if (xhci_urb_suitable_for_idt(urb)) {
3601 memcpy(&send_addr, urb->transfer_buffer,
3603 le64_to_cpus(&send_addr);
3608 /* Only set interrupt on short packet for IN endpoints */
3609 if (usb_urb_dir_in(urb))
3612 /* Set the TRB length, TD size, and interrupter fields. */
3613 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3614 full_len, urb, more_trbs_coming);
3616 length_field = TRB_LEN(trb_buff_len) |
3617 TRB_TD_SIZE(remainder) |
3620 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3621 lower_32_bits(send_addr),
3622 upper_32_bits(send_addr),
3626 addr += trb_buff_len;
3627 sent_len = trb_buff_len;
3629 while (sg && sent_len >= block_len) {
3632 sent_len -= block_len;
3634 if (num_sgs != 0 && sg) {
3635 block_len = sg_dma_len(sg);
3636 addr = (u64) sg_dma_address(sg);
3640 block_len -= sent_len;
3644 if (need_zero_pkt) {
3645 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3646 ep_index, urb->stream_id,
3647 1, urb, 1, mem_flags);
3648 urb_priv->td[1].last_trb = ring->enqueue;
3649 urb_priv->td[1].last_trb_seg = ring->enq_seg;
3650 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3651 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3652 urb_priv->td[1].num_trbs++;
3655 check_trb_math(urb, enqd_len);
3656 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3657 start_cycle, start_trb);
3661 /* Caller must have locked xhci->lock */
3662 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3663 struct urb *urb, int slot_id, unsigned int ep_index)
3665 struct xhci_ring *ep_ring;
3668 struct usb_ctrlrequest *setup;
3669 struct xhci_generic_trb *start_trb;
3672 struct urb_priv *urb_priv;
3675 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3680 * Need to copy setup packet into setup TRB, so we can't use the setup
3683 if (!urb->setup_packet)
3686 /* 1 TRB for setup, 1 for status */
3689 * Don't need to check if we need additional event data and normal TRBs,
3690 * since data in control transfers will never get bigger than 16MB
3691 * XXX: can we get a buffer that crosses 64KB boundaries?
3693 if (urb->transfer_buffer_length > 0)
3695 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3696 ep_index, urb->stream_id,
3697 num_trbs, urb, 0, mem_flags);
3701 urb_priv = urb->hcpriv;
3702 td = &urb_priv->td[0];
3703 td->num_trbs = num_trbs;
3706 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3707 * until we've finished creating all the other TRBs. The ring's cycle
3708 * state may change as we enqueue the other TRBs, so save it too.
3710 start_trb = &ep_ring->enqueue->generic;
3711 start_cycle = ep_ring->cycle_state;
3713 /* Queue setup TRB - see section 6.4.1.2.1 */
3714 /* FIXME better way to translate setup_packet into two u32 fields? */
3715 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3717 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3718 if (start_cycle == 0)
3721 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3722 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3723 if (urb->transfer_buffer_length > 0) {
3724 if (setup->bRequestType & USB_DIR_IN)
3725 field |= TRB_TX_TYPE(TRB_DATA_IN);
3727 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3731 queue_trb(xhci, ep_ring, true,
3732 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3733 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3734 TRB_LEN(8) | TRB_INTR_TARGET(0),
3735 /* Immediate data in pointer */
3738 /* If there's data, queue data TRBs */
3739 /* Only set interrupt on short packet for IN endpoints */
3740 if (usb_urb_dir_in(urb))
3741 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3743 field = TRB_TYPE(TRB_DATA);
3745 if (urb->transfer_buffer_length > 0) {
3746 u32 length_field, remainder;
3749 if (xhci_urb_suitable_for_idt(urb)) {
3750 memcpy(&addr, urb->transfer_buffer,
3751 urb->transfer_buffer_length);
3752 le64_to_cpus(&addr);
3755 addr = (u64) urb->transfer_dma;
3758 remainder = xhci_td_remainder(xhci, 0,
3759 urb->transfer_buffer_length,
3760 urb->transfer_buffer_length,
3762 length_field = TRB_LEN(urb->transfer_buffer_length) |
3763 TRB_TD_SIZE(remainder) |
3765 if (setup->bRequestType & USB_DIR_IN)
3766 field |= TRB_DIR_IN;
3767 queue_trb(xhci, ep_ring, true,
3768 lower_32_bits(addr),
3769 upper_32_bits(addr),
3771 field | ep_ring->cycle_state);
3774 /* Save the DMA address of the last TRB in the TD */
3775 td->last_trb = ep_ring->enqueue;
3776 td->last_trb_seg = ep_ring->enq_seg;
3778 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3779 /* If the device sent data, the status stage is an OUT transfer */
3780 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3784 queue_trb(xhci, ep_ring, false,
3788 /* Event on completion */
3789 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3791 giveback_first_trb(xhci, slot_id, ep_index, 0,
3792 start_cycle, start_trb);
3797 * The transfer burst count field of the isochronous TRB defines the number of
3798 * bursts that are required to move all packets in this TD. Only SuperSpeed
3799 * devices can burst up to bMaxBurst number of packets per service interval.
3800 * This field is zero based, meaning a value of zero in the field means one
3801 * burst. Basically, for everything but SuperSpeed devices, this field will be
3802 * zero. Only xHCI 1.0 host controllers support this field.
3804 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3805 struct urb *urb, unsigned int total_packet_count)
3807 unsigned int max_burst;
3809 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3812 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3813 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3817 * Returns the number of packets in the last "burst" of packets. This field is
3818 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3819 * the last burst packet count is equal to the total number of packets in the
3820 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3821 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3822 * contain 1 to (bMaxBurst + 1) packets.
3824 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3825 struct urb *urb, unsigned int total_packet_count)
3827 unsigned int max_burst;
3828 unsigned int residue;
3830 if (xhci->hci_version < 0x100)
3833 if (urb->dev->speed >= USB_SPEED_SUPER) {
3834 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3835 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3836 residue = total_packet_count % (max_burst + 1);
3837 /* If residue is zero, the last burst contains (max_burst + 1)
3838 * number of packets, but the TLBPC field is zero-based.
3844 if (total_packet_count == 0)
3846 return total_packet_count - 1;
3850 * Calculates Frame ID field of the isochronous TRB identifies the
3851 * target frame that the Interval associated with this Isochronous
3852 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3854 * Returns actual frame id on success, negative value on error.
3856 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3857 struct urb *urb, int index)
3859 int start_frame, ist, ret = 0;
3860 int start_frame_id, end_frame_id, current_frame_id;
3862 if (urb->dev->speed == USB_SPEED_LOW ||
3863 urb->dev->speed == USB_SPEED_FULL)
3864 start_frame = urb->start_frame + index * urb->interval;
3866 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3868 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3870 * If bit [3] of IST is cleared to '0', software can add a TRB no
3871 * later than IST[2:0] Microframes before that TRB is scheduled to
3873 * If bit [3] of IST is set to '1', software can add a TRB no later
3874 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3876 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3877 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3880 /* Software shall not schedule an Isoch TD with a Frame ID value that
3881 * is less than the Start Frame ID or greater than the End Frame ID,
3884 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3885 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3887 * Both the End Frame ID and Start Frame ID values are calculated
3888 * in microframes. When software determines the valid Frame ID value;
3889 * The End Frame ID value should be rounded down to the nearest Frame
3890 * boundary, and the Start Frame ID value should be rounded up to the
3891 * nearest Frame boundary.
3893 current_frame_id = readl(&xhci->run_regs->microframe_index);
3894 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3895 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3897 start_frame &= 0x7ff;
3898 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3899 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3901 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3902 __func__, index, readl(&xhci->run_regs->microframe_index),
3903 start_frame_id, end_frame_id, start_frame);
3905 if (start_frame_id < end_frame_id) {
3906 if (start_frame > end_frame_id ||
3907 start_frame < start_frame_id)
3909 } else if (start_frame_id > end_frame_id) {
3910 if ((start_frame > end_frame_id &&
3911 start_frame < start_frame_id))
3918 if (ret == -EINVAL || start_frame == start_frame_id) {
3919 start_frame = start_frame_id + 1;
3920 if (urb->dev->speed == USB_SPEED_LOW ||
3921 urb->dev->speed == USB_SPEED_FULL)
3922 urb->start_frame = start_frame;
3924 urb->start_frame = start_frame << 3;
3930 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3931 start_frame, current_frame_id, index,
3932 start_frame_id, end_frame_id);
3933 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3940 /* Check if we should generate event interrupt for a TD in an isoc URB */
3941 static bool trb_block_event_intr(struct xhci_hcd *xhci, int num_tds, int i)
3943 if (xhci->hci_version < 0x100)
3945 /* always generate an event interrupt for the last TD */
3946 if (i == num_tds - 1)
3949 * If AVOID_BEI is set the host handles full event rings poorly,
3950 * generate an event at least every 8th TD to clear the event ring
3952 if (i && xhci->quirks & XHCI_AVOID_BEI)
3958 /* This is for isoc transfer */
3959 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3960 struct urb *urb, int slot_id, unsigned int ep_index)
3962 struct xhci_ring *ep_ring;
3963 struct urb_priv *urb_priv;
3965 int num_tds, trbs_per_td;
3966 struct xhci_generic_trb *start_trb;
3969 u32 field, length_field;
3970 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3971 u64 start_addr, addr;
3973 bool more_trbs_coming;
3974 struct xhci_virt_ep *xep;
3977 xep = &xhci->devs[slot_id]->eps[ep_index];
3978 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3980 num_tds = urb->number_of_packets;
3982 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3985 start_addr = (u64) urb->transfer_dma;
3986 start_trb = &ep_ring->enqueue->generic;
3987 start_cycle = ep_ring->cycle_state;
3989 urb_priv = urb->hcpriv;
3990 /* Queue the TRBs for each TD, even if they are zero-length */
3991 for (i = 0; i < num_tds; i++) {
3992 unsigned int total_pkt_count, max_pkt;
3993 unsigned int burst_count, last_burst_pkt_count;
3998 addr = start_addr + urb->iso_frame_desc[i].offset;
3999 td_len = urb->iso_frame_desc[i].length;
4000 td_remain_len = td_len;
4001 max_pkt = usb_endpoint_maxp(&urb->ep->desc);
4002 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
4004 /* A zero-length transfer still involves at least one packet. */
4005 if (total_pkt_count == 0)
4007 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
4008 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
4009 urb, total_pkt_count);
4011 trbs_per_td = count_isoc_trbs_needed(urb, i);
4013 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
4014 urb->stream_id, trbs_per_td, urb, i, mem_flags);
4020 td = &urb_priv->td[i];
4021 td->num_trbs = trbs_per_td;
4022 /* use SIA as default, if frame id is used overwrite it */
4023 sia_frame_id = TRB_SIA;
4024 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
4025 HCC_CFC(xhci->hcc_params)) {
4026 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
4028 sia_frame_id = TRB_FRAME_ID(frame_id);
4031 * Set isoc specific data for the first TRB in a TD.
4032 * Prevent HW from getting the TRBs by keeping the cycle state
4033 * inverted in the first TDs isoc TRB.
4035 field = TRB_TYPE(TRB_ISOC) |
4036 TRB_TLBPC(last_burst_pkt_count) |
4038 (i ? ep_ring->cycle_state : !start_cycle);
4040 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
4041 if (!xep->use_extended_tbc)
4042 field |= TRB_TBC(burst_count);
4044 /* fill the rest of the TRB fields, and remaining normal TRBs */
4045 for (j = 0; j < trbs_per_td; j++) {
4048 /* only first TRB is isoc, overwrite otherwise */
4050 field = TRB_TYPE(TRB_NORMAL) |
4051 ep_ring->cycle_state;
4053 /* Only set interrupt on short packet for IN EPs */
4054 if (usb_urb_dir_in(urb))
4057 /* Set the chain bit for all except the last TRB */
4058 if (j < trbs_per_td - 1) {
4059 more_trbs_coming = true;
4062 more_trbs_coming = false;
4063 td->last_trb = ep_ring->enqueue;
4064 td->last_trb_seg = ep_ring->enq_seg;
4066 if (trb_block_event_intr(xhci, num_tds, i))
4069 /* Calculate TRB length */
4070 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
4071 if (trb_buff_len > td_remain_len)
4072 trb_buff_len = td_remain_len;
4074 /* Set the TRB length, TD size, & interrupter fields. */
4075 remainder = xhci_td_remainder(xhci, running_total,
4076 trb_buff_len, td_len,
4077 urb, more_trbs_coming);
4079 length_field = TRB_LEN(trb_buff_len) |
4082 /* xhci 1.1 with ETE uses TD Size field for TBC */
4083 if (first_trb && xep->use_extended_tbc)
4084 length_field |= TRB_TD_SIZE_TBC(burst_count);
4086 length_field |= TRB_TD_SIZE(remainder);
4089 queue_trb(xhci, ep_ring, more_trbs_coming,
4090 lower_32_bits(addr),
4091 upper_32_bits(addr),
4094 running_total += trb_buff_len;
4096 addr += trb_buff_len;
4097 td_remain_len -= trb_buff_len;
4100 /* Check TD length */
4101 if (running_total != td_len) {
4102 xhci_err(xhci, "ISOC TD length unmatch\n");
4108 /* store the next frame id */
4109 if (HCC_CFC(xhci->hcc_params))
4110 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
4112 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
4113 if (xhci->quirks & XHCI_AMD_PLL_FIX)
4114 usb_amd_quirk_pll_disable();
4116 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
4118 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
4119 start_cycle, start_trb);
4122 /* Clean up a partially enqueued isoc transfer. */
4124 for (i--; i >= 0; i--)
4125 list_del_init(&urb_priv->td[i].td_list);
4127 /* Use the first TD as a temporary variable to turn the TDs we've queued
4128 * into No-ops with a software-owned cycle bit. That way the hardware
4129 * won't accidentally start executing bogus TDs when we partially
4130 * overwrite them. td->first_trb and td->start_seg are already set.
4132 urb_priv->td[0].last_trb = ep_ring->enqueue;
4133 /* Every TRB except the first & last will have its cycle bit flipped. */
4134 td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
4136 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
4137 ep_ring->enqueue = urb_priv->td[0].first_trb;
4138 ep_ring->enq_seg = urb_priv->td[0].start_seg;
4139 ep_ring->cycle_state = start_cycle;
4140 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
4141 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
4146 * Check transfer ring to guarantee there is enough room for the urb.
4147 * Update ISO URB start_frame and interval.
4148 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
4149 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
4150 * Contiguous Frame ID is not supported by HC.
4152 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
4153 struct urb *urb, int slot_id, unsigned int ep_index)
4155 struct xhci_virt_device *xdev;
4156 struct xhci_ring *ep_ring;
4157 struct xhci_ep_ctx *ep_ctx;
4159 int num_tds, num_trbs, i;
4161 struct xhci_virt_ep *xep;
4164 xdev = xhci->devs[slot_id];
4165 xep = &xhci->devs[slot_id]->eps[ep_index];
4166 ep_ring = xdev->eps[ep_index].ring;
4167 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
4170 num_tds = urb->number_of_packets;
4171 for (i = 0; i < num_tds; i++)
4172 num_trbs += count_isoc_trbs_needed(urb, i);
4174 /* Check the ring to guarantee there is enough room for the whole urb.
4175 * Do not insert any td of the urb to the ring if the check failed.
4177 ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
4178 num_trbs, mem_flags);
4183 * Check interval value. This should be done before we start to
4184 * calculate the start frame value.
4186 check_interval(xhci, urb, ep_ctx);
4188 /* Calculate the start frame and put it in urb->start_frame. */
4189 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
4190 if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
4191 urb->start_frame = xep->next_frame_id;
4192 goto skip_start_over;
4196 start_frame = readl(&xhci->run_regs->microframe_index);
4197 start_frame &= 0x3fff;
4199 * Round up to the next frame and consider the time before trb really
4200 * gets scheduled by hardare.
4202 ist = HCS_IST(xhci->hcs_params2) & 0x7;
4203 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
4205 start_frame += ist + XHCI_CFC_DELAY;
4206 start_frame = roundup(start_frame, 8);
4209 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
4210 * is greate than 8 microframes.
4212 if (urb->dev->speed == USB_SPEED_LOW ||
4213 urb->dev->speed == USB_SPEED_FULL) {
4214 start_frame = roundup(start_frame, urb->interval << 3);
4215 urb->start_frame = start_frame >> 3;
4217 start_frame = roundup(start_frame, urb->interval);
4218 urb->start_frame = start_frame;
4222 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
4224 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
4227 /**** Command Ring Operations ****/
4229 /* Generic function for queueing a command TRB on the command ring.
4230 * Check to make sure there's room on the command ring for one command TRB.
4231 * Also check that there's room reserved for commands that must not fail.
4232 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4233 * then only check for the number of reserved spots.
4234 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4235 * because the command event handler may want to resubmit a failed command.
4237 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4238 u32 field1, u32 field2,
4239 u32 field3, u32 field4, bool command_must_succeed)
4241 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
4244 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
4245 (xhci->xhc_state & XHCI_STATE_HALTED)) {
4246 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
4250 if (!command_must_succeed)
4253 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
4254 reserved_trbs, GFP_ATOMIC);
4256 xhci_err(xhci, "ERR: No room for command on command ring\n");
4257 if (command_must_succeed)
4258 xhci_err(xhci, "ERR: Reserved TRB counting for "
4259 "unfailable commands failed.\n");
4263 cmd->command_trb = xhci->cmd_ring->enqueue;
4265 /* if there are no other commands queued we start the timeout timer */
4266 if (list_empty(&xhci->cmd_list)) {
4267 xhci->current_cmd = cmd;
4268 xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
4271 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
4273 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
4274 field4 | xhci->cmd_ring->cycle_state);
4278 /* Queue a slot enable or disable request on the command ring */
4279 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
4280 u32 trb_type, u32 slot_id)
4282 return queue_command(xhci, cmd, 0, 0, 0,
4283 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
4286 /* Queue an address device command TRB */
4287 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4288 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
4290 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4291 upper_32_bits(in_ctx_ptr), 0,
4292 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
4293 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
4296 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
4297 u32 field1, u32 field2, u32 field3, u32 field4)
4299 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
4302 /* Queue a reset device command TRB */
4303 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
4306 return queue_command(xhci, cmd, 0, 0, 0,
4307 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
4311 /* Queue a configure endpoint command TRB */
4312 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
4313 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
4314 u32 slot_id, bool command_must_succeed)
4316 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4317 upper_32_bits(in_ctx_ptr), 0,
4318 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
4319 command_must_succeed);
4322 /* Queue an evaluate context command TRB */
4323 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
4324 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
4326 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
4327 upper_32_bits(in_ctx_ptr), 0,
4328 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
4329 command_must_succeed);
4333 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4334 * activity on an endpoint that is about to be suspended.
4336 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
4337 int slot_id, unsigned int ep_index, int suspend)
4339 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4340 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4341 u32 type = TRB_TYPE(TRB_STOP_RING);
4342 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
4344 return queue_command(xhci, cmd, 0, 0, 0,
4345 trb_slot_id | trb_ep_index | type | trb_suspend, false);
4348 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4349 int slot_id, unsigned int ep_index,
4350 enum xhci_ep_reset_type reset_type)
4352 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4353 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4354 u32 type = TRB_TYPE(TRB_RESET_EP);
4356 if (reset_type == EP_SOFT_RESET)
4359 return queue_command(xhci, cmd, 0, 0, 0,
4360 trb_slot_id | trb_ep_index | type, false);