drivers/usb/host/xhci-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver PCI Bus Glue.
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11 #include <linux/pci.h>
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <linux/acpi.h>
  15 #include <linux/reset.h>
  16
  17 #include "xhci.h"
  18 #include "xhci-trace.h"
  19 #include "xhci-pci.h"
  20
  21 #define SSIC_PORT_NUM           2
  22 #define SSIC_PORT_CFG2          0x880c
  23 #define SSIC_PORT_CFG2_OFFSET   0x30
  24 #define PROG_DONE               (1 << 30)
  25 #define SSIC_PORT_UNUSED        (1 << 31)
  26 #define SPARSE_DISABLE_BIT      17
  27 #define SPARSE_CNTL_ENABLE      0xC12C
  28
  29 /* Device for a quirk */
  30 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  34
  35 #define PCI_VENDOR_ID_ETRON             0x1b6f
  36 #define PCI_DEVICE_ID_EJ168             0x7023
  37
  38 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  40 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  41 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  42 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  43 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  44 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  45 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  46 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  47 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  48 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI        0x15b5
  49 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI        0x15b6
  50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI      0x15db
  51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI      0x15d4
  52 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI         0x15e9
  53 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI         0x15ec
  54 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI         0x15f0
  55 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI               0x8a13
  56 #define PCI_DEVICE_ID_INTEL_CML_XHCI                    0xa3af
  57 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI             0x9a13
  58
  59 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4                 0x43b9
  60 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3                 0x43ba
  61 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2                 0x43bb
  62 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1                 0x43bc
  63 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI                 0x1042
  64 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  65 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI                 0x1242
  66 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI                 0x2142
  67
  68 static const char hcd_name[] = "xhci_hcd";
  69
  70 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  71
  72 static int xhci_pci_setup(struct usb_hcd *hcd);
  73
  74 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  75         .reset = xhci_pci_setup,
  76 };
  77
  78 /* called after powerup, by probe or system-pm "wakeup" */
  79 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  80 {
  81         /*
  82          * TODO: Implement finding debug ports later.
  83          * TODO: see if there are any quirks that need to be added to handle
  84          * new extended capabilities.
  85          */
  86
  87         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  88         if (!pci_set_mwi(pdev))
  89                 xhci_dbg(xhci, "MWI active\n");
  90
  91         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  92         return 0;
  93 }
  94
  95 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  96 {
  97         struct pci_dev                  *pdev = to_pci_dev(dev);
  98         struct xhci_driver_data         *driver_data;
  99         const struct pci_device_id      *id;
 100
 101         id = pci_match_id(pdev->driver->id_table, pdev);
 102
 103         if (id && id->driver_data) {
 104                 driver_data = (struct xhci_driver_data *)id->driver_data;
 105                 xhci->quirks |= driver_data->quirks;
 106         }
 107
 108         /* Look for vendor-specific quirks */
 109         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 110                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
 111                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
 112                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 113                                 pdev->revision == 0x0) {
 114                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
 115                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 116                                 "QUIRK: Fresco Logic xHC needs configure"
 117                                 " endpoint cmd after reset endpoint");
 118                 }
 119                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 120                                 pdev->revision == 0x4) {
 121                         xhci->quirks |= XHCI_SLOW_SUSPEND;
 122                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 123                                 "QUIRK: Fresco Logic xHC revision %u"
 124                                 "must be suspended extra slowly",
 125                                 pdev->revision);
 126                 }
 127                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 128                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 129                 /* Fresco Logic confirms: all revisions of this chip do not
 130                  * support MSI, even though some of them claim to in their PCI
 131                  * capabilities.
 132                  */
 133                 xhci->quirks |= XHCI_BROKEN_MSI;
 134                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 135                                 "QUIRK: Fresco Logic revision %u "
 136                                 "has broken MSI implementation",
 137                                 pdev->revision);
 138                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 139         }
 140
 141         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 142                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 143                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 144
 145         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 146                 xhci->quirks |= XHCI_NEC_HOST;
 147
 148         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 149                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 150
 151         /* AMD PLL quirk */
 152         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
 153                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 154
 155         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 156                 (pdev->device == 0x145c ||
 157                  pdev->device == 0x15e0 ||
 158                  pdev->device == 0x15e1 ||
 159                  pdev->device == 0x43bb))
 160                 xhci->quirks |= XHCI_SUSPEND_DELAY;
 161
 162         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 163             (pdev->device == 0x15e0 || pdev->device == 0x15e1))
 164                 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
 165
 166         if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5)
 167                 xhci->quirks |= XHCI_DISABLE_SPARSE;
 168
 169         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 170                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 171
 172         if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
 173                 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
 174                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
 175                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
 176                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
 177                 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
 178
 179         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 180                 xhci->quirks |= XHCI_LPM_SUPPORT;
 181                 xhci->quirks |= XHCI_INTEL_HOST;
 182                 xhci->quirks |= XHCI_AVOID_BEI;
 183         }
 184         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 185                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 186                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 187                 xhci->limit_active_eps = 64;
 188                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 189                 /*
 190                  * PPT desktop boards DH77EB and DH77DF will power back on after
 191                  * a few seconds of being shutdown.  The fix for this is to
 192                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 193                  * DMI information to find those particular boards (since each
 194                  * vendor will change the board name), so we have to key off all
 195                  * PPT chipsets.
 196                  */
 197                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 198         }
 199         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 200                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 201                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 202                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 203                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 204         }
 205         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 206                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 207                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 208                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 209                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 210                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 211                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 212                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
 213                  pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
 214                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 215         }
 216         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 217             pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
 218                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 219         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 220             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 221              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 222              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
 223                 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
 224         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 225             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 226              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 227              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 228              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 229              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 230                 xhci->quirks |= XHCI_MISSING_CAS;
 231
 232         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 233             (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
 234              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
 235              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
 236              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
 237              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
 238              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
 239              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
 240              pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
 241              pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI))
 242                 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 243
 244         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 245                         pdev->device == PCI_DEVICE_ID_EJ168) {
 246                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 247                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 248                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 249         }
 250         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 251             pdev->device == 0x0014) {
 252                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 253                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 254         }
 255         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 256             pdev->device == 0x0015) {
 257                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 258                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 259         }
 260         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 261                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 262
 263         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 264         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 265                         pdev->device == 0x3432)
 266                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 267
 268         if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483)
 269                 xhci->quirks |= XHCI_LPM_SUPPORT;
 270
 271         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 272                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI)
 273                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 274         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 275                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 276                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 277         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 278             (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
 279              pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI))
 280                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 281
 282         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 283                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 284                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 285
 286         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 287                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 288
 289         if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
 290              pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
 291              pdev->device == 0x9026)
 292                 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
 293
 294         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 295                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 296                                 "QUIRK: Resetting on resume");
 297 }
 298
 299 #ifdef CONFIG_ACPI
 300 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 301 {
 302         static const guid_t intel_dsm_guid =
 303                 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
 304                           0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
 305         union acpi_object *obj;
 306
 307         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
 308                                 NULL);
 309         ACPI_FREE(obj);
 310 }
 311 #else
 312 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 313 #endif /* CONFIG_ACPI */
 314
 315 /* called during probe() after chip reset completes */
 316 static int xhci_pci_setup(struct usb_hcd *hcd)
 317 {
 318         struct xhci_hcd         *xhci;
 319         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 320         int                     retval;
 321
 322         xhci = hcd_to_xhci(hcd);
 323         if (!xhci->sbrn)
 324                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 325
 326         /* imod_interval is the interrupt moderation value in nanoseconds. */
 327         xhci->imod_interval = 40000;
 328
 329         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 330         if (retval)
 331                 return retval;
 332
 333         if (!usb_hcd_is_primary_hcd(hcd))
 334                 return 0;
 335
 336         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 337                 xhci_pme_acpi_rtd3_enable(pdev);
 338
 339         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 340
 341         /* Find any debug ports */
 342         return xhci_pci_reinit(xhci, pdev);
 343 }
 344
 345 /*
 346  * We need to register our own PCI probe function (instead of the USB core's
 347  * function) in order to create a second roothub under xHCI.
 348  */
 349 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 350 {
 351         int retval;
 352         struct xhci_hcd *xhci;
 353         struct usb_hcd *hcd;
 354         struct xhci_driver_data *driver_data;
 355         struct reset_control *reset;
 356
 357         driver_data = (struct xhci_driver_data *)id->driver_data;
 358         if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
 359                 retval = renesas_xhci_check_request_fw(dev, id);
 360                 if (retval)
 361                         return retval;
 362         }
 363
 364         reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
 365         if (IS_ERR(reset))
 366                 return PTR_ERR(reset);
 367         reset_control_reset(reset);
 368
 369         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 370         pm_runtime_get_noresume(&dev->dev);
 371
 372         /* Register the USB 2.0 roothub.
 373          * FIXME: USB core must know to register the USB 2.0 roothub first.
 374          * This is sort of silly, because we could just set the HCD driver flags
 375          * to say USB 2.0, but I'm not sure what the implications would be in
 376          * the other parts of the HCD code.
 377          */
 378         retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver);
 379
 380         if (retval)
 381                 goto put_runtime_pm;
 382
 383         /* USB 2.0 roothub is stored in the PCI device now. */
 384         hcd = dev_get_drvdata(&dev->dev);
 385         xhci = hcd_to_xhci(hcd);
 386         xhci->reset = reset;
 387         xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
 388                                                  pci_name(dev), hcd);
 389         if (!xhci->shared_hcd) {
 390                 retval = -ENOMEM;
 391                 goto dealloc_usb2_hcd;
 392         }
 393
 394         retval = xhci_ext_cap_init(xhci);
 395         if (retval)
 396                 goto put_usb3_hcd;
 397
 398         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 399                         IRQF_SHARED);
 400         if (retval)
 401                 goto put_usb3_hcd;
 402         /* Roothub already marked as USB 3.0 speed */
 403
 404         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 405                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 406                 xhci->shared_hcd->can_do_streams = 1;
 407
 408         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 409         pm_runtime_put_noidle(&dev->dev);
 410
 411         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 412                 pm_runtime_allow(&dev->dev);
 413
 414         return 0;
 415
 416 put_usb3_hcd:
 417         usb_put_hcd(xhci->shared_hcd);
 418 dealloc_usb2_hcd:
 419         usb_hcd_pci_remove(dev);
 420 put_runtime_pm:
 421         pm_runtime_put_noidle(&dev->dev);
 422         return retval;
 423 }
 424
 425 static void xhci_pci_remove(struct pci_dev *dev)
 426 {
 427         struct xhci_hcd *xhci;
 428
 429         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 430         if (xhci->quirks & XHCI_RENESAS_FW_QUIRK)
 431                 renesas_xhci_pci_exit(dev);
 432
 433         xhci->xhc_state |= XHCI_STATE_REMOVING;
 434
 435         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 436                 pm_runtime_forbid(&dev->dev);
 437
 438         if (xhci->shared_hcd) {
 439                 usb_remove_hcd(xhci->shared_hcd);
 440                 usb_put_hcd(xhci->shared_hcd);
 441                 xhci->shared_hcd = NULL;
 442         }
 443
 444         /* Workaround for spurious wakeups at shutdown with HSW */
 445         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 446                 pci_set_power_state(dev, PCI_D3hot);
 447
 448         usb_hcd_pci_remove(dev);
 449 }
 450
 451 #ifdef CONFIG_PM
 452 /*
 453  * In some Intel xHCI controllers, in order to get D3 working,
 454  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 455  * SSIC PORT need to be marked as "unused" before putting xHCI
 456  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 457  * Without this change, xHCI might not enter D3 state.
 458  */
 459 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 460 {
 461         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 462         u32 val;
 463         void __iomem *reg;
 464         int i;
 465
 466         for (i = 0; i < SSIC_PORT_NUM; i++) {
 467                 reg = (void __iomem *) xhci->cap_regs +
 468                                 SSIC_PORT_CFG2 +
 469                                 i * SSIC_PORT_CFG2_OFFSET;
 470
 471                 /* Notify SSIC that SSIC profile programming is not done. */
 472                 val = readl(reg) & ~PROG_DONE;
 473                 writel(val, reg);
 474
 475                 /* Mark SSIC port as unused(suspend) or used(resume) */
 476                 val = readl(reg);
 477                 if (suspend)
 478                         val |= SSIC_PORT_UNUSED;
 479                 else
 480                         val &= ~SSIC_PORT_UNUSED;
 481                 writel(val, reg);
 482
 483                 /* Notify SSIC that SSIC profile programming is done */
 484                 val = readl(reg) | PROG_DONE;
 485                 writel(val, reg);
 486                 readl(reg);
 487         }
 488 }
 489
 490 /*
 491  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 492  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 493  */
 494 static void xhci_pme_quirk(struct usb_hcd *hcd)
 495 {
 496         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 497         void __iomem *reg;
 498         u32 val;
 499
 500         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 501         val = readl(reg);
 502         writel(val | BIT(28), reg);
 503         readl(reg);
 504 }
 505
 506 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
 507 {
 508         u32 reg;
 509
 510         reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
 511         reg &= ~BIT(SPARSE_DISABLE_BIT);
 512         writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
 513 }
 514
 515 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 516 {
 517         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 518         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 519         int                     ret;
 520
 521         /*
 522          * Systems with the TI redriver that loses port status change events
 523          * need to have the registers polled during D3, so avoid D3cold.
 524          */
 525         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 526                 pci_d3cold_disable(pdev);
 527
 528         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 529                 xhci_pme_quirk(hcd);
 530
 531         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 532                 xhci_ssic_port_unused_quirk(hcd, true);
 533
 534         if (xhci->quirks & XHCI_DISABLE_SPARSE)
 535                 xhci_sparse_control_quirk(hcd);
 536
 537         ret = xhci_suspend(xhci, do_wakeup);
 538         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 539                 xhci_ssic_port_unused_quirk(hcd, false);
 540
 541         return ret;
 542 }
 543
 544 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 545 {
 546         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 547         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 548         int                     retval = 0;
 549
 550         reset_control_reset(xhci->reset);
 551
 552         /* The BIOS on systems with the Intel Panther Point chipset may or may
 553          * not support xHCI natively.  That means that during system resume, it
 554          * may switch the ports back to EHCI so that users can use their
 555          * keyboard to select a kernel from GRUB after resume from hibernate.
 556          *
 557          * The BIOS is supposed to remember whether the OS had xHCI ports
 558          * enabled before resume, and switch the ports back to xHCI when the
 559          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 560          * writers.
 561          *
 562          * Unconditionally switch the ports back to xHCI after a system resume.
 563          * It should not matter whether the EHCI or xHCI controller is
 564          * resumed first. It's enough to do the switchover in xHCI because
 565          * USB core won't notice anything as the hub driver doesn't start
 566          * running again until after all the devices (including both EHCI and
 567          * xHCI host controllers) have been resumed.
 568          */
 569
 570         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 571                 usb_enable_intel_xhci_ports(pdev);
 572
 573         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 574                 xhci_ssic_port_unused_quirk(hcd, false);
 575
 576         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 577                 xhci_pme_quirk(hcd);
 578
 579         retval = xhci_resume(xhci, hibernated);
 580         return retval;
 581 }
 582
 583 static void xhci_pci_shutdown(struct usb_hcd *hcd)
 584 {
 585         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 586         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 587
 588         xhci_shutdown(hcd);
 589
 590         /* Yet another workaround for spurious wakeups at shutdown with HSW */
 591         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 592                 pci_set_power_state(pdev, PCI_D3hot);
 593 }
 594 #endif /* CONFIG_PM */
 595
 596 /*-------------------------------------------------------------------------*/
 597
 598 static const struct xhci_driver_data reneses_data = {
 599         .quirks  = XHCI_RENESAS_FW_QUIRK,
 600         .firmware = "renesas_usb_fw.mem",
 601 };
 602
 603 /* PCI driver selection metadata; PCI hotplugging uses this */
 604 static const struct pci_device_id pci_ids[] = {
 605         { PCI_DEVICE(0x1912, 0x0014),
 606                 .driver_data =  (unsigned long)&reneses_data,
 607         },
 608         { PCI_DEVICE(0x1912, 0x0015),
 609                 .driver_data =  (unsigned long)&reneses_data,
 610         },
 611         /* handle any USB 3.0 xHCI controller */
 612         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 613         },
 614         { /* end: all zeroes */ }
 615 };
 616 MODULE_DEVICE_TABLE(pci, pci_ids);
 617 MODULE_FIRMWARE("renesas_usb_fw.mem");
 618
 619 /* pci driver glue; this is a "new style" PCI driver module */
 620 static struct pci_driver xhci_pci_driver = {
 621         .name =         hcd_name,
 622         .id_table =     pci_ids,
 623
 624         .probe =        xhci_pci_probe,
 625         .remove =       xhci_pci_remove,
 626         /* suspend and resume implemented later */
 627
 628         .shutdown =     usb_hcd_pci_shutdown,
 629 #ifdef CONFIG_PM
 630         .driver = {
 631                 .pm = &usb_hcd_pci_pm_ops
 632         },
 633 #endif
 634 };
 635
 636 static int __init xhci_pci_init(void)
 637 {
 638         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 639 #ifdef CONFIG_PM
 640         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 641         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 642         xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
 643 #endif
 644         return pci_register_driver(&xhci_pci_driver);
 645 }
 646 module_init(xhci_pci_init);
 647
 648 static void __exit xhci_pci_exit(void)
 649 {
 650         pci_unregister_driver(&xhci_pci_driver);
 651 }
 652 module_exit(xhci_pci_exit);
 653
 654 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 655 MODULE_LICENSE("GPL");