drivers/usb/host/xhci-pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver PCI Bus Glue.
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11 #include <linux/pci.h>
  12 #include <linux/slab.h>
  13 #include <linux/module.h>
  14 #include <linux/acpi.h>
  15
  16 #include "xhci.h"
  17 #include "xhci-trace.h"
  18 #include "xhci-pci.h"
  19
  20 #define SSIC_PORT_NUM           2
  21 #define SSIC_PORT_CFG2          0x880c
  22 #define SSIC_PORT_CFG2_OFFSET   0x30
  23 #define PROG_DONE               (1 << 30)
  24 #define SSIC_PORT_UNUSED        (1 << 31)
  25
  26 /* Device for a quirk */
  27 #define PCI_VENDOR_ID_FRESCO_LOGIC      0x1b73
  28 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK  0x1000
  29 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009       0x1009
  30 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400       0x1400
  31
  32 #define PCI_VENDOR_ID_ETRON             0x1b6f
  33 #define PCI_DEVICE_ID_EJ168             0x7023
  34
  35 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI      0x8c31
  36 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI   0x9c31
  37 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI        0x9cb1
  38 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI             0x22b5
  39 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI         0xa12f
  40 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI        0x9d2f
  41 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI              0x0aa8
  42 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI              0x1aa8
  43 #define PCI_DEVICE_ID_INTEL_APL_XHCI                    0x5aa8
  44 #define PCI_DEVICE_ID_INTEL_DNV_XHCI                    0x19d0
  45 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI        0x15b5
  46 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI        0x15b6
  47 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI      0x15db
  48 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI      0x15d4
  49 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI         0x15e9
  50 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI         0x15ec
  51 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI         0x15f0
  52 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI               0x8a13
  53 #define PCI_DEVICE_ID_INTEL_CML_XHCI                    0xa3af
  54 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI             0x9a13
  55
  56 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4                 0x43b9
  57 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3                 0x43ba
  58 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2                 0x43bb
  59 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1                 0x43bc
  60 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI                 0x1042
  61 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI                0x1142
  62 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI                 0x2142
  63
  64 static const char hcd_name[] = "xhci_hcd";
  65
  66 static struct hc_driver __read_mostly xhci_pci_hc_driver;
  67
  68 static int xhci_pci_setup(struct usb_hcd *hcd);
  69
  70 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
  71         .reset = xhci_pci_setup,
  72 };
  73
  74 /* called after powerup, by probe or system-pm "wakeup" */
  75 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
  76 {
  77         /*
  78          * TODO: Implement finding debug ports later.
  79          * TODO: see if there are any quirks that need to be added to handle
  80          * new extended capabilities.
  81          */
  82
  83         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  84         if (!pci_set_mwi(pdev))
  85                 xhci_dbg(xhci, "MWI active\n");
  86
  87         xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
  88         return 0;
  89 }
  90
  91 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
  92 {
  93         struct pci_dev                  *pdev = to_pci_dev(dev);
  94         struct xhci_driver_data         *driver_data;
  95         const struct pci_device_id      *id;
  96
  97         id = pci_match_id(pdev->driver->id_table, pdev);
  98
  99         if (id && id->driver_data) {
 100                 driver_data = (struct xhci_driver_data *)id->driver_data;
 101                 xhci->quirks |= driver_data->quirks;
 102         }
 103
 104         /* Look for vendor-specific quirks */
 105         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 106                         (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
 107                          pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
 108                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 109                                 pdev->revision == 0x0) {
 110                         xhci->quirks |= XHCI_RESET_EP_QUIRK;
 111                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 112                                 "QUIRK: Fresco Logic xHC needs configure"
 113                                 " endpoint cmd after reset endpoint");
 114                 }
 115                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
 116                                 pdev->revision == 0x4) {
 117                         xhci->quirks |= XHCI_SLOW_SUSPEND;
 118                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 119                                 "QUIRK: Fresco Logic xHC revision %u"
 120                                 "must be suspended extra slowly",
 121                                 pdev->revision);
 122                 }
 123                 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
 124                         xhci->quirks |= XHCI_BROKEN_STREAMS;
 125                 /* Fresco Logic confirms: all revisions of this chip do not
 126                  * support MSI, even though some of them claim to in their PCI
 127                  * capabilities.
 128                  */
 129                 xhci->quirks |= XHCI_BROKEN_MSI;
 130                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 131                                 "QUIRK: Fresco Logic revision %u "
 132                                 "has broken MSI implementation",
 133                                 pdev->revision);
 134                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 135         }
 136
 137         if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
 138                         pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
 139                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 140
 141         if (pdev->vendor == PCI_VENDOR_ID_NEC)
 142                 xhci->quirks |= XHCI_NEC_HOST;
 143
 144         if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
 145                 xhci->quirks |= XHCI_AMD_0x96_HOST;
 146
 147         /* AMD PLL quirk */
 148         if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
 149                 xhci->quirks |= XHCI_AMD_PLL_FIX;
 150
 151         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 152                 (pdev->device == 0x145c ||
 153                  pdev->device == 0x15e0 ||
 154                  pdev->device == 0x15e1 ||
 155                  pdev->device == 0x43bb))
 156                 xhci->quirks |= XHCI_SUSPEND_DELAY;
 157
 158         if (pdev->vendor == PCI_VENDOR_ID_AMD &&
 159             (pdev->device == 0x15e0 || pdev->device == 0x15e1))
 160                 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
 161
 162         if (pdev->vendor == PCI_VENDOR_ID_AMD)
 163                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 164
 165         if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
 166                 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
 167                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
 168                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
 169                 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
 170                 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
 171
 172         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
 173                 xhci->quirks |= XHCI_LPM_SUPPORT;
 174                 xhci->quirks |= XHCI_INTEL_HOST;
 175                 xhci->quirks |= XHCI_AVOID_BEI;
 176         }
 177         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 178                         pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
 179                 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
 180                 xhci->limit_active_eps = 64;
 181                 xhci->quirks |= XHCI_SW_BW_CHECKING;
 182                 /*
 183                  * PPT desktop boards DH77EB and DH77DF will power back on after
 184                  * a few seconds of being shutdown.  The fix for this is to
 185                  * switch the ports from xHCI to EHCI on shutdown.  We can't use
 186                  * DMI information to find those particular boards (since each
 187                  * vendor will change the board name), so we have to key off all
 188                  * PPT chipsets.
 189                  */
 190                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 191         }
 192         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 193                 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
 194                  pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
 195                 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
 196                 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
 197         }
 198         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 199                 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 200                  pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 201                  pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 202                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
 203                  pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
 204                  pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 205                  pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
 206                  pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
 207                 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
 208         }
 209         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 210             pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
 211                 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
 212         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 213             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 214              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 215              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
 216                 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
 217         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 218             (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
 219              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
 220              pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
 221              pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
 222              pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
 223                 xhci->quirks |= XHCI_MISSING_CAS;
 224
 225         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
 226             (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
 227              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
 228              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
 229              pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
 230              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
 231              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
 232              pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
 233              pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
 234              pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI))
 235                 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
 236
 237         if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
 238                         pdev->device == PCI_DEVICE_ID_EJ168) {
 239                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 240                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 241                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 242         }
 243         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 244             pdev->device == 0x0014) {
 245                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 246                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 247         }
 248         if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
 249             pdev->device == 0x0015) {
 250                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 251                 xhci->quirks |= XHCI_ZERO_64B_REGS;
 252         }
 253         if (pdev->vendor == PCI_VENDOR_ID_VIA)
 254                 xhci->quirks |= XHCI_RESET_ON_RESUME;
 255
 256         /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
 257         if (pdev->vendor == PCI_VENDOR_ID_VIA &&
 258                         pdev->device == 0x3432)
 259                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 260
 261         if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483)
 262                 xhci->quirks |= XHCI_LPM_SUPPORT;
 263
 264         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 265                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI)
 266                 xhci->quirks |= XHCI_BROKEN_STREAMS;
 267         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 268                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 269                 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 270         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 271                 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI)
 272                 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
 273
 274         if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
 275                 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
 276                 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
 277
 278         if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
 279                 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
 280
 281         if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
 282              pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
 283              pdev->device == 0x9026)
 284                 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
 285
 286         if (xhci->quirks & XHCI_RESET_ON_RESUME)
 287                 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 288                                 "QUIRK: Resetting on resume");
 289 }
 290
 291 #ifdef CONFIG_ACPI
 292 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
 293 {
 294         static const guid_t intel_dsm_guid =
 295                 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
 296                           0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
 297         union acpi_object *obj;
 298
 299         obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
 300                                 NULL);
 301         ACPI_FREE(obj);
 302 }
 303 #else
 304 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
 305 #endif /* CONFIG_ACPI */
 306
 307 /* called during probe() after chip reset completes */
 308 static int xhci_pci_setup(struct usb_hcd *hcd)
 309 {
 310         struct xhci_hcd         *xhci;
 311         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 312         int                     retval;
 313
 314         xhci = hcd_to_xhci(hcd);
 315         if (!xhci->sbrn)
 316                 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
 317
 318         /* imod_interval is the interrupt moderation value in nanoseconds. */
 319         xhci->imod_interval = 40000;
 320
 321         retval = xhci_gen_setup(hcd, xhci_pci_quirks);
 322         if (retval)
 323                 return retval;
 324
 325         if (!usb_hcd_is_primary_hcd(hcd))
 326                 return 0;
 327
 328         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 329                 xhci_pme_acpi_rtd3_enable(pdev);
 330
 331         xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
 332
 333         /* Find any debug ports */
 334         return xhci_pci_reinit(xhci, pdev);
 335 }
 336
 337 /*
 338  * We need to register our own PCI probe function (instead of the USB core's
 339  * function) in order to create a second roothub under xHCI.
 340  */
 341 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 342 {
 343         int retval;
 344         struct xhci_hcd *xhci;
 345         struct usb_hcd *hcd;
 346         struct xhci_driver_data *driver_data;
 347
 348         driver_data = (struct xhci_driver_data *)id->driver_data;
 349         if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
 350                 retval = renesas_xhci_check_request_fw(dev, id);
 351                 if (retval)
 352                         return retval;
 353         }
 354
 355         /* Prevent runtime suspending between USB-2 and USB-3 initialization */
 356         pm_runtime_get_noresume(&dev->dev);
 357
 358         /* Register the USB 2.0 roothub.
 359          * FIXME: USB core must know to register the USB 2.0 roothub first.
 360          * This is sort of silly, because we could just set the HCD driver flags
 361          * to say USB 2.0, but I'm not sure what the implications would be in
 362          * the other parts of the HCD code.
 363          */
 364         retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver);
 365
 366         if (retval)
 367                 goto put_runtime_pm;
 368
 369         /* USB 2.0 roothub is stored in the PCI device now. */
 370         hcd = dev_get_drvdata(&dev->dev);
 371         xhci = hcd_to_xhci(hcd);
 372         xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
 373                                                  pci_name(dev), hcd);
 374         if (!xhci->shared_hcd) {
 375                 retval = -ENOMEM;
 376                 goto dealloc_usb2_hcd;
 377         }
 378
 379         retval = xhci_ext_cap_init(xhci);
 380         if (retval)
 381                 goto put_usb3_hcd;
 382
 383         retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
 384                         IRQF_SHARED);
 385         if (retval)
 386                 goto put_usb3_hcd;
 387         /* Roothub already marked as USB 3.0 speed */
 388
 389         if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
 390                         HCC_MAX_PSA(xhci->hcc_params) >= 4)
 391                 xhci->shared_hcd->can_do_streams = 1;
 392
 393         /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
 394         pm_runtime_put_noidle(&dev->dev);
 395
 396         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 397                 pm_runtime_allow(&dev->dev);
 398
 399         return 0;
 400
 401 put_usb3_hcd:
 402         usb_put_hcd(xhci->shared_hcd);
 403 dealloc_usb2_hcd:
 404         usb_hcd_pci_remove(dev);
 405 put_runtime_pm:
 406         pm_runtime_put_noidle(&dev->dev);
 407         return retval;
 408 }
 409
 410 static void xhci_pci_remove(struct pci_dev *dev)
 411 {
 412         struct xhci_hcd *xhci;
 413
 414         xhci = hcd_to_xhci(pci_get_drvdata(dev));
 415         if (xhci->quirks & XHCI_RENESAS_FW_QUIRK)
 416                 renesas_xhci_pci_exit(dev);
 417
 418         xhci->xhc_state |= XHCI_STATE_REMOVING;
 419
 420         if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
 421                 pm_runtime_forbid(&dev->dev);
 422
 423         if (xhci->shared_hcd) {
 424                 usb_remove_hcd(xhci->shared_hcd);
 425                 usb_put_hcd(xhci->shared_hcd);
 426                 xhci->shared_hcd = NULL;
 427         }
 428
 429         /* Workaround for spurious wakeups at shutdown with HSW */
 430         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 431                 pci_set_power_state(dev, PCI_D3hot);
 432
 433         usb_hcd_pci_remove(dev);
 434 }
 435
 436 #ifdef CONFIG_PM
 437 /*
 438  * In some Intel xHCI controllers, in order to get D3 working,
 439  * through a vendor specific SSIC CONFIG register at offset 0x883c,
 440  * SSIC PORT need to be marked as "unused" before putting xHCI
 441  * into D3. After D3 exit, the SSIC port need to be marked as "used".
 442  * Without this change, xHCI might not enter D3 state.
 443  */
 444 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
 445 {
 446         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 447         u32 val;
 448         void __iomem *reg;
 449         int i;
 450
 451         for (i = 0; i < SSIC_PORT_NUM; i++) {
 452                 reg = (void __iomem *) xhci->cap_regs +
 453                                 SSIC_PORT_CFG2 +
 454                                 i * SSIC_PORT_CFG2_OFFSET;
 455
 456                 /* Notify SSIC that SSIC profile programming is not done. */
 457                 val = readl(reg) & ~PROG_DONE;
 458                 writel(val, reg);
 459
 460                 /* Mark SSIC port as unused(suspend) or used(resume) */
 461                 val = readl(reg);
 462                 if (suspend)
 463                         val |= SSIC_PORT_UNUSED;
 464                 else
 465                         val &= ~SSIC_PORT_UNUSED;
 466                 writel(val, reg);
 467
 468                 /* Notify SSIC that SSIC profile programming is done */
 469                 val = readl(reg) | PROG_DONE;
 470                 writel(val, reg);
 471                 readl(reg);
 472         }
 473 }
 474
 475 /*
 476  * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
 477  * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
 478  */
 479 static void xhci_pme_quirk(struct usb_hcd *hcd)
 480 {
 481         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 482         void __iomem *reg;
 483         u32 val;
 484
 485         reg = (void __iomem *) xhci->cap_regs + 0x80a4;
 486         val = readl(reg);
 487         writel(val | BIT(28), reg);
 488         readl(reg);
 489 }
 490
 491 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 492 {
 493         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 494         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 495         int                     ret;
 496
 497         /*
 498          * Systems with the TI redriver that loses port status change events
 499          * need to have the registers polled during D3, so avoid D3cold.
 500          */
 501         if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
 502                 pci_d3cold_disable(pdev);
 503
 504         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 505                 xhci_pme_quirk(hcd);
 506
 507         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 508                 xhci_ssic_port_unused_quirk(hcd, true);
 509
 510         ret = xhci_suspend(xhci, do_wakeup);
 511         if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
 512                 xhci_ssic_port_unused_quirk(hcd, false);
 513
 514         return ret;
 515 }
 516
 517 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 518 {
 519         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 520         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 521         int                     retval = 0;
 522
 523         /* The BIOS on systems with the Intel Panther Point chipset may or may
 524          * not support xHCI natively.  That means that during system resume, it
 525          * may switch the ports back to EHCI so that users can use their
 526          * keyboard to select a kernel from GRUB after resume from hibernate.
 527          *
 528          * The BIOS is supposed to remember whether the OS had xHCI ports
 529          * enabled before resume, and switch the ports back to xHCI when the
 530          * BIOS/OS semaphore is written, but we all know we can't trust BIOS
 531          * writers.
 532          *
 533          * Unconditionally switch the ports back to xHCI after a system resume.
 534          * It should not matter whether the EHCI or xHCI controller is
 535          * resumed first. It's enough to do the switchover in xHCI because
 536          * USB core won't notice anything as the hub driver doesn't start
 537          * running again until after all the devices (including both EHCI and
 538          * xHCI host controllers) have been resumed.
 539          */
 540
 541         if (pdev->vendor == PCI_VENDOR_ID_INTEL)
 542                 usb_enable_intel_xhci_ports(pdev);
 543
 544         if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
 545                 xhci_ssic_port_unused_quirk(hcd, false);
 546
 547         if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
 548                 xhci_pme_quirk(hcd);
 549
 550         retval = xhci_resume(xhci, hibernated);
 551         return retval;
 552 }
 553
 554 static void xhci_pci_shutdown(struct usb_hcd *hcd)
 555 {
 556         struct xhci_hcd         *xhci = hcd_to_xhci(hcd);
 557         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 558
 559         xhci_shutdown(hcd);
 560
 561         /* Yet another workaround for spurious wakeups at shutdown with HSW */
 562         if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
 563                 pci_set_power_state(pdev, PCI_D3hot);
 564 }
 565 #endif /* CONFIG_PM */
 566
 567 /*-------------------------------------------------------------------------*/
 568
 569 static const struct xhci_driver_data reneses_data = {
 570         .quirks  = XHCI_RENESAS_FW_QUIRK,
 571         .firmware = "renesas_usb_fw.mem",
 572 };
 573
 574 /* PCI driver selection metadata; PCI hotplugging uses this */
 575 static const struct pci_device_id pci_ids[] = {
 576         { PCI_DEVICE(0x1912, 0x0014),
 577                 .driver_data =  (unsigned long)&reneses_data,
 578         },
 579         { PCI_DEVICE(0x1912, 0x0015),
 580                 .driver_data =  (unsigned long)&reneses_data,
 581         },
 582         /* handle any USB 3.0 xHCI controller */
 583         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
 584         },
 585         { /* end: all zeroes */ }
 586 };
 587 MODULE_DEVICE_TABLE(pci, pci_ids);
 588 MODULE_FIRMWARE("renesas_usb_fw.mem");
 589
 590 /* pci driver glue; this is a "new style" PCI driver module */
 591 static struct pci_driver xhci_pci_driver = {
 592         .name =         hcd_name,
 593         .id_table =     pci_ids,
 594
 595         .probe =        xhci_pci_probe,
 596         .remove =       xhci_pci_remove,
 597         /* suspend and resume implemented later */
 598
 599         .shutdown =     usb_hcd_pci_shutdown,
 600 #ifdef CONFIG_PM
 601         .driver = {
 602                 .pm = &usb_hcd_pci_pm_ops
 603         },
 604 #endif
 605 };
 606
 607 static int __init xhci_pci_init(void)
 608 {
 609         xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
 610 #ifdef CONFIG_PM
 611         xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
 612         xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
 613         xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
 614 #endif
 615         return pci_register_driver(&xhci_pci_driver);
 616 }
 617 module_init(xhci_pci_init);
 618
 619 static void __exit xhci_pci_exit(void)
 620 {
 621         pci_unregister_driver(&xhci_pci_driver);
 622 }
 623 module_exit(xhci_pci_exit);
 624
 625 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
 626 MODULE_LICENSE("GPL");