1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver PCI Bus Glue.
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/acpi.h>
17 #include "xhci-trace.h"
19 #define SSIC_PORT_NUM 2
20 #define SSIC_PORT_CFG2 0x880c
21 #define SSIC_PORT_CFG2_OFFSET 0x30
22 #define PROG_DONE (1 << 30)
23 #define SSIC_PORT_UNUSED (1 << 31)
25 /* Device for a quirk */
26 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
27 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
28 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
29 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
31 #define PCI_VENDOR_ID_ETRON 0x1b6f
32 #define PCI_DEVICE_ID_EJ168 0x7023
34 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
35 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
36 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
37 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
38 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
39 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
40 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
41 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
42 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
43 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
44 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5
45 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6
46 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db
47 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4
48 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9
49 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec
50 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0
52 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
53 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
54 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
55 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
56 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
58 static const char hcd_name[] = "xhci_hcd";
60 static struct hc_driver __read_mostly xhci_pci_hc_driver;
62 static int xhci_pci_setup(struct usb_hcd *hcd);
64 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
65 .reset = xhci_pci_setup,
68 /* called after powerup, by probe or system-pm "wakeup" */
69 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
72 * TODO: Implement finding debug ports later.
73 * TODO: see if there are any quirks that need to be added to handle
74 * new extended capabilities.
77 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
78 if (!pci_set_mwi(pdev))
79 xhci_dbg(xhci, "MWI active\n");
81 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
85 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
87 struct pci_dev *pdev = to_pci_dev(dev);
89 /* Look for vendor-specific quirks */
90 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
91 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
92 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
93 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
94 pdev->revision == 0x0) {
95 xhci->quirks |= XHCI_RESET_EP_QUIRK;
96 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
97 "QUIRK: Fresco Logic xHC needs configure"
98 " endpoint cmd after reset endpoint");
100 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
101 pdev->revision == 0x4) {
102 xhci->quirks |= XHCI_SLOW_SUSPEND;
103 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
104 "QUIRK: Fresco Logic xHC revision %u"
105 "must be suspended extra slowly",
108 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
109 xhci->quirks |= XHCI_BROKEN_STREAMS;
110 /* Fresco Logic confirms: all revisions of this chip do not
111 * support MSI, even though some of them claim to in their PCI
114 xhci->quirks |= XHCI_BROKEN_MSI;
115 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
116 "QUIRK: Fresco Logic revision %u "
117 "has broken MSI implementation",
119 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
122 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
123 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
124 xhci->quirks |= XHCI_BROKEN_STREAMS;
126 if (pdev->vendor == PCI_VENDOR_ID_NEC)
127 xhci->quirks |= XHCI_NEC_HOST;
129 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
130 xhci->quirks |= XHCI_AMD_0x96_HOST;
133 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
134 xhci->quirks |= XHCI_AMD_PLL_FIX;
136 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
137 (pdev->device == 0x15e0 ||
138 pdev->device == 0x15e1 ||
139 pdev->device == 0x43bb))
140 xhci->quirks |= XHCI_SUSPEND_DELAY;
142 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
143 (pdev->device == 0x15e0 || pdev->device == 0x15e1))
144 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
146 if (pdev->vendor == PCI_VENDOR_ID_AMD)
147 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
149 if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
150 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
151 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
152 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
153 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
154 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
156 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
157 xhci->quirks |= XHCI_LPM_SUPPORT;
158 xhci->quirks |= XHCI_INTEL_HOST;
159 xhci->quirks |= XHCI_AVOID_BEI;
161 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
162 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
163 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
164 xhci->limit_active_eps = 64;
165 xhci->quirks |= XHCI_SW_BW_CHECKING;
167 * PPT desktop boards DH77EB and DH77DF will power back on after
168 * a few seconds of being shutdown. The fix for this is to
169 * switch the ports from xHCI to EHCI on shutdown. We can't use
170 * DMI information to find those particular boards (since each
171 * vendor will change the board name), so we have to key off all
174 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
176 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
177 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
178 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
179 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
180 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
182 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
183 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
184 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
185 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
186 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
187 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
188 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
189 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) {
190 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
192 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
193 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
194 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
195 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
196 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
197 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
198 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
199 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
200 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
201 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
202 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
203 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
204 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
205 xhci->quirks |= XHCI_MISSING_CAS;
207 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
208 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
209 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
210 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
211 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
212 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
213 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
214 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI))
215 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
217 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
218 pdev->device == PCI_DEVICE_ID_EJ168) {
219 xhci->quirks |= XHCI_RESET_ON_RESUME;
220 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
221 xhci->quirks |= XHCI_BROKEN_STREAMS;
223 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
224 pdev->device == 0x0014) {
225 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
226 xhci->quirks |= XHCI_ZERO_64B_REGS;
228 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
229 pdev->device == 0x0015) {
230 xhci->quirks |= XHCI_RESET_ON_RESUME;
231 xhci->quirks |= XHCI_ZERO_64B_REGS;
233 if (pdev->vendor == PCI_VENDOR_ID_VIA)
234 xhci->quirks |= XHCI_RESET_ON_RESUME;
236 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
237 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
238 pdev->device == 0x3432)
239 xhci->quirks |= XHCI_BROKEN_STREAMS;
241 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
242 pdev->device == 0x1042)
243 xhci->quirks |= XHCI_BROKEN_STREAMS;
244 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
245 pdev->device == 0x1142)
246 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
248 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
249 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
250 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
252 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
253 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
255 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
256 pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
257 pdev->device == 0x9026)
258 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
260 if (xhci->quirks & XHCI_RESET_ON_RESUME)
261 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
262 "QUIRK: Resetting on resume");
266 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
268 static const guid_t intel_dsm_guid =
269 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
270 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
271 union acpi_object *obj;
273 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
278 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
279 #endif /* CONFIG_ACPI */
281 /* called during probe() after chip reset completes */
282 static int xhci_pci_setup(struct usb_hcd *hcd)
284 struct xhci_hcd *xhci;
285 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
288 xhci = hcd_to_xhci(hcd);
290 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
292 /* imod_interval is the interrupt moderation value in nanoseconds. */
293 xhci->imod_interval = 40000;
295 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
299 if (!usb_hcd_is_primary_hcd(hcd))
302 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
304 /* Find any debug ports */
305 return xhci_pci_reinit(xhci, pdev);
309 * We need to register our own PCI probe function (instead of the USB core's
310 * function) in order to create a second roothub under xHCI.
312 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
315 struct xhci_hcd *xhci;
316 struct hc_driver *driver;
319 driver = (struct hc_driver *)id->driver_data;
321 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
322 pm_runtime_get_noresume(&dev->dev);
324 /* Register the USB 2.0 roothub.
325 * FIXME: USB core must know to register the USB 2.0 roothub first.
326 * This is sort of silly, because we could just set the HCD driver flags
327 * to say USB 2.0, but I'm not sure what the implications would be in
328 * the other parts of the HCD code.
330 retval = usb_hcd_pci_probe(dev, id);
335 /* USB 2.0 roothub is stored in the PCI device now. */
336 hcd = dev_get_drvdata(&dev->dev);
337 xhci = hcd_to_xhci(hcd);
338 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
340 if (!xhci->shared_hcd) {
342 goto dealloc_usb2_hcd;
345 retval = xhci_ext_cap_init(xhci);
349 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
353 /* Roothub already marked as USB 3.0 speed */
355 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
356 HCC_MAX_PSA(xhci->hcc_params) >= 4)
357 xhci->shared_hcd->can_do_streams = 1;
359 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
360 xhci_pme_acpi_rtd3_enable(dev);
362 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
363 pm_runtime_put_noidle(&dev->dev);
365 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
366 pm_runtime_allow(&dev->dev);
371 usb_put_hcd(xhci->shared_hcd);
373 usb_hcd_pci_remove(dev);
375 pm_runtime_put_noidle(&dev->dev);
379 static void xhci_pci_remove(struct pci_dev *dev)
381 struct xhci_hcd *xhci;
383 xhci = hcd_to_xhci(pci_get_drvdata(dev));
384 xhci->xhc_state |= XHCI_STATE_REMOVING;
386 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
387 pm_runtime_forbid(&dev->dev);
389 if (xhci->shared_hcd) {
390 usb_remove_hcd(xhci->shared_hcd);
391 usb_put_hcd(xhci->shared_hcd);
392 xhci->shared_hcd = NULL;
395 /* Workaround for spurious wakeups at shutdown with HSW */
396 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
397 pci_set_power_state(dev, PCI_D3hot);
399 usb_hcd_pci_remove(dev);
404 * In some Intel xHCI controllers, in order to get D3 working,
405 * through a vendor specific SSIC CONFIG register at offset 0x883c,
406 * SSIC PORT need to be marked as "unused" before putting xHCI
407 * into D3. After D3 exit, the SSIC port need to be marked as "used".
408 * Without this change, xHCI might not enter D3 state.
410 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
412 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
417 for (i = 0; i < SSIC_PORT_NUM; i++) {
418 reg = (void __iomem *) xhci->cap_regs +
420 i * SSIC_PORT_CFG2_OFFSET;
422 /* Notify SSIC that SSIC profile programming is not done. */
423 val = readl(reg) & ~PROG_DONE;
426 /* Mark SSIC port as unused(suspend) or used(resume) */
429 val |= SSIC_PORT_UNUSED;
431 val &= ~SSIC_PORT_UNUSED;
434 /* Notify SSIC that SSIC profile programming is done */
435 val = readl(reg) | PROG_DONE;
442 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
443 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
445 static void xhci_pme_quirk(struct usb_hcd *hcd)
447 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
451 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
453 writel(val | BIT(28), reg);
457 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
459 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
460 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
464 * Systems with the TI redriver that loses port status change events
465 * need to have the registers polled during D3, so avoid D3cold.
467 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
468 pci_d3cold_disable(pdev);
470 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
473 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
474 xhci_ssic_port_unused_quirk(hcd, true);
476 ret = xhci_suspend(xhci, do_wakeup);
477 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
478 xhci_ssic_port_unused_quirk(hcd, false);
483 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
485 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
486 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
489 /* The BIOS on systems with the Intel Panther Point chipset may or may
490 * not support xHCI natively. That means that during system resume, it
491 * may switch the ports back to EHCI so that users can use their
492 * keyboard to select a kernel from GRUB after resume from hibernate.
494 * The BIOS is supposed to remember whether the OS had xHCI ports
495 * enabled before resume, and switch the ports back to xHCI when the
496 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
499 * Unconditionally switch the ports back to xHCI after a system resume.
500 * It should not matter whether the EHCI or xHCI controller is
501 * resumed first. It's enough to do the switchover in xHCI because
502 * USB core won't notice anything as the hub driver doesn't start
503 * running again until after all the devices (including both EHCI and
504 * xHCI host controllers) have been resumed.
507 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
508 usb_enable_intel_xhci_ports(pdev);
510 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
511 xhci_ssic_port_unused_quirk(hcd, false);
513 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
516 retval = xhci_resume(xhci, hibernated);
519 #endif /* CONFIG_PM */
521 /*-------------------------------------------------------------------------*/
523 /* PCI driver selection metadata; PCI hotplugging uses this */
524 static const struct pci_device_id pci_ids[] = { {
525 /* handle any USB 3.0 xHCI controller */
526 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
527 .driver_data = (unsigned long) &xhci_pci_hc_driver,
529 { /* end: all zeroes */ }
531 MODULE_DEVICE_TABLE(pci, pci_ids);
533 /* pci driver glue; this is a "new style" PCI driver module */
534 static struct pci_driver xhci_pci_driver = {
535 .name = (char *) hcd_name,
538 .probe = xhci_pci_probe,
539 .remove = xhci_pci_remove,
540 /* suspend and resume implemented later */
542 .shutdown = usb_hcd_pci_shutdown,
545 .pm = &usb_hcd_pci_pm_ops
550 static int __init xhci_pci_init(void)
552 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
554 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
555 xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
557 return pci_register_driver(&xhci_pci_driver);
559 module_init(xhci_pci_init);
561 static void __exit xhci_pci_exit(void)
563 pci_unregister_driver(&xhci_pci_driver);
565 module_exit(xhci_pci_exit);
567 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
568 MODULE_LICENSE("GPL");