1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver PCI Bus Glue.
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/acpi.h>
15 #include <linux/reset.h>
18 #include "xhci-trace.h"
21 #define SSIC_PORT_NUM 2
22 #define SSIC_PORT_CFG2 0x880c
23 #define SSIC_PORT_CFG2_OFFSET 0x30
24 #define PROG_DONE (1 << 30)
25 #define SSIC_PORT_UNUSED (1 << 31)
26 #define SPARSE_DISABLE_BIT 17
27 #define SPARSE_CNTL_ENABLE 0xC12C
29 /* Device for a quirk */
30 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
31 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
32 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
33 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1100 0x1100
34 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
36 #define PCI_VENDOR_ID_ETRON 0x1b6f
37 #define PCI_DEVICE_ID_EJ168 0x7023
39 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
40 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
41 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
42 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
43 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
44 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
45 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
46 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
47 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
48 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
49 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI 0x15b5
50 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI 0x15b6
51 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI 0x15c1
52 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI 0x15db
53 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI 0x15d4
54 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI 0x15e9
55 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI 0x15ec
56 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI 0x15f0
57 #define PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI 0x8a13
58 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af
59 #define PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI 0x9a13
60 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI 0x1138
61 #define PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI 0x461e
63 #define PCI_DEVICE_ID_AMD_RENOIR_XHCI 0x1639
64 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
65 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
66 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
67 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
68 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1 0x161a
69 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2 0x161b
70 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3 0x161d
71 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4 0x161e
72 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5 0x15d6
73 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6 0x15d7
74 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7 0x161c
75 #define PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8 0x161f
77 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042
78 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
79 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242
80 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142
81 #define PCI_DEVICE_ID_ASMEDIA_3242_XHCI 0x3242
83 static const char hcd_name[] = "xhci_hcd";
85 static struct hc_driver __read_mostly xhci_pci_hc_driver;
87 static int xhci_pci_setup(struct usb_hcd *hcd);
89 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
90 .reset = xhci_pci_setup,
93 /* called after powerup, by probe or system-pm "wakeup" */
94 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
97 * TODO: Implement finding debug ports later.
98 * TODO: see if there are any quirks that need to be added to handle
99 * new extended capabilities.
102 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
103 if (!pci_set_mwi(pdev))
104 xhci_dbg(xhci, "MWI active\n");
106 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
110 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
112 struct pci_dev *pdev = to_pci_dev(dev);
113 struct xhci_driver_data *driver_data;
114 const struct pci_device_id *id;
116 id = pci_match_id(to_pci_driver(pdev->dev.driver)->id_table, pdev);
118 if (id && id->driver_data) {
119 driver_data = (struct xhci_driver_data *)id->driver_data;
120 xhci->quirks |= driver_data->quirks;
123 /* Look for vendor-specific quirks */
124 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
125 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
126 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
127 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
128 pdev->revision == 0x0) {
129 xhci->quirks |= XHCI_RESET_EP_QUIRK;
130 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
131 "QUIRK: Fresco Logic xHC needs configure"
132 " endpoint cmd after reset endpoint");
134 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
135 pdev->revision == 0x4) {
136 xhci->quirks |= XHCI_SLOW_SUSPEND;
137 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
138 "QUIRK: Fresco Logic xHC revision %u"
139 "must be suspended extra slowly",
142 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
143 xhci->quirks |= XHCI_BROKEN_STREAMS;
144 /* Fresco Logic confirms: all revisions of this chip do not
145 * support MSI, even though some of them claim to in their PCI
148 xhci->quirks |= XHCI_BROKEN_MSI;
149 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
150 "QUIRK: Fresco Logic revision %u "
151 "has broken MSI implementation",
153 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
156 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
157 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
158 xhci->quirks |= XHCI_BROKEN_STREAMS;
160 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
161 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1100)
162 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
164 if (pdev->vendor == PCI_VENDOR_ID_NEC)
165 xhci->quirks |= XHCI_NEC_HOST;
167 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
168 xhci->quirks |= XHCI_AMD_0x96_HOST;
171 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_quirk_pll_check())
172 xhci->quirks |= XHCI_AMD_PLL_FIX;
174 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
175 (pdev->device == 0x145c ||
176 pdev->device == 0x15e0 ||
177 pdev->device == 0x15e1 ||
178 pdev->device == 0x43bb))
179 xhci->quirks |= XHCI_SUSPEND_DELAY;
181 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
182 (pdev->device == 0x15e0 || pdev->device == 0x15e1))
183 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
185 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5) {
186 xhci->quirks |= XHCI_DISABLE_SPARSE;
187 xhci->quirks |= XHCI_RESET_ON_RESUME;
190 if (pdev->vendor == PCI_VENDOR_ID_AMD)
191 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
193 if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
194 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
195 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
196 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
197 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
198 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
200 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
201 pdev->device == PCI_DEVICE_ID_AMD_RENOIR_XHCI)
202 xhci->quirks |= XHCI_BROKEN_D3COLD;
204 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
205 xhci->quirks |= XHCI_LPM_SUPPORT;
206 xhci->quirks |= XHCI_INTEL_HOST;
207 xhci->quirks |= XHCI_AVOID_BEI;
209 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
210 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
211 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
212 xhci->limit_active_eps = 64;
213 xhci->quirks |= XHCI_SW_BW_CHECKING;
215 * PPT desktop boards DH77EB and DH77DF will power back on after
216 * a few seconds of being shutdown. The fix for this is to
217 * switch the ports from xHCI to EHCI on shutdown. We can't use
218 * DMI information to find those particular boards (since each
219 * vendor will change the board name), so we have to key off all
222 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
224 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
225 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
226 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
227 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
228 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
230 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
231 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
232 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
233 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
234 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
235 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
236 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
237 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
238 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
239 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
241 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
242 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
243 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
244 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
245 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
246 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
247 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
248 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
249 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
250 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
251 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
252 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
253 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
254 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
255 xhci->quirks |= XHCI_MISSING_CAS;
257 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
258 (pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_XHCI ||
259 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_XHCI ||
260 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_XHCI ||
261 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_XHCI ||
262 pdev->device == PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_XHCI ||
263 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_XHCI ||
264 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_XHCI ||
265 pdev->device == PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_XHCI ||
266 pdev->device == PCI_DEVICE_ID_INTEL_ICE_LAKE_XHCI ||
267 pdev->device == PCI_DEVICE_ID_INTEL_TIGER_LAKE_XHCI ||
268 pdev->device == PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_XHCI ||
269 pdev->device == PCI_DEVICE_ID_INTEL_ALDER_LAKE_XHCI))
270 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
272 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
273 pdev->device == PCI_DEVICE_ID_EJ168) {
274 xhci->quirks |= XHCI_RESET_ON_RESUME;
275 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
276 xhci->quirks |= XHCI_BROKEN_STREAMS;
278 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
279 pdev->device == 0x0014) {
280 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
281 xhci->quirks |= XHCI_ZERO_64B_REGS;
283 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
284 pdev->device == 0x0015) {
285 xhci->quirks |= XHCI_RESET_ON_RESUME;
286 xhci->quirks |= XHCI_ZERO_64B_REGS;
288 if (pdev->vendor == PCI_VENDOR_ID_VIA)
289 xhci->quirks |= XHCI_RESET_ON_RESUME;
291 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
292 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
293 pdev->device == 0x3432)
294 xhci->quirks |= XHCI_BROKEN_STREAMS;
296 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {
297 xhci->quirks |= XHCI_LPM_SUPPORT;
298 xhci->quirks |= XHCI_EP_CTX_BROKEN_DCS;
301 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
302 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI)
303 xhci->quirks |= XHCI_BROKEN_STREAMS;
304 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
305 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI) {
306 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
307 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
309 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
310 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
311 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI ||
312 pdev->device == PCI_DEVICE_ID_ASMEDIA_3242_XHCI))
313 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
315 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
316 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
317 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
319 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
320 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
322 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
323 pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
324 pdev->device == 0x9026)
325 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
327 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
328 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2 ||
329 pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4))
330 xhci->quirks |= XHCI_NO_SOFT_RETRY;
332 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
333 (pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_1 ||
334 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_2 ||
335 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_3 ||
336 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_4 ||
337 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_5 ||
338 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_6 ||
339 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_7 ||
340 pdev->device == PCI_DEVICE_ID_AMD_YELLOW_CARP_XHCI_8))
341 xhci->quirks |= XHCI_DEFAULT_PM_RUNTIME_ALLOW;
343 if (xhci->quirks & XHCI_RESET_ON_RESUME)
344 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
345 "QUIRK: Resetting on resume");
349 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
351 static const guid_t intel_dsm_guid =
352 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
353 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
354 union acpi_object *obj;
356 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
361 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
362 #endif /* CONFIG_ACPI */
364 /* called during probe() after chip reset completes */
365 static int xhci_pci_setup(struct usb_hcd *hcd)
367 struct xhci_hcd *xhci;
368 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
371 xhci = hcd_to_xhci(hcd);
373 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
375 /* imod_interval is the interrupt moderation value in nanoseconds. */
376 xhci->imod_interval = 40000;
378 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
382 if (!usb_hcd_is_primary_hcd(hcd))
385 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
386 xhci_pme_acpi_rtd3_enable(pdev);
388 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
390 /* Find any debug ports */
391 return xhci_pci_reinit(xhci, pdev);
395 * We need to register our own PCI probe function (instead of the USB core's
396 * function) in order to create a second roothub under xHCI.
398 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
401 struct xhci_hcd *xhci;
403 struct xhci_driver_data *driver_data;
404 struct reset_control *reset;
406 driver_data = (struct xhci_driver_data *)id->driver_data;
407 if (driver_data && driver_data->quirks & XHCI_RENESAS_FW_QUIRK) {
408 retval = renesas_xhci_check_request_fw(dev, id);
413 reset = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
415 return PTR_ERR(reset);
416 reset_control_reset(reset);
418 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
419 pm_runtime_get_noresume(&dev->dev);
421 /* Register the USB 2.0 roothub.
422 * FIXME: USB core must know to register the USB 2.0 roothub first.
423 * This is sort of silly, because we could just set the HCD driver flags
424 * to say USB 2.0, but I'm not sure what the implications would be in
425 * the other parts of the HCD code.
427 retval = usb_hcd_pci_probe(dev, id, &xhci_pci_hc_driver);
432 /* USB 2.0 roothub is stored in the PCI device now. */
433 hcd = dev_get_drvdata(&dev->dev);
434 xhci = hcd_to_xhci(hcd);
436 xhci->shared_hcd = usb_create_shared_hcd(&xhci_pci_hc_driver, &dev->dev,
438 if (!xhci->shared_hcd) {
440 goto dealloc_usb2_hcd;
443 retval = xhci_ext_cap_init(xhci);
447 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
451 /* Roothub already marked as USB 3.0 speed */
453 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
454 HCC_MAX_PSA(xhci->hcc_params) >= 4)
455 xhci->shared_hcd->can_do_streams = 1;
457 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
458 pm_runtime_put_noidle(&dev->dev);
460 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
461 pm_runtime_allow(&dev->dev);
466 usb_put_hcd(xhci->shared_hcd);
468 usb_hcd_pci_remove(dev);
470 pm_runtime_put_noidle(&dev->dev);
474 static void xhci_pci_remove(struct pci_dev *dev)
476 struct xhci_hcd *xhci;
478 xhci = hcd_to_xhci(pci_get_drvdata(dev));
480 xhci->xhc_state |= XHCI_STATE_REMOVING;
482 if (xhci->quirks & XHCI_DEFAULT_PM_RUNTIME_ALLOW)
483 pm_runtime_forbid(&dev->dev);
485 if (xhci->shared_hcd) {
486 usb_remove_hcd(xhci->shared_hcd);
487 usb_put_hcd(xhci->shared_hcd);
488 xhci->shared_hcd = NULL;
491 /* Workaround for spurious wakeups at shutdown with HSW */
492 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
493 pci_set_power_state(dev, PCI_D3hot);
495 usb_hcd_pci_remove(dev);
500 * In some Intel xHCI controllers, in order to get D3 working,
501 * through a vendor specific SSIC CONFIG register at offset 0x883c,
502 * SSIC PORT need to be marked as "unused" before putting xHCI
503 * into D3. After D3 exit, the SSIC port need to be marked as "used".
504 * Without this change, xHCI might not enter D3 state.
506 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
508 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
513 for (i = 0; i < SSIC_PORT_NUM; i++) {
514 reg = (void __iomem *) xhci->cap_regs +
516 i * SSIC_PORT_CFG2_OFFSET;
518 /* Notify SSIC that SSIC profile programming is not done. */
519 val = readl(reg) & ~PROG_DONE;
522 /* Mark SSIC port as unused(suspend) or used(resume) */
525 val |= SSIC_PORT_UNUSED;
527 val &= ~SSIC_PORT_UNUSED;
530 /* Notify SSIC that SSIC profile programming is done */
531 val = readl(reg) | PROG_DONE;
538 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
539 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
541 static void xhci_pme_quirk(struct usb_hcd *hcd)
543 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
547 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
549 writel(val | BIT(28), reg);
553 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
557 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
558 reg &= ~BIT(SPARSE_DISABLE_BIT);
559 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
562 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
564 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
565 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
569 * Systems with the TI redriver that loses port status change events
570 * need to have the registers polled during D3, so avoid D3cold.
572 if (xhci->quirks & (XHCI_COMP_MODE_QUIRK | XHCI_BROKEN_D3COLD))
573 pci_d3cold_disable(pdev);
575 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
578 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
579 xhci_ssic_port_unused_quirk(hcd, true);
581 if (xhci->quirks & XHCI_DISABLE_SPARSE)
582 xhci_sparse_control_quirk(hcd);
584 ret = xhci_suspend(xhci, do_wakeup);
585 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
586 xhci_ssic_port_unused_quirk(hcd, false);
591 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
593 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
594 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
597 reset_control_reset(xhci->reset);
599 /* The BIOS on systems with the Intel Panther Point chipset may or may
600 * not support xHCI natively. That means that during system resume, it
601 * may switch the ports back to EHCI so that users can use their
602 * keyboard to select a kernel from GRUB after resume from hibernate.
604 * The BIOS is supposed to remember whether the OS had xHCI ports
605 * enabled before resume, and switch the ports back to xHCI when the
606 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
609 * Unconditionally switch the ports back to xHCI after a system resume.
610 * It should not matter whether the EHCI or xHCI controller is
611 * resumed first. It's enough to do the switchover in xHCI because
612 * USB core won't notice anything as the hub driver doesn't start
613 * running again until after all the devices (including both EHCI and
614 * xHCI host controllers) have been resumed.
617 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
618 usb_enable_intel_xhci_ports(pdev);
620 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
621 xhci_ssic_port_unused_quirk(hcd, false);
623 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
626 retval = xhci_resume(xhci, hibernated);
630 static void xhci_pci_shutdown(struct usb_hcd *hcd)
632 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
633 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
637 /* Yet another workaround for spurious wakeups at shutdown with HSW */
638 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
639 pci_set_power_state(pdev, PCI_D3hot);
641 #endif /* CONFIG_PM */
643 /*-------------------------------------------------------------------------*/
645 static const struct xhci_driver_data reneses_data = {
646 .quirks = XHCI_RENESAS_FW_QUIRK,
647 .firmware = "renesas_usb_fw.mem",
650 /* PCI driver selection metadata; PCI hotplugging uses this */
651 static const struct pci_device_id pci_ids[] = {
652 { PCI_DEVICE(0x1912, 0x0014),
653 .driver_data = (unsigned long)&reneses_data,
655 { PCI_DEVICE(0x1912, 0x0015),
656 .driver_data = (unsigned long)&reneses_data,
658 /* handle any USB 3.0 xHCI controller */
659 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
661 { /* end: all zeroes */ }
663 MODULE_DEVICE_TABLE(pci, pci_ids);
666 * Without CONFIG_USB_XHCI_PCI_RENESAS renesas_xhci_check_request_fw() won't
667 * load firmware, so don't encumber the xhci-pci driver with it.
669 #if IS_ENABLED(CONFIG_USB_XHCI_PCI_RENESAS)
670 MODULE_FIRMWARE("renesas_usb_fw.mem");
673 /* pci driver glue; this is a "new style" PCI driver module */
674 static struct pci_driver xhci_pci_driver = {
678 .probe = xhci_pci_probe,
679 .remove = xhci_pci_remove,
680 /* suspend and resume implemented later */
682 .shutdown = usb_hcd_pci_shutdown,
685 .pm = &usb_hcd_pci_pm_ops
690 static int __init xhci_pci_init(void)
692 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
694 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
695 xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
696 xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
698 return pci_register_driver(&xhci_pci_driver);
700 module_init(xhci_pci_init);
702 static void __exit xhci_pci_exit(void)
704 pci_unregister_driver(&xhci_pci_driver);
706 module_exit(xhci_pci_exit);
708 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
709 MODULE_LICENSE("GPL");