1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek xHCI Host Controller Driver
5 * Copyright (c) 2015 MediaTek Inc.
7 * Chunfeng Yun <chunfeng.yun@mediatek.com>
10 #include <linux/clk.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/iopoll.h>
13 #include <linux/kernel.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
25 /* ip_pw_ctrl0 register */
26 #define CTRL0_IP_SW_RST BIT(0)
28 /* ip_pw_ctrl1 register */
29 #define CTRL1_IP_HOST_PDN BIT(0)
31 /* ip_pw_ctrl2 register */
32 #define CTRL2_IP_DEV_PDN BIT(0)
34 /* ip_pw_sts1 register */
35 #define STS1_IP_SLEEP_STS BIT(30)
36 #define STS1_U3_MAC_RST BIT(16)
37 #define STS1_XHCI_RST BIT(11)
38 #define STS1_SYS125_RST BIT(10)
39 #define STS1_REF_RST BIT(8)
40 #define STS1_SYSPLL_STABLE BIT(0)
42 /* ip_xhci_cap register */
43 #define CAP_U3_PORT_NUM(p) ((p) & 0xff)
44 #define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
46 /* u3_ctrl_p register */
47 #define CTRL_U3_PORT_HOST_SEL BIT(2)
48 #define CTRL_U3_PORT_PDN BIT(1)
49 #define CTRL_U3_PORT_DIS BIT(0)
51 /* u2_ctrl_p register */
52 #define CTRL_U2_PORT_HOST_SEL BIT(2)
53 #define CTRL_U2_PORT_PDN BIT(1)
54 #define CTRL_U2_PORT_DIS BIT(0)
56 /* u2_phy_pll register */
57 #define CTRL_U2_FORCE_PLL_STB BIT(28)
59 /* usb remote wakeup registers in syscon */
62 #define PERI_WK_CTRL1 0x4
63 #define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */
64 #define WC1_IS_EN BIT(25)
65 #define WC1_IS_P BIT(6) /* polarity for ip sleep */
68 #define PERI_WK_CTRL0 0x0
69 #define WC0_IS_C(x) ((u32)(((x) & 0xf) << 28)) /* cycle debounce */
70 #define WC0_IS_P BIT(12) /* polarity */
71 #define WC0_IS_EN BIT(6)
74 #define WC0_SSUSB0_CDEN BIT(6)
75 #define WC0_IS_SPM_EN BIT(1)
78 #define PERI_SSUSB_SPM_CTRL 0x0
79 #define SSC_IP_SLEEP_EN BIT(4)
80 #define SSC_SPM_INT_EN BIT(1)
85 SSUSB_UWK_V1_1 = 101, /* specific revision 1.01 */
86 SSUSB_UWK_V1_2, /* specific revision 1.2 */
89 static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
91 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
93 int u3_ports_disabled = 0;
100 /* power on host ip */
101 value = readl(&ippc->ip_pw_ctr1);
102 value &= ~CTRL1_IP_HOST_PDN;
103 writel(value, &ippc->ip_pw_ctr1);
105 /* power on and enable u3 ports except skipped ones */
106 for (i = 0; i < mtk->num_u3_ports; i++) {
107 if ((0x1 << i) & mtk->u3p_dis_msk) {
112 value = readl(&ippc->u3_ctrl_p[i]);
113 value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
114 value |= CTRL_U3_PORT_HOST_SEL;
115 writel(value, &ippc->u3_ctrl_p[i]);
118 /* power on and enable all u2 ports */
119 for (i = 0; i < mtk->num_u2_ports; i++) {
120 value = readl(&ippc->u2_ctrl_p[i]);
121 value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
122 value |= CTRL_U2_PORT_HOST_SEL;
123 writel(value, &ippc->u2_ctrl_p[i]);
127 * wait for clocks to be stable, and clock domains reset to
128 * be inactive after power on and enable ports
130 check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
131 STS1_SYS125_RST | STS1_XHCI_RST;
133 if (mtk->num_u3_ports > u3_ports_disabled)
134 check_val |= STS1_U3_MAC_RST;
136 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
137 (check_val == (value & check_val)), 100, 20000);
139 dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
146 static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
148 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
156 /* power down u3 ports except skipped ones */
157 for (i = 0; i < mtk->num_u3_ports; i++) {
158 if ((0x1 << i) & mtk->u3p_dis_msk)
161 value = readl(&ippc->u3_ctrl_p[i]);
162 value |= CTRL_U3_PORT_PDN;
163 writel(value, &ippc->u3_ctrl_p[i]);
166 /* power down all u2 ports */
167 for (i = 0; i < mtk->num_u2_ports; i++) {
168 value = readl(&ippc->u2_ctrl_p[i]);
169 value |= CTRL_U2_PORT_PDN;
170 writel(value, &ippc->u2_ctrl_p[i]);
173 /* power down host ip */
174 value = readl(&ippc->ip_pw_ctr1);
175 value |= CTRL1_IP_HOST_PDN;
176 writel(value, &ippc->ip_pw_ctr1);
178 /* wait for host ip to sleep */
179 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
180 (value & STS1_IP_SLEEP_STS), 100, 100000);
182 dev_err(mtk->dev, "ip sleep failed!!!\n");
188 static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
190 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
197 value = readl(&ippc->ip_pw_ctr0);
198 value |= CTRL0_IP_SW_RST;
199 writel(value, &ippc->ip_pw_ctr0);
201 value = readl(&ippc->ip_pw_ctr0);
202 value &= ~CTRL0_IP_SW_RST;
203 writel(value, &ippc->ip_pw_ctr0);
206 * device ip is default power-on in fact
207 * power down device ip, otherwise ip-sleep will fail
209 value = readl(&ippc->ip_pw_ctr2);
210 value |= CTRL2_IP_DEV_PDN;
211 writel(value, &ippc->ip_pw_ctr2);
213 value = readl(&ippc->ip_xhci_cap);
214 mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
215 mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
216 dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
217 mtk->num_u2_ports, mtk->num_u3_ports);
219 return xhci_mtk_host_enable(mtk);
222 static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk)
224 struct device *dev = mtk->dev;
226 mtk->sys_clk = devm_clk_get(dev, "sys_ck");
227 if (IS_ERR(mtk->sys_clk)) {
228 dev_err(dev, "fail to get sys_ck\n");
229 return PTR_ERR(mtk->sys_clk);
232 mtk->xhci_clk = devm_clk_get_optional(dev, "xhci_ck");
233 if (IS_ERR(mtk->xhci_clk))
234 return PTR_ERR(mtk->xhci_clk);
236 mtk->ref_clk = devm_clk_get_optional(dev, "ref_ck");
237 if (IS_ERR(mtk->ref_clk))
238 return PTR_ERR(mtk->ref_clk);
240 mtk->mcu_clk = devm_clk_get_optional(dev, "mcu_ck");
241 if (IS_ERR(mtk->mcu_clk))
242 return PTR_ERR(mtk->mcu_clk);
244 mtk->dma_clk = devm_clk_get_optional(dev, "dma_ck");
245 return PTR_ERR_OR_ZERO(mtk->dma_clk);
248 static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
252 ret = clk_prepare_enable(mtk->ref_clk);
254 dev_err(mtk->dev, "failed to enable ref_clk\n");
258 ret = clk_prepare_enable(mtk->sys_clk);
260 dev_err(mtk->dev, "failed to enable sys_clk\n");
264 ret = clk_prepare_enable(mtk->xhci_clk);
266 dev_err(mtk->dev, "failed to enable xhci_clk\n");
270 ret = clk_prepare_enable(mtk->mcu_clk);
272 dev_err(mtk->dev, "failed to enable mcu_clk\n");
276 ret = clk_prepare_enable(mtk->dma_clk);
278 dev_err(mtk->dev, "failed to enable dma_clk\n");
285 clk_disable_unprepare(mtk->mcu_clk);
287 clk_disable_unprepare(mtk->xhci_clk);
289 clk_disable_unprepare(mtk->sys_clk);
291 clk_disable_unprepare(mtk->ref_clk);
296 static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk)
298 clk_disable_unprepare(mtk->dma_clk);
299 clk_disable_unprepare(mtk->mcu_clk);
300 clk_disable_unprepare(mtk->xhci_clk);
301 clk_disable_unprepare(mtk->sys_clk);
302 clk_disable_unprepare(mtk->ref_clk);
305 /* only clocks can be turn off for ip-sleep wakeup mode */
306 static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable)
310 switch (mtk->uwk_vers) {
312 reg = mtk->uwk_reg_base + PERI_WK_CTRL1;
313 msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;
314 val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0;
317 reg = mtk->uwk_reg_base + PERI_WK_CTRL0;
318 msk = WC0_IS_EN | WC0_IS_C(0xf) | WC0_IS_P;
319 val = enable ? (WC0_IS_EN | WC0_IS_C(0x8)) : 0;
322 reg = mtk->uwk_reg_base + PERI_WK_CTRL0;
323 msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN;
324 val = enable ? msk : 0;
327 reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
328 msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;
329 val = enable ? msk : 0;
334 regmap_update_bits(mtk->uwk, reg, msk, val);
337 static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
338 struct device_node *dn)
340 struct of_phandle_args args;
343 /* Wakeup function is optional */
344 mtk->uwk_en = of_property_read_bool(dn, "wakeup-source");
348 ret = of_parse_phandle_with_fixed_args(dn,
349 "mediatek,syscon-wakeup", 2, 0, &args);
353 mtk->uwk_reg_base = args.args[0];
354 mtk->uwk_vers = args.args[1];
355 mtk->uwk = syscon_node_to_regmap(args.np);
356 of_node_put(args.np);
357 dev_info(mtk->dev, "uwk - reg:0x%x, version:%d\n",
358 mtk->uwk_reg_base, mtk->uwk_vers);
360 return PTR_ERR_OR_ZERO(mtk->uwk);
364 static void usb_wakeup_set(struct xhci_hcd_mtk *mtk, bool enable)
367 usb_wakeup_ip_sleep_set(mtk, enable);
370 static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk)
374 ret = regulator_enable(mtk->vbus);
376 dev_err(mtk->dev, "failed to enable vbus\n");
380 ret = regulator_enable(mtk->vusb33);
382 dev_err(mtk->dev, "failed to enable vusb33\n");
383 regulator_disable(mtk->vbus);
389 static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk)
391 regulator_disable(mtk->vbus);
392 regulator_disable(mtk->vusb33);
395 static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
397 struct usb_hcd *hcd = xhci_to_hcd(xhci);
398 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
401 * As of now platform drivers don't provide MSI support so we ensure
402 * here that the generic code does not try to make a pci_dev from our
403 * dev struct in order to setup MSI
405 xhci->quirks |= XHCI_PLAT;
406 xhci->quirks |= XHCI_MTK_HOST;
408 * MTK host controller gives a spurious successful event after a
409 * short transfer. Ignore it.
411 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
412 if (mtk->lpm_support)
413 xhci->quirks |= XHCI_LPM_SUPPORT;
414 if (mtk->u2_lpm_disable)
415 xhci->quirks |= XHCI_HW_LPM_DISABLE;
418 * MTK xHCI 0.96: PSA is 1 by default even if doesn't support stream,
419 * and it's 3 when support it.
421 if (xhci->hci_version < 0x100 && HCC_MAX_PSA(xhci->hcc_params) == 4)
422 xhci->quirks |= XHCI_BROKEN_STREAMS;
425 /* called during probe() after chip reset completes */
426 static int xhci_mtk_setup(struct usb_hcd *hcd)
428 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
431 if (usb_hcd_is_primary_hcd(hcd)) {
432 ret = xhci_mtk_ssusb_config(mtk);
437 ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
441 if (usb_hcd_is_primary_hcd(hcd)) {
442 ret = xhci_mtk_sch_init(mtk);
450 static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
451 .reset = xhci_mtk_setup,
452 .add_endpoint = xhci_mtk_add_ep,
453 .drop_endpoint = xhci_mtk_drop_ep,
454 .check_bandwidth = xhci_mtk_check_bandwidth,
455 .reset_bandwidth = xhci_mtk_reset_bandwidth,
458 static struct hc_driver __read_mostly xhci_mtk_hc_driver;
460 static int xhci_mtk_probe(struct platform_device *pdev)
462 struct device *dev = &pdev->dev;
463 struct device_node *node = dev->of_node;
464 struct xhci_hcd_mtk *mtk;
465 const struct hc_driver *driver;
466 struct xhci_hcd *xhci;
467 struct resource *res;
475 driver = &xhci_mtk_hc_driver;
476 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
481 mtk->vbus = devm_regulator_get(dev, "vbus");
482 if (IS_ERR(mtk->vbus)) {
483 dev_err(dev, "fail to get vbus\n");
484 return PTR_ERR(mtk->vbus);
487 mtk->vusb33 = devm_regulator_get(dev, "vusb33");
488 if (IS_ERR(mtk->vusb33)) {
489 dev_err(dev, "fail to get vusb33\n");
490 return PTR_ERR(mtk->vusb33);
493 ret = xhci_mtk_clks_get(mtk);
497 mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
498 mtk->u2_lpm_disable = of_property_read_bool(node, "usb2-lpm-disable");
499 /* optional property, ignore the error if it does not exist */
500 of_property_read_u32(node, "mediatek,u3p-dis-msk",
503 ret = usb_wakeup_of_property_parse(mtk, node);
505 dev_err(dev, "failed to parse uwk property\n");
509 pm_runtime_enable(dev);
510 pm_runtime_get_sync(dev);
511 device_enable_async_suspend(dev);
513 ret = xhci_mtk_ldos_enable(mtk);
517 ret = xhci_mtk_clks_enable(mtk);
521 irq = platform_get_irq(pdev, 0);
527 hcd = usb_create_hcd(driver, dev, dev_name(dev));
534 * USB 2.0 roothub is stored in the platform_device.
535 * Swap it with mtk HCD.
537 mtk->hcd = platform_get_drvdata(pdev);
538 platform_set_drvdata(pdev, mtk);
540 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
541 hcd->regs = devm_ioremap_resource(dev, res);
542 if (IS_ERR(hcd->regs)) {
543 ret = PTR_ERR(hcd->regs);
546 hcd->rsrc_start = res->start;
547 hcd->rsrc_len = resource_size(res);
549 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
550 if (res) { /* ippc register is optional */
551 mtk->ippc_regs = devm_ioremap_resource(dev, res);
552 if (IS_ERR(mtk->ippc_regs)) {
553 ret = PTR_ERR(mtk->ippc_regs);
556 mtk->has_ippc = true;
558 mtk->has_ippc = false;
561 device_init_wakeup(dev, true);
563 xhci = hcd_to_xhci(hcd);
564 xhci->main_hcd = hcd;
567 * imod_interval is the interrupt moderation value in nanoseconds.
568 * The increment interval is 8 times as much as that defined in
569 * the xHCI spec on MTK's controller.
571 xhci->imod_interval = 5000;
572 device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval);
574 xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
576 if (!xhci->shared_hcd) {
578 goto disable_device_wakeup;
581 ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
585 if (HCC_MAX_PSA(xhci->hcc_params) >= 4 &&
586 !(xhci->quirks & XHCI_BROKEN_STREAMS))
587 xhci->shared_hcd->can_do_streams = 1;
589 ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
591 goto dealloc_usb2_hcd;
599 xhci_mtk_sch_exit(mtk);
600 usb_put_hcd(xhci->shared_hcd);
602 disable_device_wakeup:
603 device_init_wakeup(dev, false);
609 xhci_mtk_clks_disable(mtk);
612 xhci_mtk_ldos_disable(mtk);
615 pm_runtime_put_sync(dev);
616 pm_runtime_disable(dev);
620 static int xhci_mtk_remove(struct platform_device *dev)
622 struct xhci_hcd_mtk *mtk = platform_get_drvdata(dev);
623 struct usb_hcd *hcd = mtk->hcd;
624 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
625 struct usb_hcd *shared_hcd = xhci->shared_hcd;
627 pm_runtime_put_noidle(&dev->dev);
628 pm_runtime_disable(&dev->dev);
630 usb_remove_hcd(shared_hcd);
631 xhci->shared_hcd = NULL;
632 device_init_wakeup(&dev->dev, false);
635 usb_put_hcd(shared_hcd);
637 xhci_mtk_sch_exit(mtk);
638 xhci_mtk_clks_disable(mtk);
639 xhci_mtk_ldos_disable(mtk);
644 static int __maybe_unused xhci_mtk_suspend(struct device *dev)
646 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
647 struct usb_hcd *hcd = mtk->hcd;
648 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
651 xhci_dbg(xhci, "%s: stop port polling\n", __func__);
652 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
653 del_timer_sync(&hcd->rh_timer);
654 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
655 del_timer_sync(&xhci->shared_hcd->rh_timer);
657 ret = xhci_mtk_host_disable(mtk);
659 goto restart_poll_rh;
661 xhci_mtk_clks_disable(mtk);
662 usb_wakeup_set(mtk, true);
666 xhci_dbg(xhci, "%s: restart port polling\n", __func__);
667 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
668 usb_hcd_poll_rh_status(xhci->shared_hcd);
669 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
670 usb_hcd_poll_rh_status(hcd);
674 static int __maybe_unused xhci_mtk_resume(struct device *dev)
676 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
677 struct usb_hcd *hcd = mtk->hcd;
678 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
681 usb_wakeup_set(mtk, false);
682 ret = xhci_mtk_clks_enable(mtk);
686 ret = xhci_mtk_host_enable(mtk);
690 xhci_dbg(xhci, "%s: restart port polling\n", __func__);
691 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
692 usb_hcd_poll_rh_status(xhci->shared_hcd);
693 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
694 usb_hcd_poll_rh_status(hcd);
698 xhci_mtk_clks_disable(mtk);
700 usb_wakeup_set(mtk, true);
704 static const struct dev_pm_ops xhci_mtk_pm_ops = {
705 SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
707 #define DEV_PM_OPS IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL
709 static const struct of_device_id mtk_xhci_of_match[] = {
710 { .compatible = "mediatek,mt8173-xhci"},
711 { .compatible = "mediatek,mtk-xhci"},
714 MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
716 static struct platform_driver mtk_xhci_driver = {
717 .probe = xhci_mtk_probe,
718 .remove = xhci_mtk_remove,
722 .of_match_table = mtk_xhci_of_match,
726 static int __init xhci_mtk_init(void)
728 xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
729 return platform_driver_register(&mtk_xhci_driver);
731 module_init(xhci_mtk_init);
733 static void __exit xhci_mtk_exit(void)
735 platform_driver_unregister(&mtk_xhci_driver);
737 module_exit(xhci_mtk_exit);
739 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
740 MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
741 MODULE_LICENSE("GPL v2");