1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek xHCI Host Controller Driver
5 * Copyright (c) 2015 MediaTek Inc.
7 * Chunfeng Yun <chunfeng.yun@mediatek.com>
10 #include <linux/dma-mapping.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/pm_wakeirq.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
25 /* ip_pw_ctrl0 register */
26 #define CTRL0_IP_SW_RST BIT(0)
28 /* ip_pw_ctrl1 register */
29 #define CTRL1_IP_HOST_PDN BIT(0)
31 /* ip_pw_ctrl2 register */
32 #define CTRL2_IP_DEV_PDN BIT(0)
34 /* ip_pw_sts1 register */
35 #define STS1_IP_SLEEP_STS BIT(30)
36 #define STS1_U3_MAC_RST BIT(16)
37 #define STS1_XHCI_RST BIT(11)
38 #define STS1_SYS125_RST BIT(10)
39 #define STS1_REF_RST BIT(8)
40 #define STS1_SYSPLL_STABLE BIT(0)
42 /* ip_xhci_cap register */
43 #define CAP_U3_PORT_NUM(p) ((p) & 0xff)
44 #define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
46 /* u3_ctrl_p register */
47 #define CTRL_U3_PORT_HOST_SEL BIT(2)
48 #define CTRL_U3_PORT_PDN BIT(1)
49 #define CTRL_U3_PORT_DIS BIT(0)
51 /* u2_ctrl_p register */
52 #define CTRL_U2_PORT_HOST_SEL BIT(2)
53 #define CTRL_U2_PORT_PDN BIT(1)
54 #define CTRL_U2_PORT_DIS BIT(0)
56 /* u2_phy_pll register */
57 #define CTRL_U2_FORCE_PLL_STB BIT(28)
59 /* usb remote wakeup registers in syscon */
62 #define PERI_WK_CTRL1 0x4
63 #define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */
64 #define WC1_IS_EN BIT(25)
65 #define WC1_IS_P BIT(6) /* polarity for ip sleep */
68 #define PERI_WK_CTRL0 0x0
69 #define WC0_IS_C(x) ((u32)(((x) & 0xf) << 28)) /* cycle debounce */
70 #define WC0_IS_P BIT(12) /* polarity */
71 #define WC0_IS_EN BIT(6)
74 #define WC0_SSUSB0_CDEN BIT(6)
75 #define WC0_IS_SPM_EN BIT(1)
78 #define PERI_SSUSB_SPM_CTRL 0x0
79 #define SSC_IP_SLEEP_EN BIT(4)
80 #define SSC_SPM_INT_EN BIT(1)
85 SSUSB_UWK_V1_1 = 101, /* specific revision 1.01 */
86 SSUSB_UWK_V1_2, /* specific revision 1.2 */
89 static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
91 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
93 int u3_ports_disabled = 0;
100 /* power on host ip */
101 value = readl(&ippc->ip_pw_ctr1);
102 value &= ~CTRL1_IP_HOST_PDN;
103 writel(value, &ippc->ip_pw_ctr1);
105 /* power on and enable u3 ports except skipped ones */
106 for (i = 0; i < mtk->num_u3_ports; i++) {
107 if ((0x1 << i) & mtk->u3p_dis_msk) {
112 value = readl(&ippc->u3_ctrl_p[i]);
113 value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
114 value |= CTRL_U3_PORT_HOST_SEL;
115 writel(value, &ippc->u3_ctrl_p[i]);
118 /* power on and enable all u2 ports */
119 for (i = 0; i < mtk->num_u2_ports; i++) {
120 value = readl(&ippc->u2_ctrl_p[i]);
121 value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
122 value |= CTRL_U2_PORT_HOST_SEL;
123 writel(value, &ippc->u2_ctrl_p[i]);
127 * wait for clocks to be stable, and clock domains reset to
128 * be inactive after power on and enable ports
130 check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
131 STS1_SYS125_RST | STS1_XHCI_RST;
133 if (mtk->num_u3_ports > u3_ports_disabled)
134 check_val |= STS1_U3_MAC_RST;
136 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
137 (check_val == (value & check_val)), 100, 20000);
139 dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
146 static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
148 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
156 /* power down u3 ports except skipped ones */
157 for (i = 0; i < mtk->num_u3_ports; i++) {
158 if ((0x1 << i) & mtk->u3p_dis_msk)
161 value = readl(&ippc->u3_ctrl_p[i]);
162 value |= CTRL_U3_PORT_PDN;
163 writel(value, &ippc->u3_ctrl_p[i]);
166 /* power down all u2 ports */
167 for (i = 0; i < mtk->num_u2_ports; i++) {
168 value = readl(&ippc->u2_ctrl_p[i]);
169 value |= CTRL_U2_PORT_PDN;
170 writel(value, &ippc->u2_ctrl_p[i]);
173 /* power down host ip */
174 value = readl(&ippc->ip_pw_ctr1);
175 value |= CTRL1_IP_HOST_PDN;
176 writel(value, &ippc->ip_pw_ctr1);
178 /* wait for host ip to sleep */
179 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
180 (value & STS1_IP_SLEEP_STS), 100, 100000);
182 dev_err(mtk->dev, "ip sleep failed!!!\n");
188 static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
190 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
197 value = readl(&ippc->ip_pw_ctr0);
198 value |= CTRL0_IP_SW_RST;
199 writel(value, &ippc->ip_pw_ctr0);
201 value = readl(&ippc->ip_pw_ctr0);
202 value &= ~CTRL0_IP_SW_RST;
203 writel(value, &ippc->ip_pw_ctr0);
206 * device ip is default power-on in fact
207 * power down device ip, otherwise ip-sleep will fail
209 value = readl(&ippc->ip_pw_ctr2);
210 value |= CTRL2_IP_DEV_PDN;
211 writel(value, &ippc->ip_pw_ctr2);
213 value = readl(&ippc->ip_xhci_cap);
214 mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
215 mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
216 dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
217 mtk->num_u2_ports, mtk->num_u3_ports);
219 return xhci_mtk_host_enable(mtk);
222 /* only clocks can be turn off for ip-sleep wakeup mode */
223 static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable)
227 switch (mtk->uwk_vers) {
229 reg = mtk->uwk_reg_base + PERI_WK_CTRL1;
230 msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;
231 val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0;
234 reg = mtk->uwk_reg_base + PERI_WK_CTRL0;
235 msk = WC0_IS_EN | WC0_IS_C(0xf) | WC0_IS_P;
236 val = enable ? (WC0_IS_EN | WC0_IS_C(0x8)) : 0;
239 reg = mtk->uwk_reg_base + PERI_WK_CTRL0;
240 msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN;
241 val = enable ? msk : 0;
244 reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
245 msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;
246 val = enable ? msk : 0;
251 regmap_update_bits(mtk->uwk, reg, msk, val);
254 static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
255 struct device_node *dn)
257 struct of_phandle_args args;
260 /* Wakeup function is optional */
261 mtk->uwk_en = of_property_read_bool(dn, "wakeup-source");
265 ret = of_parse_phandle_with_fixed_args(dn,
266 "mediatek,syscon-wakeup", 2, 0, &args);
270 mtk->uwk_reg_base = args.args[0];
271 mtk->uwk_vers = args.args[1];
272 mtk->uwk = syscon_node_to_regmap(args.np);
273 of_node_put(args.np);
274 dev_info(mtk->dev, "uwk - reg:0x%x, version:%d\n",
275 mtk->uwk_reg_base, mtk->uwk_vers);
277 return PTR_ERR_OR_ZERO(mtk->uwk);
280 static void usb_wakeup_set(struct xhci_hcd_mtk *mtk, bool enable)
283 usb_wakeup_ip_sleep_set(mtk, enable);
286 static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk)
288 struct clk_bulk_data *clks = mtk->clks;
290 clks[0].id = "sys_ck";
291 clks[1].id = "xhci_ck";
292 clks[2].id = "ref_ck";
293 clks[3].id = "mcu_ck";
294 clks[4].id = "dma_ck";
296 return devm_clk_bulk_get_optional(mtk->dev, BULK_CLKS_NUM, clks);
299 static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk)
303 ret = regulator_enable(mtk->vbus);
305 dev_err(mtk->dev, "failed to enable vbus\n");
309 ret = regulator_enable(mtk->vusb33);
311 dev_err(mtk->dev, "failed to enable vusb33\n");
312 regulator_disable(mtk->vbus);
318 static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk)
320 regulator_disable(mtk->vbus);
321 regulator_disable(mtk->vusb33);
324 static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
326 struct usb_hcd *hcd = xhci_to_hcd(xhci);
327 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
330 * As of now platform drivers don't provide MSI support so we ensure
331 * here that the generic code does not try to make a pci_dev from our
332 * dev struct in order to setup MSI
334 xhci->quirks |= XHCI_PLAT;
335 xhci->quirks |= XHCI_MTK_HOST;
337 * MTK host controller gives a spurious successful event after a
338 * short transfer. Ignore it.
340 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
341 if (mtk->lpm_support)
342 xhci->quirks |= XHCI_LPM_SUPPORT;
343 if (mtk->u2_lpm_disable)
344 xhci->quirks |= XHCI_HW_LPM_DISABLE;
347 * MTK xHCI 0.96: PSA is 1 by default even if doesn't support stream,
348 * and it's 3 when support it.
350 if (xhci->hci_version < 0x100 && HCC_MAX_PSA(xhci->hcc_params) == 4)
351 xhci->quirks |= XHCI_BROKEN_STREAMS;
354 /* called during probe() after chip reset completes */
355 static int xhci_mtk_setup(struct usb_hcd *hcd)
357 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
360 if (usb_hcd_is_primary_hcd(hcd)) {
361 ret = xhci_mtk_ssusb_config(mtk);
366 ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
370 if (usb_hcd_is_primary_hcd(hcd)) {
371 ret = xhci_mtk_sch_init(mtk);
379 static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
380 .reset = xhci_mtk_setup,
381 .add_endpoint = xhci_mtk_add_ep,
382 .drop_endpoint = xhci_mtk_drop_ep,
383 .check_bandwidth = xhci_mtk_check_bandwidth,
384 .reset_bandwidth = xhci_mtk_reset_bandwidth,
387 static struct hc_driver __read_mostly xhci_mtk_hc_driver;
389 static int xhci_mtk_probe(struct platform_device *pdev)
391 struct device *dev = &pdev->dev;
392 struct device_node *node = dev->of_node;
393 struct xhci_hcd_mtk *mtk;
394 const struct hc_driver *driver;
395 struct xhci_hcd *xhci;
396 struct resource *res;
405 driver = &xhci_mtk_hc_driver;
406 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
411 mtk->vbus = devm_regulator_get(dev, "vbus");
412 if (IS_ERR(mtk->vbus)) {
413 dev_err(dev, "fail to get vbus\n");
414 return PTR_ERR(mtk->vbus);
417 mtk->vusb33 = devm_regulator_get(dev, "vusb33");
418 if (IS_ERR(mtk->vusb33)) {
419 dev_err(dev, "fail to get vusb33\n");
420 return PTR_ERR(mtk->vusb33);
423 ret = xhci_mtk_clks_get(mtk);
427 irq = platform_get_irq_byname_optional(pdev, "host");
429 if (irq == -EPROBE_DEFER)
432 /* for backward compatibility */
433 irq = platform_get_irq(pdev, 0);
438 wakeup_irq = platform_get_irq_byname_optional(pdev, "wakeup");
439 if (wakeup_irq == -EPROBE_DEFER)
442 mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
443 mtk->u2_lpm_disable = of_property_read_bool(node, "usb2-lpm-disable");
444 /* optional property, ignore the error if it does not exist */
445 of_property_read_u32(node, "mediatek,u3p-dis-msk",
448 ret = usb_wakeup_of_property_parse(mtk, node);
450 dev_err(dev, "failed to parse uwk property\n");
454 pm_runtime_set_active(dev);
455 pm_runtime_use_autosuspend(dev);
456 pm_runtime_set_autosuspend_delay(dev, 4000);
457 pm_runtime_enable(dev);
458 pm_runtime_get_sync(dev);
460 ret = xhci_mtk_ldos_enable(mtk);
464 ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks);
468 hcd = usb_create_hcd(driver, dev, dev_name(dev));
475 * USB 2.0 roothub is stored in the platform_device.
476 * Swap it with mtk HCD.
478 mtk->hcd = platform_get_drvdata(pdev);
479 platform_set_drvdata(pdev, mtk);
481 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
482 hcd->regs = devm_ioremap_resource(dev, res);
483 if (IS_ERR(hcd->regs)) {
484 ret = PTR_ERR(hcd->regs);
487 hcd->rsrc_start = res->start;
488 hcd->rsrc_len = resource_size(res);
490 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
491 if (res) { /* ippc register is optional */
492 mtk->ippc_regs = devm_ioremap_resource(dev, res);
493 if (IS_ERR(mtk->ippc_regs)) {
494 ret = PTR_ERR(mtk->ippc_regs);
497 mtk->has_ippc = true;
500 device_init_wakeup(dev, true);
502 xhci = hcd_to_xhci(hcd);
503 xhci->main_hcd = hcd;
506 * imod_interval is the interrupt moderation value in nanoseconds.
507 * The increment interval is 8 times as much as that defined in
508 * the xHCI spec on MTK's controller.
510 xhci->imod_interval = 5000;
511 device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval);
513 xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
515 if (!xhci->shared_hcd) {
517 goto disable_device_wakeup;
520 ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
524 if (HCC_MAX_PSA(xhci->hcc_params) >= 4 &&
525 !(xhci->quirks & XHCI_BROKEN_STREAMS))
526 xhci->shared_hcd->can_do_streams = 1;
528 ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
530 goto dealloc_usb2_hcd;
532 if (wakeup_irq > 0) {
533 ret = dev_pm_set_dedicated_wake_irq(dev, wakeup_irq);
535 dev_err(dev, "set wakeup irq %d failed\n", wakeup_irq);
536 goto dealloc_usb3_hcd;
538 dev_info(dev, "wakeup irq %d\n", wakeup_irq);
541 device_enable_async_suspend(dev);
542 pm_runtime_mark_last_busy(dev);
543 pm_runtime_put_autosuspend(dev);
544 pm_runtime_forbid(dev);
549 usb_remove_hcd(xhci->shared_hcd);
550 xhci->shared_hcd = NULL;
556 xhci_mtk_sch_exit(mtk);
557 usb_put_hcd(xhci->shared_hcd);
559 disable_device_wakeup:
560 device_init_wakeup(dev, false);
566 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
569 xhci_mtk_ldos_disable(mtk);
572 pm_runtime_put_sync_autosuspend(dev);
573 pm_runtime_disable(dev);
577 static int xhci_mtk_remove(struct platform_device *pdev)
579 struct xhci_hcd_mtk *mtk = platform_get_drvdata(pdev);
580 struct usb_hcd *hcd = mtk->hcd;
581 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
582 struct usb_hcd *shared_hcd = xhci->shared_hcd;
583 struct device *dev = &pdev->dev;
585 pm_runtime_get_sync(dev);
586 xhci->xhc_state |= XHCI_STATE_REMOVING;
587 dev_pm_clear_wake_irq(dev);
588 device_init_wakeup(dev, false);
590 usb_remove_hcd(shared_hcd);
591 xhci->shared_hcd = NULL;
593 usb_put_hcd(shared_hcd);
595 xhci_mtk_sch_exit(mtk);
596 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
597 xhci_mtk_ldos_disable(mtk);
599 pm_runtime_disable(dev);
600 pm_runtime_put_noidle(dev);
601 pm_runtime_set_suspended(dev);
606 static int __maybe_unused xhci_mtk_suspend(struct device *dev)
608 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
609 struct usb_hcd *hcd = mtk->hcd;
610 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
613 xhci_dbg(xhci, "%s: stop port polling\n", __func__);
614 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
615 del_timer_sync(&hcd->rh_timer);
616 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
617 del_timer_sync(&xhci->shared_hcd->rh_timer);
619 ret = xhci_mtk_host_disable(mtk);
621 goto restart_poll_rh;
623 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
624 usb_wakeup_set(mtk, true);
628 xhci_dbg(xhci, "%s: restart port polling\n", __func__);
629 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
630 usb_hcd_poll_rh_status(xhci->shared_hcd);
631 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
632 usb_hcd_poll_rh_status(hcd);
636 static int __maybe_unused xhci_mtk_resume(struct device *dev)
638 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
639 struct usb_hcd *hcd = mtk->hcd;
640 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
643 usb_wakeup_set(mtk, false);
644 ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks);
648 ret = xhci_mtk_host_enable(mtk);
652 xhci_dbg(xhci, "%s: restart port polling\n", __func__);
653 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
654 usb_hcd_poll_rh_status(xhci->shared_hcd);
655 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
656 usb_hcd_poll_rh_status(hcd);
660 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
662 usb_wakeup_set(mtk, true);
666 static int __maybe_unused xhci_mtk_runtime_suspend(struct device *dev)
668 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
669 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd);
675 if (device_may_wakeup(dev))
676 ret = xhci_mtk_suspend(dev);
678 /* -EBUSY: let PM automatically reschedule another autosuspend */
679 return ret ? -EBUSY : 0;
682 static int __maybe_unused xhci_mtk_runtime_resume(struct device *dev)
684 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
685 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd);
691 if (device_may_wakeup(dev))
692 ret = xhci_mtk_resume(dev);
697 static const struct dev_pm_ops xhci_mtk_pm_ops = {
698 SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
699 SET_RUNTIME_PM_OPS(xhci_mtk_runtime_suspend,
700 xhci_mtk_runtime_resume, NULL)
703 #define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL)
705 static const struct of_device_id mtk_xhci_of_match[] = {
706 { .compatible = "mediatek,mt8173-xhci"},
707 { .compatible = "mediatek,mtk-xhci"},
710 MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
712 static struct platform_driver mtk_xhci_driver = {
713 .probe = xhci_mtk_probe,
714 .remove = xhci_mtk_remove,
718 .of_match_table = mtk_xhci_of_match,
722 static int __init xhci_mtk_init(void)
724 xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
725 return platform_driver_register(&mtk_xhci_driver);
727 module_init(xhci_mtk_init);
729 static void __exit xhci_mtk_exit(void)
731 platform_driver_unregister(&mtk_xhci_driver);
733 module_exit(xhci_mtk_exit);
735 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
736 MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
737 MODULE_LICENSE("GPL v2");