drivers/usb/host/xhci-mem.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/usb.h>
  24 #include <linux/pci.h>
  25 #include <linux/slab.h>
  26 #include <linux/dmapool.h>
  27
  28 #include "xhci.h"
  29
  30 /*
  31  * Allocates a generic ring segment from the ring pool, sets the dma address,
  32  * initializes the segment to zero, and sets the private next pointer to NULL.
  33  *
  34  * Section 4.11.1.1:
  35  * "All components of all Command and Transfer TRBs shall be initialized to '0'"
  36  */
  37 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci,
  38                                         unsigned int cycle_state, gfp_t flags)
  39 {
  40         struct xhci_segment *seg;
  41         dma_addr_t      dma;
  42         int             i;
  43
  44         seg = kzalloc(sizeof *seg, flags);
  45         if (!seg)
  46                 return NULL;
  47
  48         seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
  49         if (!seg->trbs) {
  50                 kfree(seg);
  51                 return NULL;
  52         }
  53
  54         memset(seg->trbs, 0, TRB_SEGMENT_SIZE);
  55         /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
  56         if (cycle_state == 0) {
  57                 for (i = 0; i < TRBS_PER_SEGMENT; i++)
  58                         seg->trbs[i].link.control |= TRB_CYCLE;
  59         }
  60         seg->dma = dma;
  61         seg->next = NULL;
  62
  63         return seg;
  64 }
  65
  66 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
  67 {
  68         if (seg->trbs) {
  69                 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
  70                 seg->trbs = NULL;
  71         }
  72         kfree(seg);
  73 }
  74
  75 static void xhci_free_segments_for_ring(struct xhci_hcd *xhci,
  76                                 struct xhci_segment *first)
  77 {
  78         struct xhci_segment *seg;
  79
  80         seg = first->next;
  81         while (seg != first) {
  82                 struct xhci_segment *next = seg->next;
  83                 xhci_segment_free(xhci, seg);
  84                 seg = next;
  85         }
  86         xhci_segment_free(xhci, first);
  87 }
  88
  89 /*
  90  * Make the prev segment point to the next segment.
  91  *
  92  * Change the last TRB in the prev segment to be a Link TRB which points to the
  93  * DMA address of the next segment.  The caller needs to set any Link TRB
  94  * related flags, such as End TRB, Toggle Cycle, and no snoop.
  95  */
  96 static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
  97                 struct xhci_segment *next, enum xhci_ring_type type)
  98 {
  99         u32 val;
 100
 101         if (!prev || !next)
 102                 return;
 103         prev->next = next;
 104         if (type != TYPE_EVENT) {
 105                 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
 106                         cpu_to_le64(next->dma);
 107
 108                 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
 109                 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
 110                 val &= ~TRB_TYPE_BITMASK;
 111                 val |= TRB_TYPE(TRB_LINK);
 112                 /* Always set the chain bit with 0.95 hardware */
 113                 /* Set chain bit for isoc rings on AMD 0.96 host */
 114                 if (xhci_link_trb_quirk(xhci) ||
 115                                 (type == TYPE_ISOC &&
 116                                  (xhci->quirks & XHCI_AMD_0x96_HOST)))
 117                         val |= TRB_CHAIN;
 118                 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
 119         }
 120 }
 121
 122 /*
 123  * Link the ring to the new segments.
 124  * Set Toggle Cycle for the new ring if needed.
 125  */
 126 static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring,
 127                 struct xhci_segment *first, struct xhci_segment *last,
 128                 unsigned int num_segs)
 129 {
 130         struct xhci_segment *next;
 131
 132         if (!ring || !first || !last)
 133                 return;
 134
 135         next = ring->enq_seg->next;
 136         xhci_link_segments(xhci, ring->enq_seg, first, ring->type);
 137         xhci_link_segments(xhci, last, next, ring->type);
 138         ring->num_segs += num_segs;
 139         ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs;
 140
 141         if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) {
 142                 ring->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control
 143                         &= ~cpu_to_le32(LINK_TOGGLE);
 144                 last->trbs[TRBS_PER_SEGMENT-1].link.control
 145                         |= cpu_to_le32(LINK_TOGGLE);
 146                 ring->last_seg = last;
 147         }
 148 }
 149
 150 /* XXX: Do we need the hcd structure in all these functions? */
 151 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
 152 {
 153         if (!ring)
 154                 return;
 155
 156         if (ring->first_seg)
 157                 xhci_free_segments_for_ring(xhci, ring->first_seg);
 158
 159         kfree(ring);
 160 }
 161
 162 static void xhci_initialize_ring_info(struct xhci_ring *ring,
 163                                         unsigned int cycle_state)
 164 {
 165         /* The ring is empty, so the enqueue pointer == dequeue pointer */
 166         ring->enqueue = ring->first_seg->trbs;
 167         ring->enq_seg = ring->first_seg;
 168         ring->dequeue = ring->enqueue;
 169         ring->deq_seg = ring->first_seg;
 170         /* The ring is initialized to 0. The producer must write 1 to the cycle
 171          * bit to handover ownership of the TRB, so PCS = 1.  The consumer must
 172          * compare CCS to the cycle bit to check ownership, so CCS = 1.
 173          *
 174          * New rings are initialized with cycle state equal to 1; if we are
 175          * handling ring expansion, set the cycle state equal to the old ring.
 176          */
 177         ring->cycle_state = cycle_state;
 178         /* Not necessary for new rings, but needed for re-initialized rings */
 179         ring->enq_updates = 0;
 180         ring->deq_updates = 0;
 181
 182         /*
 183          * Each segment has a link TRB, and leave an extra TRB for SW
 184          * accounting purpose
 185          */
 186         ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
 187 }
 188
 189 /* Allocate segments and link them for a ring */
 190 static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci,
 191                 struct xhci_segment **first, struct xhci_segment **last,
 192                 unsigned int num_segs, unsigned int cycle_state,
 193                 enum xhci_ring_type type, gfp_t flags)
 194 {
 195         struct xhci_segment *prev;
 196
 197         prev = xhci_segment_alloc(xhci, cycle_state, flags);
 198         if (!prev)
 199                 return -ENOMEM;
 200         num_segs--;
 201
 202         *first = prev;
 203         while (num_segs > 0) {
 204                 struct xhci_segment     *next;
 205
 206                 next = xhci_segment_alloc(xhci, cycle_state, flags);
 207                 if (!next) {
 208                         prev = *first;
 209                         while (prev) {
 210                                 next = prev->next;
 211                                 xhci_segment_free(xhci, prev);
 212                                 prev = next;
 213                         }
 214                         return -ENOMEM;
 215                 }
 216                 xhci_link_segments(xhci, prev, next, type);
 217
 218                 prev = next;
 219                 num_segs--;
 220         }
 221         xhci_link_segments(xhci, prev, *first, type);
 222         *last = prev;
 223
 224         return 0;
 225 }
 226
 227 /**
 228  * Create a new ring with zero or more segments.
 229  *
 230  * Link each segment together into a ring.
 231  * Set the end flag and the cycle toggle bit on the last segment.
 232  * See section 4.9.1 and figures 15 and 16.
 233  */
 234 static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
 235                 unsigned int num_segs, unsigned int cycle_state,
 236                 enum xhci_ring_type type, gfp_t flags)
 237 {
 238         struct xhci_ring        *ring;
 239         int ret;
 240
 241         ring = kzalloc(sizeof *(ring), flags);
 242         if (!ring)
 243                 return NULL;
 244
 245         ring->num_segs = num_segs;
 246         INIT_LIST_HEAD(&ring->td_list);
 247         ring->type = type;
 248         if (num_segs == 0)
 249                 return ring;
 250
 251         ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg,
 252                         &ring->last_seg, num_segs, cycle_state, type, flags);
 253         if (ret)
 254                 goto fail;
 255
 256         /* Only event ring does not use link TRB */
 257         if (type != TYPE_EVENT) {
 258                 /* See section 4.9.2.1 and 6.4.4.1 */
 259                 ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |=
 260                         cpu_to_le32(LINK_TOGGLE);
 261         }
 262         xhci_initialize_ring_info(ring, cycle_state);
 263         return ring;
 264
 265 fail:
 266         kfree(ring);
 267         return NULL;
 268 }
 269
 270 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
 271                 struct xhci_virt_device *virt_dev,
 272                 unsigned int ep_index)
 273 {
 274         int rings_cached;
 275
 276         rings_cached = virt_dev->num_rings_cached;
 277         if (rings_cached < XHCI_MAX_RINGS_CACHED) {
 278                 virt_dev->ring_cache[rings_cached] =
 279                         virt_dev->eps[ep_index].ring;
 280                 virt_dev->num_rings_cached++;
 281                 xhci_dbg(xhci, "Cached old ring, "
 282                                 "%d ring%s cached\n",
 283                                 virt_dev->num_rings_cached,
 284                                 (virt_dev->num_rings_cached > 1) ? "s" : "");
 285         } else {
 286                 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
 287                 xhci_dbg(xhci, "Ring cache full (%d rings), "
 288                                 "freeing ring\n",
 289                                 virt_dev->num_rings_cached);
 290         }
 291         virt_dev->eps[ep_index].ring = NULL;
 292 }
 293
 294 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
 295  * pointers to the beginning of the ring.
 296  */
 297 static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
 298                         struct xhci_ring *ring, unsigned int cycle_state,
 299                         enum xhci_ring_type type)
 300 {
 301         struct xhci_segment     *seg = ring->first_seg;
 302         int i;
 303
 304         do {
 305                 memset(seg->trbs, 0,
 306                                 sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
 307                 if (cycle_state == 0) {
 308                         for (i = 0; i < TRBS_PER_SEGMENT; i++)
 309                                 seg->trbs[i].link.control |= TRB_CYCLE;
 310                 }
 311                 /* All endpoint rings have link TRBs */
 312                 xhci_link_segments(xhci, seg, seg->next, type);
 313                 seg = seg->next;
 314         } while (seg != ring->first_seg);
 315         ring->type = type;
 316         xhci_initialize_ring_info(ring, cycle_state);
 317         /* td list should be empty since all URBs have been cancelled,
 318          * but just in case...
 319          */
 320         INIT_LIST_HEAD(&ring->td_list);
 321 }
 322
 323 /*
 324  * Expand an existing ring.
 325  * Look for a cached ring or allocate a new ring which has same segment numbers
 326  * and link the two rings.
 327  */
 328 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
 329                                 unsigned int num_trbs, gfp_t flags)
 330 {
 331         struct xhci_segment     *first;
 332         struct xhci_segment     *last;
 333         unsigned int            num_segs;
 334         unsigned int            num_segs_needed;
 335         int                     ret;
 336
 337         num_segs_needed = (num_trbs + (TRBS_PER_SEGMENT - 1) - 1) /
 338                                 (TRBS_PER_SEGMENT - 1);
 339
 340         /* Allocate number of segments we needed, or double the ring size */
 341         num_segs = ring->num_segs > num_segs_needed ?
 342                         ring->num_segs : num_segs_needed;
 343
 344         ret = xhci_alloc_segments_for_ring(xhci, &first, &last,
 345                         num_segs, ring->cycle_state, ring->type, flags);
 346         if (ret)
 347                 return -ENOMEM;
 348
 349         xhci_link_rings(xhci, ring, first, last, num_segs);
 350         xhci_dbg(xhci, "ring expansion succeed, now has %d segments\n",
 351                         ring->num_segs);
 352
 353         return 0;
 354 }
 355
 356 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
 357
 358 static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
 359                                                     int type, gfp_t flags)
 360 {
 361         struct xhci_container_ctx *ctx;
 362
 363         if ((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT))
 364                 return NULL;
 365
 366         ctx = kzalloc(sizeof(*ctx), flags);
 367         if (!ctx)
 368                 return NULL;
 369
 370         ctx->type = type;
 371         ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
 372         if (type == XHCI_CTX_TYPE_INPUT)
 373                 ctx->size += CTX_SIZE(xhci->hcc_params);
 374
 375         ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
 376         memset(ctx->bytes, 0, ctx->size);
 377         return ctx;
 378 }
 379
 380 static void xhci_free_container_ctx(struct xhci_hcd *xhci,
 381                              struct xhci_container_ctx *ctx)
 382 {
 383         if (!ctx)
 384                 return;
 385         dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
 386         kfree(ctx);
 387 }
 388
 389 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
 390                                               struct xhci_container_ctx *ctx)
 391 {
 392         if (ctx->type != XHCI_CTX_TYPE_INPUT)
 393                 return NULL;
 394
 395         return (struct xhci_input_control_ctx *)ctx->bytes;
 396 }
 397
 398 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
 399                                         struct xhci_container_ctx *ctx)
 400 {
 401         if (ctx->type == XHCI_CTX_TYPE_DEVICE)
 402                 return (struct xhci_slot_ctx *)ctx->bytes;
 403
 404         return (struct xhci_slot_ctx *)
 405                 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
 406 }
 407
 408 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
 409                                     struct xhci_container_ctx *ctx,
 410                                     unsigned int ep_index)
 411 {
 412         /* increment ep index by offset of start of ep ctx array */
 413         ep_index++;
 414         if (ctx->type == XHCI_CTX_TYPE_INPUT)
 415                 ep_index++;
 416
 417         return (struct xhci_ep_ctx *)
 418                 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
 419 }
 420
 421
 422 /***************** Streams structures manipulation *************************/
 423
 424 static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
 425                 unsigned int num_stream_ctxs,
 426                 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
 427 {
 428         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 429
 430         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
 431                 dma_free_coherent(&pdev->dev,
 432                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
 433                                 stream_ctx, dma);
 434         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
 435                 return dma_pool_free(xhci->small_streams_pool,
 436                                 stream_ctx, dma);
 437         else
 438                 return dma_pool_free(xhci->medium_streams_pool,
 439                                 stream_ctx, dma);
 440 }
 441
 442 /*
 443  * The stream context array for each endpoint with bulk streams enabled can
 444  * vary in size, based on:
 445  *  - how many streams the endpoint supports,
 446  *  - the maximum primary stream array size the host controller supports,
 447  *  - and how many streams the device driver asks for.
 448  *
 449  * The stream context array must be a power of 2, and can be as small as
 450  * 64 bytes or as large as 1MB.
 451  */
 452 static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
 453                 unsigned int num_stream_ctxs, dma_addr_t *dma,
 454                 gfp_t mem_flags)
 455 {
 456         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 457
 458         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
 459                 return dma_alloc_coherent(&pdev->dev,
 460                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
 461                                 dma, mem_flags);
 462         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
 463                 return dma_pool_alloc(xhci->small_streams_pool,
 464                                 mem_flags, dma);
 465         else
 466                 return dma_pool_alloc(xhci->medium_streams_pool,
 467                                 mem_flags, dma);
 468 }
 469
 470 struct xhci_ring *xhci_dma_to_transfer_ring(
 471                 struct xhci_virt_ep *ep,
 472                 u64 address)
 473 {
 474         if (ep->ep_state & EP_HAS_STREAMS)
 475                 return radix_tree_lookup(&ep->stream_info->trb_address_map,
 476                                 address >> TRB_SEGMENT_SHIFT);
 477         return ep->ring;
 478 }
 479
 480 /* Only use this when you know stream_info is valid */
 481 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 482 static struct xhci_ring *dma_to_stream_ring(
 483                 struct xhci_stream_info *stream_info,
 484                 u64 address)
 485 {
 486         return radix_tree_lookup(&stream_info->trb_address_map,
 487                         address >> TRB_SEGMENT_SHIFT);
 488 }
 489 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
 490
 491 struct xhci_ring *xhci_stream_id_to_ring(
 492                 struct xhci_virt_device *dev,
 493                 unsigned int ep_index,
 494                 unsigned int stream_id)
 495 {
 496         struct xhci_virt_ep *ep = &dev->eps[ep_index];
 497
 498         if (stream_id == 0)
 499                 return ep->ring;
 500         if (!ep->stream_info)
 501                 return NULL;
 502
 503         if (stream_id > ep->stream_info->num_streams)
 504                 return NULL;
 505         return ep->stream_info->stream_rings[stream_id];
 506 }
 507
 508 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 509 static int xhci_test_radix_tree(struct xhci_hcd *xhci,
 510                 unsigned int num_streams,
 511                 struct xhci_stream_info *stream_info)
 512 {
 513         u32 cur_stream;
 514         struct xhci_ring *cur_ring;
 515         u64 addr;
 516
 517         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 518                 struct xhci_ring *mapped_ring;
 519                 int trb_size = sizeof(union xhci_trb);
 520
 521                 cur_ring = stream_info->stream_rings[cur_stream];
 522                 for (addr = cur_ring->first_seg->dma;
 523                                 addr < cur_ring->first_seg->dma + TRB_SEGMENT_SIZE;
 524                                 addr += trb_size) {
 525                         mapped_ring = dma_to_stream_ring(stream_info, addr);
 526                         if (cur_ring != mapped_ring) {
 527                                 xhci_warn(xhci, "WARN: DMA address 0x%08llx "
 528                                                 "didn't map to stream ID %u; "
 529                                                 "mapped to ring %p\n",
 530                                                 (unsigned long long) addr,
 531                                                 cur_stream,
 532                                                 mapped_ring);
 533                                 return -EINVAL;
 534                         }
 535                 }
 536                 /* One TRB after the end of the ring segment shouldn't return a
 537                  * pointer to the current ring (although it may be a part of a
 538                  * different ring).
 539                  */
 540                 mapped_ring = dma_to_stream_ring(stream_info, addr);
 541                 if (mapped_ring != cur_ring) {
 542                         /* One TRB before should also fail */
 543                         addr = cur_ring->first_seg->dma - trb_size;
 544                         mapped_ring = dma_to_stream_ring(stream_info, addr);
 545                 }
 546                 if (mapped_ring == cur_ring) {
 547                         xhci_warn(xhci, "WARN: Bad DMA address 0x%08llx "
 548                                         "mapped to valid stream ID %u; "
 549                                         "mapped ring = %p\n",
 550                                         (unsigned long long) addr,
 551                                         cur_stream,
 552                                         mapped_ring);
 553                         return -EINVAL;
 554                 }
 555         }
 556         return 0;
 557 }
 558 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
 559
 560 /*
 561  * Change an endpoint's internal structure so it supports stream IDs.  The
 562  * number of requested streams includes stream 0, which cannot be used by device
 563  * drivers.
 564  *
 565  * The number of stream contexts in the stream context array may be bigger than
 566  * the number of streams the driver wants to use.  This is because the number of
 567  * stream context array entries must be a power of two.
 568  *
 569  * We need a radix tree for mapping physical addresses of TRBs to which stream
 570  * ID they belong to.  We need to do this because the host controller won't tell
 571  * us which stream ring the TRB came from.  We could store the stream ID in an
 572  * event data TRB, but that doesn't help us for the cancellation case, since the
 573  * endpoint may stop before it reaches that event data TRB.
 574  *
 575  * The radix tree maps the upper portion of the TRB DMA address to a ring
 576  * segment that has the same upper portion of DMA addresses.  For example, say I
 577  * have segments of size 1KB, that are always 64-byte aligned.  A segment may
 578  * start at 0x10c91000 and end at 0x10c913f0.  If I use the upper 10 bits, the
 579  * key to the stream ID is 0x43244.  I can use the DMA address of the TRB to
 580  * pass the radix tree a key to get the right stream ID:
 581  *
 582  *      0x10c90fff >> 10 = 0x43243
 583  *      0x10c912c0 >> 10 = 0x43244
 584  *      0x10c91400 >> 10 = 0x43245
 585  *
 586  * Obviously, only those TRBs with DMA addresses that are within the segment
 587  * will make the radix tree return the stream ID for that ring.
 588  *
 589  * Caveats for the radix tree:
 590  *
 591  * The radix tree uses an unsigned long as a key pair.  On 32-bit systems, an
 592  * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
 593  * 64-bits.  Since we only request 32-bit DMA addresses, we can use that as the
 594  * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
 595  * PCI DMA addresses on a 64-bit system).  There might be a problem on 32-bit
 596  * extended systems (where the DMA address can be bigger than 32-bits),
 597  * if we allow the PCI dma mask to be bigger than 32-bits.  So don't do that.
 598  */
 599 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
 600                 unsigned int num_stream_ctxs,
 601                 unsigned int num_streams, gfp_t mem_flags)
 602 {
 603         struct xhci_stream_info *stream_info;
 604         u32 cur_stream;
 605         struct xhci_ring *cur_ring;
 606         unsigned long key;
 607         u64 addr;
 608         int ret;
 609
 610         xhci_dbg(xhci, "Allocating %u streams and %u "
 611                         "stream context array entries.\n",
 612                         num_streams, num_stream_ctxs);
 613         if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
 614                 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
 615                 return NULL;
 616         }
 617         xhci->cmd_ring_reserved_trbs++;
 618
 619         stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags);
 620         if (!stream_info)
 621                 goto cleanup_trbs;
 622
 623         stream_info->num_streams = num_streams;
 624         stream_info->num_stream_ctxs = num_stream_ctxs;
 625
 626         /* Initialize the array of virtual pointers to stream rings. */
 627         stream_info->stream_rings = kzalloc(
 628                         sizeof(struct xhci_ring *)*num_streams,
 629                         mem_flags);
 630         if (!stream_info->stream_rings)
 631                 goto cleanup_info;
 632
 633         /* Initialize the array of DMA addresses for stream rings for the HW. */
 634         stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
 635                         num_stream_ctxs, &stream_info->ctx_array_dma,
 636                         mem_flags);
 637         if (!stream_info->stream_ctx_array)
 638                 goto cleanup_ctx;
 639         memset(stream_info->stream_ctx_array, 0,
 640                         sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
 641
 642         /* Allocate everything needed to free the stream rings later */
 643         stream_info->free_streams_command =
 644                 xhci_alloc_command(xhci, true, true, mem_flags);
 645         if (!stream_info->free_streams_command)
 646                 goto cleanup_ctx;
 647
 648         INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
 649
 650         /* Allocate rings for all the streams that the driver will use,
 651          * and add their segment DMA addresses to the radix tree.
 652          * Stream 0 is reserved.
 653          */
 654         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 655                 stream_info->stream_rings[cur_stream] =
 656                         xhci_ring_alloc(xhci, 2, 1, TYPE_STREAM, mem_flags);
 657                 cur_ring = stream_info->stream_rings[cur_stream];
 658                 if (!cur_ring)
 659                         goto cleanup_rings;
 660                 cur_ring->stream_id = cur_stream;
 661                 /* Set deq ptr, cycle bit, and stream context type */
 662                 addr = cur_ring->first_seg->dma |
 663                         SCT_FOR_CTX(SCT_PRI_TR) |
 664                         cur_ring->cycle_state;
 665                 stream_info->stream_ctx_array[cur_stream].stream_ring =
 666                         cpu_to_le64(addr);
 667                 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
 668                                 cur_stream, (unsigned long long) addr);
 669
 670                 key = (unsigned long)
 671                         (cur_ring->first_seg->dma >> TRB_SEGMENT_SHIFT);
 672                 ret = radix_tree_insert(&stream_info->trb_address_map,
 673                                 key, cur_ring);
 674                 if (ret) {
 675                         xhci_ring_free(xhci, cur_ring);
 676                         stream_info->stream_rings[cur_stream] = NULL;
 677                         goto cleanup_rings;
 678                 }
 679         }
 680         /* Leave the other unused stream ring pointers in the stream context
 681          * array initialized to zero.  This will cause the xHC to give us an
 682          * error if the device asks for a stream ID we don't have setup (if it
 683          * was any other way, the host controller would assume the ring is
 684          * "empty" and wait forever for data to be queued to that stream ID).
 685          */
 686 #if XHCI_DEBUG
 687         /* Do a little test on the radix tree to make sure it returns the
 688          * correct values.
 689          */
 690         if (xhci_test_radix_tree(xhci, num_streams, stream_info))
 691                 goto cleanup_rings;
 692 #endif
 693
 694         return stream_info;
 695
 696 cleanup_rings:
 697         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 698                 cur_ring = stream_info->stream_rings[cur_stream];
 699                 if (cur_ring) {
 700                         addr = cur_ring->first_seg->dma;
 701                         radix_tree_delete(&stream_info->trb_address_map,
 702                                         addr >> TRB_SEGMENT_SHIFT);
 703                         xhci_ring_free(xhci, cur_ring);
 704                         stream_info->stream_rings[cur_stream] = NULL;
 705                 }
 706         }
 707         xhci_free_command(xhci, stream_info->free_streams_command);
 708 cleanup_ctx:
 709         kfree(stream_info->stream_rings);
 710 cleanup_info:
 711         kfree(stream_info);
 712 cleanup_trbs:
 713         xhci->cmd_ring_reserved_trbs--;
 714         return NULL;
 715 }
 716 /*
 717  * Sets the MaxPStreams field and the Linear Stream Array field.
 718  * Sets the dequeue pointer to the stream context array.
 719  */
 720 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
 721                 struct xhci_ep_ctx *ep_ctx,
 722                 struct xhci_stream_info *stream_info)
 723 {
 724         u32 max_primary_streams;
 725         /* MaxPStreams is the number of stream context array entries, not the
 726          * number we're actually using.  Must be in 2^(MaxPstreams + 1) format.
 727          * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
 728          */
 729         max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
 730         xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n",
 731                         1 << (max_primary_streams + 1));
 732         ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
 733         ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
 734                                        | EP_HAS_LSA);
 735         ep_ctx->deq  = cpu_to_le64(stream_info->ctx_array_dma);
 736 }
 737
 738 /*
 739  * Sets the MaxPStreams field and the Linear Stream Array field to 0.
 740  * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
 741  * not at the beginning of the ring).
 742  */
 743 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
 744                 struct xhci_ep_ctx *ep_ctx,
 745                 struct xhci_virt_ep *ep)
 746 {
 747         dma_addr_t addr;
 748         ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
 749         addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
 750         ep_ctx->deq  = cpu_to_le64(addr | ep->ring->cycle_state);
 751 }
 752
 753 /* Frees all stream contexts associated with the endpoint,
 754  *
 755  * Caller should fix the endpoint context streams fields.
 756  */
 757 void xhci_free_stream_info(struct xhci_hcd *xhci,
 758                 struct xhci_stream_info *stream_info)
 759 {
 760         int cur_stream;
 761         struct xhci_ring *cur_ring;
 762         dma_addr_t addr;
 763
 764         if (!stream_info)
 765                 return;
 766
 767         for (cur_stream = 1; cur_stream < stream_info->num_streams;
 768                         cur_stream++) {
 769                 cur_ring = stream_info->stream_rings[cur_stream];
 770                 if (cur_ring) {
 771                         addr = cur_ring->first_seg->dma;
 772                         radix_tree_delete(&stream_info->trb_address_map,
 773                                         addr >> TRB_SEGMENT_SHIFT);
 774                         xhci_ring_free(xhci, cur_ring);
 775                         stream_info->stream_rings[cur_stream] = NULL;
 776                 }
 777         }
 778         xhci_free_command(xhci, stream_info->free_streams_command);
 779         xhci->cmd_ring_reserved_trbs--;
 780         if (stream_info->stream_ctx_array)
 781                 xhci_free_stream_ctx(xhci,
 782                                 stream_info->num_stream_ctxs,
 783                                 stream_info->stream_ctx_array,
 784                                 stream_info->ctx_array_dma);
 785
 786         if (stream_info)
 787                 kfree(stream_info->stream_rings);
 788         kfree(stream_info);
 789 }
 790
 791
 792 /***************** Device context manipulation *************************/
 793
 794 static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
 795                 struct xhci_virt_ep *ep)
 796 {
 797         init_timer(&ep->stop_cmd_timer);
 798         ep->stop_cmd_timer.data = (unsigned long) ep;
 799         ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog;
 800         ep->xhci = xhci;
 801 }
 802
 803 static void xhci_free_tt_info(struct xhci_hcd *xhci,
 804                 struct xhci_virt_device *virt_dev,
 805                 int slot_id)
 806 {
 807         struct list_head *tt_list_head;
 808         struct xhci_tt_bw_info *tt_info, *next;
 809         bool slot_found = false;
 810
 811         /* If the device never made it past the Set Address stage,
 812          * it may not have the real_port set correctly.
 813          */
 814         if (virt_dev->real_port == 0 ||
 815                         virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
 816                 xhci_dbg(xhci, "Bad real port.\n");
 817                 return;
 818         }
 819
 820         tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
 821         list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
 822                 /* Multi-TT hubs will have more than one entry */
 823                 if (tt_info->slot_id == slot_id) {
 824                         slot_found = true;
 825                         list_del(&tt_info->tt_list);
 826                         kfree(tt_info);
 827                 } else if (slot_found) {
 828                         break;
 829                 }
 830         }
 831 }
 832
 833 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
 834                 struct xhci_virt_device *virt_dev,
 835                 struct usb_device *hdev,
 836                 struct usb_tt *tt, gfp_t mem_flags)
 837 {
 838         struct xhci_tt_bw_info          *tt_info;
 839         unsigned int                    num_ports;
 840         int                             i, j;
 841
 842         if (!tt->multi)
 843                 num_ports = 1;
 844         else
 845                 num_ports = hdev->maxchild;
 846
 847         for (i = 0; i < num_ports; i++, tt_info++) {
 848                 struct xhci_interval_bw_table *bw_table;
 849
 850                 tt_info = kzalloc(sizeof(*tt_info), mem_flags);
 851                 if (!tt_info)
 852                         goto free_tts;
 853                 INIT_LIST_HEAD(&tt_info->tt_list);
 854                 list_add(&tt_info->tt_list,
 855                                 &xhci->rh_bw[virt_dev->real_port - 1].tts);
 856                 tt_info->slot_id = virt_dev->udev->slot_id;
 857                 if (tt->multi)
 858                         tt_info->ttport = i+1;
 859                 bw_table = &tt_info->bw_table;
 860                 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
 861                         INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
 862         }
 863         return 0;
 864
 865 free_tts:
 866         xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
 867         return -ENOMEM;
 868 }
 869
 870
 871 /* All the xhci_tds in the ring's TD list should be freed at this point.
 872  * Should be called with xhci->lock held if there is any chance the TT lists
 873  * will be manipulated by the configure endpoint, allocate device, or update
 874  * hub functions while this function is removing the TT entries from the list.
 875  */
 876 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
 877 {
 878         struct xhci_virt_device *dev;
 879         int i;
 880         int old_active_eps = 0;
 881
 882         /* Slot ID 0 is reserved */
 883         if (slot_id == 0 || !xhci->devs[slot_id])
 884                 return;
 885
 886         dev = xhci->devs[slot_id];
 887         xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
 888         if (!dev)
 889                 return;
 890
 891         if (dev->tt_info)
 892                 old_active_eps = dev->tt_info->active_eps;
 893
 894         for (i = 0; i < 31; ++i) {
 895                 if (dev->eps[i].ring)
 896                         xhci_ring_free(xhci, dev->eps[i].ring);
 897                 if (dev->eps[i].stream_info)
 898                         xhci_free_stream_info(xhci,
 899                                         dev->eps[i].stream_info);
 900                 /* Endpoints on the TT/root port lists should have been removed
 901                  * when usb_disable_device() was called for the device.
 902                  * We can't drop them anyway, because the udev might have gone
 903                  * away by this point, and we can't tell what speed it was.
 904                  */
 905                 if (!list_empty(&dev->eps[i].bw_endpoint_list))
 906                         xhci_warn(xhci, "Slot %u endpoint %u "
 907                                         "not removed from BW list!\n",
 908                                         slot_id, i);
 909         }
 910         /* If this is a hub, free the TT(s) from the TT list */
 911         xhci_free_tt_info(xhci, dev, slot_id);
 912         /* If necessary, update the number of active TTs on this root port */
 913         xhci_update_tt_active_eps(xhci, dev, old_active_eps);
 914
 915         if (dev->ring_cache) {
 916                 for (i = 0; i < dev->num_rings_cached; i++)
 917                         xhci_ring_free(xhci, dev->ring_cache[i]);
 918                 kfree(dev->ring_cache);
 919         }
 920
 921         if (dev->in_ctx)
 922                 xhci_free_container_ctx(xhci, dev->in_ctx);
 923         if (dev->out_ctx)
 924                 xhci_free_container_ctx(xhci, dev->out_ctx);
 925
 926         kfree(xhci->devs[slot_id]);
 927         xhci->devs[slot_id] = NULL;
 928 }
 929
 930 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
 931                 struct usb_device *udev, gfp_t flags)
 932 {
 933         struct xhci_virt_device *dev;
 934         int i;
 935
 936         /* Slot ID 0 is reserved */
 937         if (slot_id == 0 || xhci->devs[slot_id]) {
 938                 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
 939                 return 0;
 940         }
 941
 942         xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
 943         if (!xhci->devs[slot_id])
 944                 return 0;
 945         dev = xhci->devs[slot_id];
 946
 947         /* Allocate the (output) device context that will be used in the HC. */
 948         dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
 949         if (!dev->out_ctx)
 950                 goto fail;
 951
 952         xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
 953                         (unsigned long long)dev->out_ctx->dma);
 954
 955         /* Allocate the (input) device context for address device command */
 956         dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
 957         if (!dev->in_ctx)
 958                 goto fail;
 959
 960         xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
 961                         (unsigned long long)dev->in_ctx->dma);
 962
 963         /* Initialize the cancellation list and watchdog timers for each ep */
 964         for (i = 0; i < 31; i++) {
 965                 xhci_init_endpoint_timer(xhci, &dev->eps[i]);
 966                 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
 967                 INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
 968         }
 969
 970         /* Allocate endpoint 0 ring */
 971         dev->eps[0].ring = xhci_ring_alloc(xhci, 2, 1, TYPE_CTRL, flags);
 972         if (!dev->eps[0].ring)
 973                 goto fail;
 974
 975         /* Allocate pointers to the ring cache */
 976         dev->ring_cache = kzalloc(
 977                         sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED,
 978                         flags);
 979         if (!dev->ring_cache)
 980                 goto fail;
 981         dev->num_rings_cached = 0;
 982
 983         init_completion(&dev->cmd_completion);
 984         INIT_LIST_HEAD(&dev->cmd_list);
 985         dev->udev = udev;
 986
 987         /* Point to output device context in dcbaa. */
 988         xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
 989         xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
 990                  slot_id,
 991                  &xhci->dcbaa->dev_context_ptrs[slot_id],
 992                  le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
 993
 994         return 1;
 995 fail:
 996         xhci_free_virt_device(xhci, slot_id);
 997         return 0;
 998 }
 999
1000 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1001                 struct usb_device *udev)
1002 {
1003         struct xhci_virt_device *virt_dev;
1004         struct xhci_ep_ctx      *ep0_ctx;
1005         struct xhci_ring        *ep_ring;
1006
1007         virt_dev = xhci->devs[udev->slot_id];
1008         ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
1009         ep_ring = virt_dev->eps[0].ring;
1010         /*
1011          * FIXME we don't keep track of the dequeue pointer very well after a
1012          * Set TR dequeue pointer, so we're setting the dequeue pointer of the
1013          * host to our enqueue pointer.  This should only be called after a
1014          * configured device has reset, so all control transfers should have
1015          * been completed or cancelled before the reset.
1016          */
1017         ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
1018                                                         ep_ring->enqueue)
1019                                    | ep_ring->cycle_state);
1020 }
1021
1022 /*
1023  * The xHCI roothub may have ports of differing speeds in any order in the port
1024  * status registers.  xhci->port_array provides an array of the port speed for
1025  * each offset into the port status registers.
1026  *
1027  * The xHCI hardware wants to know the roothub port number that the USB device
1028  * is attached to (or the roothub port its ancestor hub is attached to).  All we
1029  * know is the index of that port under either the USB 2.0 or the USB 3.0
1030  * roothub, but that doesn't give us the real index into the HW port status
1031  * registers. Call xhci_find_raw_port_number() to get real index.
1032  */
1033 static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
1034                 struct usb_device *udev)
1035 {
1036         struct usb_device *top_dev;
1037         struct usb_hcd *hcd;
1038
1039         if (udev->speed == USB_SPEED_SUPER)
1040                 hcd = xhci->shared_hcd;
1041         else
1042                 hcd = xhci->main_hcd;
1043
1044         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1045                         top_dev = top_dev->parent)
1046                 /* Found device below root hub */;
1047
1048         return  xhci_find_raw_port_number(hcd, top_dev->portnum);
1049 }
1050
1051 /* Setup an xHCI virtual device for a Set Address command */
1052 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
1053 {
1054         struct xhci_virt_device *dev;
1055         struct xhci_ep_ctx      *ep0_ctx;
1056         struct xhci_slot_ctx    *slot_ctx;
1057         u32                     port_num;
1058         struct usb_device *top_dev;
1059
1060         dev = xhci->devs[udev->slot_id];
1061         /* Slot ID 0 is reserved */
1062         if (udev->slot_id == 0 || !dev) {
1063                 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
1064                                 udev->slot_id);
1065                 return -EINVAL;
1066         }
1067         ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
1068         slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
1069
1070         /* 3) Only the control endpoint is valid - one endpoint context */
1071         slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
1072         switch (udev->speed) {
1073         case USB_SPEED_SUPER:
1074                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
1075                 break;
1076         case USB_SPEED_HIGH:
1077                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
1078                 break;
1079         case USB_SPEED_FULL:
1080                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
1081                 break;
1082         case USB_SPEED_LOW:
1083                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
1084                 break;
1085         case USB_SPEED_WIRELESS:
1086                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1087                 return -EINVAL;
1088                 break;
1089         default:
1090                 /* Speed was set earlier, this shouldn't happen. */
1091                 BUG();
1092         }
1093         /* Find the root hub port this device is under */
1094         port_num = xhci_find_real_port_number(xhci, udev);
1095         if (!port_num)
1096                 return -EINVAL;
1097         slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
1098         /* Set the port number in the virtual_device to the faked port number */
1099         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1100                         top_dev = top_dev->parent)
1101                 /* Found device below root hub */;
1102         dev->fake_port = top_dev->portnum;
1103         dev->real_port = port_num;
1104         xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
1105         xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
1106
1107         /* Find the right bandwidth table that this device will be a part of.
1108          * If this is a full speed device attached directly to a root port (or a
1109          * decendent of one), it counts as a primary bandwidth domain, not a
1110          * secondary bandwidth domain under a TT.  An xhci_tt_info structure
1111          * will never be created for the HS root hub.
1112          */
1113         if (!udev->tt || !udev->tt->hub->parent) {
1114                 dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
1115         } else {
1116                 struct xhci_root_port_bw_info *rh_bw;
1117                 struct xhci_tt_bw_info *tt_bw;
1118
1119                 rh_bw = &xhci->rh_bw[port_num - 1];
1120                 /* Find the right TT. */
1121                 list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
1122                         if (tt_bw->slot_id != udev->tt->hub->slot_id)
1123                                 continue;
1124
1125                         if (!dev->udev->tt->multi ||
1126                                         (udev->tt->multi &&
1127                                          tt_bw->ttport == dev->udev->ttport)) {
1128                                 dev->bw_table = &tt_bw->bw_table;
1129                                 dev->tt_info = tt_bw;
1130                                 break;
1131                         }
1132                 }
1133                 if (!dev->tt_info)
1134                         xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
1135         }
1136
1137         /* Is this a LS/FS device under an external HS hub? */
1138         if (udev->tt && udev->tt->hub->parent) {
1139                 slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
1140                                                 (udev->ttport << 8));
1141                 if (udev->tt->multi)
1142                         slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1143         }
1144         xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1145         xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
1146
1147         /* Step 4 - ring already allocated */
1148         /* Step 5 */
1149         ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1150         /*
1151          * XXX: Not sure about wireless USB devices.
1152          */
1153         switch (udev->speed) {
1154         case USB_SPEED_SUPER:
1155                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512));
1156                 break;
1157         case USB_SPEED_HIGH:
1158         /* USB core guesses at a 64-byte max packet first for FS devices */
1159         case USB_SPEED_FULL:
1160                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64));
1161                 break;
1162         case USB_SPEED_LOW:
1163                 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8));
1164                 break;
1165         case USB_SPEED_WIRELESS:
1166                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1167                 return -EINVAL;
1168                 break;
1169         default:
1170                 /* New speed? */
1171                 BUG();
1172         }
1173         /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1174         ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3));
1175
1176         ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
1177                                    dev->eps[0].ring->cycle_state);
1178
1179         /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1180
1181         return 0;
1182 }
1183
1184 /*
1185  * Convert interval expressed as 2^(bInterval - 1) == interval into
1186  * straight exponent value 2^n == interval.
1187  *
1188  */
1189 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
1190                 struct usb_host_endpoint *ep)
1191 {
1192         unsigned int interval;
1193
1194         interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
1195         if (interval != ep->desc.bInterval - 1)
1196                 dev_warn(&udev->dev,
1197                          "ep %#x - rounding interval to %d %sframes\n",
1198                          ep->desc.bEndpointAddress,
1199                          1 << interval,
1200                          udev->speed == USB_SPEED_FULL ? "" : "micro");
1201
1202         if (udev->speed == USB_SPEED_FULL) {
1203                 /*
1204                  * Full speed isoc endpoints specify interval in frames,
1205                  * not microframes. We are using microframes everywhere,
1206                  * so adjust accordingly.
1207                  */
1208                 interval += 3;  /* 1 frame = 2^3 uframes */
1209         }
1210
1211         return interval;
1212 }
1213
1214 /*
1215  * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1216  * microframes, rounded down to nearest power of 2.
1217  */
1218 static unsigned int xhci_microframes_to_exponent(struct usb_device *udev,
1219                 struct usb_host_endpoint *ep, unsigned int desc_interval,
1220                 unsigned int min_exponent, unsigned int max_exponent)
1221 {
1222         unsigned int interval;
1223
1224         interval = fls(desc_interval) - 1;
1225         interval = clamp_val(interval, min_exponent, max_exponent);
1226         if ((1 << interval) != desc_interval)
1227                 dev_warn(&udev->dev,
1228                          "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1229                          ep->desc.bEndpointAddress,
1230                          1 << interval,
1231                          desc_interval);
1232
1233         return interval;
1234 }
1235
1236 static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
1237                 struct usb_host_endpoint *ep)
1238 {
1239         if (ep->desc.bInterval == 0)
1240                 return 0;
1241         return xhci_microframes_to_exponent(udev, ep,
1242                         ep->desc.bInterval, 0, 15);
1243 }
1244
1245
1246 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1247                 struct usb_host_endpoint *ep)
1248 {
1249         return xhci_microframes_to_exponent(udev, ep,
1250                         ep->desc.bInterval * 8, 3, 10);
1251 }
1252
1253 /* Return the polling or NAK interval.
1254  *
1255  * The polling interval is expressed in "microframes".  If xHCI's Interval field
1256  * is set to N, it will service the endpoint every 2^(Interval)*125us.
1257  *
1258  * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1259  * is set to 0.
1260  */
1261 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1262                 struct usb_host_endpoint *ep)
1263 {
1264         unsigned int interval = 0;
1265
1266         switch (udev->speed) {
1267         case USB_SPEED_HIGH:
1268                 /* Max NAK rate */
1269                 if (usb_endpoint_xfer_control(&ep->desc) ||
1270                     usb_endpoint_xfer_bulk(&ep->desc)) {
1271                         interval = xhci_parse_microframe_interval(udev, ep);
1272                         break;
1273                 }
1274                 /* Fall through - SS and HS isoc/int have same decoding */
1275
1276         case USB_SPEED_SUPER:
1277                 if (usb_endpoint_xfer_int(&ep->desc) ||
1278                     usb_endpoint_xfer_isoc(&ep->desc)) {
1279                         interval = xhci_parse_exponent_interval(udev, ep);
1280                 }
1281                 break;
1282
1283         case USB_SPEED_FULL:
1284                 if (usb_endpoint_xfer_isoc(&ep->desc)) {
1285                         interval = xhci_parse_exponent_interval(udev, ep);
1286                         break;
1287                 }
1288                 /*
1289                  * Fall through for interrupt endpoint interval decoding
1290                  * since it uses the same rules as low speed interrupt
1291                  * endpoints.
1292                  */
1293
1294         case USB_SPEED_LOW:
1295                 if (usb_endpoint_xfer_int(&ep->desc) ||
1296                     usb_endpoint_xfer_isoc(&ep->desc)) {
1297
1298                         interval = xhci_parse_frame_interval(udev, ep);
1299                 }
1300                 break;
1301
1302         default:
1303                 BUG();
1304         }
1305         return EP_INTERVAL(interval);
1306 }
1307
1308 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1309  * High speed endpoint descriptors can define "the number of additional
1310  * transaction opportunities per microframe", but that goes in the Max Burst
1311  * endpoint context field.
1312  */
1313 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1314                 struct usb_host_endpoint *ep)
1315 {
1316         if (udev->speed != USB_SPEED_SUPER ||
1317                         !usb_endpoint_xfer_isoc(&ep->desc))
1318                 return 0;
1319         return ep->ss_ep_comp.bmAttributes;
1320 }
1321
1322 static u32 xhci_get_endpoint_type(struct usb_device *udev,
1323                 struct usb_host_endpoint *ep)
1324 {
1325         int in;
1326         u32 type;
1327
1328         in = usb_endpoint_dir_in(&ep->desc);
1329         if (usb_endpoint_xfer_control(&ep->desc)) {
1330                 type = EP_TYPE(CTRL_EP);
1331         } else if (usb_endpoint_xfer_bulk(&ep->desc)) {
1332                 if (in)
1333                         type = EP_TYPE(BULK_IN_EP);
1334                 else
1335                         type = EP_TYPE(BULK_OUT_EP);
1336         } else if (usb_endpoint_xfer_isoc(&ep->desc)) {
1337                 if (in)
1338                         type = EP_TYPE(ISOC_IN_EP);
1339                 else
1340                         type = EP_TYPE(ISOC_OUT_EP);
1341         } else if (usb_endpoint_xfer_int(&ep->desc)) {
1342                 if (in)
1343                         type = EP_TYPE(INT_IN_EP);
1344                 else
1345                         type = EP_TYPE(INT_OUT_EP);
1346         } else {
1347                 BUG();
1348         }
1349         return type;
1350 }
1351
1352 /* Return the maximum endpoint service interval time (ESIT) payload.
1353  * Basically, this is the maxpacket size, multiplied by the burst size
1354  * and mult size.
1355  */
1356 static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci,
1357                 struct usb_device *udev,
1358                 struct usb_host_endpoint *ep)
1359 {
1360         int max_burst;
1361         int max_packet;
1362
1363         /* Only applies for interrupt or isochronous endpoints */
1364         if (usb_endpoint_xfer_control(&ep->desc) ||
1365                         usb_endpoint_xfer_bulk(&ep->desc))
1366                 return 0;
1367
1368         if (udev->speed == USB_SPEED_SUPER)
1369                 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1370
1371         max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1372         max_burst = (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11;
1373         /* A 0 in max burst means 1 transfer per ESIT */
1374         return max_packet * (max_burst + 1);
1375 }
1376
1377 /* Set up an endpoint with one ring segment.  Do not allocate stream rings.
1378  * Drivers will have to call usb_alloc_streams() to do that.
1379  */
1380 int xhci_endpoint_init(struct xhci_hcd *xhci,
1381                 struct xhci_virt_device *virt_dev,
1382                 struct usb_device *udev,
1383                 struct usb_host_endpoint *ep,
1384                 gfp_t mem_flags)
1385 {
1386         unsigned int ep_index;
1387         struct xhci_ep_ctx *ep_ctx;
1388         struct xhci_ring *ep_ring;
1389         unsigned int max_packet;
1390         unsigned int max_burst;
1391         enum xhci_ring_type type;
1392         u32 max_esit_payload;
1393
1394         ep_index = xhci_get_endpoint_index(&ep->desc);
1395         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1396
1397         type = usb_endpoint_type(&ep->desc);
1398         /* Set up the endpoint ring */
1399         virt_dev->eps[ep_index].new_ring =
1400                 xhci_ring_alloc(xhci, 2, 1, type, mem_flags);
1401         if (!virt_dev->eps[ep_index].new_ring) {
1402                 /* Attempt to use the ring cache */
1403                 if (virt_dev->num_rings_cached == 0)
1404                         return -ENOMEM;
1405                 virt_dev->eps[ep_index].new_ring =
1406                         virt_dev->ring_cache[virt_dev->num_rings_cached];
1407                 virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
1408                 virt_dev->num_rings_cached--;
1409                 xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring,
1410                                         1, type);
1411         }
1412         virt_dev->eps[ep_index].skip = false;
1413         ep_ring = virt_dev->eps[ep_index].new_ring;
1414         ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state);
1415
1416         ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep)
1417                                       | EP_MULT(xhci_get_endpoint_mult(udev, ep)));
1418
1419         /* FIXME dig Mult and streams info out of ep companion desc */
1420
1421         /* Allow 3 retries for everything but isoc;
1422          * CErr shall be set to 0 for Isoch endpoints.
1423          */
1424         if (!usb_endpoint_xfer_isoc(&ep->desc))
1425                 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(3));
1426         else
1427                 ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(0));
1428
1429         ep_ctx->ep_info2 |= cpu_to_le32(xhci_get_endpoint_type(udev, ep));
1430
1431         /* Set the max packet size and max burst */
1432         max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1433         max_burst = 0;
1434         switch (udev->speed) {
1435         case USB_SPEED_SUPER:
1436                 /* dig out max burst from ep companion desc */
1437                 max_burst = ep->ss_ep_comp.bMaxBurst;
1438                 break;
1439         case USB_SPEED_HIGH:
1440                 /* Some devices get this wrong */
1441                 if (usb_endpoint_xfer_bulk(&ep->desc))
1442                         max_packet = 512;
1443                 /* bits 11:12 specify the number of additional transaction
1444                  * opportunities per microframe (USB 2.0, section 9.6.6)
1445                  */
1446                 if (usb_endpoint_xfer_isoc(&ep->desc) ||
1447                                 usb_endpoint_xfer_int(&ep->desc)) {
1448                         max_burst = (usb_endpoint_maxp(&ep->desc)
1449                                      & 0x1800) >> 11;
1450                 }
1451                 break;
1452         case USB_SPEED_FULL:
1453         case USB_SPEED_LOW:
1454                 break;
1455         default:
1456                 BUG();
1457         }
1458         ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet) |
1459                         MAX_BURST(max_burst));
1460         max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep);
1461         ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload));
1462
1463         /*
1464          * XXX no idea how to calculate the average TRB buffer length for bulk
1465          * endpoints, as the driver gives us no clue how big each scatter gather
1466          * list entry (or buffer) is going to be.
1467          *
1468          * For isochronous and interrupt endpoints, we set it to the max
1469          * available, until we have new API in the USB core to allow drivers to
1470          * declare how much bandwidth they actually need.
1471          *
1472          * Normally, it would be calculated by taking the total of the buffer
1473          * lengths in the TD and then dividing by the number of TRBs in a TD,
1474          * including link TRBs, No-op TRBs, and Event data TRBs.  Since we don't
1475          * use Event Data TRBs, and we don't chain in a link TRB on short
1476          * transfers, we're basically dividing by 1.
1477          *
1478          * xHCI 1.0 specification indicates that the Average TRB Length should
1479          * be set to 8 for control endpoints.
1480          */
1481         if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100)
1482                 ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
1483         else
1484                 ep_ctx->tx_info |=
1485                          cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload));
1486
1487         /* FIXME Debug endpoint context */
1488         return 0;
1489 }
1490
1491 void xhci_endpoint_zero(struct xhci_hcd *xhci,
1492                 struct xhci_virt_device *virt_dev,
1493                 struct usb_host_endpoint *ep)
1494 {
1495         unsigned int ep_index;
1496         struct xhci_ep_ctx *ep_ctx;
1497
1498         ep_index = xhci_get_endpoint_index(&ep->desc);
1499         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1500
1501         ep_ctx->ep_info = 0;
1502         ep_ctx->ep_info2 = 0;
1503         ep_ctx->deq = 0;
1504         ep_ctx->tx_info = 0;
1505         /* Don't free the endpoint ring until the set interface or configuration
1506          * request succeeds.
1507          */
1508 }
1509
1510 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
1511 {
1512         bw_info->ep_interval = 0;
1513         bw_info->mult = 0;
1514         bw_info->num_packets = 0;
1515         bw_info->max_packet_size = 0;
1516         bw_info->type = 0;
1517         bw_info->max_esit_payload = 0;
1518 }
1519
1520 void xhci_update_bw_info(struct xhci_hcd *xhci,
1521                 struct xhci_container_ctx *in_ctx,
1522                 struct xhci_input_control_ctx *ctrl_ctx,
1523                 struct xhci_virt_device *virt_dev)
1524 {
1525         struct xhci_bw_info *bw_info;
1526         struct xhci_ep_ctx *ep_ctx;
1527         unsigned int ep_type;
1528         int i;
1529
1530         for (i = 1; i < 31; ++i) {
1531                 bw_info = &virt_dev->eps[i].bw_info;
1532
1533                 /* We can't tell what endpoint type is being dropped, but
1534                  * unconditionally clearing the bandwidth info for non-periodic
1535                  * endpoints should be harmless because the info will never be
1536                  * set in the first place.
1537                  */
1538                 if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
1539                         /* Dropped endpoint */
1540                         xhci_clear_endpoint_bw_info(bw_info);
1541                         continue;
1542                 }
1543
1544                 if (EP_IS_ADDED(ctrl_ctx, i)) {
1545                         ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
1546                         ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
1547
1548                         /* Ignore non-periodic endpoints */
1549                         if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
1550                                         ep_type != ISOC_IN_EP &&
1551                                         ep_type != INT_IN_EP)
1552                                 continue;
1553
1554                         /* Added or changed endpoint */
1555                         bw_info->ep_interval = CTX_TO_EP_INTERVAL(
1556                                         le32_to_cpu(ep_ctx->ep_info));
1557                         /* Number of packets and mult are zero-based in the
1558                          * input context, but we want one-based for the
1559                          * interval table.
1560                          */
1561                         bw_info->mult = CTX_TO_EP_MULT(
1562                                         le32_to_cpu(ep_ctx->ep_info)) + 1;
1563                         bw_info->num_packets = CTX_TO_MAX_BURST(
1564                                         le32_to_cpu(ep_ctx->ep_info2)) + 1;
1565                         bw_info->max_packet_size = MAX_PACKET_DECODED(
1566                                         le32_to_cpu(ep_ctx->ep_info2));
1567                         bw_info->type = ep_type;
1568                         bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
1569                                         le32_to_cpu(ep_ctx->tx_info));
1570                 }
1571         }
1572 }
1573
1574 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1575  * Useful when you want to change one particular aspect of the endpoint and then
1576  * issue a configure endpoint command.
1577  */
1578 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1579                 struct xhci_container_ctx *in_ctx,
1580                 struct xhci_container_ctx *out_ctx,
1581                 unsigned int ep_index)
1582 {
1583         struct xhci_ep_ctx *out_ep_ctx;
1584         struct xhci_ep_ctx *in_ep_ctx;
1585
1586         out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1587         in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1588
1589         in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1590         in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1591         in_ep_ctx->deq = out_ep_ctx->deq;
1592         in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1593 }
1594
1595 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1596  * Useful when you want to change one particular aspect of the endpoint and then
1597  * issue a configure endpoint command.  Only the context entries field matters,
1598  * but we'll copy the whole thing anyway.
1599  */
1600 void xhci_slot_copy(struct xhci_hcd *xhci,
1601                 struct xhci_container_ctx *in_ctx,
1602                 struct xhci_container_ctx *out_ctx)
1603 {
1604         struct xhci_slot_ctx *in_slot_ctx;
1605         struct xhci_slot_ctx *out_slot_ctx;
1606
1607         in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1608         out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1609
1610         in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1611         in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1612         in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1613         in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1614 }
1615
1616 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1617 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1618 {
1619         int i;
1620         struct device *dev = xhci_to_hcd(xhci)->self.controller;
1621         int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1622
1623         xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp);
1624
1625         if (!num_sp)
1626                 return 0;
1627
1628         xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
1629         if (!xhci->scratchpad)
1630                 goto fail_sp;
1631
1632         xhci->scratchpad->sp_array = dma_alloc_coherent(dev,
1633                                      num_sp * sizeof(u64),
1634                                      &xhci->scratchpad->sp_dma, flags);
1635         if (!xhci->scratchpad->sp_array)
1636                 goto fail_sp2;
1637
1638         xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
1639         if (!xhci->scratchpad->sp_buffers)
1640                 goto fail_sp3;
1641
1642         xhci->scratchpad->sp_dma_buffers =
1643                 kzalloc(sizeof(dma_addr_t) * num_sp, flags);
1644
1645         if (!xhci->scratchpad->sp_dma_buffers)
1646                 goto fail_sp4;
1647
1648         xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1649         for (i = 0; i < num_sp; i++) {
1650                 dma_addr_t dma;
1651                 void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma,
1652                                 flags);
1653                 if (!buf)
1654                         goto fail_sp5;
1655
1656                 xhci->scratchpad->sp_array[i] = dma;
1657                 xhci->scratchpad->sp_buffers[i] = buf;
1658                 xhci->scratchpad->sp_dma_buffers[i] = dma;
1659         }
1660
1661         return 0;
1662
1663  fail_sp5:
1664         for (i = i - 1; i >= 0; i--) {
1665                 dma_free_coherent(dev, xhci->page_size,
1666                                     xhci->scratchpad->sp_buffers[i],
1667                                     xhci->scratchpad->sp_dma_buffers[i]);
1668         }
1669         kfree(xhci->scratchpad->sp_dma_buffers);
1670
1671  fail_sp4:
1672         kfree(xhci->scratchpad->sp_buffers);
1673
1674  fail_sp3:
1675         dma_free_coherent(dev, num_sp * sizeof(u64),
1676                             xhci->scratchpad->sp_array,
1677                             xhci->scratchpad->sp_dma);
1678
1679  fail_sp2:
1680         kfree(xhci->scratchpad);
1681         xhci->scratchpad = NULL;
1682
1683  fail_sp:
1684         return -ENOMEM;
1685 }
1686
1687 static void scratchpad_free(struct xhci_hcd *xhci)
1688 {
1689         int num_sp;
1690         int i;
1691         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1692
1693         if (!xhci->scratchpad)
1694                 return;
1695
1696         num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1697
1698         for (i = 0; i < num_sp; i++) {
1699                 dma_free_coherent(&pdev->dev, xhci->page_size,
1700                                     xhci->scratchpad->sp_buffers[i],
1701                                     xhci->scratchpad->sp_dma_buffers[i]);
1702         }
1703         kfree(xhci->scratchpad->sp_dma_buffers);
1704         kfree(xhci->scratchpad->sp_buffers);
1705         dma_free_coherent(&pdev->dev, num_sp * sizeof(u64),
1706                             xhci->scratchpad->sp_array,
1707                             xhci->scratchpad->sp_dma);
1708         kfree(xhci->scratchpad);
1709         xhci->scratchpad = NULL;
1710 }
1711
1712 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1713                 bool allocate_in_ctx, bool allocate_completion,
1714                 gfp_t mem_flags)
1715 {
1716         struct xhci_command *command;
1717
1718         command = kzalloc(sizeof(*command), mem_flags);
1719         if (!command)
1720                 return NULL;
1721
1722         if (allocate_in_ctx) {
1723                 command->in_ctx =
1724                         xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1725                                         mem_flags);
1726                 if (!command->in_ctx) {
1727                         kfree(command);
1728                         return NULL;
1729                 }
1730         }
1731
1732         if (allocate_completion) {
1733                 command->completion =
1734                         kzalloc(sizeof(struct completion), mem_flags);
1735                 if (!command->completion) {
1736                         xhci_free_container_ctx(xhci, command->in_ctx);
1737                         kfree(command);
1738                         return NULL;
1739                 }
1740                 init_completion(command->completion);
1741         }
1742
1743         command->status = 0;
1744         INIT_LIST_HEAD(&command->cmd_list);
1745         return command;
1746 }
1747
1748 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv)
1749 {
1750         if (urb_priv) {
1751                 kfree(urb_priv->td[0]);
1752                 kfree(urb_priv);
1753         }
1754 }
1755
1756 void xhci_free_command(struct xhci_hcd *xhci,
1757                 struct xhci_command *command)
1758 {
1759         xhci_free_container_ctx(xhci,
1760                         command->in_ctx);
1761         kfree(command->completion);
1762         kfree(command);
1763 }
1764
1765 void xhci_mem_cleanup(struct xhci_hcd *xhci)
1766 {
1767         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1768         struct dev_info *dev_info, *next;
1769         struct xhci_cd  *cur_cd, *next_cd;
1770         unsigned long   flags;
1771         int size;
1772         int i, j, num_ports;
1773
1774         /* Free the Event Ring Segment Table and the actual Event Ring */
1775         size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
1776         if (xhci->erst.entries)
1777                 dma_free_coherent(&pdev->dev, size,
1778                                 xhci->erst.entries, xhci->erst.erst_dma_addr);
1779         xhci->erst.entries = NULL;
1780         xhci_dbg(xhci, "Freed ERST\n");
1781         if (xhci->event_ring)
1782                 xhci_ring_free(xhci, xhci->event_ring);
1783         xhci->event_ring = NULL;
1784         xhci_dbg(xhci, "Freed event ring\n");
1785
1786         if (xhci->lpm_command)
1787                 xhci_free_command(xhci, xhci->lpm_command);
1788         xhci->cmd_ring_reserved_trbs = 0;
1789         if (xhci->cmd_ring)
1790                 xhci_ring_free(xhci, xhci->cmd_ring);
1791         xhci->cmd_ring = NULL;
1792         xhci_dbg(xhci, "Freed command ring\n");
1793         list_for_each_entry_safe(cur_cd, next_cd,
1794                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1795                 list_del(&cur_cd->cancel_cmd_list);
1796                 kfree(cur_cd);
1797         }
1798
1799         for (i = 1; i < MAX_HC_SLOTS; ++i)
1800                 xhci_free_virt_device(xhci, i);
1801
1802         if (xhci->segment_pool)
1803                 dma_pool_destroy(xhci->segment_pool);
1804         xhci->segment_pool = NULL;
1805         xhci_dbg(xhci, "Freed segment pool\n");
1806
1807         if (xhci->device_pool)
1808                 dma_pool_destroy(xhci->device_pool);
1809         xhci->device_pool = NULL;
1810         xhci_dbg(xhci, "Freed device context pool\n");
1811
1812         if (xhci->small_streams_pool)
1813                 dma_pool_destroy(xhci->small_streams_pool);
1814         xhci->small_streams_pool = NULL;
1815         xhci_dbg(xhci, "Freed small stream array pool\n");
1816
1817         if (xhci->medium_streams_pool)
1818                 dma_pool_destroy(xhci->medium_streams_pool);
1819         xhci->medium_streams_pool = NULL;
1820         xhci_dbg(xhci, "Freed medium stream array pool\n");
1821
1822         if (xhci->dcbaa)
1823                 dma_free_coherent(&pdev->dev, sizeof(*xhci->dcbaa),
1824                                 xhci->dcbaa, xhci->dcbaa->dma);
1825         xhci->dcbaa = NULL;
1826
1827         scratchpad_free(xhci);
1828
1829         spin_lock_irqsave(&xhci->lock, flags);
1830         list_for_each_entry_safe(dev_info, next, &xhci->lpm_failed_devs, list) {
1831                 list_del(&dev_info->list);
1832                 kfree(dev_info);
1833         }
1834         spin_unlock_irqrestore(&xhci->lock, flags);
1835
1836         if (!xhci->rh_bw)
1837                 goto no_bw;
1838
1839         num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1840         for (i = 0; i < num_ports; i++) {
1841                 struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table;
1842                 for (j = 0; j < XHCI_MAX_INTERVAL; j++) {
1843                         struct list_head *ep = &bwt->interval_bw[j].endpoints;
1844                         while (!list_empty(ep))
1845                                 list_del_init(ep->next);
1846                 }
1847         }
1848
1849         for (i = 0; i < num_ports; i++) {
1850                 struct xhci_tt_bw_info *tt, *n;
1851                 list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) {
1852                         list_del(&tt->tt_list);
1853                         kfree(tt);
1854                 }
1855         }
1856
1857 no_bw:
1858         xhci->num_usb2_ports = 0;
1859         xhci->num_usb3_ports = 0;
1860         xhci->num_active_eps = 0;
1861         kfree(xhci->usb2_ports);
1862         kfree(xhci->usb3_ports);
1863         kfree(xhci->port_array);
1864         kfree(xhci->rh_bw);
1865         kfree(xhci->ext_caps);
1866
1867         xhci->page_size = 0;
1868         xhci->page_shift = 0;
1869         xhci->bus_state[0].bus_suspended = 0;
1870         xhci->bus_state[1].bus_suspended = 0;
1871 }
1872
1873 static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
1874                 struct xhci_segment *input_seg,
1875                 union xhci_trb *start_trb,
1876                 union xhci_trb *end_trb,
1877                 dma_addr_t input_dma,
1878                 struct xhci_segment *result_seg,
1879                 char *test_name, int test_number)
1880 {
1881         unsigned long long start_dma;
1882         unsigned long long end_dma;
1883         struct xhci_segment *seg;
1884
1885         start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
1886         end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
1887
1888         seg = trb_in_td(input_seg, start_trb, end_trb, input_dma);
1889         if (seg != result_seg) {
1890                 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
1891                                 test_name, test_number);
1892                 xhci_warn(xhci, "Tested TRB math w/ seg %p and "
1893                                 "input DMA 0x%llx\n",
1894                                 input_seg,
1895                                 (unsigned long long) input_dma);
1896                 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
1897                                 "ending TRB %p (0x%llx DMA)\n",
1898                                 start_trb, start_dma,
1899                                 end_trb, end_dma);
1900                 xhci_warn(xhci, "Expected seg %p, got seg %p\n",
1901                                 result_seg, seg);
1902                 return -1;
1903         }
1904         return 0;
1905 }
1906
1907 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1908 static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags)
1909 {
1910         struct {
1911                 dma_addr_t              input_dma;
1912                 struct xhci_segment     *result_seg;
1913         } simple_test_vector [] = {
1914                 /* A zeroed DMA field should fail */
1915                 { 0, NULL },
1916                 /* One TRB before the ring start should fail */
1917                 { xhci->event_ring->first_seg->dma - 16, NULL },
1918                 /* One byte before the ring start should fail */
1919                 { xhci->event_ring->first_seg->dma - 1, NULL },
1920                 /* Starting TRB should succeed */
1921                 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
1922                 /* Ending TRB should succeed */
1923                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
1924                         xhci->event_ring->first_seg },
1925                 /* One byte after the ring end should fail */
1926                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
1927                 /* One TRB after the ring end should fail */
1928                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
1929                 /* An address of all ones should fail */
1930                 { (dma_addr_t) (~0), NULL },
1931         };
1932         struct {
1933                 struct xhci_segment     *input_seg;
1934                 union xhci_trb          *start_trb;
1935                 union xhci_trb          *end_trb;
1936                 dma_addr_t              input_dma;
1937                 struct xhci_segment     *result_seg;
1938         } complex_test_vector [] = {
1939                 /* Test feeding a valid DMA address from a different ring */
1940                 {       .input_seg = xhci->event_ring->first_seg,
1941                         .start_trb = xhci->event_ring->first_seg->trbs,
1942                         .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1943                         .input_dma = xhci->cmd_ring->first_seg->dma,
1944                         .result_seg = NULL,
1945                 },
1946                 /* Test feeding a valid end TRB from a different ring */
1947                 {       .input_seg = xhci->event_ring->first_seg,
1948                         .start_trb = xhci->event_ring->first_seg->trbs,
1949                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1950                         .input_dma = xhci->cmd_ring->first_seg->dma,
1951                         .result_seg = NULL,
1952                 },
1953                 /* Test feeding a valid start and end TRB from a different ring */
1954                 {       .input_seg = xhci->event_ring->first_seg,
1955                         .start_trb = xhci->cmd_ring->first_seg->trbs,
1956                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1957                         .input_dma = xhci->cmd_ring->first_seg->dma,
1958                         .result_seg = NULL,
1959                 },
1960                 /* TRB in this ring, but after this TD */
1961                 {       .input_seg = xhci->event_ring->first_seg,
1962                         .start_trb = &xhci->event_ring->first_seg->trbs[0],
1963                         .end_trb = &xhci->event_ring->first_seg->trbs[3],
1964                         .input_dma = xhci->event_ring->first_seg->dma + 4*16,
1965                         .result_seg = NULL,
1966                 },
1967                 /* TRB in this ring, but before this TD */
1968                 {       .input_seg = xhci->event_ring->first_seg,
1969                         .start_trb = &xhci->event_ring->first_seg->trbs[3],
1970                         .end_trb = &xhci->event_ring->first_seg->trbs[6],
1971                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1972                         .result_seg = NULL,
1973                 },
1974                 /* TRB in this ring, but after this wrapped TD */
1975                 {       .input_seg = xhci->event_ring->first_seg,
1976                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1977                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1978                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1979                         .result_seg = NULL,
1980                 },
1981                 /* TRB in this ring, but before this wrapped TD */
1982                 {       .input_seg = xhci->event_ring->first_seg,
1983                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1984                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1985                         .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
1986                         .result_seg = NULL,
1987                 },
1988                 /* TRB not in this ring, and we have a wrapped TD */
1989                 {       .input_seg = xhci->event_ring->first_seg,
1990                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1991                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1992                         .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
1993                         .result_seg = NULL,
1994                 },
1995         };
1996
1997         unsigned int num_tests;
1998         int i, ret;
1999
2000         num_tests = ARRAY_SIZE(simple_test_vector);
2001         for (i = 0; i < num_tests; i++) {
2002                 ret = xhci_test_trb_in_td(xhci,
2003                                 xhci->event_ring->first_seg,
2004                                 xhci->event_ring->first_seg->trbs,
2005                                 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
2006                                 simple_test_vector[i].input_dma,
2007                                 simple_test_vector[i].result_seg,
2008                                 "Simple", i);
2009                 if (ret < 0)
2010                         return ret;
2011         }
2012
2013         num_tests = ARRAY_SIZE(complex_test_vector);
2014         for (i = 0; i < num_tests; i++) {
2015                 ret = xhci_test_trb_in_td(xhci,
2016                                 complex_test_vector[i].input_seg,
2017                                 complex_test_vector[i].start_trb,
2018                                 complex_test_vector[i].end_trb,
2019                                 complex_test_vector[i].input_dma,
2020                                 complex_test_vector[i].result_seg,
2021                                 "Complex", i);
2022                 if (ret < 0)
2023                         return ret;
2024         }
2025         xhci_dbg(xhci, "TRB math tests passed.\n");
2026         return 0;
2027 }
2028
2029 static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
2030 {
2031         u64 temp;
2032         dma_addr_t deq;
2033
2034         deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2035                         xhci->event_ring->dequeue);
2036         if (deq == 0 && !in_interrupt())
2037                 xhci_warn(xhci, "WARN something wrong with SW event ring "
2038                                 "dequeue ptr.\n");
2039         /* Update HC event ring dequeue pointer */
2040         temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2041         temp &= ERST_PTR_MASK;
2042         /* Don't clear the EHB bit (which is RW1C) because
2043          * there might be more events to service.
2044          */
2045         temp &= ~ERST_EHB;
2046         xhci_dbg(xhci, "// Write event ring dequeue pointer, "
2047                         "preserving EHB bit\n");
2048         xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
2049                         &xhci->ir_set->erst_dequeue);
2050 }
2051
2052 static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
2053                 __le32 __iomem *addr, u8 major_revision, int max_caps)
2054 {
2055         u32 temp, port_offset, port_count;
2056         int i;
2057
2058         if (major_revision > 0x03) {
2059                 xhci_warn(xhci, "Ignoring unknown port speed, "
2060                                 "Ext Cap %p, revision = 0x%x\n",
2061                                 addr, major_revision);
2062                 /* Ignoring port protocol we can't understand. FIXME */
2063                 return;
2064         }
2065
2066         /* Port offset and count in the third dword, see section 7.2 */
2067         temp = xhci_readl(xhci, addr + 2);
2068         port_offset = XHCI_EXT_PORT_OFF(temp);
2069         port_count = XHCI_EXT_PORT_COUNT(temp);
2070         xhci_dbg(xhci, "Ext Cap %p, port offset = %u, "
2071                         "count = %u, revision = 0x%x\n",
2072                         addr, port_offset, port_count, major_revision);
2073         /* Port count includes the current port offset */
2074         if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
2075                 /* WTF? "Valid values are ‘1’ to MaxPorts" */
2076                 return;
2077
2078         /* cache usb2 port capabilities */
2079         if (major_revision < 0x03 && xhci->num_ext_caps < max_caps)
2080                 xhci->ext_caps[xhci->num_ext_caps++] = temp;
2081
2082         /* Check the host's USB2 LPM capability */
2083         if ((xhci->hci_version == 0x96) && (major_revision != 0x03) &&
2084                         (temp & XHCI_L1C)) {
2085                 xhci_dbg(xhci, "xHCI 0.96: support USB2 software lpm\n");
2086                 xhci->sw_lpm_support = 1;
2087         }
2088
2089         if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) {
2090                 xhci_dbg(xhci, "xHCI 1.0: support USB2 software lpm\n");
2091                 xhci->sw_lpm_support = 1;
2092                 if (temp & XHCI_HLC) {
2093                         xhci_dbg(xhci, "xHCI 1.0: support USB2 hardware lpm\n");
2094                         xhci->hw_lpm_support = 1;
2095                 }
2096         }
2097
2098         port_offset--;
2099         for (i = port_offset; i < (port_offset + port_count); i++) {
2100                 /* Duplicate entry.  Ignore the port if the revisions differ. */
2101                 if (xhci->port_array[i] != 0) {
2102                         xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
2103                                         " port %u\n", addr, i);
2104                         xhci_warn(xhci, "Port was marked as USB %u, "
2105                                         "duplicated as USB %u\n",
2106                                         xhci->port_array[i], major_revision);
2107                         /* Only adjust the roothub port counts if we haven't
2108                          * found a similar duplicate.
2109                          */
2110                         if (xhci->port_array[i] != major_revision &&
2111                                 xhci->port_array[i] != DUPLICATE_ENTRY) {
2112                                 if (xhci->port_array[i] == 0x03)
2113                                         xhci->num_usb3_ports--;
2114                                 else
2115                                         xhci->num_usb2_ports--;
2116                                 xhci->port_array[i] = DUPLICATE_ENTRY;
2117                         }
2118                         /* FIXME: Should we disable the port? */
2119                         continue;
2120                 }
2121                 xhci->port_array[i] = major_revision;
2122                 if (major_revision == 0x03)
2123                         xhci->num_usb3_ports++;
2124                 else
2125                         xhci->num_usb2_ports++;
2126         }
2127         /* FIXME: Should we disable ports not in the Extended Capabilities? */
2128 }
2129
2130 /*
2131  * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2132  * specify what speeds each port is supposed to be.  We can't count on the port
2133  * speed bits in the PORTSC register being correct until a device is connected,
2134  * but we need to set up the two fake roothubs with the correct number of USB
2135  * 3.0 and USB 2.0 ports at host controller initialization time.
2136  */
2137 static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
2138 {
2139         __le32 __iomem *addr, *tmp_addr;
2140         u32 offset, tmp_offset;
2141         unsigned int num_ports;
2142         int i, j, port_index;
2143         int cap_count = 0;
2144
2145         addr = &xhci->cap_regs->hcc_params;
2146         offset = XHCI_HCC_EXT_CAPS(xhci_readl(xhci, addr));
2147         if (offset == 0) {
2148                 xhci_err(xhci, "No Extended Capability registers, "
2149                                 "unable to set up roothub.\n");
2150                 return -ENODEV;
2151         }
2152
2153         num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
2154         xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags);
2155         if (!xhci->port_array)
2156                 return -ENOMEM;
2157
2158         xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags);
2159         if (!xhci->rh_bw)
2160                 return -ENOMEM;
2161         for (i = 0; i < num_ports; i++) {
2162                 struct xhci_interval_bw_table *bw_table;
2163
2164                 INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
2165                 bw_table = &xhci->rh_bw[i].bw_table;
2166                 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
2167                         INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
2168         }
2169
2170         /*
2171          * For whatever reason, the first capability offset is from the
2172          * capability register base, not from the HCCPARAMS register.
2173          * See section 5.3.6 for offset calculation.
2174          */
2175         addr = &xhci->cap_regs->hc_capbase + offset;
2176
2177         tmp_addr = addr;
2178         tmp_offset = offset;
2179
2180         /* count extended protocol capability entries for later caching */
2181         do {
2182                 u32 cap_id;
2183                 cap_id = xhci_readl(xhci, tmp_addr);
2184                 if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
2185                         cap_count++;
2186                 tmp_offset = XHCI_EXT_CAPS_NEXT(cap_id);
2187                 tmp_addr += tmp_offset;
2188         } while (tmp_offset);
2189
2190         xhci->ext_caps = kzalloc(sizeof(*xhci->ext_caps) * cap_count, flags);
2191         if (!xhci->ext_caps)
2192                 return -ENOMEM;
2193
2194         while (1) {
2195                 u32 cap_id;
2196
2197                 cap_id = xhci_readl(xhci, addr);
2198                 if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
2199                         xhci_add_in_port(xhci, num_ports, addr,
2200                                         (u8) XHCI_EXT_PORT_MAJOR(cap_id),
2201                                         cap_count);
2202                 offset = XHCI_EXT_CAPS_NEXT(cap_id);
2203                 if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports)
2204                                 == num_ports)
2205                         break;
2206                 /*
2207                  * Once you're into the Extended Capabilities, the offset is
2208                  * always relative to the register holding the offset.
2209                  */
2210                 addr += offset;
2211         }
2212
2213         if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) {
2214                 xhci_warn(xhci, "No ports on the roothubs?\n");
2215                 return -ENODEV;
2216         }
2217         xhci_dbg(xhci, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n",
2218                         xhci->num_usb2_ports, xhci->num_usb3_ports);
2219
2220         /* Place limits on the number of roothub ports so that the hub
2221          * descriptors aren't longer than the USB core will allocate.
2222          */
2223         if (xhci->num_usb3_ports > 15) {
2224                 xhci_dbg(xhci, "Limiting USB 3.0 roothub ports to 15.\n");
2225                 xhci->num_usb3_ports = 15;
2226         }
2227         if (xhci->num_usb2_ports > USB_MAXCHILDREN) {
2228                 xhci_dbg(xhci, "Limiting USB 2.0 roothub ports to %u.\n",
2229                                 USB_MAXCHILDREN);
2230                 xhci->num_usb2_ports = USB_MAXCHILDREN;
2231         }
2232
2233         /*
2234          * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2235          * Not sure how the USB core will handle a hub with no ports...
2236          */
2237         if (xhci->num_usb2_ports) {
2238                 xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)*
2239                                 xhci->num_usb2_ports, flags);
2240                 if (!xhci->usb2_ports)
2241                         return -ENOMEM;
2242
2243                 port_index = 0;
2244                 for (i = 0; i < num_ports; i++) {
2245                         if (xhci->port_array[i] == 0x03 ||
2246                                         xhci->port_array[i] == 0 ||
2247                                         xhci->port_array[i] == DUPLICATE_ENTRY)
2248                                 continue;
2249
2250                         xhci->usb2_ports[port_index] =
2251                                 &xhci->op_regs->port_status_base +
2252                                 NUM_PORT_REGS*i;
2253                         xhci_dbg(xhci, "USB 2.0 port at index %u, "
2254                                         "addr = %p\n", i,
2255                                         xhci->usb2_ports[port_index]);
2256                         port_index++;
2257                         if (port_index == xhci->num_usb2_ports)
2258                                 break;
2259                 }
2260         }
2261         if (xhci->num_usb3_ports) {
2262                 xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)*
2263                                 xhci->num_usb3_ports, flags);
2264                 if (!xhci->usb3_ports)
2265                         return -ENOMEM;
2266
2267                 port_index = 0;
2268                 for (i = 0; i < num_ports; i++)
2269                         if (xhci->port_array[i] == 0x03) {
2270                                 xhci->usb3_ports[port_index] =
2271                                         &xhci->op_regs->port_status_base +
2272                                         NUM_PORT_REGS*i;
2273                                 xhci_dbg(xhci, "USB 3.0 port at index %u, "
2274                                                 "addr = %p\n", i,
2275                                                 xhci->usb3_ports[port_index]);
2276                                 port_index++;
2277                                 if (port_index == xhci->num_usb3_ports)
2278                                         break;
2279                         }
2280         }
2281         return 0;
2282 }
2283
2284 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2285 {
2286         dma_addr_t      dma;
2287         struct device   *dev = xhci_to_hcd(xhci)->self.controller;
2288         unsigned int    val, val2;
2289         u64             val_64;
2290         struct xhci_segment     *seg;
2291         u32 page_size, temp;
2292         int i;
2293
2294         INIT_LIST_HEAD(&xhci->lpm_failed_devs);
2295         INIT_LIST_HEAD(&xhci->cancel_cmd_list);
2296
2297         page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
2298         xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
2299         for (i = 0; i < 16; i++) {
2300                 if ((0x1 & page_size) != 0)
2301                         break;
2302                 page_size = page_size >> 1;
2303         }
2304         if (i < 16)
2305                 xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
2306         else
2307                 xhci_warn(xhci, "WARN: no supported page size\n");
2308         /* Use 4K pages, since that's common and the minimum the HC supports */
2309         xhci->page_shift = 12;
2310         xhci->page_size = 1 << xhci->page_shift;
2311         xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
2312
2313         /*
2314          * Program the Number of Device Slots Enabled field in the CONFIG
2315          * register with the max value of slots the HC can handle.
2316          */
2317         val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
2318         xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
2319                         (unsigned int) val);
2320         val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
2321         val |= (val2 & ~HCS_SLOTS_MASK);
2322         xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
2323                         (unsigned int) val);
2324         xhci_writel(xhci, val, &xhci->op_regs->config_reg);
2325
2326         /*
2327          * Section 5.4.8 - doorbell array must be
2328          * "physically contiguous and 64-byte (cache line) aligned".
2329          */
2330         xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma,
2331                         GFP_KERNEL);
2332         if (!xhci->dcbaa)
2333                 goto fail;
2334         memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
2335         xhci->dcbaa->dma = dma;
2336         xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
2337                         (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
2338         xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
2339
2340         /*
2341          * Initialize the ring segment pool.  The ring must be a contiguous
2342          * structure comprised of TRBs.  The TRBs must be 16 byte aligned,
2343          * however, the command ring segment needs 64-byte aligned segments,
2344          * so we pick the greater alignment need.
2345          */
2346         xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2347                         TRB_SEGMENT_SIZE, 64, xhci->page_size);
2348
2349         /* See Table 46 and Note on Figure 55 */
2350         xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
2351                         2112, 64, xhci->page_size);
2352         if (!xhci->segment_pool || !xhci->device_pool)
2353                 goto fail;
2354
2355         /* Linear stream context arrays don't have any boundary restrictions,
2356          * and only need to be 16-byte aligned.
2357          */
2358         xhci->small_streams_pool =
2359                 dma_pool_create("xHCI 256 byte stream ctx arrays",
2360                         dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
2361         xhci->medium_streams_pool =
2362                 dma_pool_create("xHCI 1KB stream ctx arrays",
2363                         dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
2364         /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2365          * will be allocated with dma_alloc_coherent()
2366          */
2367
2368         if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
2369                 goto fail;
2370
2371         /* Set up the command ring to have one segments for now. */
2372         xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, flags);
2373         if (!xhci->cmd_ring)
2374                 goto fail;
2375         xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
2376         xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
2377                         (unsigned long long)xhci->cmd_ring->first_seg->dma);
2378
2379         /* Set the address in the Command Ring Control register */
2380         val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2381         val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2382                 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2383                 xhci->cmd_ring->cycle_state;
2384         xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val);
2385         xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2386         xhci_dbg_cmd_ptrs(xhci);
2387
2388         xhci->lpm_command = xhci_alloc_command(xhci, true, true, flags);
2389         if (!xhci->lpm_command)
2390                 goto fail;
2391
2392         /* Reserve one command ring TRB for disabling LPM.
2393          * Since the USB core grabs the shared usb_bus bandwidth mutex before
2394          * disabling LPM, we only need to reserve one TRB for all devices.
2395          */
2396         xhci->cmd_ring_reserved_trbs++;
2397
2398         val = xhci_readl(xhci, &xhci->cap_regs->db_off);
2399         val &= DBOFF_MASK;
2400         xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
2401                         " from cap regs base addr\n", val);
2402         xhci->dba = (void __iomem *) xhci->cap_regs + val;
2403         xhci_dbg_regs(xhci);
2404         xhci_print_run_regs(xhci);
2405         /* Set ir_set to interrupt register set 0 */
2406         xhci->ir_set = &xhci->run_regs->ir_set[0];
2407
2408         /*
2409          * Event ring setup: Allocate a normal ring, but also setup
2410          * the event ring segment table (ERST).  Section 4.9.3.
2411          */
2412         xhci_dbg(xhci, "// Allocating event ring\n");
2413         xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT,
2414                                                 flags);
2415         if (!xhci->event_ring)
2416                 goto fail;
2417         if (xhci_check_trb_in_td_math(xhci, flags) < 0)
2418                 goto fail;
2419
2420         xhci->erst.entries = dma_alloc_coherent(dev,
2421                         sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma,
2422                         GFP_KERNEL);
2423         if (!xhci->erst.entries)
2424                 goto fail;
2425         xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
2426                         (unsigned long long)dma);
2427
2428         memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
2429         xhci->erst.num_entries = ERST_NUM_SEGS;
2430         xhci->erst.erst_dma_addr = dma;
2431         xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
2432                         xhci->erst.num_entries,
2433                         xhci->erst.entries,
2434                         (unsigned long long)xhci->erst.erst_dma_addr);
2435
2436         /* set ring base address and size for each segment table entry */
2437         for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
2438                 struct xhci_erst_entry *entry = &xhci->erst.entries[val];
2439                 entry->seg_addr = cpu_to_le64(seg->dma);
2440                 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
2441                 entry->rsvd = 0;
2442                 seg = seg->next;
2443         }
2444
2445         /* set ERST count with the number of entries in the segment table */
2446         val = xhci_readl(xhci, &xhci->ir_set->erst_size);
2447         val &= ERST_SIZE_MASK;
2448         val |= ERST_NUM_SEGS;
2449         xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
2450                         val);
2451         xhci_writel(xhci, val, &xhci->ir_set->erst_size);
2452
2453         xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
2454         /* set the segment table base address */
2455         xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
2456                         (unsigned long long)xhci->erst.erst_dma_addr);
2457         val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2458         val_64 &= ERST_PTR_MASK;
2459         val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2460         xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
2461
2462         /* Set the event ring dequeue address */
2463         xhci_set_hc_event_deq(xhci);
2464         xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
2465         xhci_print_ir_set(xhci, 0);
2466
2467         /*
2468          * XXX: Might need to set the Interrupter Moderation Register to
2469          * something other than the default (~1ms minimum between interrupts).
2470          * See section 5.5.1.2.
2471          */
2472         init_completion(&xhci->addr_dev);
2473         for (i = 0; i < MAX_HC_SLOTS; ++i)
2474                 xhci->devs[i] = NULL;
2475         for (i = 0; i < USB_MAXCHILDREN; ++i) {
2476                 xhci->bus_state[0].resume_done[i] = 0;
2477                 xhci->bus_state[1].resume_done[i] = 0;
2478         }
2479
2480         if (scratchpad_alloc(xhci, flags))
2481                 goto fail;
2482         if (xhci_setup_port_arrays(xhci, flags))
2483                 goto fail;
2484
2485         /* Enable USB 3.0 device notifications for function remote wake, which
2486          * is necessary for allowing USB 3.0 devices to do remote wakeup from
2487          * U3 (device suspend).
2488          */
2489         temp = xhci_readl(xhci, &xhci->op_regs->dev_notification);
2490         temp &= ~DEV_NOTE_MASK;
2491         temp |= DEV_NOTE_FWAKE;
2492         xhci_writel(xhci, temp, &xhci->op_regs->dev_notification);
2493
2494         return 0;
2495
2496 fail:
2497         xhci_warn(xhci, "Couldn't initialize memory\n");
2498         xhci_halt(xhci);
2499         xhci_reset(xhci);
2500         xhci_mem_cleanup(xhci);
2501         return -ENOMEM;
2502 }