1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/usb.h>
12 #include <linux/pci.h>
13 #include <linux/slab.h>
14 #include <linux/dmapool.h>
15 #include <linux/dma-mapping.h>
18 #include "xhci-trace.h"
19 #include "xhci-debugfs.h"
22 * Allocates a generic ring segment from the ring pool, sets the dma address,
23 * initializes the segment to zero, and sets the private next pointer to NULL.
26 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
28 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci,
29 unsigned int cycle_state,
30 unsigned int max_packet,
33 struct xhci_segment *seg;
36 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
38 seg = kzalloc_node(sizeof(*seg), flags, dev_to_node(dev));
42 seg->trbs = dma_pool_zalloc(xhci->segment_pool, flags, &dma);
49 seg->bounce_buf = kzalloc_node(max_packet, flags,
51 if (!seg->bounce_buf) {
52 dma_pool_free(xhci->segment_pool, seg->trbs, dma);
57 /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
58 if (cycle_state == 0) {
59 for (i = 0; i < TRBS_PER_SEGMENT; i++)
60 seg->trbs[i].link.control |= cpu_to_le32(TRB_CYCLE);
68 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
71 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
74 kfree(seg->bounce_buf);
78 static void xhci_free_segments_for_ring(struct xhci_hcd *xhci,
79 struct xhci_segment *first)
81 struct xhci_segment *seg;
84 while (seg != first) {
85 struct xhci_segment *next = seg->next;
86 xhci_segment_free(xhci, seg);
89 xhci_segment_free(xhci, first);
93 * Make the prev segment point to the next segment.
95 * Change the last TRB in the prev segment to be a Link TRB which points to the
96 * DMA address of the next segment. The caller needs to set any Link TRB
97 * related flags, such as End TRB, Toggle Cycle, and no snoop.
99 static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
100 struct xhci_segment *next, enum xhci_ring_type type)
107 if (type != TYPE_EVENT) {
108 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
109 cpu_to_le64(next->dma);
111 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
112 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
113 val &= ~TRB_TYPE_BITMASK;
114 val |= TRB_TYPE(TRB_LINK);
115 /* Always set the chain bit with 0.95 hardware */
116 /* Set chain bit for isoc rings on AMD 0.96 host */
117 if (xhci_link_trb_quirk(xhci) ||
118 (type == TYPE_ISOC &&
119 (xhci->quirks & XHCI_AMD_0x96_HOST)))
121 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
126 * Link the ring to the new segments.
127 * Set Toggle Cycle for the new ring if needed.
129 static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring,
130 struct xhci_segment *first, struct xhci_segment *last,
131 unsigned int num_segs)
133 struct xhci_segment *next;
135 if (!ring || !first || !last)
138 next = ring->enq_seg->next;
139 xhci_link_segments(xhci, ring->enq_seg, first, ring->type);
140 xhci_link_segments(xhci, last, next, ring->type);
141 ring->num_segs += num_segs;
142 ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs;
144 if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) {
145 ring->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control
146 &= ~cpu_to_le32(LINK_TOGGLE);
147 last->trbs[TRBS_PER_SEGMENT-1].link.control
148 |= cpu_to_le32(LINK_TOGGLE);
149 ring->last_seg = last;
154 * We need a radix tree for mapping physical addresses of TRBs to which stream
155 * ID they belong to. We need to do this because the host controller won't tell
156 * us which stream ring the TRB came from. We could store the stream ID in an
157 * event data TRB, but that doesn't help us for the cancellation case, since the
158 * endpoint may stop before it reaches that event data TRB.
160 * The radix tree maps the upper portion of the TRB DMA address to a ring
161 * segment that has the same upper portion of DMA addresses. For example, say I
162 * have segments of size 1KB, that are always 1KB aligned. A segment may
163 * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the
164 * key to the stream ID is 0x43244. I can use the DMA address of the TRB to
165 * pass the radix tree a key to get the right stream ID:
167 * 0x10c90fff >> 10 = 0x43243
168 * 0x10c912c0 >> 10 = 0x43244
169 * 0x10c91400 >> 10 = 0x43245
171 * Obviously, only those TRBs with DMA addresses that are within the segment
172 * will make the radix tree return the stream ID for that ring.
174 * Caveats for the radix tree:
176 * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an
177 * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
178 * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the
179 * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
180 * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit
181 * extended systems (where the DMA address can be bigger than 32-bits),
182 * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that.
184 static int xhci_insert_segment_mapping(struct radix_tree_root *trb_address_map,
185 struct xhci_ring *ring,
186 struct xhci_segment *seg,
192 key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT);
193 /* Skip any segments that were already added. */
194 if (radix_tree_lookup(trb_address_map, key))
197 ret = radix_tree_maybe_preload(mem_flags);
200 ret = radix_tree_insert(trb_address_map,
202 radix_tree_preload_end();
206 static void xhci_remove_segment_mapping(struct radix_tree_root *trb_address_map,
207 struct xhci_segment *seg)
211 key = (unsigned long)(seg->dma >> TRB_SEGMENT_SHIFT);
212 if (radix_tree_lookup(trb_address_map, key))
213 radix_tree_delete(trb_address_map, key);
216 static int xhci_update_stream_segment_mapping(
217 struct radix_tree_root *trb_address_map,
218 struct xhci_ring *ring,
219 struct xhci_segment *first_seg,
220 struct xhci_segment *last_seg,
223 struct xhci_segment *seg;
224 struct xhci_segment *failed_seg;
227 if (WARN_ON_ONCE(trb_address_map == NULL))
232 ret = xhci_insert_segment_mapping(trb_address_map,
233 ring, seg, mem_flags);
239 } while (seg != first_seg);
247 xhci_remove_segment_mapping(trb_address_map, seg);
248 if (seg == failed_seg)
251 } while (seg != first_seg);
256 static void xhci_remove_stream_mapping(struct xhci_ring *ring)
258 struct xhci_segment *seg;
260 if (WARN_ON_ONCE(ring->trb_address_map == NULL))
263 seg = ring->first_seg;
265 xhci_remove_segment_mapping(ring->trb_address_map, seg);
267 } while (seg != ring->first_seg);
270 static int xhci_update_stream_mapping(struct xhci_ring *ring, gfp_t mem_flags)
272 return xhci_update_stream_segment_mapping(ring->trb_address_map, ring,
273 ring->first_seg, ring->last_seg, mem_flags);
276 /* XXX: Do we need the hcd structure in all these functions? */
277 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
282 trace_xhci_ring_free(ring);
284 if (ring->first_seg) {
285 if (ring->type == TYPE_STREAM)
286 xhci_remove_stream_mapping(ring);
287 xhci_free_segments_for_ring(xhci, ring->first_seg);
293 static void xhci_initialize_ring_info(struct xhci_ring *ring,
294 unsigned int cycle_state)
296 /* The ring is empty, so the enqueue pointer == dequeue pointer */
297 ring->enqueue = ring->first_seg->trbs;
298 ring->enq_seg = ring->first_seg;
299 ring->dequeue = ring->enqueue;
300 ring->deq_seg = ring->first_seg;
301 /* The ring is initialized to 0. The producer must write 1 to the cycle
302 * bit to handover ownership of the TRB, so PCS = 1. The consumer must
303 * compare CCS to the cycle bit to check ownership, so CCS = 1.
305 * New rings are initialized with cycle state equal to 1; if we are
306 * handling ring expansion, set the cycle state equal to the old ring.
308 ring->cycle_state = cycle_state;
311 * Each segment has a link TRB, and leave an extra TRB for SW
314 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
317 /* Allocate segments and link them for a ring */
318 static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci,
319 struct xhci_segment **first, struct xhci_segment **last,
320 unsigned int num_segs, unsigned int cycle_state,
321 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags)
323 struct xhci_segment *prev;
325 prev = xhci_segment_alloc(xhci, cycle_state, max_packet, flags);
331 while (num_segs > 0) {
332 struct xhci_segment *next;
334 next = xhci_segment_alloc(xhci, cycle_state, max_packet, flags);
339 xhci_segment_free(xhci, prev);
344 xhci_link_segments(xhci, prev, next, type);
349 xhci_link_segments(xhci, prev, *first, type);
356 * Create a new ring with zero or more segments.
358 * Link each segment together into a ring.
359 * Set the end flag and the cycle toggle bit on the last segment.
360 * See section 4.9.1 and figures 15 and 16.
362 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
363 unsigned int num_segs, unsigned int cycle_state,
364 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags)
366 struct xhci_ring *ring;
368 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
370 ring = kzalloc_node(sizeof(*ring), flags, dev_to_node(dev));
374 ring->num_segs = num_segs;
375 ring->bounce_buf_len = max_packet;
376 INIT_LIST_HEAD(&ring->td_list);
381 ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg,
382 &ring->last_seg, num_segs, cycle_state, type,
387 /* Only event ring does not use link TRB */
388 if (type != TYPE_EVENT) {
389 /* See section 4.9.2.1 and 6.4.4.1 */
390 ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |=
391 cpu_to_le32(LINK_TOGGLE);
393 xhci_initialize_ring_info(ring, cycle_state);
394 trace_xhci_ring_alloc(ring);
402 void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
403 struct xhci_virt_device *virt_dev,
404 unsigned int ep_index)
406 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
407 virt_dev->eps[ep_index].ring = NULL;
411 * Expand an existing ring.
412 * Allocate a new ring which has same segment numbers and link the two rings.
414 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
415 unsigned int num_trbs, gfp_t flags)
417 struct xhci_segment *first;
418 struct xhci_segment *last;
419 unsigned int num_segs;
420 unsigned int num_segs_needed;
423 num_segs_needed = (num_trbs + (TRBS_PER_SEGMENT - 1) - 1) /
424 (TRBS_PER_SEGMENT - 1);
426 /* Allocate number of segments we needed, or double the ring size */
427 num_segs = ring->num_segs > num_segs_needed ?
428 ring->num_segs : num_segs_needed;
430 ret = xhci_alloc_segments_for_ring(xhci, &first, &last,
431 num_segs, ring->cycle_state, ring->type,
432 ring->bounce_buf_len, flags);
436 if (ring->type == TYPE_STREAM)
437 ret = xhci_update_stream_segment_mapping(ring->trb_address_map,
438 ring, first, last, flags);
440 struct xhci_segment *next;
443 xhci_segment_free(xhci, first);
451 xhci_link_rings(xhci, ring, first, last, num_segs);
452 trace_xhci_ring_expansion(ring);
453 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
454 "ring expansion succeed, now has %d segments",
460 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
461 int type, gfp_t flags)
463 struct xhci_container_ctx *ctx;
464 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
466 if ((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT))
469 ctx = kzalloc_node(sizeof(*ctx), flags, dev_to_node(dev));
474 ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
475 if (type == XHCI_CTX_TYPE_INPUT)
476 ctx->size += CTX_SIZE(xhci->hcc_params);
478 ctx->bytes = dma_pool_zalloc(xhci->device_pool, flags, &ctx->dma);
486 void xhci_free_container_ctx(struct xhci_hcd *xhci,
487 struct xhci_container_ctx *ctx)
491 dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
495 struct xhci_input_control_ctx *xhci_get_input_control_ctx(
496 struct xhci_container_ctx *ctx)
498 if (ctx->type != XHCI_CTX_TYPE_INPUT)
501 return (struct xhci_input_control_ctx *)ctx->bytes;
504 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
505 struct xhci_container_ctx *ctx)
507 if (ctx->type == XHCI_CTX_TYPE_DEVICE)
508 return (struct xhci_slot_ctx *)ctx->bytes;
510 return (struct xhci_slot_ctx *)
511 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
514 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
515 struct xhci_container_ctx *ctx,
516 unsigned int ep_index)
518 /* increment ep index by offset of start of ep ctx array */
520 if (ctx->type == XHCI_CTX_TYPE_INPUT)
523 return (struct xhci_ep_ctx *)
524 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
528 /***************** Streams structures manipulation *************************/
530 static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
531 unsigned int num_stream_ctxs,
532 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
534 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
535 size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs;
537 if (size > MEDIUM_STREAM_ARRAY_SIZE)
538 dma_free_coherent(dev, size,
540 else if (size <= SMALL_STREAM_ARRAY_SIZE)
541 return dma_pool_free(xhci->small_streams_pool,
544 return dma_pool_free(xhci->medium_streams_pool,
549 * The stream context array for each endpoint with bulk streams enabled can
550 * vary in size, based on:
551 * - how many streams the endpoint supports,
552 * - the maximum primary stream array size the host controller supports,
553 * - and how many streams the device driver asks for.
555 * The stream context array must be a power of 2, and can be as small as
556 * 64 bytes or as large as 1MB.
558 static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
559 unsigned int num_stream_ctxs, dma_addr_t *dma,
562 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
563 size_t size = sizeof(struct xhci_stream_ctx) * num_stream_ctxs;
565 if (size > MEDIUM_STREAM_ARRAY_SIZE)
566 return dma_alloc_coherent(dev, size,
568 else if (size <= SMALL_STREAM_ARRAY_SIZE)
569 return dma_pool_alloc(xhci->small_streams_pool,
572 return dma_pool_alloc(xhci->medium_streams_pool,
576 struct xhci_ring *xhci_dma_to_transfer_ring(
577 struct xhci_virt_ep *ep,
580 if (ep->ep_state & EP_HAS_STREAMS)
581 return radix_tree_lookup(&ep->stream_info->trb_address_map,
582 address >> TRB_SEGMENT_SHIFT);
586 struct xhci_ring *xhci_stream_id_to_ring(
587 struct xhci_virt_device *dev,
588 unsigned int ep_index,
589 unsigned int stream_id)
591 struct xhci_virt_ep *ep = &dev->eps[ep_index];
595 if (!ep->stream_info)
598 if (stream_id > ep->stream_info->num_streams)
600 return ep->stream_info->stream_rings[stream_id];
604 * Change an endpoint's internal structure so it supports stream IDs. The
605 * number of requested streams includes stream 0, which cannot be used by device
608 * The number of stream contexts in the stream context array may be bigger than
609 * the number of streams the driver wants to use. This is because the number of
610 * stream context array entries must be a power of two.
612 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
613 unsigned int num_stream_ctxs,
614 unsigned int num_streams,
615 unsigned int max_packet, gfp_t mem_flags)
617 struct xhci_stream_info *stream_info;
619 struct xhci_ring *cur_ring;
622 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
624 xhci_dbg(xhci, "Allocating %u streams and %u "
625 "stream context array entries.\n",
626 num_streams, num_stream_ctxs);
627 if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
628 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
631 xhci->cmd_ring_reserved_trbs++;
633 stream_info = kzalloc_node(sizeof(*stream_info), mem_flags,
638 stream_info->num_streams = num_streams;
639 stream_info->num_stream_ctxs = num_stream_ctxs;
641 /* Initialize the array of virtual pointers to stream rings. */
642 stream_info->stream_rings = kcalloc_node(
643 num_streams, sizeof(struct xhci_ring *), mem_flags,
645 if (!stream_info->stream_rings)
648 /* Initialize the array of DMA addresses for stream rings for the HW. */
649 stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
650 num_stream_ctxs, &stream_info->ctx_array_dma,
652 if (!stream_info->stream_ctx_array)
654 memset(stream_info->stream_ctx_array, 0,
655 sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
657 /* Allocate everything needed to free the stream rings later */
658 stream_info->free_streams_command =
659 xhci_alloc_command_with_ctx(xhci, true, mem_flags);
660 if (!stream_info->free_streams_command)
663 INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
665 /* Allocate rings for all the streams that the driver will use,
666 * and add their segment DMA addresses to the radix tree.
667 * Stream 0 is reserved.
670 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
671 stream_info->stream_rings[cur_stream] =
672 xhci_ring_alloc(xhci, 2, 1, TYPE_STREAM, max_packet,
674 cur_ring = stream_info->stream_rings[cur_stream];
677 cur_ring->stream_id = cur_stream;
678 cur_ring->trb_address_map = &stream_info->trb_address_map;
679 /* Set deq ptr, cycle bit, and stream context type */
680 addr = cur_ring->first_seg->dma |
681 SCT_FOR_CTX(SCT_PRI_TR) |
682 cur_ring->cycle_state;
683 stream_info->stream_ctx_array[cur_stream].stream_ring =
685 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
686 cur_stream, (unsigned long long) addr);
688 ret = xhci_update_stream_mapping(cur_ring, mem_flags);
690 xhci_ring_free(xhci, cur_ring);
691 stream_info->stream_rings[cur_stream] = NULL;
695 /* Leave the other unused stream ring pointers in the stream context
696 * array initialized to zero. This will cause the xHC to give us an
697 * error if the device asks for a stream ID we don't have setup (if it
698 * was any other way, the host controller would assume the ring is
699 * "empty" and wait forever for data to be queued to that stream ID).
705 for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
706 cur_ring = stream_info->stream_rings[cur_stream];
708 xhci_ring_free(xhci, cur_ring);
709 stream_info->stream_rings[cur_stream] = NULL;
712 xhci_free_command(xhci, stream_info->free_streams_command);
714 kfree(stream_info->stream_rings);
718 xhci->cmd_ring_reserved_trbs--;
722 * Sets the MaxPStreams field and the Linear Stream Array field.
723 * Sets the dequeue pointer to the stream context array.
725 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
726 struct xhci_ep_ctx *ep_ctx,
727 struct xhci_stream_info *stream_info)
729 u32 max_primary_streams;
730 /* MaxPStreams is the number of stream context array entries, not the
731 * number we're actually using. Must be in 2^(MaxPstreams + 1) format.
732 * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
734 max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
735 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
736 "Setting number of stream ctx array entries to %u",
737 1 << (max_primary_streams + 1));
738 ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
739 ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
741 ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma);
745 * Sets the MaxPStreams field and the Linear Stream Array field to 0.
746 * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
747 * not at the beginning of the ring).
749 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
750 struct xhci_virt_ep *ep)
753 ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
754 addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
755 ep_ctx->deq = cpu_to_le64(addr | ep->ring->cycle_state);
758 /* Frees all stream contexts associated with the endpoint,
760 * Caller should fix the endpoint context streams fields.
762 void xhci_free_stream_info(struct xhci_hcd *xhci,
763 struct xhci_stream_info *stream_info)
766 struct xhci_ring *cur_ring;
771 for (cur_stream = 1; cur_stream < stream_info->num_streams;
773 cur_ring = stream_info->stream_rings[cur_stream];
775 xhci_ring_free(xhci, cur_ring);
776 stream_info->stream_rings[cur_stream] = NULL;
779 xhci_free_command(xhci, stream_info->free_streams_command);
780 xhci->cmd_ring_reserved_trbs--;
781 if (stream_info->stream_ctx_array)
782 xhci_free_stream_ctx(xhci,
783 stream_info->num_stream_ctxs,
784 stream_info->stream_ctx_array,
785 stream_info->ctx_array_dma);
787 kfree(stream_info->stream_rings);
792 /***************** Device context manipulation *************************/
794 static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
795 struct xhci_virt_ep *ep)
797 timer_setup(&ep->stop_cmd_timer, xhci_stop_endpoint_command_watchdog,
802 static void xhci_free_tt_info(struct xhci_hcd *xhci,
803 struct xhci_virt_device *virt_dev,
806 struct list_head *tt_list_head;
807 struct xhci_tt_bw_info *tt_info, *next;
808 bool slot_found = false;
810 /* If the device never made it past the Set Address stage,
811 * it may not have the real_port set correctly.
813 if (virt_dev->real_port == 0 ||
814 virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
815 xhci_dbg(xhci, "Bad real port.\n");
819 tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
820 list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
821 /* Multi-TT hubs will have more than one entry */
822 if (tt_info->slot_id == slot_id) {
824 list_del(&tt_info->tt_list);
826 } else if (slot_found) {
832 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
833 struct xhci_virt_device *virt_dev,
834 struct usb_device *hdev,
835 struct usb_tt *tt, gfp_t mem_flags)
837 struct xhci_tt_bw_info *tt_info;
838 unsigned int num_ports;
840 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
845 num_ports = hdev->maxchild;
847 for (i = 0; i < num_ports; i++, tt_info++) {
848 struct xhci_interval_bw_table *bw_table;
850 tt_info = kzalloc_node(sizeof(*tt_info), mem_flags,
854 INIT_LIST_HEAD(&tt_info->tt_list);
855 list_add(&tt_info->tt_list,
856 &xhci->rh_bw[virt_dev->real_port - 1].tts);
857 tt_info->slot_id = virt_dev->udev->slot_id;
859 tt_info->ttport = i+1;
860 bw_table = &tt_info->bw_table;
861 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
862 INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
867 xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
872 /* All the xhci_tds in the ring's TD list should be freed at this point.
873 * Should be called with xhci->lock held if there is any chance the TT lists
874 * will be manipulated by the configure endpoint, allocate device, or update
875 * hub functions while this function is removing the TT entries from the list.
877 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
879 struct xhci_virt_device *dev;
881 int old_active_eps = 0;
883 /* Slot ID 0 is reserved */
884 if (slot_id == 0 || !xhci->devs[slot_id])
887 dev = xhci->devs[slot_id];
889 xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
893 trace_xhci_free_virt_device(dev);
896 old_active_eps = dev->tt_info->active_eps;
898 for (i = 0; i < 31; i++) {
899 if (dev->eps[i].ring)
900 xhci_ring_free(xhci, dev->eps[i].ring);
901 if (dev->eps[i].stream_info)
902 xhci_free_stream_info(xhci,
903 dev->eps[i].stream_info);
904 /* Endpoints on the TT/root port lists should have been removed
905 * when usb_disable_device() was called for the device.
906 * We can't drop them anyway, because the udev might have gone
907 * away by this point, and we can't tell what speed it was.
909 if (!list_empty(&dev->eps[i].bw_endpoint_list))
910 xhci_warn(xhci, "Slot %u endpoint %u "
911 "not removed from BW list!\n",
914 /* If this is a hub, free the TT(s) from the TT list */
915 xhci_free_tt_info(xhci, dev, slot_id);
916 /* If necessary, update the number of active TTs on this root port */
917 xhci_update_tt_active_eps(xhci, dev, old_active_eps);
920 xhci_free_container_ctx(xhci, dev->in_ctx);
922 xhci_free_container_ctx(xhci, dev->out_ctx);
924 if (dev->udev && dev->udev->slot_id)
925 dev->udev->slot_id = 0;
926 kfree(xhci->devs[slot_id]);
927 xhci->devs[slot_id] = NULL;
931 * Free a virt_device structure.
932 * If the virt_device added a tt_info (a hub) and has children pointing to
933 * that tt_info, then free the child first. Recursive.
934 * We can't rely on udev at this point to find child-parent relationships.
936 void xhci_free_virt_devices_depth_first(struct xhci_hcd *xhci, int slot_id)
938 struct xhci_virt_device *vdev;
939 struct list_head *tt_list_head;
940 struct xhci_tt_bw_info *tt_info, *next;
943 vdev = xhci->devs[slot_id];
947 if (vdev->real_port == 0 ||
948 vdev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
949 xhci_dbg(xhci, "Bad vdev->real_port.\n");
953 tt_list_head = &(xhci->rh_bw[vdev->real_port - 1].tts);
954 list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
955 /* is this a hub device that added a tt_info to the tts list */
956 if (tt_info->slot_id == slot_id) {
957 /* are any devices using this tt_info? */
958 for (i = 1; i < HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
959 vdev = xhci->devs[i];
960 if (vdev && (vdev->tt_info == tt_info))
961 xhci_free_virt_devices_depth_first(
967 /* we are now at a leaf device */
968 xhci_debugfs_remove_slot(xhci, slot_id);
969 xhci_free_virt_device(xhci, slot_id);
972 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
973 struct usb_device *udev, gfp_t flags)
975 struct xhci_virt_device *dev;
978 /* Slot ID 0 is reserved */
979 if (slot_id == 0 || xhci->devs[slot_id]) {
980 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
984 dev = kzalloc(sizeof(*dev), flags);
988 /* Allocate the (output) device context that will be used in the HC. */
989 dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
993 xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
994 (unsigned long long)dev->out_ctx->dma);
996 /* Allocate the (input) device context for address device command */
997 dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
1001 xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
1002 (unsigned long long)dev->in_ctx->dma);
1004 /* Initialize the cancellation list and watchdog timers for each ep */
1005 for (i = 0; i < 31; i++) {
1006 xhci_init_endpoint_timer(xhci, &dev->eps[i]);
1007 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
1008 INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
1011 /* Allocate endpoint 0 ring */
1012 dev->eps[0].ring = xhci_ring_alloc(xhci, 2, 1, TYPE_CTRL, 0, flags);
1013 if (!dev->eps[0].ring)
1018 /* Point to output device context in dcbaa. */
1019 xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
1020 xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
1022 &xhci->dcbaa->dev_context_ptrs[slot_id],
1023 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
1025 trace_xhci_alloc_virt_device(dev);
1027 xhci->devs[slot_id] = dev;
1033 xhci_free_container_ctx(xhci, dev->in_ctx);
1035 xhci_free_container_ctx(xhci, dev->out_ctx);
1041 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1042 struct usb_device *udev)
1044 struct xhci_virt_device *virt_dev;
1045 struct xhci_ep_ctx *ep0_ctx;
1046 struct xhci_ring *ep_ring;
1048 virt_dev = xhci->devs[udev->slot_id];
1049 ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
1050 ep_ring = virt_dev->eps[0].ring;
1052 * FIXME we don't keep track of the dequeue pointer very well after a
1053 * Set TR dequeue pointer, so we're setting the dequeue pointer of the
1054 * host to our enqueue pointer. This should only be called after a
1055 * configured device has reset, so all control transfers should have
1056 * been completed or cancelled before the reset.
1058 ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
1060 | ep_ring->cycle_state);
1064 * The xHCI roothub may have ports of differing speeds in any order in the port
1067 * The xHCI hardware wants to know the roothub port number that the USB device
1068 * is attached to (or the roothub port its ancestor hub is attached to). All we
1069 * know is the index of that port under either the USB 2.0 or the USB 3.0
1070 * roothub, but that doesn't give us the real index into the HW port status
1071 * registers. Call xhci_find_raw_port_number() to get real index.
1073 static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
1074 struct usb_device *udev)
1076 struct usb_device *top_dev;
1077 struct usb_hcd *hcd;
1079 if (udev->speed >= USB_SPEED_SUPER)
1080 hcd = xhci->shared_hcd;
1082 hcd = xhci->main_hcd;
1084 for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1085 top_dev = top_dev->parent)
1086 /* Found device below root hub */;
1088 return xhci_find_raw_port_number(hcd, top_dev->portnum);
1091 /* Setup an xHCI virtual device for a Set Address command */
1092 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
1094 struct xhci_virt_device *dev;
1095 struct xhci_ep_ctx *ep0_ctx;
1096 struct xhci_slot_ctx *slot_ctx;
1099 struct usb_device *top_dev;
1101 dev = xhci->devs[udev->slot_id];
1102 /* Slot ID 0 is reserved */
1103 if (udev->slot_id == 0 || !dev) {
1104 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
1108 ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
1109 slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
1111 /* 3) Only the control endpoint is valid - one endpoint context */
1112 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
1113 switch (udev->speed) {
1114 case USB_SPEED_SUPER_PLUS:
1115 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SSP);
1116 max_packets = MAX_PACKET(512);
1118 case USB_SPEED_SUPER:
1119 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
1120 max_packets = MAX_PACKET(512);
1122 case USB_SPEED_HIGH:
1123 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
1124 max_packets = MAX_PACKET(64);
1126 /* USB core guesses at a 64-byte max packet first for FS devices */
1127 case USB_SPEED_FULL:
1128 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
1129 max_packets = MAX_PACKET(64);
1132 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
1133 max_packets = MAX_PACKET(8);
1135 case USB_SPEED_WIRELESS:
1136 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1140 /* Speed was set earlier, this shouldn't happen. */
1143 /* Find the root hub port this device is under */
1144 port_num = xhci_find_real_port_number(xhci, udev);
1147 slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
1148 /* Set the port number in the virtual_device to the faked port number */
1149 for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1150 top_dev = top_dev->parent)
1151 /* Found device below root hub */;
1152 dev->fake_port = top_dev->portnum;
1153 dev->real_port = port_num;
1154 xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
1155 xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
1157 /* Find the right bandwidth table that this device will be a part of.
1158 * If this is a full speed device attached directly to a root port (or a
1159 * decendent of one), it counts as a primary bandwidth domain, not a
1160 * secondary bandwidth domain under a TT. An xhci_tt_info structure
1161 * will never be created for the HS root hub.
1163 if (!udev->tt || !udev->tt->hub->parent) {
1164 dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
1166 struct xhci_root_port_bw_info *rh_bw;
1167 struct xhci_tt_bw_info *tt_bw;
1169 rh_bw = &xhci->rh_bw[port_num - 1];
1170 /* Find the right TT. */
1171 list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
1172 if (tt_bw->slot_id != udev->tt->hub->slot_id)
1175 if (!dev->udev->tt->multi ||
1177 tt_bw->ttport == dev->udev->ttport)) {
1178 dev->bw_table = &tt_bw->bw_table;
1179 dev->tt_info = tt_bw;
1184 xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
1187 /* Is this a LS/FS device under an external HS hub? */
1188 if (udev->tt && udev->tt->hub->parent) {
1189 slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
1190 (udev->ttport << 8));
1191 if (udev->tt->multi)
1192 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1194 xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1195 xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
1197 /* Step 4 - ring already allocated */
1199 ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1201 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1202 ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3) |
1205 ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
1206 dev->eps[0].ring->cycle_state);
1208 trace_xhci_setup_addressable_virt_device(dev);
1210 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1216 * Convert interval expressed as 2^(bInterval - 1) == interval into
1217 * straight exponent value 2^n == interval.
1220 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
1221 struct usb_host_endpoint *ep)
1223 unsigned int interval;
1225 interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
1226 if (interval != ep->desc.bInterval - 1)
1227 dev_warn(&udev->dev,
1228 "ep %#x - rounding interval to %d %sframes\n",
1229 ep->desc.bEndpointAddress,
1231 udev->speed == USB_SPEED_FULL ? "" : "micro");
1233 if (udev->speed == USB_SPEED_FULL) {
1235 * Full speed isoc endpoints specify interval in frames,
1236 * not microframes. We are using microframes everywhere,
1237 * so adjust accordingly.
1239 interval += 3; /* 1 frame = 2^3 uframes */
1246 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1247 * microframes, rounded down to nearest power of 2.
1249 static unsigned int xhci_microframes_to_exponent(struct usb_device *udev,
1250 struct usb_host_endpoint *ep, unsigned int desc_interval,
1251 unsigned int min_exponent, unsigned int max_exponent)
1253 unsigned int interval;
1255 interval = fls(desc_interval) - 1;
1256 interval = clamp_val(interval, min_exponent, max_exponent);
1257 if ((1 << interval) != desc_interval)
1259 "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1260 ep->desc.bEndpointAddress,
1267 static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
1268 struct usb_host_endpoint *ep)
1270 if (ep->desc.bInterval == 0)
1272 return xhci_microframes_to_exponent(udev, ep,
1273 ep->desc.bInterval, 0, 15);
1277 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1278 struct usb_host_endpoint *ep)
1280 return xhci_microframes_to_exponent(udev, ep,
1281 ep->desc.bInterval * 8, 3, 10);
1284 /* Return the polling or NAK interval.
1286 * The polling interval is expressed in "microframes". If xHCI's Interval field
1287 * is set to N, it will service the endpoint every 2^(Interval)*125us.
1289 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1292 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1293 struct usb_host_endpoint *ep)
1295 unsigned int interval = 0;
1297 switch (udev->speed) {
1298 case USB_SPEED_HIGH:
1300 if (usb_endpoint_xfer_control(&ep->desc) ||
1301 usb_endpoint_xfer_bulk(&ep->desc)) {
1302 interval = xhci_parse_microframe_interval(udev, ep);
1305 /* Fall through - SS and HS isoc/int have same decoding */
1307 case USB_SPEED_SUPER_PLUS:
1308 case USB_SPEED_SUPER:
1309 if (usb_endpoint_xfer_int(&ep->desc) ||
1310 usb_endpoint_xfer_isoc(&ep->desc)) {
1311 interval = xhci_parse_exponent_interval(udev, ep);
1315 case USB_SPEED_FULL:
1316 if (usb_endpoint_xfer_isoc(&ep->desc)) {
1317 interval = xhci_parse_exponent_interval(udev, ep);
1321 * Fall through for interrupt endpoint interval decoding
1322 * since it uses the same rules as low speed interrupt
1328 if (usb_endpoint_xfer_int(&ep->desc) ||
1329 usb_endpoint_xfer_isoc(&ep->desc)) {
1331 interval = xhci_parse_frame_interval(udev, ep);
1341 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1342 * High speed endpoint descriptors can define "the number of additional
1343 * transaction opportunities per microframe", but that goes in the Max Burst
1344 * endpoint context field.
1346 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1347 struct usb_host_endpoint *ep)
1349 if (udev->speed < USB_SPEED_SUPER ||
1350 !usb_endpoint_xfer_isoc(&ep->desc))
1352 return ep->ss_ep_comp.bmAttributes;
1355 static u32 xhci_get_endpoint_max_burst(struct usb_device *udev,
1356 struct usb_host_endpoint *ep)
1358 /* Super speed and Plus have max burst in ep companion desc */
1359 if (udev->speed >= USB_SPEED_SUPER)
1360 return ep->ss_ep_comp.bMaxBurst;
1362 if (udev->speed == USB_SPEED_HIGH &&
1363 (usb_endpoint_xfer_isoc(&ep->desc) ||
1364 usb_endpoint_xfer_int(&ep->desc)))
1365 return usb_endpoint_maxp_mult(&ep->desc) - 1;
1370 static u32 xhci_get_endpoint_type(struct usb_host_endpoint *ep)
1374 in = usb_endpoint_dir_in(&ep->desc);
1376 switch (usb_endpoint_type(&ep->desc)) {
1377 case USB_ENDPOINT_XFER_CONTROL:
1379 case USB_ENDPOINT_XFER_BULK:
1380 return in ? BULK_IN_EP : BULK_OUT_EP;
1381 case USB_ENDPOINT_XFER_ISOC:
1382 return in ? ISOC_IN_EP : ISOC_OUT_EP;
1383 case USB_ENDPOINT_XFER_INT:
1384 return in ? INT_IN_EP : INT_OUT_EP;
1389 /* Return the maximum endpoint service interval time (ESIT) payload.
1390 * Basically, this is the maxpacket size, multiplied by the burst size
1393 static u32 xhci_get_max_esit_payload(struct usb_device *udev,
1394 struct usb_host_endpoint *ep)
1399 /* Only applies for interrupt or isochronous endpoints */
1400 if (usb_endpoint_xfer_control(&ep->desc) ||
1401 usb_endpoint_xfer_bulk(&ep->desc))
1404 /* SuperSpeedPlus Isoc ep sending over 48k per esit */
1405 if ((udev->speed >= USB_SPEED_SUPER_PLUS) &&
1406 USB_SS_SSP_ISOC_COMP(ep->ss_ep_comp.bmAttributes))
1407 return le32_to_cpu(ep->ssp_isoc_ep_comp.dwBytesPerInterval);
1408 /* SuperSpeed or SuperSpeedPlus Isoc ep with less than 48k per esit */
1409 else if (udev->speed >= USB_SPEED_SUPER)
1410 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1412 max_packet = usb_endpoint_maxp(&ep->desc);
1413 max_burst = usb_endpoint_maxp_mult(&ep->desc);
1414 /* A 0 in max burst means 1 transfer per ESIT */
1415 return max_packet * max_burst;
1418 /* Set up an endpoint with one ring segment. Do not allocate stream rings.
1419 * Drivers will have to call usb_alloc_streams() to do that.
1421 int xhci_endpoint_init(struct xhci_hcd *xhci,
1422 struct xhci_virt_device *virt_dev,
1423 struct usb_device *udev,
1424 struct usb_host_endpoint *ep,
1427 unsigned int ep_index;
1428 struct xhci_ep_ctx *ep_ctx;
1429 struct xhci_ring *ep_ring;
1430 unsigned int max_packet;
1431 enum xhci_ring_type ring_type;
1432 u32 max_esit_payload;
1434 unsigned int max_burst;
1435 unsigned int interval;
1437 unsigned int avg_trb_len;
1438 unsigned int err_count = 0;
1440 ep_index = xhci_get_endpoint_index(&ep->desc);
1441 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1443 endpoint_type = xhci_get_endpoint_type(ep);
1447 ring_type = usb_endpoint_type(&ep->desc);
1450 * Get values to fill the endpoint context, mostly from ep descriptor.
1451 * The average TRB buffer lengt for bulk endpoints is unclear as we
1452 * have no clue on scatter gather list entry size. For Isoc and Int,
1453 * set it to max available. See xHCI 1.1 spec 4.14.1.1 for details.
1455 max_esit_payload = xhci_get_max_esit_payload(udev, ep);
1456 interval = xhci_get_endpoint_interval(udev, ep);
1458 /* Periodic endpoint bInterval limit quirk */
1459 if (usb_endpoint_xfer_int(&ep->desc) ||
1460 usb_endpoint_xfer_isoc(&ep->desc)) {
1461 if ((xhci->quirks & XHCI_LIMIT_ENDPOINT_INTERVAL_7) &&
1462 udev->speed >= USB_SPEED_HIGH &&
1468 mult = xhci_get_endpoint_mult(udev, ep);
1469 max_packet = usb_endpoint_maxp(&ep->desc);
1470 max_burst = xhci_get_endpoint_max_burst(udev, ep);
1471 avg_trb_len = max_esit_payload;
1473 /* FIXME dig Mult and streams info out of ep companion desc */
1475 /* Allow 3 retries for everything but isoc, set CErr = 3 */
1476 if (!usb_endpoint_xfer_isoc(&ep->desc))
1478 /* Some devices get this wrong */
1479 if (usb_endpoint_xfer_bulk(&ep->desc) && udev->speed == USB_SPEED_HIGH)
1481 /* xHCI 1.0 and 1.1 indicates that ctrl ep avg TRB Length should be 8 */
1482 if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version >= 0x100)
1484 /* xhci 1.1 with LEC support doesn't use mult field, use RsvdZ */
1485 if ((xhci->hci_version > 0x100) && HCC2_LEC(xhci->hcc_params2))
1488 /* Set up the endpoint ring */
1489 virt_dev->eps[ep_index].new_ring =
1490 xhci_ring_alloc(xhci, 2, 1, ring_type, max_packet, mem_flags);
1491 if (!virt_dev->eps[ep_index].new_ring)
1494 virt_dev->eps[ep_index].skip = false;
1495 ep_ring = virt_dev->eps[ep_index].new_ring;
1497 /* Fill the endpoint context */
1498 ep_ctx->ep_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) |
1499 EP_INTERVAL(interval) |
1501 ep_ctx->ep_info2 = cpu_to_le32(EP_TYPE(endpoint_type) |
1502 MAX_PACKET(max_packet) |
1503 MAX_BURST(max_burst) |
1504 ERROR_COUNT(err_count));
1505 ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma |
1506 ep_ring->cycle_state);
1508 ep_ctx->tx_info = cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) |
1509 EP_AVG_TRB_LENGTH(avg_trb_len));
1514 void xhci_endpoint_zero(struct xhci_hcd *xhci,
1515 struct xhci_virt_device *virt_dev,
1516 struct usb_host_endpoint *ep)
1518 unsigned int ep_index;
1519 struct xhci_ep_ctx *ep_ctx;
1521 ep_index = xhci_get_endpoint_index(&ep->desc);
1522 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1524 ep_ctx->ep_info = 0;
1525 ep_ctx->ep_info2 = 0;
1527 ep_ctx->tx_info = 0;
1528 /* Don't free the endpoint ring until the set interface or configuration
1533 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
1535 bw_info->ep_interval = 0;
1537 bw_info->num_packets = 0;
1538 bw_info->max_packet_size = 0;
1540 bw_info->max_esit_payload = 0;
1543 void xhci_update_bw_info(struct xhci_hcd *xhci,
1544 struct xhci_container_ctx *in_ctx,
1545 struct xhci_input_control_ctx *ctrl_ctx,
1546 struct xhci_virt_device *virt_dev)
1548 struct xhci_bw_info *bw_info;
1549 struct xhci_ep_ctx *ep_ctx;
1550 unsigned int ep_type;
1553 for (i = 1; i < 31; i++) {
1554 bw_info = &virt_dev->eps[i].bw_info;
1556 /* We can't tell what endpoint type is being dropped, but
1557 * unconditionally clearing the bandwidth info for non-periodic
1558 * endpoints should be harmless because the info will never be
1559 * set in the first place.
1561 if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
1562 /* Dropped endpoint */
1563 xhci_clear_endpoint_bw_info(bw_info);
1567 if (EP_IS_ADDED(ctrl_ctx, i)) {
1568 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
1569 ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
1571 /* Ignore non-periodic endpoints */
1572 if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
1573 ep_type != ISOC_IN_EP &&
1574 ep_type != INT_IN_EP)
1577 /* Added or changed endpoint */
1578 bw_info->ep_interval = CTX_TO_EP_INTERVAL(
1579 le32_to_cpu(ep_ctx->ep_info));
1580 /* Number of packets and mult are zero-based in the
1581 * input context, but we want one-based for the
1584 bw_info->mult = CTX_TO_EP_MULT(
1585 le32_to_cpu(ep_ctx->ep_info)) + 1;
1586 bw_info->num_packets = CTX_TO_MAX_BURST(
1587 le32_to_cpu(ep_ctx->ep_info2)) + 1;
1588 bw_info->max_packet_size = MAX_PACKET_DECODED(
1589 le32_to_cpu(ep_ctx->ep_info2));
1590 bw_info->type = ep_type;
1591 bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
1592 le32_to_cpu(ep_ctx->tx_info));
1597 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1598 * Useful when you want to change one particular aspect of the endpoint and then
1599 * issue a configure endpoint command.
1601 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1602 struct xhci_container_ctx *in_ctx,
1603 struct xhci_container_ctx *out_ctx,
1604 unsigned int ep_index)
1606 struct xhci_ep_ctx *out_ep_ctx;
1607 struct xhci_ep_ctx *in_ep_ctx;
1609 out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1610 in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1612 in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1613 in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1614 in_ep_ctx->deq = out_ep_ctx->deq;
1615 in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1618 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1619 * Useful when you want to change one particular aspect of the endpoint and then
1620 * issue a configure endpoint command. Only the context entries field matters,
1621 * but we'll copy the whole thing anyway.
1623 void xhci_slot_copy(struct xhci_hcd *xhci,
1624 struct xhci_container_ctx *in_ctx,
1625 struct xhci_container_ctx *out_ctx)
1627 struct xhci_slot_ctx *in_slot_ctx;
1628 struct xhci_slot_ctx *out_slot_ctx;
1630 in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1631 out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1633 in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1634 in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1635 in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1636 in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1639 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1640 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1643 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1644 int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1646 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1647 "Allocating %d scratchpad buffers", num_sp);
1652 xhci->scratchpad = kzalloc_node(sizeof(*xhci->scratchpad), flags,
1654 if (!xhci->scratchpad)
1657 xhci->scratchpad->sp_array = dma_alloc_coherent(dev,
1658 num_sp * sizeof(u64),
1659 &xhci->scratchpad->sp_dma, flags);
1660 if (!xhci->scratchpad->sp_array)
1663 xhci->scratchpad->sp_buffers = kcalloc_node(num_sp, sizeof(void *),
1664 flags, dev_to_node(dev));
1665 if (!xhci->scratchpad->sp_buffers)
1668 xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1669 for (i = 0; i < num_sp; i++) {
1671 void *buf = dma_zalloc_coherent(dev, xhci->page_size, &dma,
1676 xhci->scratchpad->sp_array[i] = dma;
1677 xhci->scratchpad->sp_buffers[i] = buf;
1683 for (i = i - 1; i >= 0; i--) {
1684 dma_free_coherent(dev, xhci->page_size,
1685 xhci->scratchpad->sp_buffers[i],
1686 xhci->scratchpad->sp_array[i]);
1689 kfree(xhci->scratchpad->sp_buffers);
1692 dma_free_coherent(dev, num_sp * sizeof(u64),
1693 xhci->scratchpad->sp_array,
1694 xhci->scratchpad->sp_dma);
1697 kfree(xhci->scratchpad);
1698 xhci->scratchpad = NULL;
1704 static void scratchpad_free(struct xhci_hcd *xhci)
1708 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1710 if (!xhci->scratchpad)
1713 num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1715 for (i = 0; i < num_sp; i++) {
1716 dma_free_coherent(dev, xhci->page_size,
1717 xhci->scratchpad->sp_buffers[i],
1718 xhci->scratchpad->sp_array[i]);
1720 kfree(xhci->scratchpad->sp_buffers);
1721 dma_free_coherent(dev, num_sp * sizeof(u64),
1722 xhci->scratchpad->sp_array,
1723 xhci->scratchpad->sp_dma);
1724 kfree(xhci->scratchpad);
1725 xhci->scratchpad = NULL;
1728 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1729 bool allocate_completion, gfp_t mem_flags)
1731 struct xhci_command *command;
1732 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1734 command = kzalloc_node(sizeof(*command), mem_flags, dev_to_node(dev));
1738 if (allocate_completion) {
1739 command->completion =
1740 kzalloc_node(sizeof(struct completion), mem_flags,
1742 if (!command->completion) {
1746 init_completion(command->completion);
1749 command->status = 0;
1750 INIT_LIST_HEAD(&command->cmd_list);
1754 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
1755 bool allocate_completion, gfp_t mem_flags)
1757 struct xhci_command *command;
1759 command = xhci_alloc_command(xhci, allocate_completion, mem_flags);
1763 command->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1765 if (!command->in_ctx) {
1766 kfree(command->completion);
1773 void xhci_urb_free_priv(struct urb_priv *urb_priv)
1778 void xhci_free_command(struct xhci_hcd *xhci,
1779 struct xhci_command *command)
1781 xhci_free_container_ctx(xhci,
1783 kfree(command->completion);
1787 int xhci_alloc_erst(struct xhci_hcd *xhci,
1788 struct xhci_ring *evt_ring,
1789 struct xhci_erst *erst,
1794 struct xhci_segment *seg;
1795 struct xhci_erst_entry *entry;
1797 size = sizeof(struct xhci_erst_entry) * evt_ring->num_segs;
1798 erst->entries = dma_zalloc_coherent(xhci_to_hcd(xhci)->self.sysdev,
1799 size, &erst->erst_dma_addr, flags);
1803 erst->num_entries = evt_ring->num_segs;
1805 seg = evt_ring->first_seg;
1806 for (val = 0; val < evt_ring->num_segs; val++) {
1807 entry = &erst->entries[val];
1808 entry->seg_addr = cpu_to_le64(seg->dma);
1809 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
1817 void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst)
1820 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1822 size = sizeof(struct xhci_erst_entry) * (erst->num_entries);
1824 dma_free_coherent(dev, size,
1826 erst->erst_dma_addr);
1827 erst->entries = NULL;
1830 void xhci_mem_cleanup(struct xhci_hcd *xhci)
1832 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
1833 int i, j, num_ports;
1835 cancel_delayed_work_sync(&xhci->cmd_timer);
1837 xhci_free_erst(xhci, &xhci->erst);
1839 if (xhci->event_ring)
1840 xhci_ring_free(xhci, xhci->event_ring);
1841 xhci->event_ring = NULL;
1842 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed event ring");
1844 if (xhci->lpm_command)
1845 xhci_free_command(xhci, xhci->lpm_command);
1846 xhci->lpm_command = NULL;
1848 xhci_ring_free(xhci, xhci->cmd_ring);
1849 xhci->cmd_ring = NULL;
1850 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed command ring");
1851 xhci_cleanup_command_queue(xhci);
1853 num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1854 for (i = 0; i < num_ports && xhci->rh_bw; i++) {
1855 struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table;
1856 for (j = 0; j < XHCI_MAX_INTERVAL; j++) {
1857 struct list_head *ep = &bwt->interval_bw[j].endpoints;
1858 while (!list_empty(ep))
1859 list_del_init(ep->next);
1863 for (i = HCS_MAX_SLOTS(xhci->hcs_params1); i > 0; i--)
1864 xhci_free_virt_devices_depth_first(xhci, i);
1866 dma_pool_destroy(xhci->segment_pool);
1867 xhci->segment_pool = NULL;
1868 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed segment pool");
1870 dma_pool_destroy(xhci->device_pool);
1871 xhci->device_pool = NULL;
1872 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Freed device context pool");
1874 dma_pool_destroy(xhci->small_streams_pool);
1875 xhci->small_streams_pool = NULL;
1876 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1877 "Freed small stream array pool");
1879 dma_pool_destroy(xhci->medium_streams_pool);
1880 xhci->medium_streams_pool = NULL;
1881 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
1882 "Freed medium stream array pool");
1885 dma_free_coherent(dev, sizeof(*xhci->dcbaa),
1886 xhci->dcbaa, xhci->dcbaa->dma);
1889 scratchpad_free(xhci);
1894 for (i = 0; i < num_ports; i++) {
1895 struct xhci_tt_bw_info *tt, *n;
1896 list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) {
1897 list_del(&tt->tt_list);
1903 xhci->cmd_ring_reserved_trbs = 0;
1904 xhci->usb2_rhub.num_ports = 0;
1905 xhci->usb3_rhub.num_ports = 0;
1906 xhci->num_active_eps = 0;
1907 kfree(xhci->usb2_rhub.ports);
1908 kfree(xhci->usb3_rhub.ports);
1909 kfree(xhci->hw_ports);
1911 kfree(xhci->ext_caps);
1913 xhci->usb2_rhub.ports = NULL;
1914 xhci->usb3_rhub.ports = NULL;
1915 xhci->hw_ports = NULL;
1917 xhci->ext_caps = NULL;
1919 xhci->page_size = 0;
1920 xhci->page_shift = 0;
1921 xhci->bus_state[0].bus_suspended = 0;
1922 xhci->bus_state[1].bus_suspended = 0;
1925 static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
1926 struct xhci_segment *input_seg,
1927 union xhci_trb *start_trb,
1928 union xhci_trb *end_trb,
1929 dma_addr_t input_dma,
1930 struct xhci_segment *result_seg,
1931 char *test_name, int test_number)
1933 unsigned long long start_dma;
1934 unsigned long long end_dma;
1935 struct xhci_segment *seg;
1937 start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
1938 end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
1940 seg = trb_in_td(xhci, input_seg, start_trb, end_trb, input_dma, false);
1941 if (seg != result_seg) {
1942 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
1943 test_name, test_number);
1944 xhci_warn(xhci, "Tested TRB math w/ seg %p and "
1945 "input DMA 0x%llx\n",
1947 (unsigned long long) input_dma);
1948 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
1949 "ending TRB %p (0x%llx DMA)\n",
1950 start_trb, start_dma,
1952 xhci_warn(xhci, "Expected seg %p, got seg %p\n",
1954 trb_in_td(xhci, input_seg, start_trb, end_trb, input_dma,
1961 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1962 static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci)
1965 dma_addr_t input_dma;
1966 struct xhci_segment *result_seg;
1967 } simple_test_vector [] = {
1968 /* A zeroed DMA field should fail */
1970 /* One TRB before the ring start should fail */
1971 { xhci->event_ring->first_seg->dma - 16, NULL },
1972 /* One byte before the ring start should fail */
1973 { xhci->event_ring->first_seg->dma - 1, NULL },
1974 /* Starting TRB should succeed */
1975 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
1976 /* Ending TRB should succeed */
1977 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
1978 xhci->event_ring->first_seg },
1979 /* One byte after the ring end should fail */
1980 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
1981 /* One TRB after the ring end should fail */
1982 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
1983 /* An address of all ones should fail */
1984 { (dma_addr_t) (~0), NULL },
1987 struct xhci_segment *input_seg;
1988 union xhci_trb *start_trb;
1989 union xhci_trb *end_trb;
1990 dma_addr_t input_dma;
1991 struct xhci_segment *result_seg;
1992 } complex_test_vector [] = {
1993 /* Test feeding a valid DMA address from a different ring */
1994 { .input_seg = xhci->event_ring->first_seg,
1995 .start_trb = xhci->event_ring->first_seg->trbs,
1996 .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1997 .input_dma = xhci->cmd_ring->first_seg->dma,
2000 /* Test feeding a valid end TRB from a different ring */
2001 { .input_seg = xhci->event_ring->first_seg,
2002 .start_trb = xhci->event_ring->first_seg->trbs,
2003 .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
2004 .input_dma = xhci->cmd_ring->first_seg->dma,
2007 /* Test feeding a valid start and end TRB from a different ring */
2008 { .input_seg = xhci->event_ring->first_seg,
2009 .start_trb = xhci->cmd_ring->first_seg->trbs,
2010 .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
2011 .input_dma = xhci->cmd_ring->first_seg->dma,
2014 /* TRB in this ring, but after this TD */
2015 { .input_seg = xhci->event_ring->first_seg,
2016 .start_trb = &xhci->event_ring->first_seg->trbs[0],
2017 .end_trb = &xhci->event_ring->first_seg->trbs[3],
2018 .input_dma = xhci->event_ring->first_seg->dma + 4*16,
2021 /* TRB in this ring, but before this TD */
2022 { .input_seg = xhci->event_ring->first_seg,
2023 .start_trb = &xhci->event_ring->first_seg->trbs[3],
2024 .end_trb = &xhci->event_ring->first_seg->trbs[6],
2025 .input_dma = xhci->event_ring->first_seg->dma + 2*16,
2028 /* TRB in this ring, but after this wrapped TD */
2029 { .input_seg = xhci->event_ring->first_seg,
2030 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
2031 .end_trb = &xhci->event_ring->first_seg->trbs[1],
2032 .input_dma = xhci->event_ring->first_seg->dma + 2*16,
2035 /* TRB in this ring, but before this wrapped TD */
2036 { .input_seg = xhci->event_ring->first_seg,
2037 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
2038 .end_trb = &xhci->event_ring->first_seg->trbs[1],
2039 .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
2042 /* TRB not in this ring, and we have a wrapped TD */
2043 { .input_seg = xhci->event_ring->first_seg,
2044 .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
2045 .end_trb = &xhci->event_ring->first_seg->trbs[1],
2046 .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
2051 unsigned int num_tests;
2054 num_tests = ARRAY_SIZE(simple_test_vector);
2055 for (i = 0; i < num_tests; i++) {
2056 ret = xhci_test_trb_in_td(xhci,
2057 xhci->event_ring->first_seg,
2058 xhci->event_ring->first_seg->trbs,
2059 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
2060 simple_test_vector[i].input_dma,
2061 simple_test_vector[i].result_seg,
2067 num_tests = ARRAY_SIZE(complex_test_vector);
2068 for (i = 0; i < num_tests; i++) {
2069 ret = xhci_test_trb_in_td(xhci,
2070 complex_test_vector[i].input_seg,
2071 complex_test_vector[i].start_trb,
2072 complex_test_vector[i].end_trb,
2073 complex_test_vector[i].input_dma,
2074 complex_test_vector[i].result_seg,
2079 xhci_dbg(xhci, "TRB math tests passed.\n");
2083 static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
2088 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2089 xhci->event_ring->dequeue);
2090 if (deq == 0 && !in_interrupt())
2091 xhci_warn(xhci, "WARN something wrong with SW event ring "
2093 /* Update HC event ring dequeue pointer */
2094 temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2095 temp &= ERST_PTR_MASK;
2096 /* Don't clear the EHB bit (which is RW1C) because
2097 * there might be more events to service.
2100 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2101 "// Write event ring dequeue pointer, "
2102 "preserving EHB bit");
2103 xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
2104 &xhci->ir_set->erst_dequeue);
2107 static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
2108 __le32 __iomem *addr, int max_caps)
2110 u32 temp, port_offset, port_count;
2112 u8 major_revision, minor_revision;
2113 struct xhci_hub *rhub;
2114 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2117 major_revision = XHCI_EXT_PORT_MAJOR(temp);
2118 minor_revision = XHCI_EXT_PORT_MINOR(temp);
2120 if (major_revision == 0x03) {
2121 rhub = &xhci->usb3_rhub;
2122 } else if (major_revision <= 0x02) {
2123 rhub = &xhci->usb2_rhub;
2125 xhci_warn(xhci, "Ignoring unknown port speed, "
2126 "Ext Cap %p, revision = 0x%x\n",
2127 addr, major_revision);
2128 /* Ignoring port protocol we can't understand. FIXME */
2131 rhub->maj_rev = XHCI_EXT_PORT_MAJOR(temp);
2133 if (rhub->min_rev < minor_revision)
2134 rhub->min_rev = minor_revision;
2136 /* Port offset and count in the third dword, see section 7.2 */
2137 temp = readl(addr + 2);
2138 port_offset = XHCI_EXT_PORT_OFF(temp);
2139 port_count = XHCI_EXT_PORT_COUNT(temp);
2140 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2141 "Ext Cap %p, port offset = %u, "
2142 "count = %u, revision = 0x%x",
2143 addr, port_offset, port_count, major_revision);
2144 /* Port count includes the current port offset */
2145 if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
2146 /* WTF? "Valid values are ‘1’ to MaxPorts" */
2149 rhub->psi_count = XHCI_EXT_PORT_PSIC(temp);
2150 if (rhub->psi_count) {
2151 rhub->psi = kcalloc_node(rhub->psi_count, sizeof(*rhub->psi),
2152 GFP_KERNEL, dev_to_node(dev));
2154 rhub->psi_count = 0;
2156 rhub->psi_uid_count++;
2157 for (i = 0; i < rhub->psi_count; i++) {
2158 rhub->psi[i] = readl(addr + 4 + i);
2160 /* count unique ID values, two consecutive entries can
2161 * have the same ID if link is assymetric
2163 if (i && (XHCI_EXT_PORT_PSIV(rhub->psi[i]) !=
2164 XHCI_EXT_PORT_PSIV(rhub->psi[i - 1])))
2165 rhub->psi_uid_count++;
2167 xhci_dbg(xhci, "PSIV:%d PSIE:%d PLT:%d PFD:%d LP:%d PSIM:%d\n",
2168 XHCI_EXT_PORT_PSIV(rhub->psi[i]),
2169 XHCI_EXT_PORT_PSIE(rhub->psi[i]),
2170 XHCI_EXT_PORT_PLT(rhub->psi[i]),
2171 XHCI_EXT_PORT_PFD(rhub->psi[i]),
2172 XHCI_EXT_PORT_LP(rhub->psi[i]),
2173 XHCI_EXT_PORT_PSIM(rhub->psi[i]));
2176 /* cache usb2 port capabilities */
2177 if (major_revision < 0x03 && xhci->num_ext_caps < max_caps)
2178 xhci->ext_caps[xhci->num_ext_caps++] = temp;
2180 /* Check the host's USB2 LPM capability */
2181 if ((xhci->hci_version == 0x96) && (major_revision != 0x03) &&
2182 (temp & XHCI_L1C)) {
2183 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2184 "xHCI 0.96: support USB2 software lpm");
2185 xhci->sw_lpm_support = 1;
2188 if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) {
2189 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2190 "xHCI 1.0: support USB2 software lpm");
2191 xhci->sw_lpm_support = 1;
2192 if (temp & XHCI_HLC) {
2193 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2194 "xHCI 1.0: support USB2 hardware lpm");
2195 xhci->hw_lpm_support = 1;
2200 for (i = port_offset; i < (port_offset + port_count); i++) {
2201 struct xhci_port *hw_port = &xhci->hw_ports[i];
2202 /* Duplicate entry. Ignore the port if the revisions differ. */
2203 if (hw_port->rhub) {
2204 xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
2205 " port %u\n", addr, i);
2206 xhci_warn(xhci, "Port was marked as USB %u, "
2207 "duplicated as USB %u\n",
2208 hw_port->rhub->maj_rev, major_revision);
2209 /* Only adjust the roothub port counts if we haven't
2210 * found a similar duplicate.
2212 if (hw_port->rhub != rhub &&
2213 hw_port->hcd_portnum != DUPLICATE_ENTRY) {
2214 hw_port->rhub->num_ports--;
2215 hw_port->hcd_portnum = DUPLICATE_ENTRY;
2219 hw_port->rhub = rhub;
2222 /* FIXME: Should we disable ports not in the Extended Capabilities? */
2225 static void xhci_create_rhub_port_array(struct xhci_hcd *xhci,
2226 struct xhci_hub *rhub, gfp_t flags)
2230 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2232 if (!rhub->num_ports)
2234 rhub->ports = kcalloc_node(rhub->num_ports, sizeof(rhub->ports), flags,
2236 for (i = 0; i < HCS_MAX_PORTS(xhci->hcs_params1); i++) {
2237 if (xhci->hw_ports[i].rhub != rhub ||
2238 xhci->hw_ports[i].hcd_portnum == DUPLICATE_ENTRY)
2240 xhci->hw_ports[i].hcd_portnum = port_index;
2241 rhub->ports[port_index] = &xhci->hw_ports[i];
2243 if (port_index == rhub->num_ports)
2249 * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2250 * specify what speeds each port is supposed to be. We can't count on the port
2251 * speed bits in the PORTSC register being correct until a device is connected,
2252 * but we need to set up the two fake roothubs with the correct number of USB
2253 * 3.0 and USB 2.0 ports at host controller initialization time.
2255 static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
2259 unsigned int num_ports;
2263 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2265 num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
2266 xhci->hw_ports = kcalloc_node(num_ports, sizeof(*xhci->hw_ports),
2267 flags, dev_to_node(dev));
2268 if (!xhci->hw_ports)
2271 for (i = 0; i < num_ports; i++) {
2272 xhci->hw_ports[i].addr = &xhci->op_regs->port_status_base +
2274 xhci->hw_ports[i].hw_portnum = i;
2277 xhci->rh_bw = kcalloc_node(num_ports, sizeof(*xhci->rh_bw), flags,
2281 for (i = 0; i < num_ports; i++) {
2282 struct xhci_interval_bw_table *bw_table;
2284 INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
2285 bw_table = &xhci->rh_bw[i].bw_table;
2286 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
2287 INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
2289 base = &xhci->cap_regs->hc_capbase;
2291 cap_start = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_PROTOCOL);
2293 xhci_err(xhci, "No Extended Capability registers, unable to set up roothub\n");
2298 /* count extended protocol capability entries for later caching */
2301 offset = xhci_find_next_ext_cap(base, offset,
2302 XHCI_EXT_CAPS_PROTOCOL);
2305 xhci->ext_caps = kcalloc_node(cap_count, sizeof(*xhci->ext_caps),
2306 flags, dev_to_node(dev));
2307 if (!xhci->ext_caps)
2313 xhci_add_in_port(xhci, num_ports, base + offset, cap_count);
2314 if (xhci->usb2_rhub.num_ports + xhci->usb3_rhub.num_ports ==
2317 offset = xhci_find_next_ext_cap(base, offset,
2318 XHCI_EXT_CAPS_PROTOCOL);
2320 if (xhci->usb2_rhub.num_ports == 0 && xhci->usb3_rhub.num_ports == 0) {
2321 xhci_warn(xhci, "No ports on the roothubs?\n");
2324 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2325 "Found %u USB 2.0 ports and %u USB 3.0 ports.",
2326 xhci->usb2_rhub.num_ports, xhci->usb3_rhub.num_ports);
2328 /* Place limits on the number of roothub ports so that the hub
2329 * descriptors aren't longer than the USB core will allocate.
2331 if (xhci->usb3_rhub.num_ports > USB_SS_MAXPORTS) {
2332 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2333 "Limiting USB 3.0 roothub ports to %u.",
2335 xhci->usb3_rhub.num_ports = USB_SS_MAXPORTS;
2337 if (xhci->usb2_rhub.num_ports > USB_MAXCHILDREN) {
2338 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2339 "Limiting USB 2.0 roothub ports to %u.",
2341 xhci->usb2_rhub.num_ports = USB_MAXCHILDREN;
2345 * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2346 * Not sure how the USB core will handle a hub with no ports...
2349 xhci_create_rhub_port_array(xhci, &xhci->usb2_rhub, flags);
2350 xhci_create_rhub_port_array(xhci, &xhci->usb3_rhub, flags);
2355 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2358 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
2359 unsigned int val, val2;
2361 u32 page_size, temp;
2364 INIT_LIST_HEAD(&xhci->cmd_list);
2366 /* init command timeout work */
2367 INIT_DELAYED_WORK(&xhci->cmd_timer, xhci_handle_command_timeout);
2368 init_completion(&xhci->cmd_ring_stop_completion);
2370 page_size = readl(&xhci->op_regs->page_size);
2371 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2372 "Supported page size register = 0x%x", page_size);
2373 for (i = 0; i < 16; i++) {
2374 if ((0x1 & page_size) != 0)
2376 page_size = page_size >> 1;
2379 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2380 "Supported page size of %iK", (1 << (i+12)) / 1024);
2382 xhci_warn(xhci, "WARN: no supported page size\n");
2383 /* Use 4K pages, since that's common and the minimum the HC supports */
2384 xhci->page_shift = 12;
2385 xhci->page_size = 1 << xhci->page_shift;
2386 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2387 "HCD page size set to %iK", xhci->page_size / 1024);
2390 * Program the Number of Device Slots Enabled field in the CONFIG
2391 * register with the max value of slots the HC can handle.
2393 val = HCS_MAX_SLOTS(readl(&xhci->cap_regs->hcs_params1));
2394 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2395 "// xHC can handle at most %d device slots.", val);
2396 val2 = readl(&xhci->op_regs->config_reg);
2397 val |= (val2 & ~HCS_SLOTS_MASK);
2398 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2399 "// Setting Max device slots reg = 0x%x.", val);
2400 writel(val, &xhci->op_regs->config_reg);
2403 * xHCI section 5.4.6 - doorbell array must be
2404 * "physically contiguous and 64-byte (cache line) aligned".
2406 xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma,
2410 memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
2411 xhci->dcbaa->dma = dma;
2412 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2413 "// Device context base array address = 0x%llx (DMA), %p (virt)",
2414 (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
2415 xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
2418 * Initialize the ring segment pool. The ring must be a contiguous
2419 * structure comprised of TRBs. The TRBs must be 16 byte aligned,
2420 * however, the command ring segment needs 64-byte aligned segments
2421 * and our use of dma addresses in the trb_address_map radix tree needs
2422 * TRB_SEGMENT_SIZE alignment, so we pick the greater alignment need.
2424 xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2425 TRB_SEGMENT_SIZE, TRB_SEGMENT_SIZE, xhci->page_size);
2427 /* See Table 46 and Note on Figure 55 */
2428 xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
2429 2112, 64, xhci->page_size);
2430 if (!xhci->segment_pool || !xhci->device_pool)
2433 /* Linear stream context arrays don't have any boundary restrictions,
2434 * and only need to be 16-byte aligned.
2436 xhci->small_streams_pool =
2437 dma_pool_create("xHCI 256 byte stream ctx arrays",
2438 dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
2439 xhci->medium_streams_pool =
2440 dma_pool_create("xHCI 1KB stream ctx arrays",
2441 dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
2442 /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2443 * will be allocated with dma_alloc_coherent()
2446 if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
2449 /* Set up the command ring to have one segments for now. */
2450 xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, 0, flags);
2451 if (!xhci->cmd_ring)
2453 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2454 "Allocated command ring at %p", xhci->cmd_ring);
2455 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "First segment DMA is 0x%llx",
2456 (unsigned long long)xhci->cmd_ring->first_seg->dma);
2458 /* Set the address in the Command Ring Control register */
2459 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2460 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2461 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2462 xhci->cmd_ring->cycle_state;
2463 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2464 "// Setting command ring address to 0x%016llx", val_64);
2465 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2467 xhci->lpm_command = xhci_alloc_command_with_ctx(xhci, true, flags);
2468 if (!xhci->lpm_command)
2471 /* Reserve one command ring TRB for disabling LPM.
2472 * Since the USB core grabs the shared usb_bus bandwidth mutex before
2473 * disabling LPM, we only need to reserve one TRB for all devices.
2475 xhci->cmd_ring_reserved_trbs++;
2477 val = readl(&xhci->cap_regs->db_off);
2479 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2480 "// Doorbell array is located at offset 0x%x"
2481 " from cap regs base addr", val);
2482 xhci->dba = (void __iomem *) xhci->cap_regs + val;
2483 /* Set ir_set to interrupt register set 0 */
2484 xhci->ir_set = &xhci->run_regs->ir_set[0];
2487 * Event ring setup: Allocate a normal ring, but also setup
2488 * the event ring segment table (ERST). Section 4.9.3.
2490 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Allocating event ring");
2491 xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT,
2493 if (!xhci->event_ring)
2495 if (xhci_check_trb_in_td_math(xhci) < 0)
2498 ret = xhci_alloc_erst(xhci, xhci->event_ring, &xhci->erst, flags);
2502 /* set ERST count with the number of entries in the segment table */
2503 val = readl(&xhci->ir_set->erst_size);
2504 val &= ERST_SIZE_MASK;
2505 val |= ERST_NUM_SEGS;
2506 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2507 "// Write ERST size = %i to ir_set 0 (some bits preserved)",
2509 writel(val, &xhci->ir_set->erst_size);
2511 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2512 "// Set ERST entries to point to event ring.");
2513 /* set the segment table base address */
2514 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2515 "// Set ERST base address for ir_set 0 = 0x%llx",
2516 (unsigned long long)xhci->erst.erst_dma_addr);
2517 val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2518 val_64 &= ERST_PTR_MASK;
2519 val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2520 xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
2522 /* Set the event ring dequeue address */
2523 xhci_set_hc_event_deq(xhci);
2524 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
2525 "Wrote ERST address to ir_set 0.");
2528 * XXX: Might need to set the Interrupter Moderation Register to
2529 * something other than the default (~1ms minimum between interrupts).
2530 * See section 5.5.1.2.
2532 for (i = 0; i < MAX_HC_SLOTS; i++)
2533 xhci->devs[i] = NULL;
2534 for (i = 0; i < USB_MAXCHILDREN; i++) {
2535 xhci->bus_state[0].resume_done[i] = 0;
2536 xhci->bus_state[1].resume_done[i] = 0;
2537 /* Only the USB 2.0 completions will ever be used. */
2538 init_completion(&xhci->bus_state[1].rexit_done[i]);
2541 if (scratchpad_alloc(xhci, flags))
2543 if (xhci_setup_port_arrays(xhci, flags))
2546 /* Enable USB 3.0 device notifications for function remote wake, which
2547 * is necessary for allowing USB 3.0 devices to do remote wakeup from
2548 * U3 (device suspend).
2550 temp = readl(&xhci->op_regs->dev_notification);
2551 temp &= ~DEV_NOTE_MASK;
2552 temp |= DEV_NOTE_FWAKE;
2553 writel(temp, &xhci->op_regs->dev_notification);
2560 xhci_mem_cleanup(xhci);