1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
12 #include <linux/slab.h>
13 #include <asm/unaligned.h>
16 #include "xhci-trace.h"
18 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
19 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
20 PORT_RC | PORT_PLC | PORT_PE)
22 /* USB 3 BOS descriptor and a capability descriptors, combined.
23 * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
25 static u8 usb_bos_descriptor [] = {
26 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
27 USB_DT_BOS, /* __u8 bDescriptorType */
28 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
29 0x1, /* __u8 bNumDeviceCaps */
30 /* First device capability, SuperSpeed */
31 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
32 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
33 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
34 0x00, /* bmAttributes, LTM off by default */
35 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
36 0x03, /* bFunctionalitySupport,
38 0x00, /* bU1DevExitLat, set later. */
39 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */
40 /* Second device capability, SuperSpeedPlus */
41 0x1c, /* bLength 28, will be adjusted later */
42 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
43 USB_SSP_CAP_TYPE, /* bDevCapabilityType SUPERSPEED_PLUS */
44 0x00, /* bReserved 0 */
45 0x23, 0x00, 0x00, 0x00, /* bmAttributes, SSAC=3 SSIC=1 */
46 0x01, 0x00, /* wFunctionalitySupport */
47 0x00, 0x00, /* wReserved 0 */
48 /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
49 0x34, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, rx, ID = 4 */
50 0xb4, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, tx, ID = 4 */
51 0x35, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, rx, ID = 5 */
52 0xb5, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, tx, ID = 5 */
55 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
58 struct xhci_port_cap *port_cap = NULL;
61 u16 desc_size, ssp_cap_size, ssa_size = 0;
64 desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
65 ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
67 /* does xhci support USB 3.1 Enhanced SuperSpeed */
68 for (i = 0; i < xhci->num_port_caps; i++) {
69 if (xhci->port_caps[i].maj_rev == 0x03 &&
70 xhci->port_caps[i].min_rev >= 0x01) {
72 port_cap = &xhci->port_caps[i];
78 /* does xhci provide a PSI table for SSA speed attributes? */
79 if (port_cap->psi_count) {
80 /* two SSA entries for each unique PSI ID, RX and TX */
81 ssa_count = port_cap->psi_uid_count * 2;
82 ssa_size = ssa_count * sizeof(u32);
83 ssp_cap_size -= 16; /* skip copying the default SSA */
85 desc_size += ssp_cap_size;
87 memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
90 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
92 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
95 if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
98 /* Indicate whether the host has LTM support. */
99 temp = readl(&xhci->cap_regs->hcc_params);
101 buf[8] |= USB_LTM_SUPPORT;
103 /* Set the U1 and U2 exit latencies. */
104 if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
105 temp = readl(&xhci->cap_regs->hcs_params3);
106 buf[12] = HCS_U1_LATENCY(temp);
107 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
110 /* If PSI table exists, add the custom speed attributes from it */
111 if (usb3_1 && port_cap->psi_count) {
112 u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
115 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
117 if (wLength < desc_size)
119 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
121 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
122 bm_attrib = (ssa_count - 1) & 0x1f;
123 bm_attrib |= (port_cap->psi_uid_count - 1) << 5;
124 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
126 if (wLength < desc_size + ssa_size)
129 * Create the Sublink Speed Attributes (SSA) array.
130 * The xhci PSI field and USB 3.1 SSA fields are very similar,
131 * but link type bits 7:6 differ for values 01b and 10b.
132 * xhci has also only one PSI entry for a symmetric link when
133 * USB 3.1 requires two SSA entries (RX and TX) for every link
136 for (i = 0; i < port_cap->psi_count; i++) {
137 psi = port_cap->psi[i];
138 psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
139 psi_exp = XHCI_EXT_PORT_PSIE(psi);
140 psi_mant = XHCI_EXT_PORT_PSIM(psi);
142 /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
143 for (; psi_exp < 3; psi_exp++)
148 if ((psi & PLT_MASK) == PLT_SYM) {
149 /* Symmetric, create SSA RX and TX from one PSI entry */
150 put_unaligned_le32(psi, &buf[offset]);
151 psi |= 1 << 7; /* turn entry to TX */
153 if (offset >= desc_size + ssa_size)
154 return desc_size + ssa_size;
155 } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
156 /* Asymetric RX, flip bits 7:6 for SSA */
159 put_unaligned_le32(psi, &buf[offset]);
161 if (offset >= desc_size + ssa_size)
162 return desc_size + ssa_size;
165 /* ssa_size is 0 for other than usb 3.1 hosts */
166 return desc_size + ssa_size;
169 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
170 struct usb_hub_descriptor *desc, int ports)
174 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
175 desc->bHubContrCurrent = 0;
177 desc->bNbrPorts = ports;
179 /* Bits 1:0 - support per-port power switching, or power always on */
180 if (HCC_PPC(xhci->hcc_params))
181 temp |= HUB_CHAR_INDV_PORT_LPSM;
183 temp |= HUB_CHAR_NO_LPSM;
184 /* Bit 2 - root hubs are not part of a compound device */
185 /* Bits 4:3 - individual port over current protection */
186 temp |= HUB_CHAR_INDV_PORT_OCPM;
187 /* Bits 6:5 - no TTs in root ports */
188 /* Bit 7 - no port indicators */
189 desc->wHubCharacteristics = cpu_to_le16(temp);
192 /* Fill in the USB 2.0 roothub descriptor */
193 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
194 struct usb_hub_descriptor *desc)
198 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
201 struct xhci_hub *rhub;
203 rhub = &xhci->usb2_rhub;
204 ports = rhub->num_ports;
205 xhci_common_hub_descriptor(xhci, desc, ports);
206 desc->bDescriptorType = USB_DT_HUB;
207 temp = 1 + (ports / 8);
208 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
210 /* The Device Removable bits are reported on a byte granularity.
211 * If the port doesn't exist within that byte, the bit is set to 0.
213 memset(port_removable, 0, sizeof(port_removable));
214 for (i = 0; i < ports; i++) {
215 portsc = readl(rhub->ports[i]->addr);
216 /* If a device is removable, PORTSC reports a 0, same as in the
217 * hub descriptor DeviceRemovable bits.
219 if (portsc & PORT_DEV_REMOVE)
220 /* This math is hairy because bit 0 of DeviceRemovable
221 * is reserved, and bit 1 is for port 1, etc.
223 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
226 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
227 * ports on it. The USB 2.0 specification says that there are two
228 * variable length fields at the end of the hub descriptor:
229 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
230 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
231 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
232 * 0xFF, so we initialize the both arrays (DeviceRemovable and
233 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
234 * set of ports that actually exist.
236 memset(desc->u.hs.DeviceRemovable, 0xff,
237 sizeof(desc->u.hs.DeviceRemovable));
238 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
239 sizeof(desc->u.hs.PortPwrCtrlMask));
241 for (i = 0; i < (ports + 1 + 7) / 8; i++)
242 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
246 /* Fill in the USB 3.0 roothub descriptor */
247 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
248 struct usb_hub_descriptor *desc)
254 struct xhci_hub *rhub;
256 rhub = &xhci->usb3_rhub;
257 ports = rhub->num_ports;
258 xhci_common_hub_descriptor(xhci, desc, ports);
259 desc->bDescriptorType = USB_DT_SS_HUB;
260 desc->bDescLength = USB_DT_SS_HUB_SIZE;
262 /* header decode latency should be zero for roothubs,
263 * see section 4.23.5.2.
265 desc->u.ss.bHubHdrDecLat = 0;
266 desc->u.ss.wHubDelay = 0;
269 /* bit 0 is reserved, bit 1 is for port 1, etc. */
270 for (i = 0; i < ports; i++) {
271 portsc = readl(rhub->ports[i]->addr);
272 if (portsc & PORT_DEV_REMOVE)
273 port_removable |= 1 << (i + 1);
276 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
279 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
280 struct usb_hub_descriptor *desc)
283 if (hcd->speed >= HCD_USB3)
284 xhci_usb3_hub_descriptor(hcd, xhci, desc);
286 xhci_usb2_hub_descriptor(hcd, xhci, desc);
290 static unsigned int xhci_port_speed(unsigned int port_status)
292 if (DEV_LOWSPEED(port_status))
293 return USB_PORT_STAT_LOW_SPEED;
294 if (DEV_HIGHSPEED(port_status))
295 return USB_PORT_STAT_HIGH_SPEED;
297 * FIXME: Yes, we should check for full speed, but the core uses that as
298 * a default in portspeed() in usb/core/hub.c (which is the only place
299 * USB_PORT_STAT_*_SPEED is used).
305 * These bits are Read Only (RO) and should be saved and written to the
306 * registers: 0, 3, 10:13, 30
307 * connect status, over-current status, port speed, and device removable.
308 * connect status and port speed are also sticky - meaning they're in
309 * the AUX well and they aren't changed by a hot, warm, or cold reset.
311 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
313 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
314 * bits 5:8, 9, 14:15, 25:27
315 * link state, port power, port indicator state, "wake on" enable state
317 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
319 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
322 #define XHCI_PORT_RW1S ((1<<4))
324 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
325 * bits 1, 17, 18, 19, 20, 21, 22, 23
326 * port enable/disable, and
327 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
328 * over-current, reset, link state, and L1 change
330 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
332 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
335 #define XHCI_PORT_RW ((1<<16))
337 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
340 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
343 * Given a port state, this function returns a value that would result in the
344 * port being in the same state, if the value was written to the port status
346 * Save Read Only (RO) bits and save read/write bits where
347 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
348 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
350 u32 xhci_port_state_to_neutral(u32 state)
352 /* Save read-only status and port state */
353 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
357 * find slot id based on port number.
358 * @port: The one-based port number from one of the two split roothubs.
360 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
365 enum usb_device_speed speed;
368 for (i = 0; i < MAX_HC_SLOTS; i++) {
369 if (!xhci->devs[i] || !xhci->devs[i]->udev)
371 speed = xhci->devs[i]->udev->speed;
372 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
373 && xhci->devs[i]->fake_port == port) {
384 * It issues stop endpoint command for EP 0 to 30. And wait the last command
386 * suspend will set to 1, if suspend bit need to set in command.
388 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
390 struct xhci_virt_device *virt_dev;
391 struct xhci_command *cmd;
397 virt_dev = xhci->devs[slot_id];
401 trace_xhci_stop_device(virt_dev);
403 cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
407 spin_lock_irqsave(&xhci->lock, flags);
408 for (i = LAST_EP_INDEX; i > 0; i--) {
409 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
410 struct xhci_ep_ctx *ep_ctx;
411 struct xhci_command *command;
413 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
415 /* Check ep is running, required by AMD SNPS 3.1 xHC */
416 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
419 command = xhci_alloc_command(xhci, false, GFP_NOWAIT);
421 spin_unlock_irqrestore(&xhci->lock, flags);
426 ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
429 spin_unlock_irqrestore(&xhci->lock, flags);
430 xhci_free_command(xhci, command);
435 ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
437 spin_unlock_irqrestore(&xhci->lock, flags);
441 xhci_ring_cmd_db(xhci);
442 spin_unlock_irqrestore(&xhci->lock, flags);
444 /* Wait for last stop endpoint command to finish */
445 wait_for_completion(cmd->completion);
447 if (cmd->status == COMP_COMMAND_ABORTED ||
448 cmd->status == COMP_COMMAND_RING_STOPPED) {
449 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
454 xhci_free_command(xhci, cmd);
459 * Ring device, it rings the all doorbells unconditionally.
461 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
464 struct xhci_virt_ep *ep;
466 for (i = 0; i < LAST_EP_INDEX + 1; i++) {
467 ep = &xhci->devs[slot_id]->eps[i];
469 if (ep->ep_state & EP_HAS_STREAMS) {
470 for (s = 1; s < ep->stream_info->num_streams; s++)
471 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
472 } else if (ep->ring && ep->ring->dequeue) {
473 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
480 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
481 u16 wIndex, __le32 __iomem *addr, u32 port_status)
483 /* Don't allow the USB core to disable SuperSpeed ports. */
484 if (hcd->speed >= HCD_USB3) {
485 xhci_dbg(xhci, "Ignoring request to disable "
486 "SuperSpeed port.\n");
490 if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
492 "Broken Port Enabled/Disabled, ignoring port disable request.\n");
496 /* Write 1 to disable the port */
497 writel(port_status | PORT_PE, addr);
498 port_status = readl(addr);
499 xhci_dbg(xhci, "disable port %d-%d, portsc: 0x%x\n",
500 hcd->self.busnum, wIndex + 1, port_status);
503 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
504 u16 wIndex, __le32 __iomem *addr, u32 port_status)
506 char *port_change_bit;
510 case USB_PORT_FEAT_C_RESET:
512 port_change_bit = "reset";
514 case USB_PORT_FEAT_C_BH_PORT_RESET:
516 port_change_bit = "warm(BH) reset";
518 case USB_PORT_FEAT_C_CONNECTION:
520 port_change_bit = "connect";
522 case USB_PORT_FEAT_C_OVER_CURRENT:
524 port_change_bit = "over-current";
526 case USB_PORT_FEAT_C_ENABLE:
528 port_change_bit = "enable/disable";
530 case USB_PORT_FEAT_C_SUSPEND:
532 port_change_bit = "suspend/resume";
534 case USB_PORT_FEAT_C_PORT_LINK_STATE:
536 port_change_bit = "link state";
538 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
540 port_change_bit = "config error";
543 /* Should never happen */
546 /* Change bits are all write 1 to clear */
547 writel(port_status | status, addr);
548 port_status = readl(addr);
550 xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n",
551 wIndex + 1, port_change_bit, port_status);
554 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
556 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
558 if (hcd->speed >= HCD_USB3)
559 return &xhci->usb3_rhub;
560 return &xhci->usb2_rhub;
564 * xhci_set_port_power() must be called with xhci->lock held.
565 * It will release and re-aquire the lock while calling ACPI
568 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
569 u16 index, bool on, unsigned long *flags)
571 struct xhci_hub *rhub;
572 struct xhci_port *port;
575 rhub = xhci_get_rhub(hcd);
576 port = rhub->ports[index];
577 temp = readl(port->addr);
579 xhci_dbg(xhci, "set port power %d-%d %s, portsc: 0x%x\n",
580 hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp);
582 temp = xhci_port_state_to_neutral(temp);
586 writel(temp | PORT_POWER, port->addr);
590 writel(temp & ~PORT_POWER, port->addr);
593 spin_unlock_irqrestore(&xhci->lock, *flags);
594 temp = usb_acpi_power_manageable(hcd->self.root_hub,
597 usb_acpi_set_power_state(hcd->self.root_hub,
599 spin_lock_irqsave(&xhci->lock, *flags);
602 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
603 u16 test_mode, u16 wIndex)
606 struct xhci_port *port;
608 /* xhci only supports test mode for usb2 ports */
609 port = xhci->usb2_rhub.ports[wIndex];
610 temp = readl(port->addr + PORTPMSC);
611 temp |= test_mode << PORT_TEST_MODE_SHIFT;
612 writel(temp, port->addr + PORTPMSC);
613 xhci->test_mode = test_mode;
614 if (test_mode == TEST_FORCE_EN)
618 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
619 u16 test_mode, u16 wIndex, unsigned long *flags)
623 /* Disable all Device Slots */
624 xhci_dbg(xhci, "Disable all slots\n");
625 spin_unlock_irqrestore(&xhci->lock, *flags);
626 for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
630 retval = xhci_disable_slot(xhci, i);
632 xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
635 spin_lock_irqsave(&xhci->lock, *flags);
636 /* Put all ports to the Disable state by clear PP */
637 xhci_dbg(xhci, "Disable all port (PP = 0)\n");
638 /* Power off USB3 ports*/
639 for (i = 0; i < xhci->usb3_rhub.num_ports; i++)
640 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
641 /* Power off USB2 ports*/
642 for (i = 0; i < xhci->usb2_rhub.num_ports; i++)
643 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
644 /* Stop the controller */
645 xhci_dbg(xhci, "Stop controller\n");
646 retval = xhci_halt(xhci);
649 /* Disable runtime PM for test mode */
650 pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
651 /* Set PORTPMSC.PTC field to enter selected test mode */
652 /* Port is selected by wIndex. port_id = wIndex + 1 */
653 xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
654 test_mode, wIndex + 1);
655 xhci_port_set_test_mode(xhci, test_mode, wIndex);
659 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
663 if (!xhci->test_mode) {
664 xhci_err(xhci, "Not in test mode, do nothing.\n");
667 if (xhci->test_mode == TEST_FORCE_EN &&
668 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
669 retval = xhci_halt(xhci);
673 pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
675 return xhci_reset(xhci);
678 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
684 portsc = readl(port->addr);
685 temp = xhci_port_state_to_neutral(portsc);
686 temp &= ~PORT_PLS_MASK;
687 temp |= PORT_LINK_STROBE | link_state;
688 writel(temp, port->addr);
690 xhci_dbg(xhci, "Set port %d-%d link state, portsc: 0x%x, write 0x%x",
691 port->rhub->hcd->self.busnum, port->hcd_portnum + 1,
695 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
696 struct xhci_port *port, u16 wake_mask)
700 temp = readl(port->addr);
701 temp = xhci_port_state_to_neutral(temp);
703 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
704 temp |= PORT_WKCONN_E;
706 temp &= ~PORT_WKCONN_E;
708 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
709 temp |= PORT_WKDISC_E;
711 temp &= ~PORT_WKDISC_E;
713 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
716 temp &= ~PORT_WKOC_E;
718 writel(temp, port->addr);
721 /* Test and clear port RWC bit */
722 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
727 temp = readl(port->addr);
728 if (temp & port_bit) {
729 temp = xhci_port_state_to_neutral(temp);
731 writel(temp, port->addr);
735 /* Updates Link Status for super Speed port */
736 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
737 u32 *status, u32 status_reg)
739 u32 pls = status_reg & PORT_PLS_MASK;
741 /* resume state is a xHCI internal state.
742 * Do not report it to usb core, instead, pretend to be U3,
743 * thus usb core knows it's not ready for transfer
745 if (pls == XDEV_RESUME) {
746 *status |= USB_SS_PORT_LS_U3;
750 /* When the CAS bit is set then warm reset
751 * should be performed on port
753 if (status_reg & PORT_CAS) {
754 /* The CAS bit can be set while the port is
756 * Only roothubs have CAS bit, so we
757 * pretend to be in compliance mode
758 * unless we're already in compliance
759 * or the inactive state.
761 if (pls != USB_SS_PORT_LS_COMP_MOD &&
762 pls != USB_SS_PORT_LS_SS_INACTIVE) {
763 pls = USB_SS_PORT_LS_COMP_MOD;
765 /* Return also connection bit -
766 * hub state machine resets port
767 * when this bit is set.
769 pls |= USB_PORT_STAT_CONNECTION;
772 * If CAS bit isn't set but the Port is already at
773 * Compliance Mode, fake a connection so the USB core
774 * notices the Compliance state and resets the port.
775 * This resolves an issue generated by the SN65LVPE502CP
776 * in which sometimes the port enters compliance mode
777 * caused by a delay on the host-device negotiation.
779 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
780 (pls == USB_SS_PORT_LS_COMP_MOD))
781 pls |= USB_PORT_STAT_CONNECTION;
784 /* update status field */
789 * Function for Compliance Mode Quirk.
791 * This Function verifies if all xhc USB3 ports have entered U0, if so,
792 * the compliance mode timer is deleted. A port won't enter
793 * compliance mode if it has previously entered U0.
795 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
798 u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1);
799 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
801 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
804 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
805 xhci->port_status_u0 |= 1 << wIndex;
806 if (xhci->port_status_u0 == all_ports_seen_u0) {
807 del_timer_sync(&xhci->comp_mode_recovery_timer);
808 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
809 "All USB3 ports have entered U0 already!");
810 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
811 "Compliance Mode Recovery Timer Deleted.");
816 static int xhci_handle_usb2_port_link_resume(struct xhci_port *port,
817 u32 *status, u32 portsc,
818 unsigned long *flags)
820 struct xhci_bus_state *bus_state;
821 struct xhci_hcd *xhci;
826 hcd = port->rhub->hcd;
827 bus_state = &port->rhub->bus_state;
828 xhci = hcd_to_xhci(hcd);
829 wIndex = port->hcd_portnum;
831 if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) {
832 *status = 0xffffffff;
835 /* did port event handler already start resume timing? */
836 if (!bus_state->resume_done[wIndex]) {
837 /* If not, maybe we are in a host initated resume? */
838 if (test_bit(wIndex, &bus_state->resuming_ports)) {
839 /* Host initated resume doesn't time the resume
840 * signalling using resume_done[].
841 * It manually sets RESUME state, sleeps 20ms
842 * and sets U0 state. This should probably be
843 * changed, but not right now.
846 /* port resume was discovered now and here,
847 * start resume timing
849 unsigned long timeout = jiffies +
850 msecs_to_jiffies(USB_RESUME_TIMEOUT);
852 set_bit(wIndex, &bus_state->resuming_ports);
853 bus_state->resume_done[wIndex] = timeout;
854 mod_timer(&hcd->rh_timer, timeout);
855 usb_hcd_start_port_resume(&hcd->self, wIndex);
857 /* Has resume been signalled for USB_RESUME_TIME yet? */
858 } else if (time_after_eq(jiffies, bus_state->resume_done[wIndex])) {
861 xhci_dbg(xhci, "resume USB2 port %d-%d\n",
862 hcd->self.busnum, wIndex + 1);
864 bus_state->resume_done[wIndex] = 0;
865 clear_bit(wIndex, &bus_state->resuming_ports);
867 set_bit(wIndex, &bus_state->rexit_ports);
869 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
870 xhci_set_link_state(xhci, port, XDEV_U0);
872 spin_unlock_irqrestore(&xhci->lock, *flags);
873 time_left = wait_for_completion_timeout(
874 &bus_state->rexit_done[wIndex],
875 msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS));
876 spin_lock_irqsave(&xhci->lock, *flags);
879 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
882 xhci_dbg(xhci, "slot_id is zero\n");
883 *status = 0xffffffff;
886 xhci_ring_device(xhci, slot_id);
888 int port_status = readl(port->addr);
890 xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n",
891 hcd->self.busnum, wIndex + 1, port_status);
892 *status |= USB_PORT_STAT_SUSPEND;
893 clear_bit(wIndex, &bus_state->rexit_ports);
896 usb_hcd_end_port_resume(&hcd->self, wIndex);
897 bus_state->port_c_suspend |= 1 << wIndex;
898 bus_state->suspended_ports &= ~(1 << wIndex);
901 * The resume has been signaling for less than
902 * USB_RESUME_TIME. Report the port status as SUSPEND,
903 * let the usbcore check port status again and clear
904 * resume signaling later.
906 *status |= USB_PORT_STAT_SUSPEND;
911 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
916 /* only support rx and tx lane counts of 1 in usb3.1 spec */
917 speed_id = DEV_PORT_SPEED(raw_port_status);
918 ext_stat |= speed_id; /* bits 3:0, RX speed id */
919 ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */
921 ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */
922 ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
927 static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status,
930 struct xhci_bus_state *bus_state;
931 struct xhci_hcd *xhci;
936 bus_state = &port->rhub->bus_state;
937 xhci = hcd_to_xhci(port->rhub->hcd);
938 hcd = port->rhub->hcd;
939 link_state = portsc & PORT_PLS_MASK;
940 portnum = port->hcd_portnum;
942 /* USB3 specific wPortChange bits
944 * Port link change with port in resume state should not be
945 * reported to usbcore, as this is an internal state to be
946 * handled by xhci driver. Reporting PLC to usbcore may
947 * cause usbcore clearing PLC first and port change event
948 * irq won't be generated.
951 if (portsc & PORT_PLC && (link_state != XDEV_RESUME))
952 *status |= USB_PORT_STAT_C_LINK_STATE << 16;
953 if (portsc & PORT_WRC)
954 *status |= USB_PORT_STAT_C_BH_RESET << 16;
955 if (portsc & PORT_CEC)
956 *status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
958 /* USB3 specific wPortStatus bits */
959 if (portsc & PORT_POWER) {
960 *status |= USB_SS_PORT_STAT_POWER;
961 /* link state handling */
962 if (link_state == XDEV_U0)
963 bus_state->suspended_ports &= ~(1 << portnum);
966 /* remote wake resume signaling complete */
967 if (bus_state->port_remote_wakeup & (1 << portnum) &&
968 link_state != XDEV_RESUME &&
969 link_state != XDEV_RECOVERY) {
970 bus_state->port_remote_wakeup &= ~(1 << portnum);
971 usb_hcd_end_port_resume(&hcd->self, portnum);
974 xhci_hub_report_usb3_link_state(xhci, status, portsc);
975 xhci_del_comp_mod_timer(xhci, portsc, portnum);
978 static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status,
979 u32 portsc, unsigned long *flags)
981 struct xhci_bus_state *bus_state;
986 bus_state = &port->rhub->bus_state;
987 link_state = portsc & PORT_PLS_MASK;
988 portnum = port->hcd_portnum;
990 /* USB2 wPortStatus bits */
991 if (portsc & PORT_POWER) {
992 *status |= USB_PORT_STAT_POWER;
994 /* link state is only valid if port is powered */
995 if (link_state == XDEV_U3)
996 *status |= USB_PORT_STAT_SUSPEND;
997 if (link_state == XDEV_U2)
998 *status |= USB_PORT_STAT_L1;
999 if (link_state == XDEV_U0) {
1000 bus_state->resume_done[portnum] = 0;
1001 clear_bit(portnum, &bus_state->resuming_ports);
1002 if (bus_state->suspended_ports & (1 << portnum)) {
1003 bus_state->suspended_ports &= ~(1 << portnum);
1004 bus_state->port_c_suspend |= 1 << portnum;
1007 if (link_state == XDEV_RESUME) {
1008 ret = xhci_handle_usb2_port_link_resume(port, status,
1017 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
1020 * Possible side effects:
1021 * - Mark a port as being done with device resume,
1022 * and ring the endpoint doorbells.
1023 * - Stop the Synopsys redriver Compliance Mode polling.
1024 * - Drop and reacquire the xHCI lock, in order to wait for port resume.
1026 static u32 xhci_get_port_status(struct usb_hcd *hcd,
1027 struct xhci_bus_state *bus_state,
1028 u16 wIndex, u32 raw_port_status,
1029 unsigned long *flags)
1030 __releases(&xhci->lock)
1031 __acquires(&xhci->lock)
1034 struct xhci_hub *rhub;
1035 struct xhci_port *port;
1037 rhub = xhci_get_rhub(hcd);
1038 port = rhub->ports[wIndex];
1040 /* common wPortChange bits */
1041 if (raw_port_status & PORT_CSC)
1042 status |= USB_PORT_STAT_C_CONNECTION << 16;
1043 if (raw_port_status & PORT_PEC)
1044 status |= USB_PORT_STAT_C_ENABLE << 16;
1045 if ((raw_port_status & PORT_OCC))
1046 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1047 if ((raw_port_status & PORT_RC))
1048 status |= USB_PORT_STAT_C_RESET << 16;
1050 /* common wPortStatus bits */
1051 if (raw_port_status & PORT_CONNECT) {
1052 status |= USB_PORT_STAT_CONNECTION;
1053 status |= xhci_port_speed(raw_port_status);
1055 if (raw_port_status & PORT_PE)
1056 status |= USB_PORT_STAT_ENABLE;
1057 if (raw_port_status & PORT_OC)
1058 status |= USB_PORT_STAT_OVERCURRENT;
1059 if (raw_port_status & PORT_RESET)
1060 status |= USB_PORT_STAT_RESET;
1062 /* USB2 and USB3 specific bits, including Port Link State */
1063 if (hcd->speed >= HCD_USB3)
1064 xhci_get_usb3_port_status(port, &status, raw_port_status);
1066 xhci_get_usb2_port_status(port, &status, raw_port_status,
1069 * Clear stale usb2 resume signalling variables in case port changed
1070 * state during resume signalling. For example on error
1072 if ((bus_state->resume_done[wIndex] ||
1073 test_bit(wIndex, &bus_state->resuming_ports)) &&
1074 (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
1075 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
1076 bus_state->resume_done[wIndex] = 0;
1077 clear_bit(wIndex, &bus_state->resuming_ports);
1078 usb_hcd_end_port_resume(&hcd->self, wIndex);
1081 if (bus_state->port_c_suspend & (1 << wIndex))
1082 status |= USB_PORT_STAT_C_SUSPEND << 16;
1087 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1088 u16 wIndex, char *buf, u16 wLength)
1090 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1092 unsigned long flags;
1096 struct xhci_bus_state *bus_state;
1101 struct xhci_hub *rhub;
1102 struct xhci_port **ports;
1104 rhub = xhci_get_rhub(hcd);
1105 ports = rhub->ports;
1106 max_ports = rhub->num_ports;
1107 bus_state = &rhub->bus_state;
1109 spin_lock_irqsave(&xhci->lock, flags);
1112 /* No power source, over-current reported per port */
1115 case GetHubDescriptor:
1116 /* Check to make sure userspace is asking for the USB 3.0 hub
1117 * descriptor for the USB 3.0 roothub. If not, we stall the
1118 * endpoint, like external hubs do.
1120 if (hcd->speed >= HCD_USB3 &&
1121 (wLength < USB_DT_SS_HUB_SIZE ||
1122 wValue != (USB_DT_SS_HUB << 8))) {
1123 xhci_dbg(xhci, "Wrong hub descriptor type for "
1124 "USB 3.0 roothub.\n");
1127 xhci_hub_descriptor(hcd, xhci,
1128 (struct usb_hub_descriptor *) buf);
1130 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1131 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1134 if (hcd->speed < HCD_USB3)
1137 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
1138 spin_unlock_irqrestore(&xhci->lock, flags);
1141 if (!wIndex || wIndex > max_ports)
1144 temp = readl(ports[wIndex]->addr);
1145 if (temp == ~(u32)0) {
1150 trace_xhci_get_port_status(wIndex, temp);
1151 status = xhci_get_port_status(hcd, bus_state, wIndex, temp,
1153 if (status == 0xffffffff)
1156 xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x",
1157 hcd->self.busnum, wIndex + 1, temp, status);
1159 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1160 /* if USB 3.1 extended port status return additional 4 bytes */
1161 if (wValue == 0x02) {
1164 if (hcd->speed < HCD_USB31 || wLength != 8) {
1165 xhci_err(xhci, "get ext port status invalid parameter\n");
1169 port_li = readl(ports[wIndex]->addr + PORTLI);
1170 status = xhci_get_ext_port_status(temp, port_li);
1171 put_unaligned_le32(status, &buf[4]);
1174 case SetPortFeature:
1175 if (wValue == USB_PORT_FEAT_LINK_STATE)
1176 link_state = (wIndex & 0xff00) >> 3;
1177 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1178 wake_mask = wIndex & 0xff00;
1179 if (wValue == USB_PORT_FEAT_TEST)
1180 test_mode = (wIndex & 0xff00) >> 8;
1181 /* The MSB of wIndex is the U1/U2 timeout */
1182 timeout = (wIndex & 0xff00) >> 8;
1184 if (!wIndex || wIndex > max_ports)
1187 temp = readl(ports[wIndex]->addr);
1188 if (temp == ~(u32)0) {
1193 temp = xhci_port_state_to_neutral(temp);
1194 /* FIXME: What new port features do we need to support? */
1196 case USB_PORT_FEAT_SUSPEND:
1197 temp = readl(ports[wIndex]->addr);
1198 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1199 /* Resume the port to U0 first */
1200 xhci_set_link_state(xhci, ports[wIndex],
1202 spin_unlock_irqrestore(&xhci->lock, flags);
1204 spin_lock_irqsave(&xhci->lock, flags);
1206 /* In spec software should not attempt to suspend
1207 * a port unless the port reports that it is in the
1208 * enabled (PED = ‘1’,PLS < ‘3’) state.
1210 temp = readl(ports[wIndex]->addr);
1211 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1212 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1213 xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n",
1214 hcd->self.busnum, wIndex + 1);
1218 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1221 xhci_warn(xhci, "slot_id is zero\n");
1224 /* unlock to execute stop endpoint commands */
1225 spin_unlock_irqrestore(&xhci->lock, flags);
1226 xhci_stop_device(xhci, slot_id, 1);
1227 spin_lock_irqsave(&xhci->lock, flags);
1229 xhci_set_link_state(xhci, ports[wIndex], XDEV_U3);
1231 spin_unlock_irqrestore(&xhci->lock, flags);
1232 msleep(10); /* wait device to enter */
1233 spin_lock_irqsave(&xhci->lock, flags);
1235 temp = readl(ports[wIndex]->addr);
1236 bus_state->suspended_ports |= 1 << wIndex;
1238 case USB_PORT_FEAT_LINK_STATE:
1239 temp = readl(ports[wIndex]->addr);
1241 if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1242 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1243 temp = xhci_port_state_to_neutral(temp);
1245 * Clear all change bits, so that we get a new
1248 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1249 PORT_OCC | PORT_RC | PORT_PLC |
1251 writel(temp | PORT_PE, ports[wIndex]->addr);
1252 temp = readl(ports[wIndex]->addr);
1256 /* Put link in RxDetect (enable port) */
1257 if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1258 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1259 xhci_set_link_state(xhci, ports[wIndex],
1261 temp = readl(ports[wIndex]->addr);
1266 * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1267 * root hub port's transition to compliance mode upon
1268 * detecting LFPS timeout may be controlled by an
1269 * Compliance Transition Enabled (CTE) flag (not
1270 * software visible). This flag is set by writing 0xA
1271 * to PORTSC PLS field which will allow transition to
1272 * compliance mode the next time LFPS timeout is
1273 * encountered. A warm reset will clear it.
1275 * The CTE flag is only supported if the HCCPARAMS2 CTC
1276 * flag is set, otherwise, the compliance substate is
1277 * automatically entered as on 1.0 and prior.
1279 if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1280 if (!HCC2_CTC(xhci->hcc_params2)) {
1281 xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1285 if ((temp & PORT_CONNECT)) {
1286 xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1290 xhci_dbg(xhci, "Enable compliance mode transition for port %d\n",
1292 xhci_set_link_state(xhci, ports[wIndex],
1295 temp = readl(ports[wIndex]->addr);
1298 /* Port must be enabled */
1299 if (!(temp & PORT_PE)) {
1303 /* Can't set port link state above '3' (U3) */
1304 if (link_state > USB_SS_PORT_LS_U3) {
1305 xhci_warn(xhci, "Cannot set port %d link state %d\n",
1306 wIndex, link_state);
1309 if (link_state == USB_SS_PORT_LS_U3) {
1310 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1313 /* unlock to execute stop endpoint
1315 spin_unlock_irqrestore(&xhci->lock,
1317 xhci_stop_device(xhci, slot_id, 1);
1318 spin_lock_irqsave(&xhci->lock, flags);
1322 xhci_set_link_state(xhci, ports[wIndex], link_state);
1324 spin_unlock_irqrestore(&xhci->lock, flags);
1325 msleep(20); /* wait device to enter */
1326 spin_lock_irqsave(&xhci->lock, flags);
1328 temp = readl(ports[wIndex]->addr);
1329 if (link_state == USB_SS_PORT_LS_U3)
1330 bus_state->suspended_ports |= 1 << wIndex;
1332 case USB_PORT_FEAT_POWER:
1334 * Turn on ports, even if there isn't per-port switching.
1335 * HC will report connect events even before this is set.
1336 * However, hub_wq will ignore the roothub events until
1337 * the roothub is registered.
1339 xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1341 case USB_PORT_FEAT_RESET:
1342 temp = (temp | PORT_RESET);
1343 writel(temp, ports[wIndex]->addr);
1345 temp = readl(ports[wIndex]->addr);
1346 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
1348 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1349 xhci_set_remote_wake_mask(xhci, ports[wIndex],
1351 temp = readl(ports[wIndex]->addr);
1352 xhci_dbg(xhci, "set port remote wake mask, "
1353 "actual port %d status = 0x%x\n",
1356 case USB_PORT_FEAT_BH_PORT_RESET:
1358 writel(temp, ports[wIndex]->addr);
1359 temp = readl(ports[wIndex]->addr);
1361 case USB_PORT_FEAT_U1_TIMEOUT:
1362 if (hcd->speed < HCD_USB3)
1364 temp = readl(ports[wIndex]->addr + PORTPMSC);
1365 temp &= ~PORT_U1_TIMEOUT_MASK;
1366 temp |= PORT_U1_TIMEOUT(timeout);
1367 writel(temp, ports[wIndex]->addr + PORTPMSC);
1369 case USB_PORT_FEAT_U2_TIMEOUT:
1370 if (hcd->speed < HCD_USB3)
1372 temp = readl(ports[wIndex]->addr + PORTPMSC);
1373 temp &= ~PORT_U2_TIMEOUT_MASK;
1374 temp |= PORT_U2_TIMEOUT(timeout);
1375 writel(temp, ports[wIndex]->addr + PORTPMSC);
1377 case USB_PORT_FEAT_TEST:
1378 /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1379 if (hcd->speed != HCD_USB2)
1381 if (test_mode > TEST_FORCE_EN || test_mode < TEST_J)
1383 retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1389 /* unblock any posted writes */
1390 temp = readl(ports[wIndex]->addr);
1392 case ClearPortFeature:
1393 if (!wIndex || wIndex > max_ports)
1396 temp = readl(ports[wIndex]->addr);
1397 if (temp == ~(u32)0) {
1402 /* FIXME: What new port features do we need to support? */
1403 temp = xhci_port_state_to_neutral(temp);
1405 case USB_PORT_FEAT_SUSPEND:
1406 temp = readl(ports[wIndex]->addr);
1407 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1408 xhci_dbg(xhci, "PORTSC %04x\n", temp);
1409 if (temp & PORT_RESET)
1411 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1412 if ((temp & PORT_PE) == 0)
1415 set_bit(wIndex, &bus_state->resuming_ports);
1416 usb_hcd_start_port_resume(&hcd->self, wIndex);
1417 xhci_set_link_state(xhci, ports[wIndex],
1419 spin_unlock_irqrestore(&xhci->lock, flags);
1420 msleep(USB_RESUME_TIMEOUT);
1421 spin_lock_irqsave(&xhci->lock, flags);
1422 xhci_set_link_state(xhci, ports[wIndex],
1424 clear_bit(wIndex, &bus_state->resuming_ports);
1425 usb_hcd_end_port_resume(&hcd->self, wIndex);
1427 bus_state->port_c_suspend |= 1 << wIndex;
1429 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1432 xhci_dbg(xhci, "slot_id is zero\n");
1435 xhci_ring_device(xhci, slot_id);
1437 case USB_PORT_FEAT_C_SUSPEND:
1438 bus_state->port_c_suspend &= ~(1 << wIndex);
1440 case USB_PORT_FEAT_C_RESET:
1441 case USB_PORT_FEAT_C_BH_PORT_RESET:
1442 case USB_PORT_FEAT_C_CONNECTION:
1443 case USB_PORT_FEAT_C_OVER_CURRENT:
1444 case USB_PORT_FEAT_C_ENABLE:
1445 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1446 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1447 xhci_clear_port_change_bit(xhci, wValue, wIndex,
1448 ports[wIndex]->addr, temp);
1450 case USB_PORT_FEAT_ENABLE:
1451 xhci_disable_port(hcd, xhci, wIndex,
1452 ports[wIndex]->addr, temp);
1454 case USB_PORT_FEAT_POWER:
1455 xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1457 case USB_PORT_FEAT_TEST:
1458 retval = xhci_exit_test_mode(xhci);
1466 /* "stall" on error */
1469 spin_unlock_irqrestore(&xhci->lock, flags);
1474 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1475 * Ports are 0-indexed from the HCD point of view,
1476 * and 1-indexed from the USB core pointer of view.
1478 * Note that the status change bits will be cleared as soon as a port status
1479 * change event is generated, so we use the saved status from that event.
1481 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1483 unsigned long flags;
1487 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1489 struct xhci_bus_state *bus_state;
1490 bool reset_change = false;
1491 struct xhci_hub *rhub;
1492 struct xhci_port **ports;
1494 rhub = xhci_get_rhub(hcd);
1495 ports = rhub->ports;
1496 max_ports = rhub->num_ports;
1497 bus_state = &rhub->bus_state;
1499 /* Initial status is no changes */
1500 retval = (max_ports + 8) / 8;
1501 memset(buf, 0, retval);
1504 * Inform the usbcore about resume-in-progress by returning
1505 * a non-zero value even if there are no status changes.
1507 status = bus_state->resuming_ports;
1509 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1511 spin_lock_irqsave(&xhci->lock, flags);
1512 /* For each port, did anything change? If so, set that bit in buf. */
1513 for (i = 0; i < max_ports; i++) {
1514 temp = readl(ports[i]->addr);
1515 if (temp == ~(u32)0) {
1520 trace_xhci_hub_status_data(i, temp);
1522 if ((temp & mask) != 0 ||
1523 (bus_state->port_c_suspend & 1 << i) ||
1524 (bus_state->resume_done[i] && time_after_eq(
1525 jiffies, bus_state->resume_done[i]))) {
1526 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1529 if ((temp & PORT_RC))
1530 reset_change = true;
1532 if (!status && !reset_change) {
1533 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1534 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1536 spin_unlock_irqrestore(&xhci->lock, flags);
1537 return status ? retval : 0;
1542 int xhci_bus_suspend(struct usb_hcd *hcd)
1544 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1545 int max_ports, port_index;
1546 struct xhci_bus_state *bus_state;
1547 unsigned long flags;
1548 struct xhci_hub *rhub;
1549 struct xhci_port **ports;
1550 u32 portsc_buf[USB_MAXCHILDREN];
1553 rhub = xhci_get_rhub(hcd);
1554 ports = rhub->ports;
1555 max_ports = rhub->num_ports;
1556 bus_state = &rhub->bus_state;
1557 wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1559 spin_lock_irqsave(&xhci->lock, flags);
1562 if (bus_state->resuming_ports || /* USB2 */
1563 bus_state->port_remote_wakeup) { /* USB3 */
1564 spin_unlock_irqrestore(&xhci->lock, flags);
1565 xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1570 * Prepare ports for suspend, but don't write anything before all ports
1571 * are checked and we know bus suspend can proceed
1573 bus_state->bus_suspended = 0;
1574 port_index = max_ports;
1575 while (port_index--) {
1579 t1 = readl(ports[port_index]->addr);
1580 t2 = xhci_port_state_to_neutral(t1);
1581 portsc_buf[port_index] = 0;
1584 * Give a USB3 port in link training time to finish, but don't
1585 * prevent suspend as port might be stuck
1587 if ((hcd->speed >= HCD_USB3) && retries-- &&
1588 (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1589 spin_unlock_irqrestore(&xhci->lock, flags);
1590 msleep(XHCI_PORT_POLLING_LFPS_TIME);
1591 spin_lock_irqsave(&xhci->lock, flags);
1592 xhci_dbg(xhci, "port %d polling in bus suspend, waiting\n",
1596 /* suspend ports in U0, or bail out for new connect changes */
1597 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1598 if ((t1 & PORT_CSC) && wake_enabled) {
1599 bus_state->bus_suspended = 0;
1600 spin_unlock_irqrestore(&xhci->lock, flags);
1601 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1604 xhci_dbg(xhci, "port %d not suspended\n", port_index);
1605 t2 &= ~PORT_PLS_MASK;
1606 t2 |= PORT_LINK_STROBE | XDEV_U3;
1607 set_bit(port_index, &bus_state->bus_suspended);
1609 /* USB core sets remote wake mask for USB 3.0 hubs,
1610 * including the USB 3.0 roothub, but only if CONFIG_PM
1611 * is enabled, so also enable remote wake here.
1614 if (t1 & PORT_CONNECT) {
1615 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1616 t2 &= ~PORT_WKCONN_E;
1618 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1619 t2 &= ~PORT_WKDISC_E;
1622 if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1623 (hcd->speed < HCD_USB3)) {
1624 if (usb_amd_pt_check_port(hcd->self.controller,
1626 t2 &= ~PORT_WAKE_BITS;
1629 t2 &= ~PORT_WAKE_BITS;
1631 t1 = xhci_port_state_to_neutral(t1);
1633 portsc_buf[port_index] = t2;
1636 /* write port settings, stopping and suspending ports if needed */
1637 port_index = max_ports;
1638 while (port_index--) {
1639 if (!portsc_buf[port_index])
1641 if (test_bit(port_index, &bus_state->bus_suspended)) {
1644 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1647 spin_unlock_irqrestore(&xhci->lock, flags);
1648 xhci_stop_device(xhci, slot_id, 1);
1649 spin_lock_irqsave(&xhci->lock, flags);
1652 writel(portsc_buf[port_index], ports[port_index]->addr);
1654 hcd->state = HC_STATE_SUSPENDED;
1655 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1656 spin_unlock_irqrestore(&xhci->lock, flags);
1661 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1662 * warm reset a USB3 device stuck in polling or compliance mode after resume.
1663 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1665 static bool xhci_port_missing_cas_quirk(struct xhci_port *port)
1669 portsc = readl(port->addr);
1671 /* if any of these are set we are not stuck */
1672 if (portsc & (PORT_CONNECT | PORT_CAS))
1675 if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1676 ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1679 /* clear wakeup/change bits, and do a warm port reset */
1680 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1682 writel(portsc, port->addr);
1688 int xhci_bus_resume(struct usb_hcd *hcd)
1690 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1691 struct xhci_bus_state *bus_state;
1692 unsigned long flags;
1693 int max_ports, port_index;
1698 struct xhci_hub *rhub;
1699 struct xhci_port **ports;
1701 rhub = xhci_get_rhub(hcd);
1702 ports = rhub->ports;
1703 max_ports = rhub->num_ports;
1704 bus_state = &rhub->bus_state;
1706 if (time_before(jiffies, bus_state->next_statechange))
1709 spin_lock_irqsave(&xhci->lock, flags);
1710 if (!HCD_HW_ACCESSIBLE(hcd)) {
1711 spin_unlock_irqrestore(&xhci->lock, flags);
1715 /* delay the irqs */
1716 temp = readl(&xhci->op_regs->command);
1718 writel(temp, &xhci->op_regs->command);
1720 /* bus specific resume for ports we suspended at bus_suspend */
1721 if (hcd->speed >= HCD_USB3)
1722 next_state = XDEV_U0;
1724 next_state = XDEV_RESUME;
1726 port_index = max_ports;
1727 while (port_index--) {
1728 portsc = readl(ports[port_index]->addr);
1730 /* warm reset CAS limited ports stuck in polling/compliance */
1731 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1732 (hcd->speed >= HCD_USB3) &&
1733 xhci_port_missing_cas_quirk(ports[port_index])) {
1734 xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1735 clear_bit(port_index, &bus_state->bus_suspended);
1738 /* resume if we suspended the link, and it is still suspended */
1739 if (test_bit(port_index, &bus_state->bus_suspended))
1740 switch (portsc & PORT_PLS_MASK) {
1742 portsc = xhci_port_state_to_neutral(portsc);
1743 portsc &= ~PORT_PLS_MASK;
1744 portsc |= PORT_LINK_STROBE | next_state;
1747 /* resume already initiated */
1750 /* not in a resumeable state, ignore it */
1751 clear_bit(port_index,
1752 &bus_state->bus_suspended);
1755 /* disable wake for all ports, write new link state if needed */
1756 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1757 writel(portsc, ports[port_index]->addr);
1760 /* USB2 specific resume signaling delay and U0 link state transition */
1761 if (hcd->speed < HCD_USB3) {
1762 if (bus_state->bus_suspended) {
1763 spin_unlock_irqrestore(&xhci->lock, flags);
1764 msleep(USB_RESUME_TIMEOUT);
1765 spin_lock_irqsave(&xhci->lock, flags);
1767 for_each_set_bit(port_index, &bus_state->bus_suspended,
1769 /* Clear PLC to poll it later for U0 transition */
1770 xhci_test_and_clear_bit(xhci, ports[port_index],
1772 xhci_set_link_state(xhci, ports[port_index], XDEV_U0);
1776 /* poll for U0 link state complete, both USB2 and USB3 */
1777 for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1778 sret = xhci_handshake(ports[port_index]->addr, PORT_PLC,
1779 PORT_PLC, 10 * 1000);
1781 xhci_warn(xhci, "port %d resume PLC timeout\n",
1785 xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC);
1786 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1788 xhci_ring_device(xhci, slot_id);
1790 (void) readl(&xhci->op_regs->command);
1792 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1793 /* re-enable irqs */
1794 temp = readl(&xhci->op_regs->command);
1796 writel(temp, &xhci->op_regs->command);
1797 temp = readl(&xhci->op_regs->command);
1799 spin_unlock_irqrestore(&xhci->lock, flags);
1803 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd)
1805 struct xhci_hub *rhub = xhci_get_rhub(hcd);
1807 /* USB3 port wakeups are reported via usb_wakeup_notification() */
1808 return rhub->bus_state.resuming_ports; /* USB2 ports only */
1811 #endif /* CONFIG_PM */