drivers/usb/host/xhci-hub.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23
  24 #include <linux/slab.h>
  25 #include <asm/unaligned.h>
  26
  27 #include "xhci.h"
  28 #include "xhci-trace.h"
  29
  30 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  31 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  32                          PORT_RC | PORT_PLC | PORT_PE)
  33
  34 /* USB 3 BOS descriptor and a capability descriptors, combined.
  35  * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
  36  */
  37 static u8 usb_bos_descriptor [] = {
  38         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  39         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  40         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  41         0x1,                            /*  __u8 bNumDeviceCaps */
  42         /* First device capability, SuperSpeed */
  43         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  44         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  45         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  46         0x00,                           /* bmAttributes, LTM off by default */
  47         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  48         0x03,                           /* bFunctionalitySupport,
  49                                            USB 3.0 speed only */
  50         0x00,                           /* bU1DevExitLat, set later. */
  51         0x00, 0x00,                     /* __le16 bU2DevExitLat, set later. */
  52         /* Second device capability, SuperSpeedPlus */
  53         0x1c,                           /* bLength 28, will be adjusted later */
  54         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  55         USB_SSP_CAP_TYPE,               /* bDevCapabilityType SUPERSPEED_PLUS */
  56         0x00,                           /* bReserved 0 */
  57         0x23, 0x00, 0x00, 0x00,         /* bmAttributes, SSAC=3 SSIC=1 */
  58         0x01, 0x00,                     /* wFunctionalitySupport */
  59         0x00, 0x00,                     /* wReserved 0 */
  60         /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
  61         0x34, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, rx, ID = 4 */
  62         0xb4, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, tx, ID = 4 */
  63         0x35, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, rx, ID = 5 */
  64         0xb5, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, tx, ID = 5 */
  65 };
  66
  67 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
  68                                      u16 wLength)
  69 {
  70         int i, ssa_count;
  71         u32 temp;
  72         u16 desc_size, ssp_cap_size, ssa_size = 0;
  73         bool usb3_1 = false;
  74
  75         desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
  76         ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
  77
  78         /* does xhci support USB 3.1 Enhanced SuperSpeed */
  79         if (xhci->usb3_rhub.min_rev >= 0x01) {
  80                 /* does xhci provide a PSI table for SSA speed attributes? */
  81                 if (xhci->usb3_rhub.psi_count) {
  82                         /* two SSA entries for each unique PSI ID, RX and TX */
  83                         ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
  84                         ssa_size = ssa_count * sizeof(u32);
  85                         ssp_cap_size -= 16; /* skip copying the default SSA */
  86                 }
  87                 desc_size += ssp_cap_size;
  88                 usb3_1 = true;
  89         }
  90         memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
  91
  92         if (usb3_1) {
  93                 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
  94                 buf[4] += 1;
  95                 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
  96         }
  97
  98         if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
  99                 return wLength;
 100
 101         /* Indicate whether the host has LTM support. */
 102         temp = readl(&xhci->cap_regs->hcc_params);
 103         if (HCC_LTC(temp))
 104                 buf[8] |= USB_LTM_SUPPORT;
 105
 106         /* Set the U1 and U2 exit latencies. */
 107         if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
 108                 temp = readl(&xhci->cap_regs->hcs_params3);
 109                 buf[12] = HCS_U1_LATENCY(temp);
 110                 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
 111         }
 112
 113         /* If PSI table exists, add the custom speed attributes from it */
 114         if (usb3_1 && xhci->usb3_rhub.psi_count) {
 115                 u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
 116                 int offset;
 117
 118                 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 119
 120                 if (wLength < desc_size)
 121                         return wLength;
 122                 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
 123
 124                 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
 125                 bm_attrib = (ssa_count - 1) & 0x1f;
 126                 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
 127                 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
 128
 129                 if (wLength < desc_size + ssa_size)
 130                         return wLength;
 131                 /*
 132                  * Create the Sublink Speed Attributes (SSA) array.
 133                  * The xhci PSI field and USB 3.1 SSA fields are very similar,
 134                  * but link type bits 7:6 differ for values 01b and 10b.
 135                  * xhci has also only one PSI entry for a symmetric link when
 136                  * USB 3.1 requires two SSA entries (RX and TX) for every link
 137                  */
 138                 offset = desc_size;
 139                 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
 140                         psi = xhci->usb3_rhub.psi[i];
 141                         psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
 142                         psi_exp = XHCI_EXT_PORT_PSIE(psi);
 143                         psi_mant = XHCI_EXT_PORT_PSIM(psi);
 144
 145                         /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
 146                         for (; psi_exp < 3; psi_exp++)
 147                                 psi_mant /= 1000;
 148                         if (psi_mant >= 10)
 149                                 psi |= BIT(14);
 150
 151                         if ((psi & PLT_MASK) == PLT_SYM) {
 152                         /* Symmetric, create SSA RX and TX from one PSI entry */
 153                                 put_unaligned_le32(psi, &buf[offset]);
 154                                 psi |= 1 << 7;  /* turn entry to TX */
 155                                 offset += 4;
 156                                 if (offset >= desc_size + ssa_size)
 157                                         return desc_size + ssa_size;
 158                         } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
 159                                 /* Asymetric RX, flip bits 7:6 for SSA */
 160                                 psi ^= PLT_MASK;
 161                         }
 162                         put_unaligned_le32(psi, &buf[offset]);
 163                         offset += 4;
 164                         if (offset >= desc_size + ssa_size)
 165                                 return desc_size + ssa_size;
 166                 }
 167         }
 168         /* ssa_size is 0 for other than usb 3.1 hosts */
 169         return desc_size + ssa_size;
 170 }
 171
 172 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
 173                 struct usb_hub_descriptor *desc, int ports)
 174 {
 175         u16 temp;
 176
 177         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.9 says 20ms max */
 178         desc->bHubContrCurrent = 0;
 179
 180         desc->bNbrPorts = ports;
 181         temp = 0;
 182         /* Bits 1:0 - support per-port power switching, or power always on */
 183         if (HCC_PPC(xhci->hcc_params))
 184                 temp |= HUB_CHAR_INDV_PORT_LPSM;
 185         else
 186                 temp |= HUB_CHAR_NO_LPSM;
 187         /* Bit  2 - root hubs are not part of a compound device */
 188         /* Bits 4:3 - individual port over current protection */
 189         temp |= HUB_CHAR_INDV_PORT_OCPM;
 190         /* Bits 6:5 - no TTs in root ports */
 191         /* Bit  7 - no port indicators */
 192         desc->wHubCharacteristics = cpu_to_le16(temp);
 193 }
 194
 195 /* Fill in the USB 2.0 roothub descriptor */
 196 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 197                 struct usb_hub_descriptor *desc)
 198 {
 199         int ports;
 200         u16 temp;
 201         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
 202         u32 portsc;
 203         unsigned int i;
 204
 205         ports = xhci->num_usb2_ports;
 206
 207         xhci_common_hub_descriptor(xhci, desc, ports);
 208         desc->bDescriptorType = USB_DT_HUB;
 209         temp = 1 + (ports / 8);
 210         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
 211
 212         /* The Device Removable bits are reported on a byte granularity.
 213          * If the port doesn't exist within that byte, the bit is set to 0.
 214          */
 215         memset(port_removable, 0, sizeof(port_removable));
 216         for (i = 0; i < ports; i++) {
 217                 portsc = readl(xhci->usb2_ports[i]);
 218                 /* If a device is removable, PORTSC reports a 0, same as in the
 219                  * hub descriptor DeviceRemovable bits.
 220                  */
 221                 if (portsc & PORT_DEV_REMOVE)
 222                         /* This math is hairy because bit 0 of DeviceRemovable
 223                          * is reserved, and bit 1 is for port 1, etc.
 224                          */
 225                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 226         }
 227
 228         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 229          * ports on it.  The USB 2.0 specification says that there are two
 230          * variable length fields at the end of the hub descriptor:
 231          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 232          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 233          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 234          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 235          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 236          * set of ports that actually exist.
 237          */
 238         memset(desc->u.hs.DeviceRemovable, 0xff,
 239                         sizeof(desc->u.hs.DeviceRemovable));
 240         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 241                         sizeof(desc->u.hs.PortPwrCtrlMask));
 242
 243         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 244                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 245                                 sizeof(__u8));
 246 }
 247
 248 /* Fill in the USB 3.0 roothub descriptor */
 249 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 250                 struct usb_hub_descriptor *desc)
 251 {
 252         int ports;
 253         u16 port_removable;
 254         u32 portsc;
 255         unsigned int i;
 256
 257         ports = xhci->num_usb3_ports;
 258         xhci_common_hub_descriptor(xhci, desc, ports);
 259         desc->bDescriptorType = USB_DT_SS_HUB;
 260         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 261
 262         /* header decode latency should be zero for roothubs,
 263          * see section 4.23.5.2.
 264          */
 265         desc->u.ss.bHubHdrDecLat = 0;
 266         desc->u.ss.wHubDelay = 0;
 267
 268         port_removable = 0;
 269         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 270         for (i = 0; i < ports; i++) {
 271                 portsc = readl(xhci->usb3_ports[i]);
 272                 if (portsc & PORT_DEV_REMOVE)
 273                         port_removable |= 1 << (i + 1);
 274         }
 275
 276         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 277 }
 278
 279 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 280                 struct usb_hub_descriptor *desc)
 281 {
 282
 283         if (hcd->speed >= HCD_USB3)
 284                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 285         else
 286                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 287
 288 }
 289
 290 static unsigned int xhci_port_speed(unsigned int port_status)
 291 {
 292         if (DEV_LOWSPEED(port_status))
 293                 return USB_PORT_STAT_LOW_SPEED;
 294         if (DEV_HIGHSPEED(port_status))
 295                 return USB_PORT_STAT_HIGH_SPEED;
 296         /*
 297          * FIXME: Yes, we should check for full speed, but the core uses that as
 298          * a default in portspeed() in usb/core/hub.c (which is the only place
 299          * USB_PORT_STAT_*_SPEED is used).
 300          */
 301         return 0;
 302 }
 303
 304 /*
 305  * These bits are Read Only (RO) and should be saved and written to the
 306  * registers: 0, 3, 10:13, 30
 307  * connect status, over-current status, port speed, and device removable.
 308  * connect status and port speed are also sticky - meaning they're in
 309  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 310  */
 311 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 312 /*
 313  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 314  * bits 5:8, 9, 14:15, 25:27
 315  * link state, port power, port indicator state, "wake on" enable state
 316  */
 317 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 318 /*
 319  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 320  * bit 4 (port reset)
 321  */
 322 #define XHCI_PORT_RW1S  ((1<<4))
 323 /*
 324  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 325  * bits 1, 17, 18, 19, 20, 21, 22, 23
 326  * port enable/disable, and
 327  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 328  * over-current, reset, link state, and L1 change
 329  */
 330 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 331 /*
 332  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 333  * latched in
 334  */
 335 #define XHCI_PORT_RW    ((1<<16))
 336 /*
 337  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 338  * bits 2, 24, 28:31
 339  */
 340 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 341
 342 /*
 343  * Given a port state, this function returns a value that would result in the
 344  * port being in the same state, if the value was written to the port status
 345  * control register.
 346  * Save Read Only (RO) bits and save read/write bits where
 347  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 348  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 349  */
 350 u32 xhci_port_state_to_neutral(u32 state)
 351 {
 352         /* Save read-only status and port state */
 353         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 354 }
 355
 356 /*
 357  * find slot id based on port number.
 358  * @port: The one-based port number from one of the two split roothubs.
 359  */
 360 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 361                 u16 port)
 362 {
 363         int slot_id;
 364         int i;
 365         enum usb_device_speed speed;
 366
 367         slot_id = 0;
 368         for (i = 0; i < MAX_HC_SLOTS; i++) {
 369                 if (!xhci->devs[i])
 370                         continue;
 371                 speed = xhci->devs[i]->udev->speed;
 372                 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
 373                                 && xhci->devs[i]->fake_port == port) {
 374                         slot_id = i;
 375                         break;
 376                 }
 377         }
 378
 379         return slot_id;
 380 }
 381
 382 /*
 383  * Stop device
 384  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 385  * to complete.
 386  * suspend will set to 1, if suspend bit need to set in command.
 387  */
 388 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 389 {
 390         struct xhci_virt_device *virt_dev;
 391         struct xhci_command *cmd;
 392         unsigned long flags;
 393         int ret;
 394         int i;
 395
 396         ret = 0;
 397         virt_dev = xhci->devs[slot_id];
 398         if (!virt_dev)
 399                 return -ENODEV;
 400
 401         trace_xhci_stop_device(virt_dev);
 402
 403         cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
 404         if (!cmd)
 405                 return -ENOMEM;
 406
 407         spin_lock_irqsave(&xhci->lock, flags);
 408         for (i = LAST_EP_INDEX; i > 0; i--) {
 409                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
 410                         struct xhci_ep_ctx *ep_ctx;
 411                         struct xhci_command *command;
 412
 413                         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
 414
 415                         /* Check ep is running, required by AMD SNPS 3.1 xHC */
 416                         if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
 417                                 continue;
 418
 419                         command = xhci_alloc_command(xhci, false, false,
 420                                                      GFP_NOWAIT);
 421                         if (!command) {
 422                                 spin_unlock_irqrestore(&xhci->lock, flags);
 423                                 ret = -ENOMEM;
 424                                 goto cmd_cleanup;
 425                         }
 426
 427                         ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
 428                                                        i, suspend);
 429                         if (ret) {
 430                                 spin_unlock_irqrestore(&xhci->lock, flags);
 431                                 xhci_free_command(xhci, command);
 432                                 goto cmd_cleanup;
 433                         }
 434                 }
 435         }
 436         ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
 437         if (ret) {
 438                 spin_unlock_irqrestore(&xhci->lock, flags);
 439                 goto cmd_cleanup;
 440         }
 441
 442         xhci_ring_cmd_db(xhci);
 443         spin_unlock_irqrestore(&xhci->lock, flags);
 444
 445         /* Wait for last stop endpoint command to finish */
 446         wait_for_completion(cmd->completion);
 447
 448         if (cmd->status == COMP_COMMAND_ABORTED ||
 449             cmd->status == COMP_COMMAND_RING_STOPPED) {
 450                 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
 451                 ret = -ETIME;
 452         }
 453
 454 cmd_cleanup:
 455         xhci_free_command(xhci, cmd);
 456         return ret;
 457 }
 458
 459 /*
 460  * Ring device, it rings the all doorbells unconditionally.
 461  */
 462 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 463 {
 464         int i, s;
 465         struct xhci_virt_ep *ep;
 466
 467         for (i = 0; i < LAST_EP_INDEX + 1; i++) {
 468                 ep = &xhci->devs[slot_id]->eps[i];
 469
 470                 if (ep->ep_state & EP_HAS_STREAMS) {
 471                         for (s = 1; s < ep->stream_info->num_streams; s++)
 472                                 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
 473                 } else if (ep->ring && ep->ring->dequeue) {
 474                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 475                 }
 476         }
 477
 478         return;
 479 }
 480
 481 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 482                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 483 {
 484         /* Don't allow the USB core to disable SuperSpeed ports. */
 485         if (hcd->speed >= HCD_USB3) {
 486                 xhci_dbg(xhci, "Ignoring request to disable "
 487                                 "SuperSpeed port.\n");
 488                 return;
 489         }
 490
 491         if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
 492                 xhci_dbg(xhci,
 493                          "Broken Port Enabled/Disabled, ignoring port disable request.\n");
 494                 return;
 495         }
 496
 497         /* Write 1 to disable the port */
 498         writel(port_status | PORT_PE, addr);
 499         port_status = readl(addr);
 500         xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
 501                         wIndex, port_status);
 502 }
 503
 504 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 505                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 506 {
 507         char *port_change_bit;
 508         u32 status;
 509
 510         switch (wValue) {
 511         case USB_PORT_FEAT_C_RESET:
 512                 status = PORT_RC;
 513                 port_change_bit = "reset";
 514                 break;
 515         case USB_PORT_FEAT_C_BH_PORT_RESET:
 516                 status = PORT_WRC;
 517                 port_change_bit = "warm(BH) reset";
 518                 break;
 519         case USB_PORT_FEAT_C_CONNECTION:
 520                 status = PORT_CSC;
 521                 port_change_bit = "connect";
 522                 break;
 523         case USB_PORT_FEAT_C_OVER_CURRENT:
 524                 status = PORT_OCC;
 525                 port_change_bit = "over-current";
 526                 break;
 527         case USB_PORT_FEAT_C_ENABLE:
 528                 status = PORT_PEC;
 529                 port_change_bit = "enable/disable";
 530                 break;
 531         case USB_PORT_FEAT_C_SUSPEND:
 532                 status = PORT_PLC;
 533                 port_change_bit = "suspend/resume";
 534                 break;
 535         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 536                 status = PORT_PLC;
 537                 port_change_bit = "link state";
 538                 break;
 539         case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
 540                 status = PORT_CEC;
 541                 port_change_bit = "config error";
 542                 break;
 543         default:
 544                 /* Should never happen */
 545                 return;
 546         }
 547         /* Change bits are all write 1 to clear */
 548         writel(port_status | status, addr);
 549         port_status = readl(addr);
 550         xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
 551                         port_change_bit, wIndex, port_status);
 552 }
 553
 554 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
 555 {
 556         int max_ports;
 557         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 558
 559         if (hcd->speed >= HCD_USB3) {
 560                 max_ports = xhci->num_usb3_ports;
 561                 *port_array = xhci->usb3_ports;
 562         } else {
 563                 max_ports = xhci->num_usb2_ports;
 564                 *port_array = xhci->usb2_ports;
 565         }
 566
 567         return max_ports;
 568 }
 569
 570 static __le32 __iomem *xhci_get_port_io_addr(struct usb_hcd *hcd, int index)
 571 {
 572         __le32 __iomem **port_array;
 573
 574         xhci_get_ports(hcd, &port_array);
 575         return port_array[index];
 576 }
 577
 578 /*
 579  * xhci_set_port_power() must be called with xhci->lock held.
 580  * It will release and re-aquire the lock while calling ACPI
 581  * method.
 582  */
 583 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
 584                                 u16 index, bool on, unsigned long *flags)
 585 {
 586         __le32 __iomem *addr;
 587         u32 temp;
 588
 589         addr = xhci_get_port_io_addr(hcd, index);
 590         temp = readl(addr);
 591         temp = xhci_port_state_to_neutral(temp);
 592         if (on) {
 593                 /* Power on */
 594                 writel(temp | PORT_POWER, addr);
 595                 temp = readl(addr);
 596                 xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n",
 597                                                 index, temp);
 598         } else {
 599                 /* Power off */
 600                 writel(temp & ~PORT_POWER, addr);
 601         }
 602
 603         spin_unlock_irqrestore(&xhci->lock, *flags);
 604         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 605                                         index);
 606         if (temp)
 607                 usb_acpi_set_power_state(hcd->self.root_hub,
 608                         index, on);
 609         spin_lock_irqsave(&xhci->lock, *flags);
 610 }
 611
 612 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
 613         u16 test_mode, u16 wIndex)
 614 {
 615         u32 temp;
 616         __le32 __iomem *addr;
 617
 618         /* xhci only supports test mode for usb2 ports, i.e. xhci->main_hcd */
 619         addr = xhci_get_port_io_addr(xhci->main_hcd, wIndex);
 620         temp = readl(addr + PORTPMSC);
 621         temp |= test_mode << PORT_TEST_MODE_SHIFT;
 622         writel(temp, addr + PORTPMSC);
 623         xhci->test_mode = test_mode;
 624         if (test_mode == TEST_FORCE_EN)
 625                 xhci_start(xhci);
 626 }
 627
 628 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
 629                                 u16 test_mode, u16 wIndex, unsigned long *flags)
 630 {
 631         int i, retval;
 632
 633         /* Disable all Device Slots */
 634         xhci_dbg(xhci, "Disable all slots\n");
 635         spin_unlock_irqrestore(&xhci->lock, *flags);
 636         for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
 637                 retval = xhci_disable_slot(xhci, NULL, i);
 638                 if (retval)
 639                         xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
 640                                  i, retval);
 641         }
 642         spin_lock_irqsave(&xhci->lock, *flags);
 643         /* Put all ports to the Disable state by clear PP */
 644         xhci_dbg(xhci, "Disable all port (PP = 0)\n");
 645         /* Power off USB3 ports*/
 646         for (i = 0; i < xhci->num_usb3_ports; i++)
 647                 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
 648         /* Power off USB2 ports*/
 649         for (i = 0; i < xhci->num_usb2_ports; i++)
 650                 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
 651         /* Stop the controller */
 652         xhci_dbg(xhci, "Stop controller\n");
 653         retval = xhci_halt(xhci);
 654         if (retval)
 655                 return retval;
 656         /* Disable runtime PM for test mode */
 657         pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
 658         /* Set PORTPMSC.PTC field to enter selected test mode */
 659         /* Port is selected by wIndex. port_id = wIndex + 1 */
 660         xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
 661                                         test_mode, wIndex + 1);
 662         xhci_port_set_test_mode(xhci, test_mode, wIndex);
 663         return retval;
 664 }
 665
 666 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
 667 {
 668         int retval;
 669
 670         if (!xhci->test_mode) {
 671                 xhci_err(xhci, "Not in test mode, do nothing.\n");
 672                 return 0;
 673         }
 674         if (xhci->test_mode == TEST_FORCE_EN &&
 675                 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
 676                 retval = xhci_halt(xhci);
 677                 if (retval)
 678                         return retval;
 679         }
 680         pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
 681         xhci->test_mode = 0;
 682         return xhci_reset(xhci);
 683 }
 684
 685 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 686                                 int port_id, u32 link_state)
 687 {
 688         u32 temp;
 689
 690         temp = readl(port_array[port_id]);
 691         temp = xhci_port_state_to_neutral(temp);
 692         temp &= ~PORT_PLS_MASK;
 693         temp |= PORT_LINK_STROBE | link_state;
 694         writel(temp, port_array[port_id]);
 695 }
 696
 697 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 698                 __le32 __iomem **port_array, int port_id, u16 wake_mask)
 699 {
 700         u32 temp;
 701
 702         temp = readl(port_array[port_id]);
 703         temp = xhci_port_state_to_neutral(temp);
 704
 705         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 706                 temp |= PORT_WKCONN_E;
 707         else
 708                 temp &= ~PORT_WKCONN_E;
 709
 710         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 711                 temp |= PORT_WKDISC_E;
 712         else
 713                 temp &= ~PORT_WKDISC_E;
 714
 715         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 716                 temp |= PORT_WKOC_E;
 717         else
 718                 temp &= ~PORT_WKOC_E;
 719
 720         writel(temp, port_array[port_id]);
 721 }
 722
 723 /* Test and clear port RWC bit */
 724 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 725                                 int port_id, u32 port_bit)
 726 {
 727         u32 temp;
 728
 729         temp = readl(port_array[port_id]);
 730         if (temp & port_bit) {
 731                 temp = xhci_port_state_to_neutral(temp);
 732                 temp |= port_bit;
 733                 writel(temp, port_array[port_id]);
 734         }
 735 }
 736
 737 /* Updates Link Status for USB 2.1 port */
 738 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
 739 {
 740         if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
 741                 *status |= USB_PORT_STAT_L1;
 742 }
 743
 744 /* Updates Link Status for super Speed port */
 745 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
 746                 u32 *status, u32 status_reg)
 747 {
 748         u32 pls = status_reg & PORT_PLS_MASK;
 749
 750         /* resume state is a xHCI internal state.
 751          * Do not report it to usb core, instead, pretend to be U3,
 752          * thus usb core knows it's not ready for transfer
 753          */
 754         if (pls == XDEV_RESUME) {
 755                 *status |= USB_SS_PORT_LS_U3;
 756                 return;
 757         }
 758
 759         /* When the CAS bit is set then warm reset
 760          * should be performed on port
 761          */
 762         if (status_reg & PORT_CAS) {
 763                 /* The CAS bit can be set while the port is
 764                  * in any link state.
 765                  * Only roothubs have CAS bit, so we
 766                  * pretend to be in compliance mode
 767                  * unless we're already in compliance
 768                  * or the inactive state.
 769                  */
 770                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 771                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 772                         pls = USB_SS_PORT_LS_COMP_MOD;
 773                 }
 774                 /* Return also connection bit -
 775                  * hub state machine resets port
 776                  * when this bit is set.
 777                  */
 778                 pls |= USB_PORT_STAT_CONNECTION;
 779         } else {
 780                 /*
 781                  * If CAS bit isn't set but the Port is already at
 782                  * Compliance Mode, fake a connection so the USB core
 783                  * notices the Compliance state and resets the port.
 784                  * This resolves an issue generated by the SN65LVPE502CP
 785                  * in which sometimes the port enters compliance mode
 786                  * caused by a delay on the host-device negotiation.
 787                  */
 788                 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 789                                 (pls == USB_SS_PORT_LS_COMP_MOD))
 790                         pls |= USB_PORT_STAT_CONNECTION;
 791         }
 792
 793         /* update status field */
 794         *status |= pls;
 795 }
 796
 797 /*
 798  * Function for Compliance Mode Quirk.
 799  *
 800  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 801  * the compliance mode timer is deleted. A port won't enter
 802  * compliance mode if it has previously entered U0.
 803  */
 804 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
 805                                     u16 wIndex)
 806 {
 807         u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
 808         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 809
 810         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 811                 return;
 812
 813         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 814                 xhci->port_status_u0 |= 1 << wIndex;
 815                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 816                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 817                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 818                                 "All USB3 ports have entered U0 already!");
 819                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 820                                 "Compliance Mode Recovery Timer Deleted.");
 821                 }
 822         }
 823 }
 824
 825 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
 826 {
 827         u32 ext_stat = 0;
 828         int speed_id;
 829
 830         /* only support rx and tx lane counts of 1 in usb3.1 spec */
 831         speed_id = DEV_PORT_SPEED(raw_port_status);
 832         ext_stat |= speed_id;           /* bits 3:0, RX speed id */
 833         ext_stat |= speed_id << 4;      /* bits 7:4, TX speed id */
 834
 835         ext_stat |= PORT_RX_LANES(port_li) << 8;  /* bits 11:8 Rx lane count */
 836         ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
 837
 838         return ext_stat;
 839 }
 840
 841 /*
 842  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
 843  * 3.0 hubs use.
 844  *
 845  * Possible side effects:
 846  *  - Mark a port as being done with device resume,
 847  *    and ring the endpoint doorbells.
 848  *  - Stop the Synopsys redriver Compliance Mode polling.
 849  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
 850  */
 851 static u32 xhci_get_port_status(struct usb_hcd *hcd,
 852                 struct xhci_bus_state *bus_state,
 853                 __le32 __iomem **port_array,
 854                 u16 wIndex, u32 raw_port_status,
 855                 unsigned long flags)
 856         __releases(&xhci->lock)
 857         __acquires(&xhci->lock)
 858 {
 859         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 860         u32 status = 0;
 861         int slot_id;
 862
 863         /* wPortChange bits */
 864         if (raw_port_status & PORT_CSC)
 865                 status |= USB_PORT_STAT_C_CONNECTION << 16;
 866         if (raw_port_status & PORT_PEC)
 867                 status |= USB_PORT_STAT_C_ENABLE << 16;
 868         if ((raw_port_status & PORT_OCC))
 869                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
 870         if ((raw_port_status & PORT_RC))
 871                 status |= USB_PORT_STAT_C_RESET << 16;
 872         /* USB3.0 only */
 873         if (hcd->speed >= HCD_USB3) {
 874                 /* Port link change with port in resume state should not be
 875                  * reported to usbcore, as this is an internal state to be
 876                  * handled by xhci driver. Reporting PLC to usbcore may
 877                  * cause usbcore clearing PLC first and port change event
 878                  * irq won't be generated.
 879                  */
 880                 if ((raw_port_status & PORT_PLC) &&
 881                         (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
 882                         status |= USB_PORT_STAT_C_LINK_STATE << 16;
 883                 if ((raw_port_status & PORT_WRC))
 884                         status |= USB_PORT_STAT_C_BH_RESET << 16;
 885                 if ((raw_port_status & PORT_CEC))
 886                         status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
 887         }
 888
 889         if (hcd->speed < HCD_USB3) {
 890                 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
 891                                 && (raw_port_status & PORT_POWER))
 892                         status |= USB_PORT_STAT_SUSPEND;
 893         }
 894         if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
 895                 !DEV_SUPERSPEED_ANY(raw_port_status)) {
 896                 if ((raw_port_status & PORT_RESET) ||
 897                                 !(raw_port_status & PORT_PE))
 898                         return 0xffffffff;
 899                 /* did port event handler already start resume timing? */
 900                 if (!bus_state->resume_done[wIndex]) {
 901                         /* If not, maybe we are in a host initated resume? */
 902                         if (test_bit(wIndex, &bus_state->resuming_ports)) {
 903                                 /* Host initated resume doesn't time the resume
 904                                  * signalling using resume_done[].
 905                                  * It manually sets RESUME state, sleeps 20ms
 906                                  * and sets U0 state. This should probably be
 907                                  * changed, but not right now.
 908                                  */
 909                         } else {
 910                                 /* port resume was discovered now and here,
 911                                  * start resume timing
 912                                  */
 913                                 unsigned long timeout = jiffies +
 914                                         msecs_to_jiffies(USB_RESUME_TIMEOUT);
 915
 916                                 set_bit(wIndex, &bus_state->resuming_ports);
 917                                 bus_state->resume_done[wIndex] = timeout;
 918                                 mod_timer(&hcd->rh_timer, timeout);
 919                         }
 920                 /* Has resume been signalled for USB_RESUME_TIME yet? */
 921                 } else if (time_after_eq(jiffies,
 922                                          bus_state->resume_done[wIndex])) {
 923                         int time_left;
 924
 925                         xhci_dbg(xhci, "Resume USB2 port %d\n",
 926                                         wIndex + 1);
 927                         bus_state->resume_done[wIndex] = 0;
 928                         clear_bit(wIndex, &bus_state->resuming_ports);
 929
 930                         set_bit(wIndex, &bus_state->rexit_ports);
 931
 932                         xhci_test_and_clear_bit(xhci, port_array, wIndex,
 933                                                 PORT_PLC);
 934                         xhci_set_link_state(xhci, port_array, wIndex,
 935                                         XDEV_U0);
 936
 937                         spin_unlock_irqrestore(&xhci->lock, flags);
 938                         time_left = wait_for_completion_timeout(
 939                                         &bus_state->rexit_done[wIndex],
 940                                         msecs_to_jiffies(
 941                                                 XHCI_MAX_REXIT_TIMEOUT));
 942                         spin_lock_irqsave(&xhci->lock, flags);
 943
 944                         if (time_left) {
 945                                 slot_id = xhci_find_slot_id_by_port(hcd,
 946                                                 xhci, wIndex + 1);
 947                                 if (!slot_id) {
 948                                         xhci_dbg(xhci, "slot_id is zero\n");
 949                                         return 0xffffffff;
 950                                 }
 951                                 xhci_ring_device(xhci, slot_id);
 952                         } else {
 953                                 int port_status = readl(port_array[wIndex]);
 954                                 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
 955                                                 XHCI_MAX_REXIT_TIMEOUT,
 956                                                 port_status);
 957                                 status |= USB_PORT_STAT_SUSPEND;
 958                                 clear_bit(wIndex, &bus_state->rexit_ports);
 959                         }
 960
 961                         bus_state->port_c_suspend |= 1 << wIndex;
 962                         bus_state->suspended_ports &= ~(1 << wIndex);
 963                 } else {
 964                         /*
 965                          * The resume has been signaling for less than
 966                          * USB_RESUME_TIME. Report the port status as SUSPEND,
 967                          * let the usbcore check port status again and clear
 968                          * resume signaling later.
 969                          */
 970                         status |= USB_PORT_STAT_SUSPEND;
 971                 }
 972         }
 973         /*
 974          * Clear stale usb2 resume signalling variables in case port changed
 975          * state during resume signalling. For example on error
 976          */
 977         if ((bus_state->resume_done[wIndex] ||
 978              test_bit(wIndex, &bus_state->resuming_ports)) &&
 979             (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
 980             (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
 981                 bus_state->resume_done[wIndex] = 0;
 982                 clear_bit(wIndex, &bus_state->resuming_ports);
 983         }
 984
 985
 986         if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
 987             (raw_port_status & PORT_POWER)) {
 988                 if (bus_state->suspended_ports & (1 << wIndex)) {
 989                         bus_state->suspended_ports &= ~(1 << wIndex);
 990                         if (hcd->speed < HCD_USB3)
 991                                 bus_state->port_c_suspend |= 1 << wIndex;
 992                 }
 993                 bus_state->resume_done[wIndex] = 0;
 994                 clear_bit(wIndex, &bus_state->resuming_ports);
 995         }
 996         if (raw_port_status & PORT_CONNECT) {
 997                 status |= USB_PORT_STAT_CONNECTION;
 998                 status |= xhci_port_speed(raw_port_status);
 999         }
1000         if (raw_port_status & PORT_PE)
1001                 status |= USB_PORT_STAT_ENABLE;
1002         if (raw_port_status & PORT_OC)
1003                 status |= USB_PORT_STAT_OVERCURRENT;
1004         if (raw_port_status & PORT_RESET)
1005                 status |= USB_PORT_STAT_RESET;
1006         if (raw_port_status & PORT_POWER) {
1007                 if (hcd->speed >= HCD_USB3)
1008                         status |= USB_SS_PORT_STAT_POWER;
1009                 else
1010                         status |= USB_PORT_STAT_POWER;
1011         }
1012         /* Update Port Link State */
1013         if (hcd->speed >= HCD_USB3) {
1014                 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
1015                 /*
1016                  * Verify if all USB3 Ports Have entered U0 already.
1017                  * Delete Compliance Mode Timer if so.
1018                  */
1019                 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
1020         } else {
1021                 xhci_hub_report_usb2_link_state(&status, raw_port_status);
1022         }
1023         if (bus_state->port_c_suspend & (1 << wIndex))
1024                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1025
1026         return status;
1027 }
1028
1029 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1030                 u16 wIndex, char *buf, u16 wLength)
1031 {
1032         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1033         int max_ports;
1034         unsigned long flags;
1035         u32 temp, status;
1036         int retval = 0;
1037         __le32 __iomem **port_array;
1038         int slot_id;
1039         struct xhci_bus_state *bus_state;
1040         u16 link_state = 0;
1041         u16 wake_mask = 0;
1042         u16 timeout = 0;
1043         u16 test_mode = 0;
1044
1045         max_ports = xhci_get_ports(hcd, &port_array);
1046         bus_state = &xhci->bus_state[hcd_index(hcd)];
1047
1048         spin_lock_irqsave(&xhci->lock, flags);
1049         switch (typeReq) {
1050         case GetHubStatus:
1051                 /* No power source, over-current reported per port */
1052                 memset(buf, 0, 4);
1053                 break;
1054         case GetHubDescriptor:
1055                 /* Check to make sure userspace is asking for the USB 3.0 hub
1056                  * descriptor for the USB 3.0 roothub.  If not, we stall the
1057                  * endpoint, like external hubs do.
1058                  */
1059                 if (hcd->speed >= HCD_USB3 &&
1060                                 (wLength < USB_DT_SS_HUB_SIZE ||
1061                                  wValue != (USB_DT_SS_HUB << 8))) {
1062                         xhci_dbg(xhci, "Wrong hub descriptor type for "
1063                                         "USB 3.0 roothub.\n");
1064                         goto error;
1065                 }
1066                 xhci_hub_descriptor(hcd, xhci,
1067                                 (struct usb_hub_descriptor *) buf);
1068                 break;
1069         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1070                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1071                         goto error;
1072
1073                 if (hcd->speed < HCD_USB3)
1074                         goto error;
1075
1076                 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
1077                 spin_unlock_irqrestore(&xhci->lock, flags);
1078                 return retval;
1079         case GetPortStatus:
1080                 if (!wIndex || wIndex > max_ports)
1081                         goto error;
1082                 wIndex--;
1083                 temp = readl(port_array[wIndex]);
1084                 if (temp == ~(u32)0) {
1085                         xhci_hc_died(xhci);
1086                         retval = -ENODEV;
1087                         break;
1088                 }
1089                 status = xhci_get_port_status(hcd, bus_state, port_array,
1090                                 wIndex, temp, flags);
1091                 if (status == 0xffffffff)
1092                         goto error;
1093
1094                 xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n",
1095                                 wIndex, temp);
1096                 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
1097
1098                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1099                 /* if USB 3.1 extended port status return additional 4 bytes */
1100                 if (wValue == 0x02) {
1101                         u32 port_li;
1102
1103                         if (hcd->speed < HCD_USB31 || wLength != 8) {
1104                                 xhci_err(xhci, "get ext port status invalid parameter\n");
1105                                 retval = -EINVAL;
1106                                 break;
1107                         }
1108                         port_li = readl(port_array[wIndex] + PORTLI);
1109                         status = xhci_get_ext_port_status(temp, port_li);
1110                         put_unaligned_le32(cpu_to_le32(status), &buf[4]);
1111                 }
1112                 break;
1113         case SetPortFeature:
1114                 if (wValue == USB_PORT_FEAT_LINK_STATE)
1115                         link_state = (wIndex & 0xff00) >> 3;
1116                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1117                         wake_mask = wIndex & 0xff00;
1118                 if (wValue == USB_PORT_FEAT_TEST)
1119                         test_mode = (wIndex & 0xff00) >> 8;
1120                 /* The MSB of wIndex is the U1/U2 timeout */
1121                 timeout = (wIndex & 0xff00) >> 8;
1122                 wIndex &= 0xff;
1123                 if (!wIndex || wIndex > max_ports)
1124                         goto error;
1125                 wIndex--;
1126                 temp = readl(port_array[wIndex]);
1127                 if (temp == ~(u32)0) {
1128                         xhci_hc_died(xhci);
1129                         retval = -ENODEV;
1130                         break;
1131                 }
1132                 temp = xhci_port_state_to_neutral(temp);
1133                 /* FIXME: What new port features do we need to support? */
1134                 switch (wValue) {
1135                 case USB_PORT_FEAT_SUSPEND:
1136                         temp = readl(port_array[wIndex]);
1137                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1138                                 /* Resume the port to U0 first */
1139                                 xhci_set_link_state(xhci, port_array, wIndex,
1140                                                         XDEV_U0);
1141                                 spin_unlock_irqrestore(&xhci->lock, flags);
1142                                 msleep(10);
1143                                 spin_lock_irqsave(&xhci->lock, flags);
1144                         }
1145                         /* In spec software should not attempt to suspend
1146                          * a port unless the port reports that it is in the
1147                          * enabled (PED = ‘1’,PLS < ‘3’) state.
1148                          */
1149                         temp = readl(port_array[wIndex]);
1150                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1151                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1152                                 xhci_warn(xhci, "USB core suspending device not in U0/U1/U2.\n");
1153                                 goto error;
1154                         }
1155
1156                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1157                                         wIndex + 1);
1158                         if (!slot_id) {
1159                                 xhci_warn(xhci, "slot_id is zero\n");
1160                                 goto error;
1161                         }
1162                         /* unlock to execute stop endpoint commands */
1163                         spin_unlock_irqrestore(&xhci->lock, flags);
1164                         xhci_stop_device(xhci, slot_id, 1);
1165                         spin_lock_irqsave(&xhci->lock, flags);
1166
1167                         xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
1168
1169                         spin_unlock_irqrestore(&xhci->lock, flags);
1170                         msleep(10); /* wait device to enter */
1171                         spin_lock_irqsave(&xhci->lock, flags);
1172
1173                         temp = readl(port_array[wIndex]);
1174                         bus_state->suspended_ports |= 1 << wIndex;
1175                         break;
1176                 case USB_PORT_FEAT_LINK_STATE:
1177                         temp = readl(port_array[wIndex]);
1178
1179                         /* Disable port */
1180                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1181                                 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1182                                 temp = xhci_port_state_to_neutral(temp);
1183                                 /*
1184                                  * Clear all change bits, so that we get a new
1185                                  * connection event.
1186                                  */
1187                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1188                                         PORT_OCC | PORT_RC | PORT_PLC |
1189                                         PORT_CEC;
1190                                 writel(temp | PORT_PE, port_array[wIndex]);
1191                                 temp = readl(port_array[wIndex]);
1192                                 break;
1193                         }
1194
1195                         /* Put link in RxDetect (enable port) */
1196                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1197                                 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1198                                 xhci_set_link_state(xhci, port_array, wIndex,
1199                                                 link_state);
1200                                 temp = readl(port_array[wIndex]);
1201                                 break;
1202                         }
1203
1204                         /*
1205                          * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1206                          * root hub port's transition to compliance mode upon
1207                          * detecting LFPS timeout may be controlled by an
1208                          * Compliance Transition Enabled (CTE) flag (not
1209                          * software visible). This flag is set by writing 0xA
1210                          * to PORTSC PLS field which will allow transition to
1211                          * compliance mode the next time LFPS timeout is
1212                          * encountered. A warm reset will clear it.
1213                          *
1214                          * The CTE flag is only supported if the HCCPARAMS2 CTC
1215                          * flag is set, otherwise, the compliance substate is
1216                          * automatically entered as on 1.0 and prior.
1217                          */
1218                         if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1219                                 if (!HCC2_CTC(xhci->hcc_params2)) {
1220                                         xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1221                                         break;
1222                                 }
1223
1224                                 if ((temp & PORT_CONNECT)) {
1225                                         xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1226                                         goto error;
1227                                 }
1228
1229                                 xhci_dbg(xhci, "Enable compliance mode transition for port %d\n",
1230                                                 wIndex);
1231                                 xhci_set_link_state(xhci, port_array, wIndex,
1232                                                 link_state);
1233                                 temp = readl(port_array[wIndex]);
1234                                 break;
1235                         }
1236
1237                         /* Software should not attempt to set
1238                          * port link state above '3' (U3) and the port
1239                          * must be enabled.
1240                          */
1241                         if ((temp & PORT_PE) == 0 ||
1242                                 (link_state > USB_SS_PORT_LS_U3)) {
1243                                 xhci_warn(xhci, "Cannot set link state.\n");
1244                                 goto error;
1245                         }
1246
1247                         if (link_state == USB_SS_PORT_LS_U3) {
1248                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1249                                                 wIndex + 1);
1250                                 if (slot_id) {
1251                                         /* unlock to execute stop endpoint
1252                                          * commands */
1253                                         spin_unlock_irqrestore(&xhci->lock,
1254                                                                 flags);
1255                                         xhci_stop_device(xhci, slot_id, 1);
1256                                         spin_lock_irqsave(&xhci->lock, flags);
1257                                 }
1258                         }
1259
1260                         xhci_set_link_state(xhci, port_array, wIndex,
1261                                                 link_state);
1262
1263                         spin_unlock_irqrestore(&xhci->lock, flags);
1264                         msleep(20); /* wait device to enter */
1265                         spin_lock_irqsave(&xhci->lock, flags);
1266
1267                         temp = readl(port_array[wIndex]);
1268                         if (link_state == USB_SS_PORT_LS_U3)
1269                                 bus_state->suspended_ports |= 1 << wIndex;
1270                         break;
1271                 case USB_PORT_FEAT_POWER:
1272                         /*
1273                          * Turn on ports, even if there isn't per-port switching.
1274                          * HC will report connect events even before this is set.
1275                          * However, hub_wq will ignore the roothub events until
1276                          * the roothub is registered.
1277                          */
1278                         xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1279                         break;
1280                 case USB_PORT_FEAT_RESET:
1281                         temp = (temp | PORT_RESET);
1282                         writel(temp, port_array[wIndex]);
1283
1284                         temp = readl(port_array[wIndex]);
1285                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
1286                         break;
1287                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1288                         xhci_set_remote_wake_mask(xhci, port_array,
1289                                         wIndex, wake_mask);
1290                         temp = readl(port_array[wIndex]);
1291                         xhci_dbg(xhci, "set port remote wake mask, "
1292                                         "actual port %d status  = 0x%x\n",
1293                                         wIndex, temp);
1294                         break;
1295                 case USB_PORT_FEAT_BH_PORT_RESET:
1296                         temp |= PORT_WR;
1297                         writel(temp, port_array[wIndex]);
1298
1299                         temp = readl(port_array[wIndex]);
1300                         break;
1301                 case USB_PORT_FEAT_U1_TIMEOUT:
1302                         if (hcd->speed < HCD_USB3)
1303                                 goto error;
1304                         temp = readl(port_array[wIndex] + PORTPMSC);
1305                         temp &= ~PORT_U1_TIMEOUT_MASK;
1306                         temp |= PORT_U1_TIMEOUT(timeout);
1307                         writel(temp, port_array[wIndex] + PORTPMSC);
1308                         break;
1309                 case USB_PORT_FEAT_U2_TIMEOUT:
1310                         if (hcd->speed < HCD_USB3)
1311                                 goto error;
1312                         temp = readl(port_array[wIndex] + PORTPMSC);
1313                         temp &= ~PORT_U2_TIMEOUT_MASK;
1314                         temp |= PORT_U2_TIMEOUT(timeout);
1315                         writel(temp, port_array[wIndex] + PORTPMSC);
1316                         break;
1317                 case USB_PORT_FEAT_TEST:
1318                         /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1319                         if (hcd->speed != HCD_USB2)
1320                                 goto error;
1321                         if (test_mode > TEST_FORCE_EN || test_mode < TEST_J)
1322                                 goto error;
1323                         retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1324                                                       &flags);
1325                         break;
1326                 default:
1327                         goto error;
1328                 }
1329                 /* unblock any posted writes */
1330                 temp = readl(port_array[wIndex]);
1331                 break;
1332         case ClearPortFeature:
1333                 if (!wIndex || wIndex > max_ports)
1334                         goto error;
1335                 wIndex--;
1336                 temp = readl(port_array[wIndex]);
1337                 if (temp == ~(u32)0) {
1338                         xhci_hc_died(xhci);
1339                         retval = -ENODEV;
1340                         break;
1341                 }
1342                 /* FIXME: What new port features do we need to support? */
1343                 temp = xhci_port_state_to_neutral(temp);
1344                 switch (wValue) {
1345                 case USB_PORT_FEAT_SUSPEND:
1346                         temp = readl(port_array[wIndex]);
1347                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1348                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
1349                         if (temp & PORT_RESET)
1350                                 goto error;
1351                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1352                                 if ((temp & PORT_PE) == 0)
1353                                         goto error;
1354
1355                                 set_bit(wIndex, &bus_state->resuming_ports);
1356                                 xhci_set_link_state(xhci, port_array, wIndex,
1357                                                         XDEV_RESUME);
1358                                 spin_unlock_irqrestore(&xhci->lock, flags);
1359                                 msleep(USB_RESUME_TIMEOUT);
1360                                 spin_lock_irqsave(&xhci->lock, flags);
1361                                 xhci_set_link_state(xhci, port_array, wIndex,
1362                                                         XDEV_U0);
1363                                 clear_bit(wIndex, &bus_state->resuming_ports);
1364                         }
1365                         bus_state->port_c_suspend |= 1 << wIndex;
1366
1367                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1368                                         wIndex + 1);
1369                         if (!slot_id) {
1370                                 xhci_dbg(xhci, "slot_id is zero\n");
1371                                 goto error;
1372                         }
1373                         xhci_ring_device(xhci, slot_id);
1374                         break;
1375                 case USB_PORT_FEAT_C_SUSPEND:
1376                         bus_state->port_c_suspend &= ~(1 << wIndex);
1377                 case USB_PORT_FEAT_C_RESET:
1378                 case USB_PORT_FEAT_C_BH_PORT_RESET:
1379                 case USB_PORT_FEAT_C_CONNECTION:
1380                 case USB_PORT_FEAT_C_OVER_CURRENT:
1381                 case USB_PORT_FEAT_C_ENABLE:
1382                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1383                 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1384                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1385                                         port_array[wIndex], temp);
1386                         break;
1387                 case USB_PORT_FEAT_ENABLE:
1388                         xhci_disable_port(hcd, xhci, wIndex,
1389                                         port_array[wIndex], temp);
1390                         break;
1391                 case USB_PORT_FEAT_POWER:
1392                         xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1393                         break;
1394                 case USB_PORT_FEAT_TEST:
1395                         retval = xhci_exit_test_mode(xhci);
1396                         break;
1397                 default:
1398                         goto error;
1399                 }
1400                 break;
1401         default:
1402 error:
1403                 /* "stall" on error */
1404                 retval = -EPIPE;
1405         }
1406         spin_unlock_irqrestore(&xhci->lock, flags);
1407         return retval;
1408 }
1409
1410 /*
1411  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1412  * Ports are 0-indexed from the HCD point of view,
1413  * and 1-indexed from the USB core pointer of view.
1414  *
1415  * Note that the status change bits will be cleared as soon as a port status
1416  * change event is generated, so we use the saved status from that event.
1417  */
1418 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1419 {
1420         unsigned long flags;
1421         u32 temp, status;
1422         u32 mask;
1423         int i, retval;
1424         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1425         int max_ports;
1426         __le32 __iomem **port_array;
1427         struct xhci_bus_state *bus_state;
1428         bool reset_change = false;
1429
1430         max_ports = xhci_get_ports(hcd, &port_array);
1431         bus_state = &xhci->bus_state[hcd_index(hcd)];
1432
1433         /* Initial status is no changes */
1434         retval = (max_ports + 8) / 8;
1435         memset(buf, 0, retval);
1436
1437         /*
1438          * Inform the usbcore about resume-in-progress by returning
1439          * a non-zero value even if there are no status changes.
1440          */
1441         status = bus_state->resuming_ports;
1442
1443         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1444
1445         spin_lock_irqsave(&xhci->lock, flags);
1446         /* For each port, did anything change?  If so, set that bit in buf. */
1447         for (i = 0; i < max_ports; i++) {
1448                 temp = readl(port_array[i]);
1449                 if (temp == ~(u32)0) {
1450                         xhci_hc_died(xhci);
1451                         retval = -ENODEV;
1452                         break;
1453                 }
1454                 if ((temp & mask) != 0 ||
1455                         (bus_state->port_c_suspend & 1 << i) ||
1456                         (bus_state->resume_done[i] && time_after_eq(
1457                             jiffies, bus_state->resume_done[i]))) {
1458                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1459                         status = 1;
1460                 }
1461                 if ((temp & PORT_RC))
1462                         reset_change = true;
1463         }
1464         if (!status && !reset_change) {
1465                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1466                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1467         }
1468         spin_unlock_irqrestore(&xhci->lock, flags);
1469         return status ? retval : 0;
1470 }
1471
1472 #ifdef CONFIG_PM
1473
1474 int xhci_bus_suspend(struct usb_hcd *hcd)
1475 {
1476         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1477         int max_ports, port_index;
1478         __le32 __iomem **port_array;
1479         struct xhci_bus_state *bus_state;
1480         unsigned long flags;
1481
1482         max_ports = xhci_get_ports(hcd, &port_array);
1483         bus_state = &xhci->bus_state[hcd_index(hcd)];
1484
1485         spin_lock_irqsave(&xhci->lock, flags);
1486
1487         if (hcd->self.root_hub->do_remote_wakeup) {
1488                 if (bus_state->resuming_ports ||        /* USB2 */
1489                     bus_state->port_remote_wakeup) {    /* USB3 */
1490                         spin_unlock_irqrestore(&xhci->lock, flags);
1491                         xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1492                         return -EBUSY;
1493                 }
1494         }
1495
1496         port_index = max_ports;
1497         bus_state->bus_suspended = 0;
1498         while (port_index--) {
1499                 /* suspend the port if the port is not suspended */
1500                 u32 t1, t2;
1501                 int slot_id;
1502
1503                 t1 = readl(port_array[port_index]);
1504                 t2 = xhci_port_state_to_neutral(t1);
1505
1506                 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1507                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1508                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1509                                         port_index + 1);
1510                         if (slot_id) {
1511                                 spin_unlock_irqrestore(&xhci->lock, flags);
1512                                 xhci_stop_device(xhci, slot_id, 1);
1513                                 spin_lock_irqsave(&xhci->lock, flags);
1514                         }
1515                         t2 &= ~PORT_PLS_MASK;
1516                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1517                         set_bit(port_index, &bus_state->bus_suspended);
1518                 }
1519                 /* USB core sets remote wake mask for USB 3.0 hubs,
1520                  * including the USB 3.0 roothub, but only if CONFIG_PM
1521                  * is enabled, so also enable remote wake here.
1522                  */
1523                 if (hcd->self.root_hub->do_remote_wakeup) {
1524                         if (t1 & PORT_CONNECT) {
1525                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1526                                 t2 &= ~PORT_WKCONN_E;
1527                         } else {
1528                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1529                                 t2 &= ~PORT_WKDISC_E;
1530                         }
1531                 } else
1532                         t2 &= ~PORT_WAKE_BITS;
1533
1534                 t1 = xhci_port_state_to_neutral(t1);
1535                 if (t1 != t2)
1536                         writel(t2, port_array[port_index]);
1537         }
1538         hcd->state = HC_STATE_SUSPENDED;
1539         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1540         spin_unlock_irqrestore(&xhci->lock, flags);
1541         return 0;
1542 }
1543
1544 /*
1545  * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1546  * warm reset a USB3 device stuck in polling or compliance mode after resume.
1547  * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1548  */
1549 static bool xhci_port_missing_cas_quirk(int port_index,
1550                                              __le32 __iomem **port_array)
1551 {
1552         u32 portsc;
1553
1554         portsc = readl(port_array[port_index]);
1555
1556         /* if any of these are set we are not stuck */
1557         if (portsc & (PORT_CONNECT | PORT_CAS))
1558                 return false;
1559
1560         if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1561             ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1562                 return false;
1563
1564         /* clear wakeup/change bits, and do a warm port reset */
1565         portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1566         portsc |= PORT_WR;
1567         writel(portsc, port_array[port_index]);
1568         /* flush write */
1569         readl(port_array[port_index]);
1570         return true;
1571 }
1572
1573 int xhci_bus_resume(struct usb_hcd *hcd)
1574 {
1575         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1576         struct xhci_bus_state *bus_state;
1577         __le32 __iomem **port_array;
1578         unsigned long flags;
1579         int max_ports, port_index;
1580         int slot_id;
1581         int sret;
1582         u32 next_state;
1583         u32 temp, portsc;
1584
1585         max_ports = xhci_get_ports(hcd, &port_array);
1586         bus_state = &xhci->bus_state[hcd_index(hcd)];
1587
1588         if (time_before(jiffies, bus_state->next_statechange))
1589                 msleep(5);
1590
1591         spin_lock_irqsave(&xhci->lock, flags);
1592         if (!HCD_HW_ACCESSIBLE(hcd)) {
1593                 spin_unlock_irqrestore(&xhci->lock, flags);
1594                 return -ESHUTDOWN;
1595         }
1596
1597         /* delay the irqs */
1598         temp = readl(&xhci->op_regs->command);
1599         temp &= ~CMD_EIE;
1600         writel(temp, &xhci->op_regs->command);
1601
1602         /* bus specific resume for ports we suspended at bus_suspend */
1603         if (hcd->speed >= HCD_USB3)
1604                 next_state = XDEV_U0;
1605         else
1606                 next_state = XDEV_RESUME;
1607
1608         port_index = max_ports;
1609         while (port_index--) {
1610                 portsc = readl(port_array[port_index]);
1611
1612                 /* warm reset CAS limited ports stuck in polling/compliance */
1613                 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1614                     (hcd->speed >= HCD_USB3) &&
1615                     xhci_port_missing_cas_quirk(port_index, port_array)) {
1616                         xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1617                         clear_bit(port_index, &bus_state->bus_suspended);
1618                         continue;
1619                 }
1620                 /* resume if we suspended the link, and it is still suspended */
1621                 if (test_bit(port_index, &bus_state->bus_suspended))
1622                         switch (portsc & PORT_PLS_MASK) {
1623                         case XDEV_U3:
1624                                 portsc = xhci_port_state_to_neutral(portsc);
1625                                 portsc &= ~PORT_PLS_MASK;
1626                                 portsc |= PORT_LINK_STROBE | next_state;
1627                                 break;
1628                         case XDEV_RESUME:
1629                                 /* resume already initiated */
1630                                 break;
1631                         default:
1632                                 /* not in a resumeable state, ignore it */
1633                                 clear_bit(port_index,
1634                                           &bus_state->bus_suspended);
1635                                 break;
1636                         }
1637                 /* disable wake for all ports, write new link state if needed */
1638                 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1639                 writel(portsc, port_array[port_index]);
1640         }
1641
1642         /* USB2 specific resume signaling delay and U0 link state transition */
1643         if (hcd->speed < HCD_USB3) {
1644                 if (bus_state->bus_suspended) {
1645                         spin_unlock_irqrestore(&xhci->lock, flags);
1646                         msleep(USB_RESUME_TIMEOUT);
1647                         spin_lock_irqsave(&xhci->lock, flags);
1648                 }
1649                 for_each_set_bit(port_index, &bus_state->bus_suspended,
1650                                  BITS_PER_LONG) {
1651                         /* Clear PLC to poll it later for U0 transition */
1652                         xhci_test_and_clear_bit(xhci, port_array, port_index,
1653                                                 PORT_PLC);
1654                         xhci_set_link_state(xhci, port_array, port_index,
1655                                             XDEV_U0);
1656                 }
1657         }
1658
1659         /* poll for U0 link state complete, both USB2 and USB3 */
1660         for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1661                 sret = xhci_handshake(port_array[port_index], PORT_PLC,
1662                                       PORT_PLC, 10 * 1000);
1663                 if (sret) {
1664                         xhci_warn(xhci, "port %d resume PLC timeout\n",
1665                                   port_index);
1666                         continue;
1667                 }
1668                 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1669                 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1670                 if (slot_id)
1671                         xhci_ring_device(xhci, slot_id);
1672         }
1673         (void) readl(&xhci->op_regs->command);
1674
1675         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1676         /* re-enable irqs */
1677         temp = readl(&xhci->op_regs->command);
1678         temp |= CMD_EIE;
1679         writel(temp, &xhci->op_regs->command);
1680         temp = readl(&xhci->op_regs->command);
1681
1682         spin_unlock_irqrestore(&xhci->lock, flags);
1683         return 0;
1684 }
1685
1686 #endif  /* CONFIG_PM */