drivers/usb/host/xhci-hub.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11
  12 #include <linux/slab.h>
  13 #include <asm/unaligned.h>
  14
  15 #include "xhci.h"
  16 #include "xhci-trace.h"
  17
  18 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  19 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  20                          PORT_RC | PORT_PLC | PORT_PE)
  21
  22 /* USB 3 BOS descriptor and a capability descriptors, combined.
  23  * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
  24  */
  25 static u8 usb_bos_descriptor [] = {
  26         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  27         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  28         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  29         0x1,                            /*  __u8 bNumDeviceCaps */
  30         /* First device capability, SuperSpeed */
  31         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  32         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  33         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  34         0x00,                           /* bmAttributes, LTM off by default */
  35         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  36         0x03,                           /* bFunctionalitySupport,
  37                                            USB 3.0 speed only */
  38         0x00,                           /* bU1DevExitLat, set later. */
  39         0x00, 0x00,                     /* __le16 bU2DevExitLat, set later. */
  40         /* Second device capability, SuperSpeedPlus */
  41         0x1c,                           /* bLength 28, will be adjusted later */
  42         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  43         USB_SSP_CAP_TYPE,               /* bDevCapabilityType SUPERSPEED_PLUS */
  44         0x00,                           /* bReserved 0 */
  45         0x23, 0x00, 0x00, 0x00,         /* bmAttributes, SSAC=3 SSIC=1 */
  46         0x01, 0x00,                     /* wFunctionalitySupport */
  47         0x00, 0x00,                     /* wReserved 0 */
  48         /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
  49         0x34, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, rx, ID = 4 */
  50         0xb4, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, tx, ID = 4 */
  51         0x35, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, rx, ID = 5 */
  52         0xb5, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, tx, ID = 5 */
  53 };
  54
  55 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
  56                                      u16 wLength)
  57 {
  58         int i, ssa_count;
  59         u32 temp;
  60         u16 desc_size, ssp_cap_size, ssa_size = 0;
  61         bool usb3_1 = false;
  62
  63         desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
  64         ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
  65
  66         /* does xhci support USB 3.1 Enhanced SuperSpeed */
  67         if (xhci->usb3_rhub.min_rev >= 0x01) {
  68                 /* does xhci provide a PSI table for SSA speed attributes? */
  69                 if (xhci->usb3_rhub.psi_count) {
  70                         /* two SSA entries for each unique PSI ID, RX and TX */
  71                         ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
  72                         ssa_size = ssa_count * sizeof(u32);
  73                         ssp_cap_size -= 16; /* skip copying the default SSA */
  74                 }
  75                 desc_size += ssp_cap_size;
  76                 usb3_1 = true;
  77         }
  78         memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
  79
  80         if (usb3_1) {
  81                 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
  82                 buf[4] += 1;
  83                 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
  84         }
  85
  86         if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
  87                 return wLength;
  88
  89         /* Indicate whether the host has LTM support. */
  90         temp = readl(&xhci->cap_regs->hcc_params);
  91         if (HCC_LTC(temp))
  92                 buf[8] |= USB_LTM_SUPPORT;
  93
  94         /* Set the U1 and U2 exit latencies. */
  95         if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
  96                 temp = readl(&xhci->cap_regs->hcs_params3);
  97                 buf[12] = HCS_U1_LATENCY(temp);
  98                 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
  99         }
 100
 101         /* If PSI table exists, add the custom speed attributes from it */
 102         if (usb3_1 && xhci->usb3_rhub.psi_count) {
 103                 u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
 104                 int offset;
 105
 106                 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 107
 108                 if (wLength < desc_size)
 109                         return wLength;
 110                 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
 111
 112                 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
 113                 bm_attrib = (ssa_count - 1) & 0x1f;
 114                 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
 115                 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
 116
 117                 if (wLength < desc_size + ssa_size)
 118                         return wLength;
 119                 /*
 120                  * Create the Sublink Speed Attributes (SSA) array.
 121                  * The xhci PSI field and USB 3.1 SSA fields are very similar,
 122                  * but link type bits 7:6 differ for values 01b and 10b.
 123                  * xhci has also only one PSI entry for a symmetric link when
 124                  * USB 3.1 requires two SSA entries (RX and TX) for every link
 125                  */
 126                 offset = desc_size;
 127                 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
 128                         psi = xhci->usb3_rhub.psi[i];
 129                         psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
 130                         psi_exp = XHCI_EXT_PORT_PSIE(psi);
 131                         psi_mant = XHCI_EXT_PORT_PSIM(psi);
 132
 133                         /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
 134                         for (; psi_exp < 3; psi_exp++)
 135                                 psi_mant /= 1000;
 136                         if (psi_mant >= 10)
 137                                 psi |= BIT(14);
 138
 139                         if ((psi & PLT_MASK) == PLT_SYM) {
 140                         /* Symmetric, create SSA RX and TX from one PSI entry */
 141                                 put_unaligned_le32(psi, &buf[offset]);
 142                                 psi |= 1 << 7;  /* turn entry to TX */
 143                                 offset += 4;
 144                                 if (offset >= desc_size + ssa_size)
 145                                         return desc_size + ssa_size;
 146                         } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
 147                                 /* Asymetric RX, flip bits 7:6 for SSA */
 148                                 psi ^= PLT_MASK;
 149                         }
 150                         put_unaligned_le32(psi, &buf[offset]);
 151                         offset += 4;
 152                         if (offset >= desc_size + ssa_size)
 153                                 return desc_size + ssa_size;
 154                 }
 155         }
 156         /* ssa_size is 0 for other than usb 3.1 hosts */
 157         return desc_size + ssa_size;
 158 }
 159
 160 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
 161                 struct usb_hub_descriptor *desc, int ports)
 162 {
 163         u16 temp;
 164
 165         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.9 says 20ms max */
 166         desc->bHubContrCurrent = 0;
 167
 168         desc->bNbrPorts = ports;
 169         temp = 0;
 170         /* Bits 1:0 - support per-port power switching, or power always on */
 171         if (HCC_PPC(xhci->hcc_params))
 172                 temp |= HUB_CHAR_INDV_PORT_LPSM;
 173         else
 174                 temp |= HUB_CHAR_NO_LPSM;
 175         /* Bit  2 - root hubs are not part of a compound device */
 176         /* Bits 4:3 - individual port over current protection */
 177         temp |= HUB_CHAR_INDV_PORT_OCPM;
 178         /* Bits 6:5 - no TTs in root ports */
 179         /* Bit  7 - no port indicators */
 180         desc->wHubCharacteristics = cpu_to_le16(temp);
 181 }
 182
 183 /* Fill in the USB 2.0 roothub descriptor */
 184 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 185                 struct usb_hub_descriptor *desc)
 186 {
 187         int ports;
 188         u16 temp;
 189         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
 190         u32 portsc;
 191         unsigned int i;
 192         struct xhci_hub *rhub;
 193
 194         rhub = &xhci->usb2_rhub;
 195         ports = rhub->num_ports;
 196         xhci_common_hub_descriptor(xhci, desc, ports);
 197         desc->bDescriptorType = USB_DT_HUB;
 198         temp = 1 + (ports / 8);
 199         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
 200
 201         /* The Device Removable bits are reported on a byte granularity.
 202          * If the port doesn't exist within that byte, the bit is set to 0.
 203          */
 204         memset(port_removable, 0, sizeof(port_removable));
 205         for (i = 0; i < ports; i++) {
 206                 portsc = readl(rhub->ports[i]->addr);
 207                 /* If a device is removable, PORTSC reports a 0, same as in the
 208                  * hub descriptor DeviceRemovable bits.
 209                  */
 210                 if (portsc & PORT_DEV_REMOVE)
 211                         /* This math is hairy because bit 0 of DeviceRemovable
 212                          * is reserved, and bit 1 is for port 1, etc.
 213                          */
 214                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 215         }
 216
 217         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 218          * ports on it.  The USB 2.0 specification says that there are two
 219          * variable length fields at the end of the hub descriptor:
 220          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 221          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 222          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 223          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 224          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 225          * set of ports that actually exist.
 226          */
 227         memset(desc->u.hs.DeviceRemovable, 0xff,
 228                         sizeof(desc->u.hs.DeviceRemovable));
 229         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 230                         sizeof(desc->u.hs.PortPwrCtrlMask));
 231
 232         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 233                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 234                                 sizeof(__u8));
 235 }
 236
 237 /* Fill in the USB 3.0 roothub descriptor */
 238 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 239                 struct usb_hub_descriptor *desc)
 240 {
 241         int ports;
 242         u16 port_removable;
 243         u32 portsc;
 244         unsigned int i;
 245         struct xhci_hub *rhub;
 246
 247         rhub = &xhci->usb3_rhub;
 248         ports = rhub->num_ports;
 249         xhci_common_hub_descriptor(xhci, desc, ports);
 250         desc->bDescriptorType = USB_DT_SS_HUB;
 251         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 252
 253         /* header decode latency should be zero for roothubs,
 254          * see section 4.23.5.2.
 255          */
 256         desc->u.ss.bHubHdrDecLat = 0;
 257         desc->u.ss.wHubDelay = 0;
 258
 259         port_removable = 0;
 260         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 261         for (i = 0; i < ports; i++) {
 262                 portsc = readl(rhub->ports[i]->addr);
 263                 if (portsc & PORT_DEV_REMOVE)
 264                         port_removable |= 1 << (i + 1);
 265         }
 266
 267         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 268 }
 269
 270 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 271                 struct usb_hub_descriptor *desc)
 272 {
 273
 274         if (hcd->speed >= HCD_USB3)
 275                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 276         else
 277                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 278
 279 }
 280
 281 static unsigned int xhci_port_speed(unsigned int port_status)
 282 {
 283         if (DEV_LOWSPEED(port_status))
 284                 return USB_PORT_STAT_LOW_SPEED;
 285         if (DEV_HIGHSPEED(port_status))
 286                 return USB_PORT_STAT_HIGH_SPEED;
 287         /*
 288          * FIXME: Yes, we should check for full speed, but the core uses that as
 289          * a default in portspeed() in usb/core/hub.c (which is the only place
 290          * USB_PORT_STAT_*_SPEED is used).
 291          */
 292         return 0;
 293 }
 294
 295 /*
 296  * These bits are Read Only (RO) and should be saved and written to the
 297  * registers: 0, 3, 10:13, 30
 298  * connect status, over-current status, port speed, and device removable.
 299  * connect status and port speed are also sticky - meaning they're in
 300  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 301  */
 302 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 303 /*
 304  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 305  * bits 5:8, 9, 14:15, 25:27
 306  * link state, port power, port indicator state, "wake on" enable state
 307  */
 308 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 309 /*
 310  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 311  * bit 4 (port reset)
 312  */
 313 #define XHCI_PORT_RW1S  ((1<<4))
 314 /*
 315  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 316  * bits 1, 17, 18, 19, 20, 21, 22, 23
 317  * port enable/disable, and
 318  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 319  * over-current, reset, link state, and L1 change
 320  */
 321 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 322 /*
 323  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 324  * latched in
 325  */
 326 #define XHCI_PORT_RW    ((1<<16))
 327 /*
 328  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 329  * bits 2, 24, 28:31
 330  */
 331 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 332
 333 /*
 334  * Given a port state, this function returns a value that would result in the
 335  * port being in the same state, if the value was written to the port status
 336  * control register.
 337  * Save Read Only (RO) bits and save read/write bits where
 338  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 339  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 340  */
 341 u32 xhci_port_state_to_neutral(u32 state)
 342 {
 343         /* Save read-only status and port state */
 344         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 345 }
 346
 347 /*
 348  * find slot id based on port number.
 349  * @port: The one-based port number from one of the two split roothubs.
 350  */
 351 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 352                 u16 port)
 353 {
 354         int slot_id;
 355         int i;
 356         enum usb_device_speed speed;
 357
 358         slot_id = 0;
 359         for (i = 0; i < MAX_HC_SLOTS; i++) {
 360                 if (!xhci->devs[i] || !xhci->devs[i]->udev)
 361                         continue;
 362                 speed = xhci->devs[i]->udev->speed;
 363                 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
 364                                 && xhci->devs[i]->fake_port == port) {
 365                         slot_id = i;
 366                         break;
 367                 }
 368         }
 369
 370         return slot_id;
 371 }
 372
 373 /*
 374  * Stop device
 375  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 376  * to complete.
 377  * suspend will set to 1, if suspend bit need to set in command.
 378  */
 379 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 380 {
 381         struct xhci_virt_device *virt_dev;
 382         struct xhci_command *cmd;
 383         unsigned long flags;
 384         int ret;
 385         int i;
 386
 387         ret = 0;
 388         virt_dev = xhci->devs[slot_id];
 389         if (!virt_dev)
 390                 return -ENODEV;
 391
 392         trace_xhci_stop_device(virt_dev);
 393
 394         cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
 395         if (!cmd)
 396                 return -ENOMEM;
 397
 398         spin_lock_irqsave(&xhci->lock, flags);
 399         for (i = LAST_EP_INDEX; i > 0; i--) {
 400                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
 401                         struct xhci_ep_ctx *ep_ctx;
 402                         struct xhci_command *command;
 403
 404                         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
 405
 406                         /* Check ep is running, required by AMD SNPS 3.1 xHC */
 407                         if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
 408                                 continue;
 409
 410                         command = xhci_alloc_command(xhci, false, GFP_NOWAIT);
 411                         if (!command) {
 412                                 spin_unlock_irqrestore(&xhci->lock, flags);
 413                                 ret = -ENOMEM;
 414                                 goto cmd_cleanup;
 415                         }
 416
 417                         ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
 418                                                        i, suspend);
 419                         if (ret) {
 420                                 spin_unlock_irqrestore(&xhci->lock, flags);
 421                                 xhci_free_command(xhci, command);
 422                                 goto cmd_cleanup;
 423                         }
 424                 }
 425         }
 426         ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
 427         if (ret) {
 428                 spin_unlock_irqrestore(&xhci->lock, flags);
 429                 goto cmd_cleanup;
 430         }
 431
 432         xhci_ring_cmd_db(xhci);
 433         spin_unlock_irqrestore(&xhci->lock, flags);
 434
 435         /* Wait for last stop endpoint command to finish */
 436         wait_for_completion(cmd->completion);
 437
 438         if (cmd->status == COMP_COMMAND_ABORTED ||
 439             cmd->status == COMP_COMMAND_RING_STOPPED) {
 440                 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
 441                 ret = -ETIME;
 442         }
 443
 444 cmd_cleanup:
 445         xhci_free_command(xhci, cmd);
 446         return ret;
 447 }
 448
 449 /*
 450  * Ring device, it rings the all doorbells unconditionally.
 451  */
 452 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 453 {
 454         int i, s;
 455         struct xhci_virt_ep *ep;
 456
 457         for (i = 0; i < LAST_EP_INDEX + 1; i++) {
 458                 ep = &xhci->devs[slot_id]->eps[i];
 459
 460                 if (ep->ep_state & EP_HAS_STREAMS) {
 461                         for (s = 1; s < ep->stream_info->num_streams; s++)
 462                                 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
 463                 } else if (ep->ring && ep->ring->dequeue) {
 464                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 465                 }
 466         }
 467
 468         return;
 469 }
 470
 471 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 472                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 473 {
 474         /* Don't allow the USB core to disable SuperSpeed ports. */
 475         if (hcd->speed >= HCD_USB3) {
 476                 xhci_dbg(xhci, "Ignoring request to disable "
 477                                 "SuperSpeed port.\n");
 478                 return;
 479         }
 480
 481         if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
 482                 xhci_dbg(xhci,
 483                          "Broken Port Enabled/Disabled, ignoring port disable request.\n");
 484                 return;
 485         }
 486
 487         /* Write 1 to disable the port */
 488         writel(port_status | PORT_PE, addr);
 489         port_status = readl(addr);
 490         xhci_dbg(xhci, "disable port %d-%d, portsc: 0x%x\n",
 491                  hcd->self.busnum, wIndex + 1, port_status);
 492 }
 493
 494 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 495                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 496 {
 497         char *port_change_bit;
 498         u32 status;
 499
 500         switch (wValue) {
 501         case USB_PORT_FEAT_C_RESET:
 502                 status = PORT_RC;
 503                 port_change_bit = "reset";
 504                 break;
 505         case USB_PORT_FEAT_C_BH_PORT_RESET:
 506                 status = PORT_WRC;
 507                 port_change_bit = "warm(BH) reset";
 508                 break;
 509         case USB_PORT_FEAT_C_CONNECTION:
 510                 status = PORT_CSC;
 511                 port_change_bit = "connect";
 512                 break;
 513         case USB_PORT_FEAT_C_OVER_CURRENT:
 514                 status = PORT_OCC;
 515                 port_change_bit = "over-current";
 516                 break;
 517         case USB_PORT_FEAT_C_ENABLE:
 518                 status = PORT_PEC;
 519                 port_change_bit = "enable/disable";
 520                 break;
 521         case USB_PORT_FEAT_C_SUSPEND:
 522                 status = PORT_PLC;
 523                 port_change_bit = "suspend/resume";
 524                 break;
 525         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 526                 status = PORT_PLC;
 527                 port_change_bit = "link state";
 528                 break;
 529         case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
 530                 status = PORT_CEC;
 531                 port_change_bit = "config error";
 532                 break;
 533         default:
 534                 /* Should never happen */
 535                 return;
 536         }
 537         /* Change bits are all write 1 to clear */
 538         writel(port_status | status, addr);
 539         port_status = readl(addr);
 540
 541         xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n",
 542                  wIndex + 1, port_change_bit, port_status);
 543 }
 544
 545 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
 546 {
 547         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 548
 549         if (hcd->speed >= HCD_USB3)
 550                 return &xhci->usb3_rhub;
 551         return &xhci->usb2_rhub;
 552 }
 553
 554 /*
 555  * xhci_set_port_power() must be called with xhci->lock held.
 556  * It will release and re-aquire the lock while calling ACPI
 557  * method.
 558  */
 559 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
 560                                 u16 index, bool on, unsigned long *flags)
 561 {
 562         struct xhci_hub *rhub;
 563         struct xhci_port *port;
 564         u32 temp;
 565
 566         rhub = xhci_get_rhub(hcd);
 567         port = rhub->ports[index];
 568         temp = readl(port->addr);
 569
 570         xhci_dbg(xhci, "set port power %d-%d %s, portsc: 0x%x\n",
 571                  hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp);
 572
 573         temp = xhci_port_state_to_neutral(temp);
 574
 575         if (on) {
 576                 /* Power on */
 577                 writel(temp | PORT_POWER, port->addr);
 578                 readl(port->addr);
 579         } else {
 580                 /* Power off */
 581                 writel(temp & ~PORT_POWER, port->addr);
 582         }
 583
 584         spin_unlock_irqrestore(&xhci->lock, *flags);
 585         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 586                                         index);
 587         if (temp)
 588                 usb_acpi_set_power_state(hcd->self.root_hub,
 589                         index, on);
 590         spin_lock_irqsave(&xhci->lock, *flags);
 591 }
 592
 593 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
 594         u16 test_mode, u16 wIndex)
 595 {
 596         u32 temp;
 597         struct xhci_port *port;
 598
 599         /* xhci only supports test mode for usb2 ports */
 600         port = xhci->usb2_rhub.ports[wIndex];
 601         temp = readl(port->addr + PORTPMSC);
 602         temp |= test_mode << PORT_TEST_MODE_SHIFT;
 603         writel(temp, port->addr + PORTPMSC);
 604         xhci->test_mode = test_mode;
 605         if (test_mode == TEST_FORCE_EN)
 606                 xhci_start(xhci);
 607 }
 608
 609 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
 610                                 u16 test_mode, u16 wIndex, unsigned long *flags)
 611 {
 612         int i, retval;
 613
 614         /* Disable all Device Slots */
 615         xhci_dbg(xhci, "Disable all slots\n");
 616         spin_unlock_irqrestore(&xhci->lock, *flags);
 617         for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
 618                 if (!xhci->devs[i])
 619                         continue;
 620
 621                 retval = xhci_disable_slot(xhci, i);
 622                 if (retval)
 623                         xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
 624                                  i, retval);
 625         }
 626         spin_lock_irqsave(&xhci->lock, *flags);
 627         /* Put all ports to the Disable state by clear PP */
 628         xhci_dbg(xhci, "Disable all port (PP = 0)\n");
 629         /* Power off USB3 ports*/
 630         for (i = 0; i < xhci->usb3_rhub.num_ports; i++)
 631                 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
 632         /* Power off USB2 ports*/
 633         for (i = 0; i < xhci->usb2_rhub.num_ports; i++)
 634                 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
 635         /* Stop the controller */
 636         xhci_dbg(xhci, "Stop controller\n");
 637         retval = xhci_halt(xhci);
 638         if (retval)
 639                 return retval;
 640         /* Disable runtime PM for test mode */
 641         pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
 642         /* Set PORTPMSC.PTC field to enter selected test mode */
 643         /* Port is selected by wIndex. port_id = wIndex + 1 */
 644         xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
 645                                         test_mode, wIndex + 1);
 646         xhci_port_set_test_mode(xhci, test_mode, wIndex);
 647         return retval;
 648 }
 649
 650 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
 651 {
 652         int retval;
 653
 654         if (!xhci->test_mode) {
 655                 xhci_err(xhci, "Not in test mode, do nothing.\n");
 656                 return 0;
 657         }
 658         if (xhci->test_mode == TEST_FORCE_EN &&
 659                 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
 660                 retval = xhci_halt(xhci);
 661                 if (retval)
 662                         return retval;
 663         }
 664         pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
 665         xhci->test_mode = 0;
 666         return xhci_reset(xhci);
 667 }
 668
 669 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
 670                          u32 link_state)
 671 {
 672         u32 temp;
 673         u32 portsc;
 674
 675         portsc = readl(port->addr);
 676         temp = xhci_port_state_to_neutral(portsc);
 677         temp &= ~PORT_PLS_MASK;
 678         temp |= PORT_LINK_STROBE | link_state;
 679         writel(temp, port->addr);
 680
 681         xhci_dbg(xhci, "Set port %d-%d link state, portsc: 0x%x, write 0x%x",
 682                  port->rhub->hcd->self.busnum, port->hcd_portnum + 1,
 683                  portsc, temp);
 684 }
 685
 686 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 687                                       struct xhci_port *port, u16 wake_mask)
 688 {
 689         u32 temp;
 690
 691         temp = readl(port->addr);
 692         temp = xhci_port_state_to_neutral(temp);
 693
 694         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 695                 temp |= PORT_WKCONN_E;
 696         else
 697                 temp &= ~PORT_WKCONN_E;
 698
 699         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 700                 temp |= PORT_WKDISC_E;
 701         else
 702                 temp &= ~PORT_WKDISC_E;
 703
 704         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 705                 temp |= PORT_WKOC_E;
 706         else
 707                 temp &= ~PORT_WKOC_E;
 708
 709         writel(temp, port->addr);
 710 }
 711
 712 /* Test and clear port RWC bit */
 713 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
 714                              u32 port_bit)
 715 {
 716         u32 temp;
 717
 718         temp = readl(port->addr);
 719         if (temp & port_bit) {
 720                 temp = xhci_port_state_to_neutral(temp);
 721                 temp |= port_bit;
 722                 writel(temp, port->addr);
 723         }
 724 }
 725
 726 /* Updates Link Status for super Speed port */
 727 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
 728                 u32 *status, u32 status_reg)
 729 {
 730         u32 pls = status_reg & PORT_PLS_MASK;
 731
 732         /* resume state is a xHCI internal state.
 733          * Do not report it to usb core, instead, pretend to be U3,
 734          * thus usb core knows it's not ready for transfer
 735          */
 736         if (pls == XDEV_RESUME) {
 737                 *status |= USB_SS_PORT_LS_U3;
 738                 return;
 739         }
 740
 741         /* When the CAS bit is set then warm reset
 742          * should be performed on port
 743          */
 744         if (status_reg & PORT_CAS) {
 745                 /* The CAS bit can be set while the port is
 746                  * in any link state.
 747                  * Only roothubs have CAS bit, so we
 748                  * pretend to be in compliance mode
 749                  * unless we're already in compliance
 750                  * or the inactive state.
 751                  */
 752                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 753                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 754                         pls = USB_SS_PORT_LS_COMP_MOD;
 755                 }
 756                 /* Return also connection bit -
 757                  * hub state machine resets port
 758                  * when this bit is set.
 759                  */
 760                 pls |= USB_PORT_STAT_CONNECTION;
 761         } else {
 762                 /*
 763                  * If CAS bit isn't set but the Port is already at
 764                  * Compliance Mode, fake a connection so the USB core
 765                  * notices the Compliance state and resets the port.
 766                  * This resolves an issue generated by the SN65LVPE502CP
 767                  * in which sometimes the port enters compliance mode
 768                  * caused by a delay on the host-device negotiation.
 769                  */
 770                 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 771                                 (pls == USB_SS_PORT_LS_COMP_MOD))
 772                         pls |= USB_PORT_STAT_CONNECTION;
 773         }
 774
 775         /* update status field */
 776         *status |= pls;
 777 }
 778
 779 /*
 780  * Function for Compliance Mode Quirk.
 781  *
 782  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 783  * the compliance mode timer is deleted. A port won't enter
 784  * compliance mode if it has previously entered U0.
 785  */
 786 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
 787                                     u16 wIndex)
 788 {
 789         u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1);
 790         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 791
 792         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 793                 return;
 794
 795         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 796                 xhci->port_status_u0 |= 1 << wIndex;
 797                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 798                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 799                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 800                                 "All USB3 ports have entered U0 already!");
 801                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 802                                 "Compliance Mode Recovery Timer Deleted.");
 803                 }
 804         }
 805 }
 806
 807 static int xhci_handle_usb2_port_link_resume(struct xhci_port *port,
 808                                              u32 *status, u32 portsc,
 809                                              unsigned long *flags)
 810 {
 811         struct xhci_bus_state *bus_state;
 812         struct xhci_hcd *xhci;
 813         struct usb_hcd *hcd;
 814         int slot_id;
 815         u32 wIndex;
 816
 817         hcd = port->rhub->hcd;
 818         bus_state = &port->rhub->bus_state;
 819         xhci = hcd_to_xhci(hcd);
 820         wIndex = port->hcd_portnum;
 821
 822         if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) {
 823                 *status = 0xffffffff;
 824                 return -EINVAL;
 825         }
 826         /* did port event handler already start resume timing? */
 827         if (!bus_state->resume_done[wIndex]) {
 828                 /* If not, maybe we are in a host initated resume? */
 829                 if (test_bit(wIndex, &bus_state->resuming_ports)) {
 830                         /* Host initated resume doesn't time the resume
 831                          * signalling using resume_done[].
 832                          * It manually sets RESUME state, sleeps 20ms
 833                          * and sets U0 state. This should probably be
 834                          * changed, but not right now.
 835                          */
 836                 } else {
 837                         /* port resume was discovered now and here,
 838                          * start resume timing
 839                          */
 840                         unsigned long timeout = jiffies +
 841                                 msecs_to_jiffies(USB_RESUME_TIMEOUT);
 842
 843                         set_bit(wIndex, &bus_state->resuming_ports);
 844                         bus_state->resume_done[wIndex] = timeout;
 845                         mod_timer(&hcd->rh_timer, timeout);
 846                         usb_hcd_start_port_resume(&hcd->self, wIndex);
 847                 }
 848         /* Has resume been signalled for USB_RESUME_TIME yet? */
 849         } else if (time_after_eq(jiffies, bus_state->resume_done[wIndex])) {
 850                 int time_left;
 851
 852                 xhci_dbg(xhci, "resume USB2 port %d-%d\n",
 853                          hcd->self.busnum, wIndex + 1);
 854
 855                 bus_state->resume_done[wIndex] = 0;
 856                 clear_bit(wIndex, &bus_state->resuming_ports);
 857
 858                 set_bit(wIndex, &bus_state->rexit_ports);
 859
 860                 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
 861                 xhci_set_link_state(xhci, port, XDEV_U0);
 862
 863                 spin_unlock_irqrestore(&xhci->lock, *flags);
 864                 time_left = wait_for_completion_timeout(
 865                         &bus_state->rexit_done[wIndex],
 866                         msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS));
 867                 spin_lock_irqsave(&xhci->lock, *flags);
 868
 869                 if (time_left) {
 870                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 871                                                             wIndex + 1);
 872                         if (!slot_id) {
 873                                 xhci_dbg(xhci, "slot_id is zero\n");
 874                                 *status = 0xffffffff;
 875                                 return -ENODEV;
 876                         }
 877                         xhci_ring_device(xhci, slot_id);
 878                 } else {
 879                         int port_status = readl(port->addr);
 880
 881                         xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n",
 882                                   hcd->self.busnum, wIndex + 1, port_status);
 883                         *status |= USB_PORT_STAT_SUSPEND;
 884                         clear_bit(wIndex, &bus_state->rexit_ports);
 885                 }
 886
 887                 usb_hcd_end_port_resume(&hcd->self, wIndex);
 888                 bus_state->port_c_suspend |= 1 << wIndex;
 889                 bus_state->suspended_ports &= ~(1 << wIndex);
 890         } else {
 891                 /*
 892                  * The resume has been signaling for less than
 893                  * USB_RESUME_TIME. Report the port status as SUSPEND,
 894                  * let the usbcore check port status again and clear
 895                  * resume signaling later.
 896                  */
 897                 *status |= USB_PORT_STAT_SUSPEND;
 898         }
 899         return 0;
 900 }
 901
 902 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
 903 {
 904         u32 ext_stat = 0;
 905         int speed_id;
 906
 907         /* only support rx and tx lane counts of 1 in usb3.1 spec */
 908         speed_id = DEV_PORT_SPEED(raw_port_status);
 909         ext_stat |= speed_id;           /* bits 3:0, RX speed id */
 910         ext_stat |= speed_id << 4;      /* bits 7:4, TX speed id */
 911
 912         ext_stat |= PORT_RX_LANES(port_li) << 8;  /* bits 11:8 Rx lane count */
 913         ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
 914
 915         return ext_stat;
 916 }
 917
 918 static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status,
 919                                       u32 portsc)
 920 {
 921         struct xhci_bus_state *bus_state;
 922         struct xhci_hcd *xhci;
 923         struct usb_hcd *hcd;
 924         u32 link_state;
 925         u32 portnum;
 926
 927         bus_state = &port->rhub->bus_state;
 928         xhci = hcd_to_xhci(port->rhub->hcd);
 929         hcd = port->rhub->hcd;
 930         link_state = portsc & PORT_PLS_MASK;
 931         portnum = port->hcd_portnum;
 932
 933         /* USB3 specific wPortChange bits
 934          *
 935          * Port link change with port in resume state should not be
 936          * reported to usbcore, as this is an internal state to be
 937          * handled by xhci driver. Reporting PLC to usbcore may
 938          * cause usbcore clearing PLC first and port change event
 939          * irq won't be generated.
 940          */
 941
 942         if (portsc & PORT_PLC && (link_state != XDEV_RESUME))
 943                 *status |= USB_PORT_STAT_C_LINK_STATE << 16;
 944         if (portsc & PORT_WRC)
 945                 *status |= USB_PORT_STAT_C_BH_RESET << 16;
 946         if (portsc & PORT_CEC)
 947                 *status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
 948
 949         /* USB3 specific wPortStatus bits */
 950         if (portsc & PORT_POWER) {
 951                 *status |= USB_SS_PORT_STAT_POWER;
 952                 /* link state handling */
 953                 if (link_state == XDEV_U0)
 954                         bus_state->suspended_ports &= ~(1 << portnum);
 955         }
 956
 957         /* remote wake resume signaling complete */
 958         if (bus_state->port_remote_wakeup & (1 << portnum) &&
 959             link_state != XDEV_RESUME &&
 960             link_state != XDEV_RECOVERY) {
 961                 bus_state->port_remote_wakeup &= ~(1 << portnum);
 962                 usb_hcd_end_port_resume(&hcd->self, portnum);
 963         }
 964
 965         xhci_hub_report_usb3_link_state(xhci, status, portsc);
 966         xhci_del_comp_mod_timer(xhci, portsc, portnum);
 967 }
 968
 969 static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status,
 970                                       u32 portsc, unsigned long *flags)
 971 {
 972         struct xhci_bus_state *bus_state;
 973         u32 link_state;
 974         u32 portnum;
 975         int ret;
 976
 977         bus_state = &port->rhub->bus_state;
 978         link_state = portsc & PORT_PLS_MASK;
 979         portnum = port->hcd_portnum;
 980
 981         /* USB2 wPortStatus bits */
 982         if (portsc & PORT_POWER) {
 983                 *status |= USB_PORT_STAT_POWER;
 984
 985                 /* link state is only valid if port is powered */
 986                 if (link_state == XDEV_U3)
 987                         *status |= USB_PORT_STAT_SUSPEND;
 988                 if (link_state == XDEV_U2)
 989                         *status |= USB_PORT_STAT_L1;
 990                 if (link_state == XDEV_U0) {
 991                         bus_state->resume_done[portnum] = 0;
 992                         clear_bit(portnum, &bus_state->resuming_ports);
 993                         if (bus_state->suspended_ports & (1 << portnum)) {
 994                                 bus_state->suspended_ports &= ~(1 << portnum);
 995                                 bus_state->port_c_suspend |= 1 << portnum;
 996                         }
 997                 }
 998                 if (link_state == XDEV_RESUME) {
 999                         ret = xhci_handle_usb2_port_link_resume(port, status,
1000                                                                 portsc, flags);
1001                         if (ret)
1002                                 return;
1003                 }
1004         }
1005 }
1006
1007 /*
1008  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
1009  * 3.0 hubs use.
1010  *
1011  * Possible side effects:
1012  *  - Mark a port as being done with device resume,
1013  *    and ring the endpoint doorbells.
1014  *  - Stop the Synopsys redriver Compliance Mode polling.
1015  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
1016  */
1017 static u32 xhci_get_port_status(struct usb_hcd *hcd,
1018                 struct xhci_bus_state *bus_state,
1019         u16 wIndex, u32 raw_port_status,
1020                 unsigned long *flags)
1021         __releases(&xhci->lock)
1022         __acquires(&xhci->lock)
1023 {
1024         u32 status = 0;
1025         struct xhci_hub *rhub;
1026         struct xhci_port *port;
1027
1028         rhub = xhci_get_rhub(hcd);
1029         port = rhub->ports[wIndex];
1030
1031         /* common wPortChange bits */
1032         if (raw_port_status & PORT_CSC)
1033                 status |= USB_PORT_STAT_C_CONNECTION << 16;
1034         if (raw_port_status & PORT_PEC)
1035                 status |= USB_PORT_STAT_C_ENABLE << 16;
1036         if ((raw_port_status & PORT_OCC))
1037                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1038         if ((raw_port_status & PORT_RC))
1039                 status |= USB_PORT_STAT_C_RESET << 16;
1040
1041         /* common wPortStatus bits */
1042         if (raw_port_status & PORT_CONNECT) {
1043                 status |= USB_PORT_STAT_CONNECTION;
1044                 status |= xhci_port_speed(raw_port_status);
1045         }
1046         if (raw_port_status & PORT_PE)
1047                 status |= USB_PORT_STAT_ENABLE;
1048         if (raw_port_status & PORT_OC)
1049                 status |= USB_PORT_STAT_OVERCURRENT;
1050         if (raw_port_status & PORT_RESET)
1051                 status |= USB_PORT_STAT_RESET;
1052
1053         /* USB2 and USB3 specific bits, including Port Link State */
1054         if (hcd->speed >= HCD_USB3)
1055                 xhci_get_usb3_port_status(port, &status, raw_port_status);
1056         else
1057                 xhci_get_usb2_port_status(port, &status, raw_port_status,
1058                                           flags);
1059         /*
1060          * Clear stale usb2 resume signalling variables in case port changed
1061          * state during resume signalling. For example on error
1062          */
1063         if ((bus_state->resume_done[wIndex] ||
1064              test_bit(wIndex, &bus_state->resuming_ports)) &&
1065             (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
1066             (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
1067                 bus_state->resume_done[wIndex] = 0;
1068                 clear_bit(wIndex, &bus_state->resuming_ports);
1069                 usb_hcd_end_port_resume(&hcd->self, wIndex);
1070         }
1071
1072         if (bus_state->port_c_suspend & (1 << wIndex))
1073                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1074
1075         return status;
1076 }
1077
1078 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1079                 u16 wIndex, char *buf, u16 wLength)
1080 {
1081         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1082         int max_ports;
1083         unsigned long flags;
1084         u32 temp, status;
1085         int retval = 0;
1086         int slot_id;
1087         struct xhci_bus_state *bus_state;
1088         u16 link_state = 0;
1089         u16 wake_mask = 0;
1090         u16 timeout = 0;
1091         u16 test_mode = 0;
1092         struct xhci_hub *rhub;
1093         struct xhci_port **ports;
1094
1095         rhub = xhci_get_rhub(hcd);
1096         ports = rhub->ports;
1097         max_ports = rhub->num_ports;
1098         bus_state = &rhub->bus_state;
1099
1100         spin_lock_irqsave(&xhci->lock, flags);
1101         switch (typeReq) {
1102         case GetHubStatus:
1103                 /* No power source, over-current reported per port */
1104                 memset(buf, 0, 4);
1105                 break;
1106         case GetHubDescriptor:
1107                 /* Check to make sure userspace is asking for the USB 3.0 hub
1108                  * descriptor for the USB 3.0 roothub.  If not, we stall the
1109                  * endpoint, like external hubs do.
1110                  */
1111                 if (hcd->speed >= HCD_USB3 &&
1112                                 (wLength < USB_DT_SS_HUB_SIZE ||
1113                                  wValue != (USB_DT_SS_HUB << 8))) {
1114                         xhci_dbg(xhci, "Wrong hub descriptor type for "
1115                                         "USB 3.0 roothub.\n");
1116                         goto error;
1117                 }
1118                 xhci_hub_descriptor(hcd, xhci,
1119                                 (struct usb_hub_descriptor *) buf);
1120                 break;
1121         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1122                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1123                         goto error;
1124
1125                 if (hcd->speed < HCD_USB3)
1126                         goto error;
1127
1128                 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
1129                 spin_unlock_irqrestore(&xhci->lock, flags);
1130                 return retval;
1131         case GetPortStatus:
1132                 if (!wIndex || wIndex > max_ports)
1133                         goto error;
1134                 wIndex--;
1135                 temp = readl(ports[wIndex]->addr);
1136                 if (temp == ~(u32)0) {
1137                         xhci_hc_died(xhci);
1138                         retval = -ENODEV;
1139                         break;
1140                 }
1141                 trace_xhci_get_port_status(wIndex, temp);
1142                 status = xhci_get_port_status(hcd, bus_state, wIndex, temp,
1143                                               &flags);
1144                 if (status == 0xffffffff)
1145                         goto error;
1146
1147                 xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x",
1148                          hcd->self.busnum, wIndex + 1, temp, status);
1149
1150                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1151                 /* if USB 3.1 extended port status return additional 4 bytes */
1152                 if (wValue == 0x02) {
1153                         u32 port_li;
1154
1155                         if (hcd->speed < HCD_USB31 || wLength != 8) {
1156                                 xhci_err(xhci, "get ext port status invalid parameter\n");
1157                                 retval = -EINVAL;
1158                                 break;
1159                         }
1160                         port_li = readl(ports[wIndex]->addr + PORTLI);
1161                         status = xhci_get_ext_port_status(temp, port_li);
1162                         put_unaligned_le32(status, &buf[4]);
1163                 }
1164                 break;
1165         case SetPortFeature:
1166                 if (wValue == USB_PORT_FEAT_LINK_STATE)
1167                         link_state = (wIndex & 0xff00) >> 3;
1168                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1169                         wake_mask = wIndex & 0xff00;
1170                 if (wValue == USB_PORT_FEAT_TEST)
1171                         test_mode = (wIndex & 0xff00) >> 8;
1172                 /* The MSB of wIndex is the U1/U2 timeout */
1173                 timeout = (wIndex & 0xff00) >> 8;
1174                 wIndex &= 0xff;
1175                 if (!wIndex || wIndex > max_ports)
1176                         goto error;
1177                 wIndex--;
1178                 temp = readl(ports[wIndex]->addr);
1179                 if (temp == ~(u32)0) {
1180                         xhci_hc_died(xhci);
1181                         retval = -ENODEV;
1182                         break;
1183                 }
1184                 temp = xhci_port_state_to_neutral(temp);
1185                 /* FIXME: What new port features do we need to support? */
1186                 switch (wValue) {
1187                 case USB_PORT_FEAT_SUSPEND:
1188                         temp = readl(ports[wIndex]->addr);
1189                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1190                                 /* Resume the port to U0 first */
1191                                 xhci_set_link_state(xhci, ports[wIndex],
1192                                                         XDEV_U0);
1193                                 spin_unlock_irqrestore(&xhci->lock, flags);
1194                                 msleep(10);
1195                                 spin_lock_irqsave(&xhci->lock, flags);
1196                         }
1197                         /* In spec software should not attempt to suspend
1198                          * a port unless the port reports that it is in the
1199                          * enabled (PED = ‘1’,PLS < ‘3’) state.
1200                          */
1201                         temp = readl(ports[wIndex]->addr);
1202                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1203                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1204                                 xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n",
1205                                           hcd->self.busnum, wIndex + 1);
1206                                 goto error;
1207                         }
1208
1209                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1210                                         wIndex + 1);
1211                         if (!slot_id) {
1212                                 xhci_warn(xhci, "slot_id is zero\n");
1213                                 goto error;
1214                         }
1215                         /* unlock to execute stop endpoint commands */
1216                         spin_unlock_irqrestore(&xhci->lock, flags);
1217                         xhci_stop_device(xhci, slot_id, 1);
1218                         spin_lock_irqsave(&xhci->lock, flags);
1219
1220                         xhci_set_link_state(xhci, ports[wIndex], XDEV_U3);
1221
1222                         spin_unlock_irqrestore(&xhci->lock, flags);
1223                         msleep(10); /* wait device to enter */
1224                         spin_lock_irqsave(&xhci->lock, flags);
1225
1226                         temp = readl(ports[wIndex]->addr);
1227                         bus_state->suspended_ports |= 1 << wIndex;
1228                         break;
1229                 case USB_PORT_FEAT_LINK_STATE:
1230                         temp = readl(ports[wIndex]->addr);
1231                         /* Disable port */
1232                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1233                                 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1234                                 temp = xhci_port_state_to_neutral(temp);
1235                                 /*
1236                                  * Clear all change bits, so that we get a new
1237                                  * connection event.
1238                                  */
1239                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1240                                         PORT_OCC | PORT_RC | PORT_PLC |
1241                                         PORT_CEC;
1242                                 writel(temp | PORT_PE, ports[wIndex]->addr);
1243                                 temp = readl(ports[wIndex]->addr);
1244                                 break;
1245                         }
1246
1247                         /* Put link in RxDetect (enable port) */
1248                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1249                                 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1250                                 xhci_set_link_state(xhci, ports[wIndex],
1251                                                         link_state);
1252                                 temp = readl(ports[wIndex]->addr);
1253                                 break;
1254                         }
1255
1256                         /*
1257                          * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1258                          * root hub port's transition to compliance mode upon
1259                          * detecting LFPS timeout may be controlled by an
1260                          * Compliance Transition Enabled (CTE) flag (not
1261                          * software visible). This flag is set by writing 0xA
1262                          * to PORTSC PLS field which will allow transition to
1263                          * compliance mode the next time LFPS timeout is
1264                          * encountered. A warm reset will clear it.
1265                          *
1266                          * The CTE flag is only supported if the HCCPARAMS2 CTC
1267                          * flag is set, otherwise, the compliance substate is
1268                          * automatically entered as on 1.0 and prior.
1269                          */
1270                         if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1271                                 if (!HCC2_CTC(xhci->hcc_params2)) {
1272                                         xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1273                                         break;
1274                                 }
1275
1276                                 if ((temp & PORT_CONNECT)) {
1277                                         xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1278                                         goto error;
1279                                 }
1280
1281                                 xhci_dbg(xhci, "Enable compliance mode transition for port %d\n",
1282                                                 wIndex);
1283                                 xhci_set_link_state(xhci, ports[wIndex],
1284                                                 link_state);
1285
1286                                 temp = readl(ports[wIndex]->addr);
1287                                 break;
1288                         }
1289                         /* Port must be enabled */
1290                         if (!(temp & PORT_PE)) {
1291                                 retval = -ENODEV;
1292                                 break;
1293                         }
1294                         /* Can't set port link state above '3' (U3) */
1295                         if (link_state > USB_SS_PORT_LS_U3) {
1296                                 xhci_warn(xhci, "Cannot set port %d link state %d\n",
1297                                          wIndex, link_state);
1298                                 goto error;
1299                         }
1300                         if (link_state == USB_SS_PORT_LS_U3) {
1301                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1302                                                 wIndex + 1);
1303                                 if (slot_id) {
1304                                         /* unlock to execute stop endpoint
1305                                          * commands */
1306                                         spin_unlock_irqrestore(&xhci->lock,
1307                                                                 flags);
1308                                         xhci_stop_device(xhci, slot_id, 1);
1309                                         spin_lock_irqsave(&xhci->lock, flags);
1310                                 }
1311                         }
1312
1313                         xhci_set_link_state(xhci, ports[wIndex], link_state);
1314
1315                         spin_unlock_irqrestore(&xhci->lock, flags);
1316                         msleep(20); /* wait device to enter */
1317                         spin_lock_irqsave(&xhci->lock, flags);
1318
1319                         temp = readl(ports[wIndex]->addr);
1320                         if (link_state == USB_SS_PORT_LS_U3)
1321                                 bus_state->suspended_ports |= 1 << wIndex;
1322                         break;
1323                 case USB_PORT_FEAT_POWER:
1324                         /*
1325                          * Turn on ports, even if there isn't per-port switching.
1326                          * HC will report connect events even before this is set.
1327                          * However, hub_wq will ignore the roothub events until
1328                          * the roothub is registered.
1329                          */
1330                         xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1331                         break;
1332                 case USB_PORT_FEAT_RESET:
1333                         temp = (temp | PORT_RESET);
1334                         writel(temp, ports[wIndex]->addr);
1335
1336                         temp = readl(ports[wIndex]->addr);
1337                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
1338                         break;
1339                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1340                         xhci_set_remote_wake_mask(xhci, ports[wIndex],
1341                                                   wake_mask);
1342                         temp = readl(ports[wIndex]->addr);
1343                         xhci_dbg(xhci, "set port remote wake mask, "
1344                                         "actual port %d status  = 0x%x\n",
1345                                         wIndex, temp);
1346                         break;
1347                 case USB_PORT_FEAT_BH_PORT_RESET:
1348                         temp |= PORT_WR;
1349                         writel(temp, ports[wIndex]->addr);
1350                         temp = readl(ports[wIndex]->addr);
1351                         break;
1352                 case USB_PORT_FEAT_U1_TIMEOUT:
1353                         if (hcd->speed < HCD_USB3)
1354                                 goto error;
1355                         temp = readl(ports[wIndex]->addr + PORTPMSC);
1356                         temp &= ~PORT_U1_TIMEOUT_MASK;
1357                         temp |= PORT_U1_TIMEOUT(timeout);
1358                         writel(temp, ports[wIndex]->addr + PORTPMSC);
1359                         break;
1360                 case USB_PORT_FEAT_U2_TIMEOUT:
1361                         if (hcd->speed < HCD_USB3)
1362                                 goto error;
1363                         temp = readl(ports[wIndex]->addr + PORTPMSC);
1364                         temp &= ~PORT_U2_TIMEOUT_MASK;
1365                         temp |= PORT_U2_TIMEOUT(timeout);
1366                         writel(temp, ports[wIndex]->addr + PORTPMSC);
1367                         break;
1368                 case USB_PORT_FEAT_TEST:
1369                         /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1370                         if (hcd->speed != HCD_USB2)
1371                                 goto error;
1372                         if (test_mode > TEST_FORCE_EN || test_mode < TEST_J)
1373                                 goto error;
1374                         retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1375                                                       &flags);
1376                         break;
1377                 default:
1378                         goto error;
1379                 }
1380                 /* unblock any posted writes */
1381                 temp = readl(ports[wIndex]->addr);
1382                 break;
1383         case ClearPortFeature:
1384                 if (!wIndex || wIndex > max_ports)
1385                         goto error;
1386                 wIndex--;
1387                 temp = readl(ports[wIndex]->addr);
1388                 if (temp == ~(u32)0) {
1389                         xhci_hc_died(xhci);
1390                         retval = -ENODEV;
1391                         break;
1392                 }
1393                 /* FIXME: What new port features do we need to support? */
1394                 temp = xhci_port_state_to_neutral(temp);
1395                 switch (wValue) {
1396                 case USB_PORT_FEAT_SUSPEND:
1397                         temp = readl(ports[wIndex]->addr);
1398                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1399                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
1400                         if (temp & PORT_RESET)
1401                                 goto error;
1402                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1403                                 if ((temp & PORT_PE) == 0)
1404                                         goto error;
1405
1406                                 set_bit(wIndex, &bus_state->resuming_ports);
1407                                 usb_hcd_start_port_resume(&hcd->self, wIndex);
1408                                 xhci_set_link_state(xhci, ports[wIndex],
1409                                                     XDEV_RESUME);
1410                                 spin_unlock_irqrestore(&xhci->lock, flags);
1411                                 msleep(USB_RESUME_TIMEOUT);
1412                                 spin_lock_irqsave(&xhci->lock, flags);
1413                                 xhci_set_link_state(xhci, ports[wIndex],
1414                                                         XDEV_U0);
1415                                 clear_bit(wIndex, &bus_state->resuming_ports);
1416                                 usb_hcd_end_port_resume(&hcd->self, wIndex);
1417                         }
1418                         bus_state->port_c_suspend |= 1 << wIndex;
1419
1420                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1421                                         wIndex + 1);
1422                         if (!slot_id) {
1423                                 xhci_dbg(xhci, "slot_id is zero\n");
1424                                 goto error;
1425                         }
1426                         xhci_ring_device(xhci, slot_id);
1427                         break;
1428                 case USB_PORT_FEAT_C_SUSPEND:
1429                         bus_state->port_c_suspend &= ~(1 << wIndex);
1430                         /* fall through */
1431                 case USB_PORT_FEAT_C_RESET:
1432                 case USB_PORT_FEAT_C_BH_PORT_RESET:
1433                 case USB_PORT_FEAT_C_CONNECTION:
1434                 case USB_PORT_FEAT_C_OVER_CURRENT:
1435                 case USB_PORT_FEAT_C_ENABLE:
1436                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1437                 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1438                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1439                                         ports[wIndex]->addr, temp);
1440                         break;
1441                 case USB_PORT_FEAT_ENABLE:
1442                         xhci_disable_port(hcd, xhci, wIndex,
1443                                         ports[wIndex]->addr, temp);
1444                         break;
1445                 case USB_PORT_FEAT_POWER:
1446                         xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1447                         break;
1448                 case USB_PORT_FEAT_TEST:
1449                         retval = xhci_exit_test_mode(xhci);
1450                         break;
1451                 default:
1452                         goto error;
1453                 }
1454                 break;
1455         default:
1456 error:
1457                 /* "stall" on error */
1458                 retval = -EPIPE;
1459         }
1460         spin_unlock_irqrestore(&xhci->lock, flags);
1461         return retval;
1462 }
1463
1464 /*
1465  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1466  * Ports are 0-indexed from the HCD point of view,
1467  * and 1-indexed from the USB core pointer of view.
1468  *
1469  * Note that the status change bits will be cleared as soon as a port status
1470  * change event is generated, so we use the saved status from that event.
1471  */
1472 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1473 {
1474         unsigned long flags;
1475         u32 temp, status;
1476         u32 mask;
1477         int i, retval;
1478         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1479         int max_ports;
1480         struct xhci_bus_state *bus_state;
1481         bool reset_change = false;
1482         struct xhci_hub *rhub;
1483         struct xhci_port **ports;
1484
1485         rhub = xhci_get_rhub(hcd);
1486         ports = rhub->ports;
1487         max_ports = rhub->num_ports;
1488         bus_state = &rhub->bus_state;
1489
1490         /* Initial status is no changes */
1491         retval = (max_ports + 8) / 8;
1492         memset(buf, 0, retval);
1493
1494         /*
1495          * Inform the usbcore about resume-in-progress by returning
1496          * a non-zero value even if there are no status changes.
1497          */
1498         status = bus_state->resuming_ports;
1499
1500         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1501
1502         spin_lock_irqsave(&xhci->lock, flags);
1503         /* For each port, did anything change?  If so, set that bit in buf. */
1504         for (i = 0; i < max_ports; i++) {
1505                 temp = readl(ports[i]->addr);
1506                 if (temp == ~(u32)0) {
1507                         xhci_hc_died(xhci);
1508                         retval = -ENODEV;
1509                         break;
1510                 }
1511                 trace_xhci_hub_status_data(i, temp);
1512
1513                 if ((temp & mask) != 0 ||
1514                         (bus_state->port_c_suspend & 1 << i) ||
1515                         (bus_state->resume_done[i] && time_after_eq(
1516                             jiffies, bus_state->resume_done[i]))) {
1517                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1518                         status = 1;
1519                 }
1520                 if ((temp & PORT_RC))
1521                         reset_change = true;
1522         }
1523         if (!status && !reset_change) {
1524                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1525                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1526         }
1527         spin_unlock_irqrestore(&xhci->lock, flags);
1528         return status ? retval : 0;
1529 }
1530
1531 #ifdef CONFIG_PM
1532
1533 int xhci_bus_suspend(struct usb_hcd *hcd)
1534 {
1535         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1536         int max_ports, port_index;
1537         struct xhci_bus_state *bus_state;
1538         unsigned long flags;
1539         struct xhci_hub *rhub;
1540         struct xhci_port **ports;
1541         u32 portsc_buf[USB_MAXCHILDREN];
1542         bool wake_enabled;
1543
1544         rhub = xhci_get_rhub(hcd);
1545         ports = rhub->ports;
1546         max_ports = rhub->num_ports;
1547         bus_state = &rhub->bus_state;
1548         wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1549
1550         spin_lock_irqsave(&xhci->lock, flags);
1551
1552         if (wake_enabled) {
1553                 if (bus_state->resuming_ports ||        /* USB2 */
1554                     bus_state->port_remote_wakeup) {    /* USB3 */
1555                         spin_unlock_irqrestore(&xhci->lock, flags);
1556                         xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1557                         return -EBUSY;
1558                 }
1559         }
1560         /*
1561          * Prepare ports for suspend, but don't write anything before all ports
1562          * are checked and we know bus suspend can proceed
1563          */
1564         bus_state->bus_suspended = 0;
1565         port_index = max_ports;
1566         while (port_index--) {
1567                 u32 t1, t2;
1568                 int retries = 10;
1569 retry:
1570                 t1 = readl(ports[port_index]->addr);
1571                 t2 = xhci_port_state_to_neutral(t1);
1572                 portsc_buf[port_index] = 0;
1573
1574                 /*
1575                  * Give a USB3 port in link training time to finish, but don't
1576                  * prevent suspend as port might be stuck
1577                  */
1578                 if ((hcd->speed >= HCD_USB3) && retries-- &&
1579                     (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1580                         spin_unlock_irqrestore(&xhci->lock, flags);
1581                         msleep(XHCI_PORT_POLLING_LFPS_TIME);
1582                         spin_lock_irqsave(&xhci->lock, flags);
1583                         xhci_dbg(xhci, "port %d polling in bus suspend, waiting\n",
1584                                  port_index);
1585                         goto retry;
1586                 }
1587                 /* suspend ports in U0, or bail out for new connect changes */
1588                 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1589                         if ((t1 & PORT_CSC) && wake_enabled) {
1590                                 bus_state->bus_suspended = 0;
1591                                 spin_unlock_irqrestore(&xhci->lock, flags);
1592                                 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1593                                 return -EBUSY;
1594                         }
1595                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1596                         t2 &= ~PORT_PLS_MASK;
1597                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1598                         set_bit(port_index, &bus_state->bus_suspended);
1599                 }
1600                 /* USB core sets remote wake mask for USB 3.0 hubs,
1601                  * including the USB 3.0 roothub, but only if CONFIG_PM
1602                  * is enabled, so also enable remote wake here.
1603                  */
1604                 if (wake_enabled) {
1605                         if (t1 & PORT_CONNECT) {
1606                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1607                                 t2 &= ~PORT_WKCONN_E;
1608                         } else {
1609                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1610                                 t2 &= ~PORT_WKDISC_E;
1611                         }
1612
1613                         if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1614                             (hcd->speed < HCD_USB3)) {
1615                                 if (usb_amd_pt_check_port(hcd->self.controller,
1616                                                           port_index))
1617                                         t2 &= ~PORT_WAKE_BITS;
1618                         }
1619                 } else
1620                         t2 &= ~PORT_WAKE_BITS;
1621
1622                 t1 = xhci_port_state_to_neutral(t1);
1623                 if (t1 != t2)
1624                         portsc_buf[port_index] = t2;
1625         }
1626
1627         /* write port settings, stopping and suspending ports if needed */
1628         port_index = max_ports;
1629         while (port_index--) {
1630                 if (!portsc_buf[port_index])
1631                         continue;
1632                 if (test_bit(port_index, &bus_state->bus_suspended)) {
1633                         int slot_id;
1634
1635                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1636                                                             port_index + 1);
1637                         if (slot_id) {
1638                                 spin_unlock_irqrestore(&xhci->lock, flags);
1639                                 xhci_stop_device(xhci, slot_id, 1);
1640                                 spin_lock_irqsave(&xhci->lock, flags);
1641                         }
1642                 }
1643                 writel(portsc_buf[port_index], ports[port_index]->addr);
1644         }
1645         hcd->state = HC_STATE_SUSPENDED;
1646         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1647         spin_unlock_irqrestore(&xhci->lock, flags);
1648         return 0;
1649 }
1650
1651 /*
1652  * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1653  * warm reset a USB3 device stuck in polling or compliance mode after resume.
1654  * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1655  */
1656 static bool xhci_port_missing_cas_quirk(struct xhci_port *port)
1657 {
1658         u32 portsc;
1659
1660         portsc = readl(port->addr);
1661
1662         /* if any of these are set we are not stuck */
1663         if (portsc & (PORT_CONNECT | PORT_CAS))
1664                 return false;
1665
1666         if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1667             ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1668                 return false;
1669
1670         /* clear wakeup/change bits, and do a warm port reset */
1671         portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1672         portsc |= PORT_WR;
1673         writel(portsc, port->addr);
1674         /* flush write */
1675         readl(port->addr);
1676         return true;
1677 }
1678
1679 int xhci_bus_resume(struct usb_hcd *hcd)
1680 {
1681         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1682         struct xhci_bus_state *bus_state;
1683         unsigned long flags;
1684         int max_ports, port_index;
1685         int slot_id;
1686         int sret;
1687         u32 next_state;
1688         u32 temp, portsc;
1689         struct xhci_hub *rhub;
1690         struct xhci_port **ports;
1691
1692         rhub = xhci_get_rhub(hcd);
1693         ports = rhub->ports;
1694         max_ports = rhub->num_ports;
1695         bus_state = &rhub->bus_state;
1696
1697         if (time_before(jiffies, bus_state->next_statechange))
1698                 msleep(5);
1699
1700         spin_lock_irqsave(&xhci->lock, flags);
1701         if (!HCD_HW_ACCESSIBLE(hcd)) {
1702                 spin_unlock_irqrestore(&xhci->lock, flags);
1703                 return -ESHUTDOWN;
1704         }
1705
1706         /* delay the irqs */
1707         temp = readl(&xhci->op_regs->command);
1708         temp &= ~CMD_EIE;
1709         writel(temp, &xhci->op_regs->command);
1710
1711         /* bus specific resume for ports we suspended at bus_suspend */
1712         if (hcd->speed >= HCD_USB3)
1713                 next_state = XDEV_U0;
1714         else
1715                 next_state = XDEV_RESUME;
1716
1717         port_index = max_ports;
1718         while (port_index--) {
1719                 portsc = readl(ports[port_index]->addr);
1720
1721                 /* warm reset CAS limited ports stuck in polling/compliance */
1722                 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1723                     (hcd->speed >= HCD_USB3) &&
1724                     xhci_port_missing_cas_quirk(ports[port_index])) {
1725                         xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1726                         clear_bit(port_index, &bus_state->bus_suspended);
1727                         continue;
1728                 }
1729                 /* resume if we suspended the link, and it is still suspended */
1730                 if (test_bit(port_index, &bus_state->bus_suspended))
1731                         switch (portsc & PORT_PLS_MASK) {
1732                         case XDEV_U3:
1733                                 portsc = xhci_port_state_to_neutral(portsc);
1734                                 portsc &= ~PORT_PLS_MASK;
1735                                 portsc |= PORT_LINK_STROBE | next_state;
1736                                 break;
1737                         case XDEV_RESUME:
1738                                 /* resume already initiated */
1739                                 break;
1740                         default:
1741                                 /* not in a resumeable state, ignore it */
1742                                 clear_bit(port_index,
1743                                           &bus_state->bus_suspended);
1744                                 break;
1745                         }
1746                 /* disable wake for all ports, write new link state if needed */
1747                 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1748                 writel(portsc, ports[port_index]->addr);
1749         }
1750
1751         /* USB2 specific resume signaling delay and U0 link state transition */
1752         if (hcd->speed < HCD_USB3) {
1753                 if (bus_state->bus_suspended) {
1754                         spin_unlock_irqrestore(&xhci->lock, flags);
1755                         msleep(USB_RESUME_TIMEOUT);
1756                         spin_lock_irqsave(&xhci->lock, flags);
1757                 }
1758                 for_each_set_bit(port_index, &bus_state->bus_suspended,
1759                                  BITS_PER_LONG) {
1760                         /* Clear PLC to poll it later for U0 transition */
1761                         xhci_test_and_clear_bit(xhci, ports[port_index],
1762                                                 PORT_PLC);
1763                         xhci_set_link_state(xhci, ports[port_index], XDEV_U0);
1764                 }
1765         }
1766
1767         /* poll for U0 link state complete, both USB2 and USB3 */
1768         for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1769                 sret = xhci_handshake(ports[port_index]->addr, PORT_PLC,
1770                                       PORT_PLC, 10 * 1000);
1771                 if (sret) {
1772                         xhci_warn(xhci, "port %d resume PLC timeout\n",
1773                                   port_index);
1774                         continue;
1775                 }
1776                 xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC);
1777                 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1778                 if (slot_id)
1779                         xhci_ring_device(xhci, slot_id);
1780         }
1781         (void) readl(&xhci->op_regs->command);
1782
1783         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1784         /* re-enable irqs */
1785         temp = readl(&xhci->op_regs->command);
1786         temp |= CMD_EIE;
1787         writel(temp, &xhci->op_regs->command);
1788         temp = readl(&xhci->op_regs->command);
1789
1790         spin_unlock_irqrestore(&xhci->lock, flags);
1791         return 0;
1792 }
1793
1794 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd)
1795 {
1796         struct xhci_hub *rhub = xhci_get_rhub(hcd);
1797
1798         /* USB3 port wakeups are reported via usb_wakeup_notification() */
1799         return rhub->bus_state.resuming_ports;  /* USB2 ports only */
1800 }
1801
1802 #endif  /* CONFIG_PM */