drivers/usb/host/xhci-hub.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11
  12 #include <linux/slab.h>
  13 #include <asm/unaligned.h>
  14
  15 #include "xhci.h"
  16 #include "xhci-trace.h"
  17
  18 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  19 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  20                          PORT_RC | PORT_PLC | PORT_PE)
  21
  22 /* USB 3 BOS descriptor and a capability descriptors, combined.
  23  * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
  24  */
  25 static u8 usb_bos_descriptor [] = {
  26         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  27         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  28         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  29         0x1,                            /*  __u8 bNumDeviceCaps */
  30         /* First device capability, SuperSpeed */
  31         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  32         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  33         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  34         0x00,                           /* bmAttributes, LTM off by default */
  35         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  36         0x03,                           /* bFunctionalitySupport,
  37                                            USB 3.0 speed only */
  38         0x00,                           /* bU1DevExitLat, set later. */
  39         0x00, 0x00,                     /* __le16 bU2DevExitLat, set later. */
  40         /* Second device capability, SuperSpeedPlus */
  41         0x1c,                           /* bLength 28, will be adjusted later */
  42         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  43         USB_SSP_CAP_TYPE,               /* bDevCapabilityType SUPERSPEED_PLUS */
  44         0x00,                           /* bReserved 0 */
  45         0x23, 0x00, 0x00, 0x00,         /* bmAttributes, SSAC=3 SSIC=1 */
  46         0x01, 0x00,                     /* wFunctionalitySupport */
  47         0x00, 0x00,                     /* wReserved 0 */
  48         /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
  49         0x34, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, rx, ID = 4 */
  50         0xb4, 0x00, 0x05, 0x00,         /* 5Gbps, symmetric, tx, ID = 4 */
  51         0x35, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, rx, ID = 5 */
  52         0xb5, 0x40, 0x0a, 0x00,         /* 10Gbps, SSP, symmetric, tx, ID = 5 */
  53 };
  54
  55 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
  56                                      u16 wLength)
  57 {
  58         int i, ssa_count;
  59         u32 temp;
  60         u16 desc_size, ssp_cap_size, ssa_size = 0;
  61         bool usb3_1 = false;
  62
  63         desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
  64         ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
  65
  66         /* does xhci support USB 3.1 Enhanced SuperSpeed */
  67         if (xhci->usb3_rhub.min_rev >= 0x01) {
  68                 /* does xhci provide a PSI table for SSA speed attributes? */
  69                 if (xhci->usb3_rhub.psi_count) {
  70                         /* two SSA entries for each unique PSI ID, RX and TX */
  71                         ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
  72                         ssa_size = ssa_count * sizeof(u32);
  73                         ssp_cap_size -= 16; /* skip copying the default SSA */
  74                 }
  75                 desc_size += ssp_cap_size;
  76                 usb3_1 = true;
  77         }
  78         memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
  79
  80         if (usb3_1) {
  81                 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
  82                 buf[4] += 1;
  83                 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
  84         }
  85
  86         if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
  87                 return wLength;
  88
  89         /* Indicate whether the host has LTM support. */
  90         temp = readl(&xhci->cap_regs->hcc_params);
  91         if (HCC_LTC(temp))
  92                 buf[8] |= USB_LTM_SUPPORT;
  93
  94         /* Set the U1 and U2 exit latencies. */
  95         if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
  96                 temp = readl(&xhci->cap_regs->hcs_params3);
  97                 buf[12] = HCS_U1_LATENCY(temp);
  98                 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
  99         }
 100
 101         /* If PSI table exists, add the custom speed attributes from it */
 102         if (usb3_1 && xhci->usb3_rhub.psi_count) {
 103                 u32 ssp_cap_base, bm_attrib, psi, psi_mant, psi_exp;
 104                 int offset;
 105
 106                 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 107
 108                 if (wLength < desc_size)
 109                         return wLength;
 110                 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
 111
 112                 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
 113                 bm_attrib = (ssa_count - 1) & 0x1f;
 114                 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
 115                 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
 116
 117                 if (wLength < desc_size + ssa_size)
 118                         return wLength;
 119                 /*
 120                  * Create the Sublink Speed Attributes (SSA) array.
 121                  * The xhci PSI field and USB 3.1 SSA fields are very similar,
 122                  * but link type bits 7:6 differ for values 01b and 10b.
 123                  * xhci has also only one PSI entry for a symmetric link when
 124                  * USB 3.1 requires two SSA entries (RX and TX) for every link
 125                  */
 126                 offset = desc_size;
 127                 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
 128                         psi = xhci->usb3_rhub.psi[i];
 129                         psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
 130                         psi_exp = XHCI_EXT_PORT_PSIE(psi);
 131                         psi_mant = XHCI_EXT_PORT_PSIM(psi);
 132
 133                         /* Shift to Gbps and set SSP Link BIT(14) if 10Gpbs */
 134                         for (; psi_exp < 3; psi_exp++)
 135                                 psi_mant /= 1000;
 136                         if (psi_mant >= 10)
 137                                 psi |= BIT(14);
 138
 139                         if ((psi & PLT_MASK) == PLT_SYM) {
 140                         /* Symmetric, create SSA RX and TX from one PSI entry */
 141                                 put_unaligned_le32(psi, &buf[offset]);
 142                                 psi |= 1 << 7;  /* turn entry to TX */
 143                                 offset += 4;
 144                                 if (offset >= desc_size + ssa_size)
 145                                         return desc_size + ssa_size;
 146                         } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
 147                                 /* Asymetric RX, flip bits 7:6 for SSA */
 148                                 psi ^= PLT_MASK;
 149                         }
 150                         put_unaligned_le32(psi, &buf[offset]);
 151                         offset += 4;
 152                         if (offset >= desc_size + ssa_size)
 153                                 return desc_size + ssa_size;
 154                 }
 155         }
 156         /* ssa_size is 0 for other than usb 3.1 hosts */
 157         return desc_size + ssa_size;
 158 }
 159
 160 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
 161                 struct usb_hub_descriptor *desc, int ports)
 162 {
 163         u16 temp;
 164
 165         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.9 says 20ms max */
 166         desc->bHubContrCurrent = 0;
 167
 168         desc->bNbrPorts = ports;
 169         temp = 0;
 170         /* Bits 1:0 - support per-port power switching, or power always on */
 171         if (HCC_PPC(xhci->hcc_params))
 172                 temp |= HUB_CHAR_INDV_PORT_LPSM;
 173         else
 174                 temp |= HUB_CHAR_NO_LPSM;
 175         /* Bit  2 - root hubs are not part of a compound device */
 176         /* Bits 4:3 - individual port over current protection */
 177         temp |= HUB_CHAR_INDV_PORT_OCPM;
 178         /* Bits 6:5 - no TTs in root ports */
 179         /* Bit  7 - no port indicators */
 180         desc->wHubCharacteristics = cpu_to_le16(temp);
 181 }
 182
 183 /* Fill in the USB 2.0 roothub descriptor */
 184 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 185                 struct usb_hub_descriptor *desc)
 186 {
 187         int ports;
 188         u16 temp;
 189         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
 190         u32 portsc;
 191         unsigned int i;
 192
 193         ports = xhci->num_usb2_ports;
 194
 195         xhci_common_hub_descriptor(xhci, desc, ports);
 196         desc->bDescriptorType = USB_DT_HUB;
 197         temp = 1 + (ports / 8);
 198         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
 199
 200         /* The Device Removable bits are reported on a byte granularity.
 201          * If the port doesn't exist within that byte, the bit is set to 0.
 202          */
 203         memset(port_removable, 0, sizeof(port_removable));
 204         for (i = 0; i < ports; i++) {
 205                 portsc = readl(xhci->usb2_ports[i]);
 206                 /* If a device is removable, PORTSC reports a 0, same as in the
 207                  * hub descriptor DeviceRemovable bits.
 208                  */
 209                 if (portsc & PORT_DEV_REMOVE)
 210                         /* This math is hairy because bit 0 of DeviceRemovable
 211                          * is reserved, and bit 1 is for port 1, etc.
 212                          */
 213                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 214         }
 215
 216         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 217          * ports on it.  The USB 2.0 specification says that there are two
 218          * variable length fields at the end of the hub descriptor:
 219          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 220          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 221          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 222          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 223          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 224          * set of ports that actually exist.
 225          */
 226         memset(desc->u.hs.DeviceRemovable, 0xff,
 227                         sizeof(desc->u.hs.DeviceRemovable));
 228         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 229                         sizeof(desc->u.hs.PortPwrCtrlMask));
 230
 231         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 232                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 233                                 sizeof(__u8));
 234 }
 235
 236 /* Fill in the USB 3.0 roothub descriptor */
 237 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 238                 struct usb_hub_descriptor *desc)
 239 {
 240         int ports;
 241         u16 port_removable;
 242         u32 portsc;
 243         unsigned int i;
 244
 245         ports = xhci->num_usb3_ports;
 246         xhci_common_hub_descriptor(xhci, desc, ports);
 247         desc->bDescriptorType = USB_DT_SS_HUB;
 248         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 249
 250         /* header decode latency should be zero for roothubs,
 251          * see section 4.23.5.2.
 252          */
 253         desc->u.ss.bHubHdrDecLat = 0;
 254         desc->u.ss.wHubDelay = 0;
 255
 256         port_removable = 0;
 257         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 258         for (i = 0; i < ports; i++) {
 259                 portsc = readl(xhci->usb3_ports[i]);
 260                 if (portsc & PORT_DEV_REMOVE)
 261                         port_removable |= 1 << (i + 1);
 262         }
 263
 264         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 265 }
 266
 267 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 268                 struct usb_hub_descriptor *desc)
 269 {
 270
 271         if (hcd->speed >= HCD_USB3)
 272                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 273         else
 274                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 275
 276 }
 277
 278 static unsigned int xhci_port_speed(unsigned int port_status)
 279 {
 280         if (DEV_LOWSPEED(port_status))
 281                 return USB_PORT_STAT_LOW_SPEED;
 282         if (DEV_HIGHSPEED(port_status))
 283                 return USB_PORT_STAT_HIGH_SPEED;
 284         /*
 285          * FIXME: Yes, we should check for full speed, but the core uses that as
 286          * a default in portspeed() in usb/core/hub.c (which is the only place
 287          * USB_PORT_STAT_*_SPEED is used).
 288          */
 289         return 0;
 290 }
 291
 292 /*
 293  * These bits are Read Only (RO) and should be saved and written to the
 294  * registers: 0, 3, 10:13, 30
 295  * connect status, over-current status, port speed, and device removable.
 296  * connect status and port speed are also sticky - meaning they're in
 297  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 298  */
 299 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 300 /*
 301  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 302  * bits 5:8, 9, 14:15, 25:27
 303  * link state, port power, port indicator state, "wake on" enable state
 304  */
 305 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 306 /*
 307  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 308  * bit 4 (port reset)
 309  */
 310 #define XHCI_PORT_RW1S  ((1<<4))
 311 /*
 312  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 313  * bits 1, 17, 18, 19, 20, 21, 22, 23
 314  * port enable/disable, and
 315  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 316  * over-current, reset, link state, and L1 change
 317  */
 318 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 319 /*
 320  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 321  * latched in
 322  */
 323 #define XHCI_PORT_RW    ((1<<16))
 324 /*
 325  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 326  * bits 2, 24, 28:31
 327  */
 328 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 329
 330 /*
 331  * Given a port state, this function returns a value that would result in the
 332  * port being in the same state, if the value was written to the port status
 333  * control register.
 334  * Save Read Only (RO) bits and save read/write bits where
 335  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 336  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 337  */
 338 u32 xhci_port_state_to_neutral(u32 state)
 339 {
 340         /* Save read-only status and port state */
 341         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 342 }
 343
 344 /*
 345  * find slot id based on port number.
 346  * @port: The one-based port number from one of the two split roothubs.
 347  */
 348 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 349                 u16 port)
 350 {
 351         int slot_id;
 352         int i;
 353         enum usb_device_speed speed;
 354
 355         slot_id = 0;
 356         for (i = 0; i < MAX_HC_SLOTS; i++) {
 357                 if (!xhci->devs[i])
 358                         continue;
 359                 speed = xhci->devs[i]->udev->speed;
 360                 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
 361                                 && xhci->devs[i]->fake_port == port) {
 362                         slot_id = i;
 363                         break;
 364                 }
 365         }
 366
 367         return slot_id;
 368 }
 369
 370 /*
 371  * Stop device
 372  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 373  * to complete.
 374  * suspend will set to 1, if suspend bit need to set in command.
 375  */
 376 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 377 {
 378         struct xhci_virt_device *virt_dev;
 379         struct xhci_command *cmd;
 380         unsigned long flags;
 381         int ret;
 382         int i;
 383
 384         ret = 0;
 385         virt_dev = xhci->devs[slot_id];
 386         if (!virt_dev)
 387                 return -ENODEV;
 388
 389         trace_xhci_stop_device(virt_dev);
 390
 391         cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
 392         if (!cmd)
 393                 return -ENOMEM;
 394
 395         spin_lock_irqsave(&xhci->lock, flags);
 396         for (i = LAST_EP_INDEX; i > 0; i--) {
 397                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
 398                         struct xhci_ep_ctx *ep_ctx;
 399                         struct xhci_command *command;
 400
 401                         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
 402
 403                         /* Check ep is running, required by AMD SNPS 3.1 xHC */
 404                         if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
 405                                 continue;
 406
 407                         command = xhci_alloc_command(xhci, false, false,
 408                                                      GFP_NOWAIT);
 409                         if (!command) {
 410                                 spin_unlock_irqrestore(&xhci->lock, flags);
 411                                 ret = -ENOMEM;
 412                                 goto cmd_cleanup;
 413                         }
 414
 415                         ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
 416                                                        i, suspend);
 417                         if (ret) {
 418                                 spin_unlock_irqrestore(&xhci->lock, flags);
 419                                 xhci_free_command(xhci, command);
 420                                 goto cmd_cleanup;
 421                         }
 422                 }
 423         }
 424         ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
 425         if (ret) {
 426                 spin_unlock_irqrestore(&xhci->lock, flags);
 427                 goto cmd_cleanup;
 428         }
 429
 430         xhci_ring_cmd_db(xhci);
 431         spin_unlock_irqrestore(&xhci->lock, flags);
 432
 433         /* Wait for last stop endpoint command to finish */
 434         wait_for_completion(cmd->completion);
 435
 436         if (cmd->status == COMP_COMMAND_ABORTED ||
 437             cmd->status == COMP_COMMAND_RING_STOPPED) {
 438                 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
 439                 ret = -ETIME;
 440         }
 441
 442 cmd_cleanup:
 443         xhci_free_command(xhci, cmd);
 444         return ret;
 445 }
 446
 447 /*
 448  * Ring device, it rings the all doorbells unconditionally.
 449  */
 450 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 451 {
 452         int i, s;
 453         struct xhci_virt_ep *ep;
 454
 455         for (i = 0; i < LAST_EP_INDEX + 1; i++) {
 456                 ep = &xhci->devs[slot_id]->eps[i];
 457
 458                 if (ep->ep_state & EP_HAS_STREAMS) {
 459                         for (s = 1; s < ep->stream_info->num_streams; s++)
 460                                 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
 461                 } else if (ep->ring && ep->ring->dequeue) {
 462                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 463                 }
 464         }
 465
 466         return;
 467 }
 468
 469 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 470                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 471 {
 472         /* Don't allow the USB core to disable SuperSpeed ports. */
 473         if (hcd->speed >= HCD_USB3) {
 474                 xhci_dbg(xhci, "Ignoring request to disable "
 475                                 "SuperSpeed port.\n");
 476                 return;
 477         }
 478
 479         if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
 480                 xhci_dbg(xhci,
 481                          "Broken Port Enabled/Disabled, ignoring port disable request.\n");
 482                 return;
 483         }
 484
 485         /* Write 1 to disable the port */
 486         writel(port_status | PORT_PE, addr);
 487         port_status = readl(addr);
 488         xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
 489                         wIndex, port_status);
 490 }
 491
 492 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 493                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 494 {
 495         char *port_change_bit;
 496         u32 status;
 497
 498         switch (wValue) {
 499         case USB_PORT_FEAT_C_RESET:
 500                 status = PORT_RC;
 501                 port_change_bit = "reset";
 502                 break;
 503         case USB_PORT_FEAT_C_BH_PORT_RESET:
 504                 status = PORT_WRC;
 505                 port_change_bit = "warm(BH) reset";
 506                 break;
 507         case USB_PORT_FEAT_C_CONNECTION:
 508                 status = PORT_CSC;
 509                 port_change_bit = "connect";
 510                 break;
 511         case USB_PORT_FEAT_C_OVER_CURRENT:
 512                 status = PORT_OCC;
 513                 port_change_bit = "over-current";
 514                 break;
 515         case USB_PORT_FEAT_C_ENABLE:
 516                 status = PORT_PEC;
 517                 port_change_bit = "enable/disable";
 518                 break;
 519         case USB_PORT_FEAT_C_SUSPEND:
 520                 status = PORT_PLC;
 521                 port_change_bit = "suspend/resume";
 522                 break;
 523         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 524                 status = PORT_PLC;
 525                 port_change_bit = "link state";
 526                 break;
 527         case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
 528                 status = PORT_CEC;
 529                 port_change_bit = "config error";
 530                 break;
 531         default:
 532                 /* Should never happen */
 533                 return;
 534         }
 535         /* Change bits are all write 1 to clear */
 536         writel(port_status | status, addr);
 537         port_status = readl(addr);
 538         xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
 539                         port_change_bit, wIndex, port_status);
 540 }
 541
 542 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
 543 {
 544         int max_ports;
 545         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 546
 547         if (hcd->speed >= HCD_USB3) {
 548                 max_ports = xhci->num_usb3_ports;
 549                 *port_array = xhci->usb3_ports;
 550         } else {
 551                 max_ports = xhci->num_usb2_ports;
 552                 *port_array = xhci->usb2_ports;
 553         }
 554
 555         return max_ports;
 556 }
 557
 558 static __le32 __iomem *xhci_get_port_io_addr(struct usb_hcd *hcd, int index)
 559 {
 560         __le32 __iomem **port_array;
 561
 562         xhci_get_ports(hcd, &port_array);
 563         return port_array[index];
 564 }
 565
 566 /*
 567  * xhci_set_port_power() must be called with xhci->lock held.
 568  * It will release and re-aquire the lock while calling ACPI
 569  * method.
 570  */
 571 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
 572                                 u16 index, bool on, unsigned long *flags)
 573 {
 574         __le32 __iomem *addr;
 575         u32 temp;
 576
 577         addr = xhci_get_port_io_addr(hcd, index);
 578         temp = readl(addr);
 579         temp = xhci_port_state_to_neutral(temp);
 580         if (on) {
 581                 /* Power on */
 582                 writel(temp | PORT_POWER, addr);
 583                 temp = readl(addr);
 584                 xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n",
 585                                                 index, temp);
 586         } else {
 587                 /* Power off */
 588                 writel(temp & ~PORT_POWER, addr);
 589         }
 590
 591         spin_unlock_irqrestore(&xhci->lock, *flags);
 592         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 593                                         index);
 594         if (temp)
 595                 usb_acpi_set_power_state(hcd->self.root_hub,
 596                         index, on);
 597         spin_lock_irqsave(&xhci->lock, *flags);
 598 }
 599
 600 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
 601         u16 test_mode, u16 wIndex)
 602 {
 603         u32 temp;
 604         __le32 __iomem *addr;
 605
 606         /* xhci only supports test mode for usb2 ports, i.e. xhci->main_hcd */
 607         addr = xhci_get_port_io_addr(xhci->main_hcd, wIndex);
 608         temp = readl(addr + PORTPMSC);
 609         temp |= test_mode << PORT_TEST_MODE_SHIFT;
 610         writel(temp, addr + PORTPMSC);
 611         xhci->test_mode = test_mode;
 612         if (test_mode == TEST_FORCE_EN)
 613                 xhci_start(xhci);
 614 }
 615
 616 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
 617                                 u16 test_mode, u16 wIndex, unsigned long *flags)
 618 {
 619         int i, retval;
 620
 621         /* Disable all Device Slots */
 622         xhci_dbg(xhci, "Disable all slots\n");
 623         spin_unlock_irqrestore(&xhci->lock, *flags);
 624         for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
 625                 if (!xhci->devs[i])
 626                         continue;
 627
 628                 retval = xhci_disable_slot(xhci, i);
 629                 if (retval)
 630                         xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
 631                                  i, retval);
 632         }
 633         spin_lock_irqsave(&xhci->lock, *flags);
 634         /* Put all ports to the Disable state by clear PP */
 635         xhci_dbg(xhci, "Disable all port (PP = 0)\n");
 636         /* Power off USB3 ports*/
 637         for (i = 0; i < xhci->num_usb3_ports; i++)
 638                 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
 639         /* Power off USB2 ports*/
 640         for (i = 0; i < xhci->num_usb2_ports; i++)
 641                 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
 642         /* Stop the controller */
 643         xhci_dbg(xhci, "Stop controller\n");
 644         retval = xhci_halt(xhci);
 645         if (retval)
 646                 return retval;
 647         /* Disable runtime PM for test mode */
 648         pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
 649         /* Set PORTPMSC.PTC field to enter selected test mode */
 650         /* Port is selected by wIndex. port_id = wIndex + 1 */
 651         xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
 652                                         test_mode, wIndex + 1);
 653         xhci_port_set_test_mode(xhci, test_mode, wIndex);
 654         return retval;
 655 }
 656
 657 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
 658 {
 659         int retval;
 660
 661         if (!xhci->test_mode) {
 662                 xhci_err(xhci, "Not in test mode, do nothing.\n");
 663                 return 0;
 664         }
 665         if (xhci->test_mode == TEST_FORCE_EN &&
 666                 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
 667                 retval = xhci_halt(xhci);
 668                 if (retval)
 669                         return retval;
 670         }
 671         pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
 672         xhci->test_mode = 0;
 673         return xhci_reset(xhci);
 674 }
 675
 676 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 677                                 int port_id, u32 link_state)
 678 {
 679         u32 temp;
 680
 681         temp = readl(port_array[port_id]);
 682         temp = xhci_port_state_to_neutral(temp);
 683         temp &= ~PORT_PLS_MASK;
 684         temp |= PORT_LINK_STROBE | link_state;
 685         writel(temp, port_array[port_id]);
 686 }
 687
 688 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 689                 __le32 __iomem **port_array, int port_id, u16 wake_mask)
 690 {
 691         u32 temp;
 692
 693         temp = readl(port_array[port_id]);
 694         temp = xhci_port_state_to_neutral(temp);
 695
 696         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 697                 temp |= PORT_WKCONN_E;
 698         else
 699                 temp &= ~PORT_WKCONN_E;
 700
 701         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 702                 temp |= PORT_WKDISC_E;
 703         else
 704                 temp &= ~PORT_WKDISC_E;
 705
 706         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 707                 temp |= PORT_WKOC_E;
 708         else
 709                 temp &= ~PORT_WKOC_E;
 710
 711         writel(temp, port_array[port_id]);
 712 }
 713
 714 /* Test and clear port RWC bit */
 715 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 716                                 int port_id, u32 port_bit)
 717 {
 718         u32 temp;
 719
 720         temp = readl(port_array[port_id]);
 721         if (temp & port_bit) {
 722                 temp = xhci_port_state_to_neutral(temp);
 723                 temp |= port_bit;
 724                 writel(temp, port_array[port_id]);
 725         }
 726 }
 727
 728 /* Updates Link Status for USB 2.1 port */
 729 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
 730 {
 731         if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
 732                 *status |= USB_PORT_STAT_L1;
 733 }
 734
 735 /* Updates Link Status for super Speed port */
 736 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
 737                 u32 *status, u32 status_reg)
 738 {
 739         u32 pls = status_reg & PORT_PLS_MASK;
 740
 741         /* resume state is a xHCI internal state.
 742          * Do not report it to usb core, instead, pretend to be U3,
 743          * thus usb core knows it's not ready for transfer
 744          */
 745         if (pls == XDEV_RESUME) {
 746                 *status |= USB_SS_PORT_LS_U3;
 747                 return;
 748         }
 749
 750         /* When the CAS bit is set then warm reset
 751          * should be performed on port
 752          */
 753         if (status_reg & PORT_CAS) {
 754                 /* The CAS bit can be set while the port is
 755                  * in any link state.
 756                  * Only roothubs have CAS bit, so we
 757                  * pretend to be in compliance mode
 758                  * unless we're already in compliance
 759                  * or the inactive state.
 760                  */
 761                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 762                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 763                         pls = USB_SS_PORT_LS_COMP_MOD;
 764                 }
 765                 /* Return also connection bit -
 766                  * hub state machine resets port
 767                  * when this bit is set.
 768                  */
 769                 pls |= USB_PORT_STAT_CONNECTION;
 770         } else {
 771                 /*
 772                  * If CAS bit isn't set but the Port is already at
 773                  * Compliance Mode, fake a connection so the USB core
 774                  * notices the Compliance state and resets the port.
 775                  * This resolves an issue generated by the SN65LVPE502CP
 776                  * in which sometimes the port enters compliance mode
 777                  * caused by a delay on the host-device negotiation.
 778                  */
 779                 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 780                                 (pls == USB_SS_PORT_LS_COMP_MOD))
 781                         pls |= USB_PORT_STAT_CONNECTION;
 782         }
 783
 784         /* update status field */
 785         *status |= pls;
 786 }
 787
 788 /*
 789  * Function for Compliance Mode Quirk.
 790  *
 791  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 792  * the compliance mode timer is deleted. A port won't enter
 793  * compliance mode if it has previously entered U0.
 794  */
 795 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
 796                                     u16 wIndex)
 797 {
 798         u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
 799         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 800
 801         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 802                 return;
 803
 804         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 805                 xhci->port_status_u0 |= 1 << wIndex;
 806                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 807                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 808                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 809                                 "All USB3 ports have entered U0 already!");
 810                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 811                                 "Compliance Mode Recovery Timer Deleted.");
 812                 }
 813         }
 814 }
 815
 816 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
 817 {
 818         u32 ext_stat = 0;
 819         int speed_id;
 820
 821         /* only support rx and tx lane counts of 1 in usb3.1 spec */
 822         speed_id = DEV_PORT_SPEED(raw_port_status);
 823         ext_stat |= speed_id;           /* bits 3:0, RX speed id */
 824         ext_stat |= speed_id << 4;      /* bits 7:4, TX speed id */
 825
 826         ext_stat |= PORT_RX_LANES(port_li) << 8;  /* bits 11:8 Rx lane count */
 827         ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
 828
 829         return ext_stat;
 830 }
 831
 832 /*
 833  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
 834  * 3.0 hubs use.
 835  *
 836  * Possible side effects:
 837  *  - Mark a port as being done with device resume,
 838  *    and ring the endpoint doorbells.
 839  *  - Stop the Synopsys redriver Compliance Mode polling.
 840  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
 841  */
 842 static u32 xhci_get_port_status(struct usb_hcd *hcd,
 843                 struct xhci_bus_state *bus_state,
 844                 __le32 __iomem **port_array,
 845                 u16 wIndex, u32 raw_port_status,
 846                 unsigned long flags)
 847         __releases(&xhci->lock)
 848         __acquires(&xhci->lock)
 849 {
 850         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 851         u32 status = 0;
 852         int slot_id;
 853
 854         /* wPortChange bits */
 855         if (raw_port_status & PORT_CSC)
 856                 status |= USB_PORT_STAT_C_CONNECTION << 16;
 857         if (raw_port_status & PORT_PEC)
 858                 status |= USB_PORT_STAT_C_ENABLE << 16;
 859         if ((raw_port_status & PORT_OCC))
 860                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
 861         if ((raw_port_status & PORT_RC))
 862                 status |= USB_PORT_STAT_C_RESET << 16;
 863         /* USB3.0 only */
 864         if (hcd->speed >= HCD_USB3) {
 865                 /* Port link change with port in resume state should not be
 866                  * reported to usbcore, as this is an internal state to be
 867                  * handled by xhci driver. Reporting PLC to usbcore may
 868                  * cause usbcore clearing PLC first and port change event
 869                  * irq won't be generated.
 870                  */
 871                 if ((raw_port_status & PORT_PLC) &&
 872                         (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
 873                         status |= USB_PORT_STAT_C_LINK_STATE << 16;
 874                 if ((raw_port_status & PORT_WRC))
 875                         status |= USB_PORT_STAT_C_BH_RESET << 16;
 876                 if ((raw_port_status & PORT_CEC))
 877                         status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
 878         }
 879
 880         if (hcd->speed < HCD_USB3) {
 881                 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
 882                                 && (raw_port_status & PORT_POWER))
 883                         status |= USB_PORT_STAT_SUSPEND;
 884         }
 885         if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
 886                 !DEV_SUPERSPEED_ANY(raw_port_status)) {
 887                 if ((raw_port_status & PORT_RESET) ||
 888                                 !(raw_port_status & PORT_PE))
 889                         return 0xffffffff;
 890                 /* did port event handler already start resume timing? */
 891                 if (!bus_state->resume_done[wIndex]) {
 892                         /* If not, maybe we are in a host initated resume? */
 893                         if (test_bit(wIndex, &bus_state->resuming_ports)) {
 894                                 /* Host initated resume doesn't time the resume
 895                                  * signalling using resume_done[].
 896                                  * It manually sets RESUME state, sleeps 20ms
 897                                  * and sets U0 state. This should probably be
 898                                  * changed, but not right now.
 899                                  */
 900                         } else {
 901                                 /* port resume was discovered now and here,
 902                                  * start resume timing
 903                                  */
 904                                 unsigned long timeout = jiffies +
 905                                         msecs_to_jiffies(USB_RESUME_TIMEOUT);
 906
 907                                 set_bit(wIndex, &bus_state->resuming_ports);
 908                                 bus_state->resume_done[wIndex] = timeout;
 909                                 mod_timer(&hcd->rh_timer, timeout);
 910                         }
 911                 /* Has resume been signalled for USB_RESUME_TIME yet? */
 912                 } else if (time_after_eq(jiffies,
 913                                          bus_state->resume_done[wIndex])) {
 914                         int time_left;
 915
 916                         xhci_dbg(xhci, "Resume USB2 port %d\n",
 917                                         wIndex + 1);
 918                         bus_state->resume_done[wIndex] = 0;
 919                         clear_bit(wIndex, &bus_state->resuming_ports);
 920
 921                         set_bit(wIndex, &bus_state->rexit_ports);
 922
 923                         xhci_test_and_clear_bit(xhci, port_array, wIndex,
 924                                                 PORT_PLC);
 925                         xhci_set_link_state(xhci, port_array, wIndex,
 926                                         XDEV_U0);
 927
 928                         spin_unlock_irqrestore(&xhci->lock, flags);
 929                         time_left = wait_for_completion_timeout(
 930                                         &bus_state->rexit_done[wIndex],
 931                                         msecs_to_jiffies(
 932                                                 XHCI_MAX_REXIT_TIMEOUT));
 933                         spin_lock_irqsave(&xhci->lock, flags);
 934
 935                         if (time_left) {
 936                                 slot_id = xhci_find_slot_id_by_port(hcd,
 937                                                 xhci, wIndex + 1);
 938                                 if (!slot_id) {
 939                                         xhci_dbg(xhci, "slot_id is zero\n");
 940                                         return 0xffffffff;
 941                                 }
 942                                 xhci_ring_device(xhci, slot_id);
 943                         } else {
 944                                 int port_status = readl(port_array[wIndex]);
 945                                 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
 946                                                 XHCI_MAX_REXIT_TIMEOUT,
 947                                                 port_status);
 948                                 status |= USB_PORT_STAT_SUSPEND;
 949                                 clear_bit(wIndex, &bus_state->rexit_ports);
 950                         }
 951
 952                         bus_state->port_c_suspend |= 1 << wIndex;
 953                         bus_state->suspended_ports &= ~(1 << wIndex);
 954                 } else {
 955                         /*
 956                          * The resume has been signaling for less than
 957                          * USB_RESUME_TIME. Report the port status as SUSPEND,
 958                          * let the usbcore check port status again and clear
 959                          * resume signaling later.
 960                          */
 961                         status |= USB_PORT_STAT_SUSPEND;
 962                 }
 963         }
 964         /*
 965          * Clear stale usb2 resume signalling variables in case port changed
 966          * state during resume signalling. For example on error
 967          */
 968         if ((bus_state->resume_done[wIndex] ||
 969              test_bit(wIndex, &bus_state->resuming_ports)) &&
 970             (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
 971             (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
 972                 bus_state->resume_done[wIndex] = 0;
 973                 clear_bit(wIndex, &bus_state->resuming_ports);
 974         }
 975
 976
 977         if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
 978             (raw_port_status & PORT_POWER)) {
 979                 if (bus_state->suspended_ports & (1 << wIndex)) {
 980                         bus_state->suspended_ports &= ~(1 << wIndex);
 981                         if (hcd->speed < HCD_USB3)
 982                                 bus_state->port_c_suspend |= 1 << wIndex;
 983                 }
 984                 bus_state->resume_done[wIndex] = 0;
 985                 clear_bit(wIndex, &bus_state->resuming_ports);
 986         }
 987         if (raw_port_status & PORT_CONNECT) {
 988                 status |= USB_PORT_STAT_CONNECTION;
 989                 status |= xhci_port_speed(raw_port_status);
 990         }
 991         if (raw_port_status & PORT_PE)
 992                 status |= USB_PORT_STAT_ENABLE;
 993         if (raw_port_status & PORT_OC)
 994                 status |= USB_PORT_STAT_OVERCURRENT;
 995         if (raw_port_status & PORT_RESET)
 996                 status |= USB_PORT_STAT_RESET;
 997         if (raw_port_status & PORT_POWER) {
 998                 if (hcd->speed >= HCD_USB3)
 999                         status |= USB_SS_PORT_STAT_POWER;
1000                 else
1001                         status |= USB_PORT_STAT_POWER;
1002         }
1003         /* Update Port Link State */
1004         if (hcd->speed >= HCD_USB3) {
1005                 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
1006                 /*
1007                  * Verify if all USB3 Ports Have entered U0 already.
1008                  * Delete Compliance Mode Timer if so.
1009                  */
1010                 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
1011         } else {
1012                 xhci_hub_report_usb2_link_state(&status, raw_port_status);
1013         }
1014         if (bus_state->port_c_suspend & (1 << wIndex))
1015                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1016
1017         return status;
1018 }
1019
1020 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1021                 u16 wIndex, char *buf, u16 wLength)
1022 {
1023         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1024         int max_ports;
1025         unsigned long flags;
1026         u32 temp, status;
1027         int retval = 0;
1028         __le32 __iomem **port_array;
1029         int slot_id;
1030         struct xhci_bus_state *bus_state;
1031         u16 link_state = 0;
1032         u16 wake_mask = 0;
1033         u16 timeout = 0;
1034         u16 test_mode = 0;
1035
1036         max_ports = xhci_get_ports(hcd, &port_array);
1037         bus_state = &xhci->bus_state[hcd_index(hcd)];
1038
1039         spin_lock_irqsave(&xhci->lock, flags);
1040         switch (typeReq) {
1041         case GetHubStatus:
1042                 /* No power source, over-current reported per port */
1043                 memset(buf, 0, 4);
1044                 break;
1045         case GetHubDescriptor:
1046                 /* Check to make sure userspace is asking for the USB 3.0 hub
1047                  * descriptor for the USB 3.0 roothub.  If not, we stall the
1048                  * endpoint, like external hubs do.
1049                  */
1050                 if (hcd->speed >= HCD_USB3 &&
1051                                 (wLength < USB_DT_SS_HUB_SIZE ||
1052                                  wValue != (USB_DT_SS_HUB << 8))) {
1053                         xhci_dbg(xhci, "Wrong hub descriptor type for "
1054                                         "USB 3.0 roothub.\n");
1055                         goto error;
1056                 }
1057                 xhci_hub_descriptor(hcd, xhci,
1058                                 (struct usb_hub_descriptor *) buf);
1059                 break;
1060         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1061                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1062                         goto error;
1063
1064                 if (hcd->speed < HCD_USB3)
1065                         goto error;
1066
1067                 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
1068                 spin_unlock_irqrestore(&xhci->lock, flags);
1069                 return retval;
1070         case GetPortStatus:
1071                 if (!wIndex || wIndex > max_ports)
1072                         goto error;
1073                 wIndex--;
1074                 temp = readl(port_array[wIndex]);
1075                 if (temp == ~(u32)0) {
1076                         xhci_hc_died(xhci);
1077                         retval = -ENODEV;
1078                         break;
1079                 }
1080                 status = xhci_get_port_status(hcd, bus_state, port_array,
1081                                 wIndex, temp, flags);
1082                 if (status == 0xffffffff)
1083                         goto error;
1084
1085                 xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n",
1086                                 wIndex, temp);
1087                 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
1088
1089                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1090                 /* if USB 3.1 extended port status return additional 4 bytes */
1091                 if (wValue == 0x02) {
1092                         u32 port_li;
1093
1094                         if (hcd->speed < HCD_USB31 || wLength != 8) {
1095                                 xhci_err(xhci, "get ext port status invalid parameter\n");
1096                                 retval = -EINVAL;
1097                                 break;
1098                         }
1099                         port_li = readl(port_array[wIndex] + PORTLI);
1100                         status = xhci_get_ext_port_status(temp, port_li);
1101                         put_unaligned_le32(cpu_to_le32(status), &buf[4]);
1102                 }
1103                 break;
1104         case SetPortFeature:
1105                 if (wValue == USB_PORT_FEAT_LINK_STATE)
1106                         link_state = (wIndex & 0xff00) >> 3;
1107                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1108                         wake_mask = wIndex & 0xff00;
1109                 if (wValue == USB_PORT_FEAT_TEST)
1110                         test_mode = (wIndex & 0xff00) >> 8;
1111                 /* The MSB of wIndex is the U1/U2 timeout */
1112                 timeout = (wIndex & 0xff00) >> 8;
1113                 wIndex &= 0xff;
1114                 if (!wIndex || wIndex > max_ports)
1115                         goto error;
1116                 wIndex--;
1117                 temp = readl(port_array[wIndex]);
1118                 if (temp == ~(u32)0) {
1119                         xhci_hc_died(xhci);
1120                         retval = -ENODEV;
1121                         break;
1122                 }
1123                 temp = xhci_port_state_to_neutral(temp);
1124                 /* FIXME: What new port features do we need to support? */
1125                 switch (wValue) {
1126                 case USB_PORT_FEAT_SUSPEND:
1127                         temp = readl(port_array[wIndex]);
1128                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1129                                 /* Resume the port to U0 first */
1130                                 xhci_set_link_state(xhci, port_array, wIndex,
1131                                                         XDEV_U0);
1132                                 spin_unlock_irqrestore(&xhci->lock, flags);
1133                                 msleep(10);
1134                                 spin_lock_irqsave(&xhci->lock, flags);
1135                         }
1136                         /* In spec software should not attempt to suspend
1137                          * a port unless the port reports that it is in the
1138                          * enabled (PED = ‘1’,PLS < ‘3’) state.
1139                          */
1140                         temp = readl(port_array[wIndex]);
1141                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1142                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1143                                 xhci_warn(xhci, "USB core suspending device not in U0/U1/U2.\n");
1144                                 goto error;
1145                         }
1146
1147                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1148                                         wIndex + 1);
1149                         if (!slot_id) {
1150                                 xhci_warn(xhci, "slot_id is zero\n");
1151                                 goto error;
1152                         }
1153                         /* unlock to execute stop endpoint commands */
1154                         spin_unlock_irqrestore(&xhci->lock, flags);
1155                         xhci_stop_device(xhci, slot_id, 1);
1156                         spin_lock_irqsave(&xhci->lock, flags);
1157
1158                         xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
1159
1160                         spin_unlock_irqrestore(&xhci->lock, flags);
1161                         msleep(10); /* wait device to enter */
1162                         spin_lock_irqsave(&xhci->lock, flags);
1163
1164                         temp = readl(port_array[wIndex]);
1165                         bus_state->suspended_ports |= 1 << wIndex;
1166                         break;
1167                 case USB_PORT_FEAT_LINK_STATE:
1168                         temp = readl(port_array[wIndex]);
1169
1170                         /* Disable port */
1171                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1172                                 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1173                                 temp = xhci_port_state_to_neutral(temp);
1174                                 /*
1175                                  * Clear all change bits, so that we get a new
1176                                  * connection event.
1177                                  */
1178                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1179                                         PORT_OCC | PORT_RC | PORT_PLC |
1180                                         PORT_CEC;
1181                                 writel(temp | PORT_PE, port_array[wIndex]);
1182                                 temp = readl(port_array[wIndex]);
1183                                 break;
1184                         }
1185
1186                         /* Put link in RxDetect (enable port) */
1187                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1188                                 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1189                                 xhci_set_link_state(xhci, port_array, wIndex,
1190                                                 link_state);
1191                                 temp = readl(port_array[wIndex]);
1192                                 break;
1193                         }
1194
1195                         /*
1196                          * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1197                          * root hub port's transition to compliance mode upon
1198                          * detecting LFPS timeout may be controlled by an
1199                          * Compliance Transition Enabled (CTE) flag (not
1200                          * software visible). This flag is set by writing 0xA
1201                          * to PORTSC PLS field which will allow transition to
1202                          * compliance mode the next time LFPS timeout is
1203                          * encountered. A warm reset will clear it.
1204                          *
1205                          * The CTE flag is only supported if the HCCPARAMS2 CTC
1206                          * flag is set, otherwise, the compliance substate is
1207                          * automatically entered as on 1.0 and prior.
1208                          */
1209                         if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1210                                 if (!HCC2_CTC(xhci->hcc_params2)) {
1211                                         xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1212                                         break;
1213                                 }
1214
1215                                 if ((temp & PORT_CONNECT)) {
1216                                         xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1217                                         goto error;
1218                                 }
1219
1220                                 xhci_dbg(xhci, "Enable compliance mode transition for port %d\n",
1221                                                 wIndex);
1222                                 xhci_set_link_state(xhci, port_array, wIndex,
1223                                                 link_state);
1224                                 temp = readl(port_array[wIndex]);
1225                                 break;
1226                         }
1227
1228                         /* Software should not attempt to set
1229                          * port link state above '3' (U3) and the port
1230                          * must be enabled.
1231                          */
1232                         if ((temp & PORT_PE) == 0 ||
1233                                 (link_state > USB_SS_PORT_LS_U3)) {
1234                                 xhci_warn(xhci, "Cannot set link state.\n");
1235                                 goto error;
1236                         }
1237
1238                         if (link_state == USB_SS_PORT_LS_U3) {
1239                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1240                                                 wIndex + 1);
1241                                 if (slot_id) {
1242                                         /* unlock to execute stop endpoint
1243                                          * commands */
1244                                         spin_unlock_irqrestore(&xhci->lock,
1245                                                                 flags);
1246                                         xhci_stop_device(xhci, slot_id, 1);
1247                                         spin_lock_irqsave(&xhci->lock, flags);
1248                                 }
1249                         }
1250
1251                         xhci_set_link_state(xhci, port_array, wIndex,
1252                                                 link_state);
1253
1254                         spin_unlock_irqrestore(&xhci->lock, flags);
1255                         msleep(20); /* wait device to enter */
1256                         spin_lock_irqsave(&xhci->lock, flags);
1257
1258                         temp = readl(port_array[wIndex]);
1259                         if (link_state == USB_SS_PORT_LS_U3)
1260                                 bus_state->suspended_ports |= 1 << wIndex;
1261                         break;
1262                 case USB_PORT_FEAT_POWER:
1263                         /*
1264                          * Turn on ports, even if there isn't per-port switching.
1265                          * HC will report connect events even before this is set.
1266                          * However, hub_wq will ignore the roothub events until
1267                          * the roothub is registered.
1268                          */
1269                         xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1270                         break;
1271                 case USB_PORT_FEAT_RESET:
1272                         temp = (temp | PORT_RESET);
1273                         writel(temp, port_array[wIndex]);
1274
1275                         temp = readl(port_array[wIndex]);
1276                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
1277                         break;
1278                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1279                         xhci_set_remote_wake_mask(xhci, port_array,
1280                                         wIndex, wake_mask);
1281                         temp = readl(port_array[wIndex]);
1282                         xhci_dbg(xhci, "set port remote wake mask, "
1283                                         "actual port %d status  = 0x%x\n",
1284                                         wIndex, temp);
1285                         break;
1286                 case USB_PORT_FEAT_BH_PORT_RESET:
1287                         temp |= PORT_WR;
1288                         writel(temp, port_array[wIndex]);
1289
1290                         temp = readl(port_array[wIndex]);
1291                         break;
1292                 case USB_PORT_FEAT_U1_TIMEOUT:
1293                         if (hcd->speed < HCD_USB3)
1294                                 goto error;
1295                         temp = readl(port_array[wIndex] + PORTPMSC);
1296                         temp &= ~PORT_U1_TIMEOUT_MASK;
1297                         temp |= PORT_U1_TIMEOUT(timeout);
1298                         writel(temp, port_array[wIndex] + PORTPMSC);
1299                         break;
1300                 case USB_PORT_FEAT_U2_TIMEOUT:
1301                         if (hcd->speed < HCD_USB3)
1302                                 goto error;
1303                         temp = readl(port_array[wIndex] + PORTPMSC);
1304                         temp &= ~PORT_U2_TIMEOUT_MASK;
1305                         temp |= PORT_U2_TIMEOUT(timeout);
1306                         writel(temp, port_array[wIndex] + PORTPMSC);
1307                         break;
1308                 case USB_PORT_FEAT_TEST:
1309                         /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1310                         if (hcd->speed != HCD_USB2)
1311                                 goto error;
1312                         if (test_mode > TEST_FORCE_EN || test_mode < TEST_J)
1313                                 goto error;
1314                         retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1315                                                       &flags);
1316                         break;
1317                 default:
1318                         goto error;
1319                 }
1320                 /* unblock any posted writes */
1321                 temp = readl(port_array[wIndex]);
1322                 break;
1323         case ClearPortFeature:
1324                 if (!wIndex || wIndex > max_ports)
1325                         goto error;
1326                 wIndex--;
1327                 temp = readl(port_array[wIndex]);
1328                 if (temp == ~(u32)0) {
1329                         xhci_hc_died(xhci);
1330                         retval = -ENODEV;
1331                         break;
1332                 }
1333                 /* FIXME: What new port features do we need to support? */
1334                 temp = xhci_port_state_to_neutral(temp);
1335                 switch (wValue) {
1336                 case USB_PORT_FEAT_SUSPEND:
1337                         temp = readl(port_array[wIndex]);
1338                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1339                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
1340                         if (temp & PORT_RESET)
1341                                 goto error;
1342                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1343                                 if ((temp & PORT_PE) == 0)
1344                                         goto error;
1345
1346                                 set_bit(wIndex, &bus_state->resuming_ports);
1347                                 xhci_set_link_state(xhci, port_array, wIndex,
1348                                                         XDEV_RESUME);
1349                                 spin_unlock_irqrestore(&xhci->lock, flags);
1350                                 msleep(USB_RESUME_TIMEOUT);
1351                                 spin_lock_irqsave(&xhci->lock, flags);
1352                                 xhci_set_link_state(xhci, port_array, wIndex,
1353                                                         XDEV_U0);
1354                                 clear_bit(wIndex, &bus_state->resuming_ports);
1355                         }
1356                         bus_state->port_c_suspend |= 1 << wIndex;
1357
1358                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1359                                         wIndex + 1);
1360                         if (!slot_id) {
1361                                 xhci_dbg(xhci, "slot_id is zero\n");
1362                                 goto error;
1363                         }
1364                         xhci_ring_device(xhci, slot_id);
1365                         break;
1366                 case USB_PORT_FEAT_C_SUSPEND:
1367                         bus_state->port_c_suspend &= ~(1 << wIndex);
1368                         /* fall through */
1369                 case USB_PORT_FEAT_C_RESET:
1370                 case USB_PORT_FEAT_C_BH_PORT_RESET:
1371                 case USB_PORT_FEAT_C_CONNECTION:
1372                 case USB_PORT_FEAT_C_OVER_CURRENT:
1373                 case USB_PORT_FEAT_C_ENABLE:
1374                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1375                 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1376                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1377                                         port_array[wIndex], temp);
1378                         break;
1379                 case USB_PORT_FEAT_ENABLE:
1380                         xhci_disable_port(hcd, xhci, wIndex,
1381                                         port_array[wIndex], temp);
1382                         break;
1383                 case USB_PORT_FEAT_POWER:
1384                         xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1385                         break;
1386                 case USB_PORT_FEAT_TEST:
1387                         retval = xhci_exit_test_mode(xhci);
1388                         break;
1389                 default:
1390                         goto error;
1391                 }
1392                 break;
1393         default:
1394 error:
1395                 /* "stall" on error */
1396                 retval = -EPIPE;
1397         }
1398         spin_unlock_irqrestore(&xhci->lock, flags);
1399         return retval;
1400 }
1401
1402 /*
1403  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1404  * Ports are 0-indexed from the HCD point of view,
1405  * and 1-indexed from the USB core pointer of view.
1406  *
1407  * Note that the status change bits will be cleared as soon as a port status
1408  * change event is generated, so we use the saved status from that event.
1409  */
1410 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1411 {
1412         unsigned long flags;
1413         u32 temp, status;
1414         u32 mask;
1415         int i, retval;
1416         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1417         int max_ports;
1418         __le32 __iomem **port_array;
1419         struct xhci_bus_state *bus_state;
1420         bool reset_change = false;
1421
1422         max_ports = xhci_get_ports(hcd, &port_array);
1423         bus_state = &xhci->bus_state[hcd_index(hcd)];
1424
1425         /* Initial status is no changes */
1426         retval = (max_ports + 8) / 8;
1427         memset(buf, 0, retval);
1428
1429         /*
1430          * Inform the usbcore about resume-in-progress by returning
1431          * a non-zero value even if there are no status changes.
1432          */
1433         status = bus_state->resuming_ports;
1434
1435         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1436
1437         spin_lock_irqsave(&xhci->lock, flags);
1438         /* For each port, did anything change?  If so, set that bit in buf. */
1439         for (i = 0; i < max_ports; i++) {
1440                 temp = readl(port_array[i]);
1441                 if (temp == ~(u32)0) {
1442                         xhci_hc_died(xhci);
1443                         retval = -ENODEV;
1444                         break;
1445                 }
1446                 if ((temp & mask) != 0 ||
1447                         (bus_state->port_c_suspend & 1 << i) ||
1448                         (bus_state->resume_done[i] && time_after_eq(
1449                             jiffies, bus_state->resume_done[i]))) {
1450                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1451                         status = 1;
1452                 }
1453                 if ((temp & PORT_RC))
1454                         reset_change = true;
1455         }
1456         if (!status && !reset_change) {
1457                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1458                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1459         }
1460         spin_unlock_irqrestore(&xhci->lock, flags);
1461         return status ? retval : 0;
1462 }
1463
1464 #ifdef CONFIG_PM
1465
1466 int xhci_bus_suspend(struct usb_hcd *hcd)
1467 {
1468         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1469         int max_ports, port_index;
1470         __le32 __iomem **port_array;
1471         struct xhci_bus_state *bus_state;
1472         unsigned long flags;
1473
1474         max_ports = xhci_get_ports(hcd, &port_array);
1475         bus_state = &xhci->bus_state[hcd_index(hcd)];
1476
1477         spin_lock_irqsave(&xhci->lock, flags);
1478
1479         if (hcd->self.root_hub->do_remote_wakeup) {
1480                 if (bus_state->resuming_ports ||        /* USB2 */
1481                     bus_state->port_remote_wakeup) {    /* USB3 */
1482                         spin_unlock_irqrestore(&xhci->lock, flags);
1483                         xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1484                         return -EBUSY;
1485                 }
1486         }
1487
1488         port_index = max_ports;
1489         bus_state->bus_suspended = 0;
1490         while (port_index--) {
1491                 /* suspend the port if the port is not suspended */
1492                 u32 t1, t2;
1493                 int slot_id;
1494
1495                 t1 = readl(port_array[port_index]);
1496                 t2 = xhci_port_state_to_neutral(t1);
1497
1498                 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1499                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1500                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1501                                         port_index + 1);
1502                         if (slot_id) {
1503                                 spin_unlock_irqrestore(&xhci->lock, flags);
1504                                 xhci_stop_device(xhci, slot_id, 1);
1505                                 spin_lock_irqsave(&xhci->lock, flags);
1506                         }
1507                         t2 &= ~PORT_PLS_MASK;
1508                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1509                         set_bit(port_index, &bus_state->bus_suspended);
1510                 }
1511                 /* USB core sets remote wake mask for USB 3.0 hubs,
1512                  * including the USB 3.0 roothub, but only if CONFIG_PM
1513                  * is enabled, so also enable remote wake here.
1514                  */
1515                 if (hcd->self.root_hub->do_remote_wakeup) {
1516                         if (t1 & PORT_CONNECT) {
1517                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1518                                 t2 &= ~PORT_WKCONN_E;
1519                         } else {
1520                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1521                                 t2 &= ~PORT_WKDISC_E;
1522                         }
1523                 } else
1524                         t2 &= ~PORT_WAKE_BITS;
1525
1526                 t1 = xhci_port_state_to_neutral(t1);
1527                 if (t1 != t2)
1528                         writel(t2, port_array[port_index]);
1529         }
1530         hcd->state = HC_STATE_SUSPENDED;
1531         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1532         spin_unlock_irqrestore(&xhci->lock, flags);
1533         return 0;
1534 }
1535
1536 /*
1537  * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1538  * warm reset a USB3 device stuck in polling or compliance mode after resume.
1539  * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1540  */
1541 static bool xhci_port_missing_cas_quirk(int port_index,
1542                                              __le32 __iomem **port_array)
1543 {
1544         u32 portsc;
1545
1546         portsc = readl(port_array[port_index]);
1547
1548         /* if any of these are set we are not stuck */
1549         if (portsc & (PORT_CONNECT | PORT_CAS))
1550                 return false;
1551
1552         if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1553             ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1554                 return false;
1555
1556         /* clear wakeup/change bits, and do a warm port reset */
1557         portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1558         portsc |= PORT_WR;
1559         writel(portsc, port_array[port_index]);
1560         /* flush write */
1561         readl(port_array[port_index]);
1562         return true;
1563 }
1564
1565 int xhci_bus_resume(struct usb_hcd *hcd)
1566 {
1567         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1568         struct xhci_bus_state *bus_state;
1569         __le32 __iomem **port_array;
1570         unsigned long flags;
1571         int max_ports, port_index;
1572         int slot_id;
1573         int sret;
1574         u32 next_state;
1575         u32 temp, portsc;
1576
1577         max_ports = xhci_get_ports(hcd, &port_array);
1578         bus_state = &xhci->bus_state[hcd_index(hcd)];
1579
1580         if (time_before(jiffies, bus_state->next_statechange))
1581                 msleep(5);
1582
1583         spin_lock_irqsave(&xhci->lock, flags);
1584         if (!HCD_HW_ACCESSIBLE(hcd)) {
1585                 spin_unlock_irqrestore(&xhci->lock, flags);
1586                 return -ESHUTDOWN;
1587         }
1588
1589         /* delay the irqs */
1590         temp = readl(&xhci->op_regs->command);
1591         temp &= ~CMD_EIE;
1592         writel(temp, &xhci->op_regs->command);
1593
1594         /* bus specific resume for ports we suspended at bus_suspend */
1595         if (hcd->speed >= HCD_USB3)
1596                 next_state = XDEV_U0;
1597         else
1598                 next_state = XDEV_RESUME;
1599
1600         port_index = max_ports;
1601         while (port_index--) {
1602                 portsc = readl(port_array[port_index]);
1603
1604                 /* warm reset CAS limited ports stuck in polling/compliance */
1605                 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1606                     (hcd->speed >= HCD_USB3) &&
1607                     xhci_port_missing_cas_quirk(port_index, port_array)) {
1608                         xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1609                         clear_bit(port_index, &bus_state->bus_suspended);
1610                         continue;
1611                 }
1612                 /* resume if we suspended the link, and it is still suspended */
1613                 if (test_bit(port_index, &bus_state->bus_suspended))
1614                         switch (portsc & PORT_PLS_MASK) {
1615                         case XDEV_U3:
1616                                 portsc = xhci_port_state_to_neutral(portsc);
1617                                 portsc &= ~PORT_PLS_MASK;
1618                                 portsc |= PORT_LINK_STROBE | next_state;
1619                                 break;
1620                         case XDEV_RESUME:
1621                                 /* resume already initiated */
1622                                 break;
1623                         default:
1624                                 /* not in a resumeable state, ignore it */
1625                                 clear_bit(port_index,
1626                                           &bus_state->bus_suspended);
1627                                 break;
1628                         }
1629                 /* disable wake for all ports, write new link state if needed */
1630                 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1631                 writel(portsc, port_array[port_index]);
1632         }
1633
1634         /* USB2 specific resume signaling delay and U0 link state transition */
1635         if (hcd->speed < HCD_USB3) {
1636                 if (bus_state->bus_suspended) {
1637                         spin_unlock_irqrestore(&xhci->lock, flags);
1638                         msleep(USB_RESUME_TIMEOUT);
1639                         spin_lock_irqsave(&xhci->lock, flags);
1640                 }
1641                 for_each_set_bit(port_index, &bus_state->bus_suspended,
1642                                  BITS_PER_LONG) {
1643                         /* Clear PLC to poll it later for U0 transition */
1644                         xhci_test_and_clear_bit(xhci, port_array, port_index,
1645                                                 PORT_PLC);
1646                         xhci_set_link_state(xhci, port_array, port_index,
1647                                             XDEV_U0);
1648                 }
1649         }
1650
1651         /* poll for U0 link state complete, both USB2 and USB3 */
1652         for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1653                 sret = xhci_handshake(port_array[port_index], PORT_PLC,
1654                                       PORT_PLC, 10 * 1000);
1655                 if (sret) {
1656                         xhci_warn(xhci, "port %d resume PLC timeout\n",
1657                                   port_index);
1658                         continue;
1659                 }
1660                 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1661                 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1662                 if (slot_id)
1663                         xhci_ring_device(xhci, slot_id);
1664         }
1665         (void) readl(&xhci->op_regs->command);
1666
1667         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1668         /* re-enable irqs */
1669         temp = readl(&xhci->op_regs->command);
1670         temp |= CMD_EIE;
1671         writel(temp, &xhci->op_regs->command);
1672         temp = readl(&xhci->op_regs->command);
1673
1674         spin_unlock_irqrestore(&xhci->lock, flags);
1675         return 0;
1676 }
1677
1678 #endif  /* CONFIG_PM */