1 /* linux/drivers/usb/gadget/s3c-hsotg.c
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * S3C USB2.0 High-speed / OtG driver
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/interrupt.h>
19 #include <linux/platform_device.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/delay.h>
26 #include <linux/usb/ch9.h>
27 #include <linux/usb/gadget.h>
31 #include <plat/regs-usb-hsotg-phy.h>
32 #include <plat/regs-usb-hsotg.h>
33 #include <plat/regs-sys.h>
34 #include <plat/udc-hs.h>
36 #define DMA_ADDR_INVALID (~((dma_addr_t)0))
40 * Unfortunately there seems to be a limit of the amount of data that can
41 * be transfered by IN transactions on EP0. This is either 127 bytes or 3
42 * packets (which practially means 1 packet and 63 bytes of data) when the
45 * This means if we are wanting to move >127 bytes of data, we need to
46 * split the transactions up, but just doing one packet at a time does
47 * not work (this may be an implicit DATA0 PID on first packet of the
48 * transaction) and doing 2 packets is outside the controller's limits.
50 * If we try to lower the MPS size for EP0, then no transfers work properly
51 * for EP0, and the system will fail basic enumeration. As no cause for this
52 * has currently been found, we cannot support any large IN transfers for
55 #define EP0_MPS_LIMIT 64
61 * struct s3c_hsotg_ep - driver endpoint definition.
62 * @ep: The gadget layer representation of the endpoint.
63 * @name: The driver generated name for the endpoint.
64 * @queue: Queue of requests for this endpoint.
65 * @parent: Reference back to the parent device structure.
66 * @req: The current request that the endpoint is processing. This is
67 * used to indicate an request has been loaded onto the endpoint
68 * and has yet to be completed (maybe due to data move, or simply
69 * awaiting an ack from the core all the data has been completed).
70 * @debugfs: File entry for debugfs file for this endpoint.
71 * @lock: State lock to protect contents of endpoint.
72 * @dir_in: Set to true if this endpoint is of the IN direction, which
73 * means that it is sending data to the Host.
74 * @index: The index for the endpoint registers.
75 * @name: The name array passed to the USB core.
76 * @halted: Set if the endpoint has been halted.
77 * @periodic: Set if this is a periodic ep, such as Interrupt
78 * @sent_zlp: Set if we've sent a zero-length packet.
79 * @total_data: The total number of data bytes done.
80 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
81 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
82 * @last_load: The offset of data for the last start of request.
83 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
85 * This is the driver's state for each registered enpoint, allowing it
86 * to keep track of transactions that need doing. Each endpoint has a
87 * lock to protect the state, to try and avoid using an overall lock
88 * for the host controller as much as possible.
90 * For periodic IN endpoints, we have fifo_size and fifo_load to try
91 * and keep track of the amount of data in the periodic FIFO for each
92 * of these as we don't have a status register that tells us how much
97 struct list_head queue;
98 struct s3c_hsotg *parent;
99 struct s3c_hsotg_req *req;
100 struct dentry *debugfs;
104 unsigned long total_data;
105 unsigned int size_loaded;
106 unsigned int last_load;
107 unsigned int fifo_load;
108 unsigned short fifo_size;
110 unsigned char dir_in;
113 unsigned int halted:1;
114 unsigned int periodic:1;
115 unsigned int sent_zlp:1;
120 #define S3C_HSOTG_EPS (8+1) /* limit to 9 for the moment */
123 * struct s3c_hsotg - driver state.
124 * @dev: The parent device supplied to the probe function
125 * @driver: USB gadget driver
126 * @plat: The platform specific configuration data.
127 * @regs: The memory area mapped for accessing registers.
128 * @regs_res: The resource that was allocated when claiming register space.
129 * @irq: The IRQ number we are using
130 * @debug_root: root directrory for debugfs.
131 * @debug_file: main status file for debugfs.
132 * @debug_fifo: FIFO status file for debugfs.
133 * @ep0_reply: Request used for ep0 reply.
134 * @ep0_buff: Buffer for EP0 reply data, if needed.
135 * @ctrl_buff: Buffer for EP0 control requests.
136 * @ctrl_req: Request for EP0 control packets.
137 * @eps: The endpoints being supplied to the gadget framework
141 struct usb_gadget_driver *driver;
142 struct s3c_hsotg_plat *plat;
145 struct resource *regs_res;
148 struct dentry *debug_root;
149 struct dentry *debug_file;
150 struct dentry *debug_fifo;
152 struct usb_request *ep0_reply;
153 struct usb_request *ctrl_req;
157 struct usb_gadget gadget;
158 struct s3c_hsotg_ep eps[];
162 * struct s3c_hsotg_req - data transfer request
163 * @req: The USB gadget request
164 * @queue: The list of requests for the endpoint this is queued for.
165 * @in_progress: Has already had size/packets written to core
166 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
168 struct s3c_hsotg_req {
169 struct usb_request req;
170 struct list_head queue;
171 unsigned char in_progress;
172 unsigned char mapped;
175 /* conversion functions */
176 static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
178 return container_of(req, struct s3c_hsotg_req, req);
181 static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
183 return container_of(ep, struct s3c_hsotg_ep, ep);
186 static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget)
188 return container_of(gadget, struct s3c_hsotg, gadget);
191 static inline void __orr32(void __iomem *ptr, u32 val)
193 writel(readl(ptr) | val, ptr);
196 static inline void __bic32(void __iomem *ptr, u32 val)
198 writel(readl(ptr) & ~val, ptr);
201 /* forward decleration of functions */
202 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg);
205 * using_dma - return the DMA status of the driver.
206 * @hsotg: The driver state.
208 * Return true if we're using DMA.
210 * Currently, we have the DMA support code worked into everywhere
211 * that needs it, but the AMBA DMA implementation in the hardware can
212 * only DMA from 32bit aligned addresses. This means that gadgets such
213 * as the CDC Ethernet cannot work as they often pass packets which are
216 * Unfortunately the choice to use DMA or not is global to the controller
217 * and seems to be only settable when the controller is being put through
218 * a core reset. This means we either need to fix the gadgets to take
219 * account of DMA alignment, or add bounce buffers (yuerk).
221 * Until this issue is sorted out, we always return 'false'.
223 static inline bool using_dma(struct s3c_hsotg *hsotg)
225 return false; /* support is not complete */
229 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
230 * @hsotg: The device state
231 * @ints: A bitmask of the interrupts to enable
233 static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
235 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
238 new_gsintmsk = gsintmsk | ints;
240 if (new_gsintmsk != gsintmsk) {
241 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
242 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
247 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
248 * @hsotg: The device state
249 * @ints: A bitmask of the interrupts to enable
251 static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
253 u32 gsintmsk = readl(hsotg->regs + S3C_GINTMSK);
256 new_gsintmsk = gsintmsk & ~ints;
258 if (new_gsintmsk != gsintmsk)
259 writel(new_gsintmsk, hsotg->regs + S3C_GINTMSK);
263 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
264 * @hsotg: The device state
265 * @ep: The endpoint index
266 * @dir_in: True if direction is in.
267 * @en: The enable value, true to enable
269 * Set or clear the mask for an individual endpoint's interrupt
272 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
273 unsigned int ep, unsigned int dir_in,
283 local_irq_save(flags);
284 daint = readl(hsotg->regs + S3C_DAINTMSK);
289 writel(daint, hsotg->regs + S3C_DAINTMSK);
290 local_irq_restore(flags);
294 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
295 * @hsotg: The device instance.
297 static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
299 /* the ryu 2.6.24 release ahs
300 writel(0x1C0, hsotg->regs + S3C_GRXFSIZ);
301 writel(S3C_GNPTXFSIZ_NPTxFStAddr(0x200) |
302 S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
303 hsotg->regs + S3C_GNPTXFSIZ);
306 /* set FIFO sizes to 2048/0x1C0 */
308 writel(2048, hsotg->regs + S3C_GRXFSIZ);
309 writel(S3C_GNPTXFSIZ_NPTxFStAddr(2048) |
310 S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
311 hsotg->regs + S3C_GNPTXFSIZ);
315 * @ep: USB endpoint to allocate request for.
316 * @flags: Allocation flags
318 * Allocate a new USB request structure appropriate for the specified endpoint
320 static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep,
323 struct s3c_hsotg_req *req;
325 req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
329 INIT_LIST_HEAD(&req->queue);
331 req->req.dma = DMA_ADDR_INVALID;
336 * is_ep_periodic - return true if the endpoint is in periodic mode.
337 * @hs_ep: The endpoint to query.
339 * Returns true if the endpoint is in periodic mode, meaning it is being
340 * used for an Interrupt or ISO transfer.
342 static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
344 return hs_ep->periodic;
348 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
349 * @hsotg: The device state.
350 * @hs_ep: The endpoint for the request
351 * @hs_req: The request being processed.
353 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
354 * of a request to ensure the buffer is ready for access by the caller.
356 static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
357 struct s3c_hsotg_ep *hs_ep,
358 struct s3c_hsotg_req *hs_req)
360 struct usb_request *req = &hs_req->req;
361 enum dma_data_direction dir;
363 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
365 /* ignore this if we're not moving any data */
366 if (hs_req->req.length == 0)
369 if (hs_req->mapped) {
370 /* we mapped this, so unmap and remove the dma */
372 dma_unmap_single(hsotg->dev, req->dma, req->length, dir);
374 req->dma = DMA_ADDR_INVALID;
377 dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir);
382 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
383 * @hsotg: The controller state.
384 * @hs_ep: The endpoint we're going to write for.
385 * @hs_req: The request to write data for.
387 * This is called when the TxFIFO has some space in it to hold a new
388 * transmission and we have something to give it. The actual setup of
389 * the data size is done elsewhere, so all we have to do is to actually
392 * The return value is zero if there is more space (or nothing was done)
393 * otherwise -ENOSPC is returned if the FIFO space was used up.
395 * This routine is only needed for PIO
397 static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
398 struct s3c_hsotg_ep *hs_ep,
399 struct s3c_hsotg_req *hs_req)
401 bool periodic = is_ep_periodic(hs_ep);
402 u32 gnptxsts = readl(hsotg->regs + S3C_GNPTXSTS);
403 int buf_pos = hs_req->req.actual;
404 int to_write = hs_ep->size_loaded;
409 to_write -= (buf_pos - hs_ep->last_load);
411 /* if there's nothing to write, get out early */
416 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
420 /* work out how much data was loaded so we can calculate
421 * how much data is left in the fifo. */
423 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
425 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
427 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
429 /* how much of the data has moved */
430 size_done = hs_ep->size_loaded - size_left;
432 /* how much data is left in the fifo */
433 can_write = hs_ep->fifo_load - size_done;
434 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
435 __func__, can_write);
437 can_write = hs_ep->fifo_size - can_write;
438 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
439 __func__, can_write);
441 if (can_write <= 0) {
442 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
446 if (S3C_GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
448 "%s: no queue slots available (0x%08x)\n",
451 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
455 can_write = S3C_GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
458 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
459 __func__, gnptxsts, can_write, to_write, hs_ep->ep.maxpacket);
461 /* limit to 512 bytes of data, it seems at least on the non-periodic
462 * FIFO, requests of >512 cause the endpoint to get stuck with a
463 * fragment of the end of the transfer in it.
468 /* see if we can write data */
470 if (to_write > can_write) {
471 to_write = can_write;
472 pkt_round = to_write % hs_ep->ep.maxpacket;
474 /* Not sure, but we probably shouldn't be writing partial
475 * packets into the FIFO, so round the write down to an
476 * exact number of packets.
478 * Note, we do not currently check to see if we can ever
479 * write a full packet or not to the FIFO.
483 to_write -= pkt_round;
485 /* enable correct FIFO interrupt to alert us when there
486 * is more room left. */
488 s3c_hsotg_en_gsint(hsotg,
489 periodic ? S3C_GINTSTS_PTxFEmp :
490 S3C_GINTSTS_NPTxFEmp);
493 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
494 to_write, hs_req->req.length, can_write, buf_pos);
499 hs_req->req.actual = buf_pos + to_write;
500 hs_ep->total_data += to_write;
503 hs_ep->fifo_load += to_write;
505 to_write = DIV_ROUND_UP(to_write, 4);
506 data = hs_req->req.buf + buf_pos;
508 writesl(hsotg->regs + S3C_EPFIFO(hs_ep->index), data, to_write);
510 return (to_write >= can_write) ? -ENOSPC : 0;
514 * get_ep_limit - get the maximum data legnth for this endpoint
515 * @hs_ep: The endpoint
517 * Return the maximum data that can be queued in one go on a given endpoint
518 * so that transfers that are too long can be split.
520 static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
522 int index = hs_ep->index;
527 maxsize = S3C_DxEPTSIZ_XferSize_LIMIT + 1;
528 maxpkt = S3C_DxEPTSIZ_PktCnt_LIMIT + 1;
531 /* maxsize = S3C_DIEPTSIZ0_XferSize_LIMIT + 1; */
533 maxpkt = S3C_DIEPTSIZ0_PktCnt_LIMIT + 1;
540 /* we made the constant loading easier above by using +1 */
544 /* constrain by packet count if maxpkts*pktsize is greater
545 * than the length register size. */
547 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
548 maxsize = maxpkt * hs_ep->ep.maxpacket;
554 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
555 * @hsotg: The controller state.
556 * @hs_ep: The endpoint to process a request for
557 * @hs_req: The request to start.
558 * @continuing: True if we are doing more for the current request.
560 * Start the given request running by setting the endpoint registers
561 * appropriately, and writing any data to the FIFOs.
563 static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
564 struct s3c_hsotg_ep *hs_ep,
565 struct s3c_hsotg_req *hs_req,
568 struct usb_request *ureq = &hs_req->req;
569 int index = hs_ep->index;
570 int dir_in = hs_ep->dir_in;
580 if (hs_ep->req && !continuing) {
581 dev_err(hsotg->dev, "%s: active request\n", __func__);
584 } else if (hs_ep->req != hs_req && continuing) {
586 "%s: continue different req\n", __func__);
592 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
593 epsize_reg = dir_in ? S3C_DIEPTSIZ(index) : S3C_DOEPTSIZ(index);
595 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
596 __func__, readl(hsotg->regs + epctrl_reg), index,
597 hs_ep->dir_in ? "in" : "out");
599 length = ureq->length - ureq->actual;
603 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
604 ureq->buf, length, ureq->dma,
605 ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
607 maxreq = get_ep_limit(hs_ep);
608 if (length > maxreq) {
609 int round = maxreq % hs_ep->ep.maxpacket;
611 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
612 __func__, length, maxreq, round);
614 /* round down to multiple of packets */
622 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
624 packets = 1; /* send one packet if length is zero. */
626 if (dir_in && index != 0)
627 epsize = S3C_DxEPTSIZ_MC(1);
631 if (index != 0 && ureq->zero) {
632 /* test for the packets being exactly right for the
635 if (length == (packets * hs_ep->ep.maxpacket))
639 epsize |= S3C_DxEPTSIZ_PktCnt(packets);
640 epsize |= S3C_DxEPTSIZ_XferSize(length);
642 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
643 __func__, packets, length, ureq->length, epsize, epsize_reg);
645 /* store the request as the current one we're doing */
648 /* write size / packets */
649 writel(epsize, hsotg->regs + epsize_reg);
651 ctrl = readl(hsotg->regs + epctrl_reg);
653 if (ctrl & S3C_DxEPCTL_Stall) {
654 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
656 /* not sure what we can do here, if it is EP0 then we should
657 * get this cleared once the endpoint has transmitted the
658 * STALL packet, otherwise it needs to be cleared by the
663 if (using_dma(hsotg)) {
664 unsigned int dma_reg;
666 /* write DMA address to control register, buffer already
667 * synced by s3c_hsotg_ep_queue(). */
669 dma_reg = dir_in ? S3C_DIEPDMA(index) : S3C_DOEPDMA(index);
670 writel(ureq->dma, hsotg->regs + dma_reg);
672 dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n",
673 __func__, ureq->dma, dma_reg);
676 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
677 ctrl |= S3C_DxEPCTL_USBActEp;
678 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
680 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
681 writel(ctrl, hsotg->regs + epctrl_reg);
683 /* set these, it seems that DMA support increments past the end
684 * of the packet buffer so we need to calculate the length from
685 * this information. */
686 hs_ep->size_loaded = length;
687 hs_ep->last_load = ureq->actual;
689 if (dir_in && !using_dma(hsotg)) {
690 /* set these anyway, we may need them for non-periodic in */
691 hs_ep->fifo_load = 0;
693 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
696 /* clear the INTknTXFEmpMsk when we start request, more as a aide
697 * to debugging to see what is going on. */
699 writel(S3C_DIEPMSK_INTknTXFEmpMsk,
700 hsotg->regs + S3C_DIEPINT(index));
702 /* Note, trying to clear the NAK here causes problems with transmit
703 * on the S3C6400 ending up with the TXFIFO becomming full. */
705 /* check ep is enabled */
706 if (!(readl(hsotg->regs + epctrl_reg) & S3C_DxEPCTL_EPEna))
708 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
709 index, readl(hsotg->regs + epctrl_reg));
711 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n",
712 __func__, readl(hsotg->regs + epctrl_reg));
716 * s3c_hsotg_map_dma - map the DMA memory being used for the request
717 * @hsotg: The device state.
718 * @hs_ep: The endpoint the request is on.
719 * @req: The request being processed.
721 * We've been asked to queue a request, so ensure that the memory buffer
722 * is correctly setup for DMA. If we've been passed an extant DMA address
723 * then ensure the buffer has been synced to memory. If our buffer has no
724 * DMA memory, then we map the memory and mark our request to allow us to
725 * cleanup on completion.
727 static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg,
728 struct s3c_hsotg_ep *hs_ep,
729 struct usb_request *req)
731 enum dma_data_direction dir;
732 struct s3c_hsotg_req *hs_req = our_req(req);
734 dir = hs_ep->dir_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
736 /* if the length is zero, ignore the DMA data */
737 if (hs_req->req.length == 0)
740 if (req->dma == DMA_ADDR_INVALID) {
743 dma = dma_map_single(hsotg->dev, req->buf, req->length, dir);
745 if (unlikely(dma_mapping_error(hsotg->dev, dma)))
749 dev_err(hsotg->dev, "%s: unaligned dma buffer\n",
752 dma_unmap_single(hsotg->dev, dma, req->length, dir);
759 dma_sync_single_for_cpu(hsotg->dev, req->dma, req->length, dir);
766 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
767 __func__, req->buf, req->length);
772 static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
775 struct s3c_hsotg_req *hs_req = our_req(req);
776 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
777 struct s3c_hsotg *hs = hs_ep->parent;
778 unsigned long irqflags;
781 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
782 ep->name, req, req->length, req->buf, req->no_interrupt,
783 req->zero, req->short_not_ok);
785 /* initialise status of the request */
786 INIT_LIST_HEAD(&hs_req->queue);
788 req->status = -EINPROGRESS;
790 /* if we're using DMA, sync the buffers as necessary */
792 int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
797 spin_lock_irqsave(&hs_ep->lock, irqflags);
799 first = list_empty(&hs_ep->queue);
800 list_add_tail(&hs_req->queue, &hs_ep->queue);
803 s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
805 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
810 static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
811 struct usb_request *req)
813 struct s3c_hsotg_req *hs_req = our_req(req);
819 * s3c_hsotg_complete_oursetup - setup completion callback
820 * @ep: The endpoint the request was on.
821 * @req: The request completed.
823 * Called on completion of any requests the driver itself
824 * submitted that need cleaning up.
826 static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
827 struct usb_request *req)
829 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
830 struct s3c_hsotg *hsotg = hs_ep->parent;
832 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
834 s3c_hsotg_ep_free_request(ep, req);
838 * ep_from_windex - convert control wIndex value to endpoint
839 * @hsotg: The driver state.
840 * @windex: The control request wIndex field (in host order).
842 * Convert the given wIndex into a pointer to an driver endpoint
843 * structure, or return NULL if it is not a valid endpoint.
845 static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
848 struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
849 int dir = (windex & USB_DIR_IN) ? 1 : 0;
850 int idx = windex & 0x7F;
855 if (idx > S3C_HSOTG_EPS)
858 if (idx && ep->dir_in != dir)
865 * s3c_hsotg_send_reply - send reply to control request
866 * @hsotg: The device state
868 * @buff: Buffer for request
869 * @length: Length of reply.
871 * Create a request and queue it on the given endpoint. This is useful as
872 * an internal method of sending replies to certain control requests, etc.
874 static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg,
875 struct s3c_hsotg_ep *ep,
879 struct usb_request *req;
882 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
884 req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
885 hsotg->ep0_reply = req;
887 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
891 req->buf = hsotg->ep0_buff;
892 req->length = length;
893 req->zero = 1; /* always do zero-length final transfer */
894 req->complete = s3c_hsotg_complete_oursetup;
897 memcpy(req->buf, buff, length);
901 ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
903 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
911 * s3c_hsotg_process_req_status - process request GET_STATUS
912 * @hsotg: The device state
913 * @ctrl: USB control request
915 static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg,
916 struct usb_ctrlrequest *ctrl)
918 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
919 struct s3c_hsotg_ep *ep;
923 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
926 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
930 switch (ctrl->bRequestType & USB_RECIP_MASK) {
931 case USB_RECIP_DEVICE:
932 reply = cpu_to_le16(0); /* bit 0 => self powered,
933 * bit 1 => remote wakeup */
936 case USB_RECIP_INTERFACE:
937 /* currently, the data result should be zero */
938 reply = cpu_to_le16(0);
941 case USB_RECIP_ENDPOINT:
942 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
946 reply = cpu_to_le16(ep->halted ? 1 : 0);
953 if (le16_to_cpu(ctrl->wLength) != 2)
956 ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
958 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
965 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
968 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
969 * @hsotg: The device state
970 * @ctrl: USB control request
972 static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
973 struct usb_ctrlrequest *ctrl)
975 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
976 struct s3c_hsotg_ep *ep;
978 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
979 __func__, set ? "SET" : "CLEAR");
981 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
982 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
984 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
985 __func__, le16_to_cpu(ctrl->wIndex));
989 switch (le16_to_cpu(ctrl->wValue)) {
990 case USB_ENDPOINT_HALT:
991 s3c_hsotg_ep_sethalt(&ep->ep, set);
998 return -ENOENT; /* currently only deal with endpoint */
1004 * s3c_hsotg_process_control - process a control request
1005 * @hsotg: The device state
1006 * @ctrl: The control request received
1008 * The controller has received the SETUP phase of a control request, and
1009 * needs to work out what to do next (and whether to pass it on to the
1012 static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1013 struct usb_ctrlrequest *ctrl)
1015 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1021 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1022 ctrl->bRequest, ctrl->bRequestType,
1023 ctrl->wValue, ctrl->wLength);
1025 /* record the direction of the request, for later use when enquing
1026 * packets onto EP0. */
1028 ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
1029 dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
1031 /* if we've no data with this request, then the last part of the
1032 * transaction is going to implicitly be IN. */
1033 if (ctrl->wLength == 0)
1036 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1037 switch (ctrl->bRequest) {
1038 case USB_REQ_SET_ADDRESS:
1039 dcfg = readl(hsotg->regs + S3C_DCFG);
1040 dcfg &= ~S3C_DCFG_DevAddr_MASK;
1041 dcfg |= ctrl->wValue << S3C_DCFG_DevAddr_SHIFT;
1042 writel(dcfg, hsotg->regs + S3C_DCFG);
1044 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1046 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1049 case USB_REQ_GET_STATUS:
1050 ret = s3c_hsotg_process_req_status(hsotg, ctrl);
1053 case USB_REQ_CLEAR_FEATURE:
1054 case USB_REQ_SET_FEATURE:
1055 ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
1060 /* as a fallback, try delivering it to the driver to deal with */
1062 if (ret == 0 && hsotg->driver) {
1063 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1065 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1070 /* need to generate zlp in reply or take data */
1071 /* todo - deal with any data we might be sent? */
1072 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1076 /* the request is either unhandlable, or is not formatted correctly
1077 * so respond with a STALL for the status stage to indicate failure.
1084 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1085 reg = (ep0->dir_in) ? S3C_DIEPCTL0 : S3C_DOEPCTL0;
1087 /* S3C_DxEPCTL_Stall will be cleared by EP once it has
1088 * taken effect, so no need to clear later. */
1090 ctrl = readl(hsotg->regs + reg);
1091 ctrl |= S3C_DxEPCTL_Stall;
1092 ctrl |= S3C_DxEPCTL_CNAK;
1093 writel(ctrl, hsotg->regs + reg);
1096 "writen DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1097 ctrl, reg, readl(hsotg->regs + reg));
1099 /* don't belive we need to anything more to get the EP
1100 * to reply with a STALL packet */
1104 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
1107 * s3c_hsotg_complete_setup - completion of a setup transfer
1108 * @ep: The endpoint the request was on.
1109 * @req: The request completed.
1111 * Called on completion of any requests the driver itself submitted for
1114 static void s3c_hsotg_complete_setup(struct usb_ep *ep,
1115 struct usb_request *req)
1117 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
1118 struct s3c_hsotg *hsotg = hs_ep->parent;
1120 if (req->status < 0) {
1121 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1125 if (req->actual == 0)
1126 s3c_hsotg_enqueue_setup(hsotg);
1128 s3c_hsotg_process_control(hsotg, req->buf);
1132 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1133 * @hsotg: The device state.
1135 * Enqueue a request on EP0 if necessary to received any SETUP packets
1136 * received from the host.
1138 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
1140 struct usb_request *req = hsotg->ctrl_req;
1141 struct s3c_hsotg_req *hs_req = our_req(req);
1144 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1148 req->buf = hsotg->ctrl_buff;
1149 req->complete = s3c_hsotg_complete_setup;
1151 if (!list_empty(&hs_req->queue)) {
1152 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1156 hsotg->eps[0].dir_in = 0;
1158 ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
1160 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1161 /* Don't think there's much we can do other than watch the
1167 * get_ep_head - return the first request on the endpoint
1168 * @hs_ep: The controller endpoint to get
1170 * Get the first request on the endpoint.
1172 static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
1174 if (list_empty(&hs_ep->queue))
1177 return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
1181 * s3c_hsotg_complete_request - complete a request given to us
1182 * @hsotg: The device state.
1183 * @hs_ep: The endpoint the request was on.
1184 * @hs_req: The request to complete.
1185 * @result: The result code (0 => Ok, otherwise errno)
1187 * The given request has finished, so call the necessary completion
1188 * if it has one and then look to see if we can start a new request
1191 * Note, expects the ep to already be locked as appropriate.
1193 static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1194 struct s3c_hsotg_ep *hs_ep,
1195 struct s3c_hsotg_req *hs_req,
1201 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1205 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1206 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1208 /* only replace the status if we've not already set an error
1209 * from a previous transaction */
1211 if (hs_req->req.status == -EINPROGRESS)
1212 hs_req->req.status = result;
1215 list_del_init(&hs_req->queue);
1217 if (using_dma(hsotg))
1218 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1220 /* call the complete request with the locks off, just in case the
1221 * request tries to queue more work for this endpoint. */
1223 if (hs_req->req.complete) {
1224 spin_unlock(&hs_ep->lock);
1225 hs_req->req.complete(&hs_ep->ep, &hs_req->req);
1226 spin_lock(&hs_ep->lock);
1229 /* Look to see if there is anything else to do. Note, the completion
1230 * of the previous request may have caused a new request to be started
1231 * so be careful when doing this. */
1233 if (!hs_ep->req && result >= 0) {
1234 restart = !list_empty(&hs_ep->queue);
1236 hs_req = get_ep_head(hs_ep);
1237 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1243 * s3c_hsotg_complete_request_lock - complete a request given to us (locked)
1244 * @hsotg: The device state.
1245 * @hs_ep: The endpoint the request was on.
1246 * @hs_req: The request to complete.
1247 * @result: The result code (0 => Ok, otherwise errno)
1249 * See s3c_hsotg_complete_request(), but called with the endpoint's
1252 static void s3c_hsotg_complete_request_lock(struct s3c_hsotg *hsotg,
1253 struct s3c_hsotg_ep *hs_ep,
1254 struct s3c_hsotg_req *hs_req,
1257 unsigned long flags;
1259 spin_lock_irqsave(&hs_ep->lock, flags);
1260 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1261 spin_unlock_irqrestore(&hs_ep->lock, flags);
1265 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1266 * @hsotg: The device state.
1267 * @ep_idx: The endpoint index for the data
1268 * @size: The size of data in the fifo, in bytes
1270 * The FIFO status shows there is data to read from the FIFO for a given
1271 * endpoint, so sort out whether we need to read the data into a request
1272 * that has been made for that endpoint.
1274 static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1276 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1277 struct s3c_hsotg_req *hs_req = hs_ep->req;
1278 void __iomem *fifo = hsotg->regs + S3C_EPFIFO(ep_idx);
1284 u32 epctl = readl(hsotg->regs + S3C_DOEPCTL(ep_idx));
1287 dev_warn(hsotg->dev,
1288 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1289 __func__, size, ep_idx, epctl);
1291 /* dump the data from the FIFO, we've nothing we can do */
1292 for (ptr = 0; ptr < size; ptr += 4)
1298 spin_lock(&hs_ep->lock);
1301 read_ptr = hs_req->req.actual;
1302 max_req = hs_req->req.length - read_ptr;
1304 if (to_read > max_req) {
1305 /* more data appeared than we where willing
1306 * to deal with in this request.
1309 /* currently we don't deal this */
1313 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1314 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1316 hs_ep->total_data += to_read;
1317 hs_req->req.actual += to_read;
1318 to_read = DIV_ROUND_UP(to_read, 4);
1320 /* note, we might over-write the buffer end by 3 bytes depending on
1321 * alignment of the data. */
1322 readsl(fifo, hs_req->req.buf + read_ptr, to_read);
1324 spin_unlock(&hs_ep->lock);
1328 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1329 * @hsotg: The device instance
1330 * @req: The request currently on this endpoint
1332 * Generate a zero-length IN packet request for terminating a SETUP
1335 * Note, since we don't write any data to the TxFIFO, then it is
1336 * currently belived that we do not need to wait for any space in
1339 static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1340 struct s3c_hsotg_req *req)
1345 dev_warn(hsotg->dev, "%s: no request?\n", __func__);
1349 if (req->req.length == 0) {
1350 hsotg->eps[0].sent_zlp = 1;
1351 s3c_hsotg_enqueue_setup(hsotg);
1355 hsotg->eps[0].dir_in = 1;
1356 hsotg->eps[0].sent_zlp = 1;
1358 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1360 /* issue a zero-sized packet to terminate this */
1361 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
1362 S3C_DxEPTSIZ_XferSize(0), hsotg->regs + S3C_DIEPTSIZ(0));
1364 ctrl = readl(hsotg->regs + S3C_DIEPCTL0);
1365 ctrl |= S3C_DxEPCTL_CNAK; /* clear NAK set by core */
1366 ctrl |= S3C_DxEPCTL_EPEna; /* ensure ep enabled */
1367 ctrl |= S3C_DxEPCTL_USBActEp;
1368 writel(ctrl, hsotg->regs + S3C_DIEPCTL0);
1372 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1373 * @hsotg: The device instance
1374 * @epnum: The endpoint received from
1375 * @was_setup: Set if processing a SetupDone event.
1377 * The RXFIFO has delivered an OutDone event, which means that the data
1378 * transfer for an OUT endpoint has been completed, either by a short
1379 * packet or by the finish of a transfer.
1381 static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1382 int epnum, bool was_setup)
1384 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1385 struct s3c_hsotg_req *hs_req = hs_ep->req;
1386 struct usb_request *req = &hs_req->req;
1390 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1394 if (using_dma(hsotg)) {
1395 u32 epsize = readl(hsotg->regs + S3C_DOEPTSIZ(epnum));
1399 /* Calculate the size of the transfer by checking how much
1400 * is left in the endpoint size register and then working it
1401 * out from the amount we loaded for the transfer.
1403 * We need to do this as DMA pointers are always 32bit aligned
1404 * so may overshoot/undershoot the transfer.
1407 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1409 size_done = hs_ep->size_loaded - size_left;
1410 size_done += hs_ep->last_load;
1412 req->actual = size_done;
1415 if (req->actual < req->length && req->short_not_ok) {
1416 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1417 __func__, req->actual, req->length);
1419 /* todo - what should we return here? there's no one else
1420 * even bothering to check the status. */
1424 if (!was_setup && req->complete != s3c_hsotg_complete_setup)
1425 s3c_hsotg_send_zlp(hsotg, hs_req);
1428 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, result);
1432 * s3c_hsotg_read_frameno - read current frame number
1433 * @hsotg: The device instance
1435 * Return the current frame number
1437 static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1441 dsts = readl(hsotg->regs + S3C_DSTS);
1442 dsts &= S3C_DSTS_SOFFN_MASK;
1443 dsts >>= S3C_DSTS_SOFFN_SHIFT;
1449 * s3c_hsotg_handle_rx - RX FIFO has data
1450 * @hsotg: The device instance
1452 * The IRQ handler has detected that the RX FIFO has some data in it
1453 * that requires processing, so find out what is in there and do the
1456 * The RXFIFO is a true FIFO, the packets comming out are still in packet
1457 * chunks, so if you have x packets received on an endpoint you'll get x
1458 * FIFO events delivered, each with a packet's worth of data in it.
1460 * When using DMA, we should not be processing events from the RXFIFO
1461 * as the actual data should be sent to the memory directly and we turn
1462 * on the completion interrupts to get notifications of transfer completion.
1464 static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1466 u32 grxstsr = readl(hsotg->regs + S3C_GRXSTSP);
1467 u32 epnum, status, size;
1469 WARN_ON(using_dma(hsotg));
1471 epnum = grxstsr & S3C_GRXSTS_EPNum_MASK;
1472 status = grxstsr & S3C_GRXSTS_PktSts_MASK;
1474 size = grxstsr & S3C_GRXSTS_ByteCnt_MASK;
1475 size >>= S3C_GRXSTS_ByteCnt_SHIFT;
1478 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1479 __func__, grxstsr, size, epnum);
1481 #define __status(x) ((x) >> S3C_GRXSTS_PktSts_SHIFT)
1483 switch (status >> S3C_GRXSTS_PktSts_SHIFT) {
1484 case __status(S3C_GRXSTS_PktSts_GlobalOutNAK):
1485 dev_dbg(hsotg->dev, "GlobalOutNAK\n");
1488 case __status(S3C_GRXSTS_PktSts_OutDone):
1489 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1490 s3c_hsotg_read_frameno(hsotg));
1492 if (!using_dma(hsotg))
1493 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1496 case __status(S3C_GRXSTS_PktSts_SetupDone):
1498 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1499 s3c_hsotg_read_frameno(hsotg),
1500 readl(hsotg->regs + S3C_DOEPCTL(0)));
1502 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1505 case __status(S3C_GRXSTS_PktSts_OutRX):
1506 s3c_hsotg_rx_data(hsotg, epnum, size);
1509 case __status(S3C_GRXSTS_PktSts_SetupRX):
1511 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1512 s3c_hsotg_read_frameno(hsotg),
1513 readl(hsotg->regs + S3C_DOEPCTL(0)));
1515 s3c_hsotg_rx_data(hsotg, epnum, size);
1519 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1522 s3c_hsotg_dump(hsotg);
1528 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1529 * @mps: The maximum packet size in bytes.
1531 static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1535 return S3C_D0EPCTL_MPS_64;
1537 return S3C_D0EPCTL_MPS_32;
1539 return S3C_D0EPCTL_MPS_16;
1541 return S3C_D0EPCTL_MPS_8;
1544 /* bad max packet size, warn and return invalid result */
1550 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1551 * @hsotg: The driver state.
1552 * @ep: The index number of the endpoint
1553 * @mps: The maximum packet size in bytes
1555 * Configure the maximum packet size for the given endpoint, updating
1556 * the hardware control registers to reflect this.
1558 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1559 unsigned int ep, unsigned int mps)
1561 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
1562 void __iomem *regs = hsotg->regs;
1567 /* EP0 is a special case */
1568 mpsval = s3c_hsotg_ep0_mps(mps);
1572 if (mps >= S3C_DxEPCTL_MPS_LIMIT+1)
1578 hs_ep->ep.maxpacket = mps;
1580 /* update both the in and out endpoint controldir_ registers, even
1581 * if one of the directions may not be in use. */
1583 reg = readl(regs + S3C_DIEPCTL(ep));
1584 reg &= ~S3C_DxEPCTL_MPS_MASK;
1586 writel(reg, regs + S3C_DIEPCTL(ep));
1588 reg = readl(regs + S3C_DOEPCTL(ep));
1589 reg &= ~S3C_DxEPCTL_MPS_MASK;
1591 writel(reg, regs + S3C_DOEPCTL(ep));
1596 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1601 * s3c_hsotg_trytx - check to see if anything needs transmitting
1602 * @hsotg: The driver state
1603 * @hs_ep: The driver endpoint to check.
1605 * Check to see if there is a request that has data to send, and if so
1606 * make an attempt to write data into the FIFO.
1608 static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg,
1609 struct s3c_hsotg_ep *hs_ep)
1611 struct s3c_hsotg_req *hs_req = hs_ep->req;
1613 if (!hs_ep->dir_in || !hs_req)
1616 if (hs_req->req.actual < hs_req->req.length) {
1617 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1619 return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1626 * s3c_hsotg_complete_in - complete IN transfer
1627 * @hsotg: The device state.
1628 * @hs_ep: The endpoint that has just completed.
1630 * An IN transfer has been completed, update the transfer's state and then
1631 * call the relevant completion routines.
1633 static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1634 struct s3c_hsotg_ep *hs_ep)
1636 struct s3c_hsotg_req *hs_req = hs_ep->req;
1637 u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
1638 int size_left, size_done;
1641 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1645 /* Calculate the size of the transfer by checking how much is left
1646 * in the endpoint size register and then working it out from
1647 * the amount we loaded for the transfer.
1649 * We do this even for DMA, as the transfer may have incremented
1650 * past the end of the buffer (DMA transfers are always 32bit
1654 size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
1656 size_done = hs_ep->size_loaded - size_left;
1657 size_done += hs_ep->last_load;
1659 if (hs_req->req.actual != size_done)
1660 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1661 __func__, hs_req->req.actual, size_done);
1663 hs_req->req.actual = size_done;
1665 /* if we did all of the transfer, and there is more data left
1666 * around, then try restarting the rest of the request */
1668 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1669 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1670 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1672 s3c_hsotg_complete_request_lock(hsotg, hs_ep, hs_req, 0);
1676 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1677 * @hsotg: The driver state
1678 * @idx: The index for the endpoint (0..15)
1679 * @dir_in: Set if this is an IN endpoint
1681 * Process and clear any interrupt pending for an individual endpoint
1683 static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1686 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
1687 u32 epint_reg = dir_in ? S3C_DIEPINT(idx) : S3C_DOEPINT(idx);
1688 u32 epctl_reg = dir_in ? S3C_DIEPCTL(idx) : S3C_DOEPCTL(idx);
1689 u32 epsiz_reg = dir_in ? S3C_DIEPTSIZ(idx) : S3C_DOEPTSIZ(idx);
1693 ints = readl(hsotg->regs + epint_reg);
1695 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1696 __func__, idx, dir_in ? "in" : "out", ints);
1698 if (ints & S3C_DxEPINT_XferCompl) {
1700 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1701 __func__, readl(hsotg->regs + epctl_reg),
1702 readl(hsotg->regs + epsiz_reg));
1704 /* we get OutDone from the FIFO, so we only need to look
1705 * at completing IN requests here */
1707 s3c_hsotg_complete_in(hsotg, hs_ep);
1710 s3c_hsotg_enqueue_setup(hsotg);
1711 } else if (using_dma(hsotg)) {
1712 /* We're using DMA, we need to fire an OutDone here
1713 * as we ignore the RXFIFO. */
1715 s3c_hsotg_handle_outdone(hsotg, idx, false);
1718 clear |= S3C_DxEPINT_XferCompl;
1721 if (ints & S3C_DxEPINT_EPDisbld) {
1722 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1723 clear |= S3C_DxEPINT_EPDisbld;
1726 if (ints & S3C_DxEPINT_AHBErr) {
1727 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
1728 clear |= S3C_DxEPINT_AHBErr;
1731 if (ints & S3C_DxEPINT_Setup) { /* Setup or Timeout */
1732 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
1734 if (using_dma(hsotg) && idx == 0) {
1735 /* this is the notification we've received a
1736 * setup packet. In non-DMA mode we'd get this
1737 * from the RXFIFO, instead we need to process
1738 * the setup here. */
1743 s3c_hsotg_handle_outdone(hsotg, 0, true);
1746 clear |= S3C_DxEPINT_Setup;
1749 if (ints & S3C_DxEPINT_Back2BackSetup) {
1750 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
1751 clear |= S3C_DxEPINT_Back2BackSetup;
1755 /* not sure if this is important, but we'll clear it anyway
1757 if (ints & S3C_DIEPMSK_INTknTXFEmpMsk) {
1758 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
1760 clear |= S3C_DIEPMSK_INTknTXFEmpMsk;
1763 /* this probably means something bad is happening */
1764 if (ints & S3C_DIEPMSK_INTknEPMisMsk) {
1765 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
1767 clear |= S3C_DIEPMSK_INTknEPMisMsk;
1771 writel(clear, hsotg->regs + epint_reg);
1775 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
1776 * @hsotg: The device state.
1778 * Handle updating the device settings after the enumeration phase has
1781 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
1783 u32 dsts = readl(hsotg->regs + S3C_DSTS);
1784 int ep0_mps = 0, ep_mps;
1786 /* This should signal the finish of the enumeration phase
1787 * of the USB handshaking, so we should now know what rate
1788 * we connected at. */
1790 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
1792 /* note, since we're limited by the size of transfer on EP0, and
1793 * it seems IN transfers must be a even number of packets we do
1794 * not advertise a 64byte MPS on EP0. */
1796 /* catch both EnumSpd_FS and EnumSpd_FS48 */
1797 switch (dsts & S3C_DSTS_EnumSpd_MASK) {
1798 case S3C_DSTS_EnumSpd_FS:
1799 case S3C_DSTS_EnumSpd_FS48:
1800 hsotg->gadget.speed = USB_SPEED_FULL;
1801 dev_info(hsotg->dev, "new device is full-speed\n");
1803 ep0_mps = EP0_MPS_LIMIT;
1807 case S3C_DSTS_EnumSpd_HS:
1808 dev_info(hsotg->dev, "new device is high-speed\n");
1809 hsotg->gadget.speed = USB_SPEED_HIGH;
1811 ep0_mps = EP0_MPS_LIMIT;
1815 case S3C_DSTS_EnumSpd_LS:
1816 hsotg->gadget.speed = USB_SPEED_LOW;
1817 dev_info(hsotg->dev, "new device is low-speed\n");
1819 /* note, we don't actually support LS in this driver at the
1820 * moment, and the documentation seems to imply that it isn't
1821 * supported by the PHYs on some of the devices.
1826 /* we should now know the maximum packet size for an
1827 * endpoint, so set the endpoints to a default value. */
1831 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
1832 for (i = 1; i < S3C_HSOTG_EPS; i++)
1833 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
1836 /* ensure after enumeration our EP0 is active */
1838 s3c_hsotg_enqueue_setup(hsotg);
1840 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
1841 readl(hsotg->regs + S3C_DIEPCTL0),
1842 readl(hsotg->regs + S3C_DOEPCTL0));
1846 * kill_all_requests - remove all requests from the endpoint's queue
1847 * @hsotg: The device state.
1848 * @ep: The endpoint the requests may be on.
1849 * @result: The result code to use.
1850 * @force: Force removal of any current requests
1852 * Go through the requests on the given endpoint and mark them
1853 * completed with the given result code.
1855 static void kill_all_requests(struct s3c_hsotg *hsotg,
1856 struct s3c_hsotg_ep *ep,
1857 int result, bool force)
1859 struct s3c_hsotg_req *req, *treq;
1860 unsigned long flags;
1862 spin_lock_irqsave(&ep->lock, flags);
1864 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
1865 /* currently, we can't do much about an already
1866 * running request on an in endpoint */
1868 if (ep->req == req && ep->dir_in && !force)
1871 s3c_hsotg_complete_request(hsotg, ep, req,
1875 spin_unlock_irqrestore(&ep->lock, flags);
1878 #define call_gadget(_hs, _entry) \
1879 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
1880 (_hs)->driver && (_hs)->driver->_entry) \
1881 (_hs)->driver->_entry(&(_hs)->gadget);
1884 * s3c_hsotg_disconnect_irq - disconnect irq service
1885 * @hsotg: The device state.
1887 * A disconnect IRQ has been received, meaning that the host has
1888 * lost contact with the bus. Remove all current transactions
1889 * and signal the gadget driver that this has happened.
1891 static void s3c_hsotg_disconnect_irq(struct s3c_hsotg *hsotg)
1895 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
1896 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
1898 call_gadget(hsotg, disconnect);
1902 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
1903 * @hsotg: The device state:
1904 * @periodic: True if this is a periodic FIFO interrupt
1906 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
1908 struct s3c_hsotg_ep *ep;
1911 /* look through for any more data to transmit */
1913 for (epno = 0; epno < S3C_HSOTG_EPS; epno++) {
1914 ep = &hsotg->eps[epno];
1919 if ((periodic && !ep->periodic) ||
1920 (!periodic && ep->periodic))
1923 ret = s3c_hsotg_trytx(hsotg, ep);
1929 static struct s3c_hsotg *our_hsotg;
1931 /* IRQ flags which will trigger a retry around the IRQ loop */
1932 #define IRQ_RETRY_MASK (S3C_GINTSTS_NPTxFEmp | \
1933 S3C_GINTSTS_PTxFEmp | \
1937 * s3c_hsotg_irq - handle device interrupt
1938 * @irq: The IRQ number triggered
1939 * @pw: The pw value when registered the handler.
1941 static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
1943 struct s3c_hsotg *hsotg = pw;
1944 int retry_count = 8;
1949 gintsts = readl(hsotg->regs + S3C_GINTSTS);
1950 gintmsk = readl(hsotg->regs + S3C_GINTMSK);
1952 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
1953 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
1957 if (gintsts & S3C_GINTSTS_OTGInt) {
1958 u32 otgint = readl(hsotg->regs + S3C_GOTGINT);
1960 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
1962 writel(otgint, hsotg->regs + S3C_GOTGINT);
1963 writel(S3C_GINTSTS_OTGInt, hsotg->regs + S3C_GINTSTS);
1966 if (gintsts & S3C_GINTSTS_DisconnInt) {
1967 dev_dbg(hsotg->dev, "%s: DisconnInt\n", __func__);
1968 writel(S3C_GINTSTS_DisconnInt, hsotg->regs + S3C_GINTSTS);
1970 s3c_hsotg_disconnect_irq(hsotg);
1973 if (gintsts & S3C_GINTSTS_SessReqInt) {
1974 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
1975 writel(S3C_GINTSTS_SessReqInt, hsotg->regs + S3C_GINTSTS);
1978 if (gintsts & S3C_GINTSTS_EnumDone) {
1979 s3c_hsotg_irq_enumdone(hsotg);
1980 writel(S3C_GINTSTS_EnumDone, hsotg->regs + S3C_GINTSTS);
1983 if (gintsts & S3C_GINTSTS_ConIDStsChng) {
1984 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
1985 readl(hsotg->regs + S3C_DSTS),
1986 readl(hsotg->regs + S3C_GOTGCTL));
1988 writel(S3C_GINTSTS_ConIDStsChng, hsotg->regs + S3C_GINTSTS);
1991 if (gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt)) {
1992 u32 daint = readl(hsotg->regs + S3C_DAINT);
1993 u32 daint_out = daint >> S3C_DAINT_OutEP_SHIFT;
1994 u32 daint_in = daint & ~(daint_out << S3C_DAINT_OutEP_SHIFT);
1997 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
1999 for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
2001 s3c_hsotg_epint(hsotg, ep, 0);
2004 for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
2006 s3c_hsotg_epint(hsotg, ep, 1);
2009 writel(daint, hsotg->regs + S3C_DAINT);
2010 writel(gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt),
2011 hsotg->regs + S3C_GINTSTS);
2014 if (gintsts & S3C_GINTSTS_USBRst) {
2015 dev_info(hsotg->dev, "%s: USBRst\n", __func__);
2016 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2017 readl(hsotg->regs + S3C_GNPTXSTS));
2019 kill_all_requests(hsotg, &hsotg->eps[0], -ECONNRESET, true);
2021 /* it seems after a reset we can end up with a situation
2022 * where the TXFIFO still has data in it... try flushing
2023 * it to remove anything that may still be in it.
2027 writel(S3C_GRSTCTL_TxFNum(0) | S3C_GRSTCTL_TxFFlsh,
2028 hsotg->regs + S3C_GRSTCTL);
2030 dev_info(hsotg->dev, "GNPTXSTS=%08x\n",
2031 readl(hsotg->regs + S3C_GNPTXSTS));
2034 s3c_hsotg_enqueue_setup(hsotg);
2036 writel(S3C_GINTSTS_USBRst, hsotg->regs + S3C_GINTSTS);
2039 /* check both FIFOs */
2041 if (gintsts & S3C_GINTSTS_NPTxFEmp) {
2042 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2044 /* Disable the interrupt to stop it happening again
2045 * unless one of these endpoint routines decides that
2046 * it needs re-enabling */
2048 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
2049 s3c_hsotg_irq_fifoempty(hsotg, false);
2051 writel(S3C_GINTSTS_NPTxFEmp, hsotg->regs + S3C_GINTSTS);
2054 if (gintsts & S3C_GINTSTS_PTxFEmp) {
2055 dev_dbg(hsotg->dev, "PTxFEmp\n");
2057 /* See note in S3C_GINTSTS_NPTxFEmp */
2059 s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
2060 s3c_hsotg_irq_fifoempty(hsotg, true);
2062 writel(S3C_GINTSTS_PTxFEmp, hsotg->regs + S3C_GINTSTS);
2065 if (gintsts & S3C_GINTSTS_RxFLvl) {
2066 /* note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2067 * we need to retry s3c_hsotg_handle_rx if this is still
2070 s3c_hsotg_handle_rx(hsotg);
2071 writel(S3C_GINTSTS_RxFLvl, hsotg->regs + S3C_GINTSTS);
2074 if (gintsts & S3C_GINTSTS_ModeMis) {
2075 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
2076 writel(S3C_GINTSTS_ModeMis, hsotg->regs + S3C_GINTSTS);
2079 if (gintsts & S3C_GINTSTS_USBSusp) {
2080 dev_info(hsotg->dev, "S3C_GINTSTS_USBSusp\n");
2081 writel(S3C_GINTSTS_USBSusp, hsotg->regs + S3C_GINTSTS);
2083 call_gadget(hsotg, suspend);
2086 if (gintsts & S3C_GINTSTS_WkUpInt) {
2087 dev_info(hsotg->dev, "S3C_GINTSTS_WkUpIn\n");
2088 writel(S3C_GINTSTS_WkUpInt, hsotg->regs + S3C_GINTSTS);
2090 call_gadget(hsotg, resume);
2093 if (gintsts & S3C_GINTSTS_ErlySusp) {
2094 dev_dbg(hsotg->dev, "S3C_GINTSTS_ErlySusp\n");
2095 writel(S3C_GINTSTS_ErlySusp, hsotg->regs + S3C_GINTSTS);
2098 /* these next two seem to crop-up occasionally causing the core
2099 * to shutdown the USB transfer, so try clearing them and logging
2102 if (gintsts & S3C_GINTSTS_GOUTNakEff) {
2103 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2105 s3c_hsotg_dump(hsotg);
2107 writel(S3C_DCTL_CGOUTNak, hsotg->regs + S3C_DCTL);
2108 writel(S3C_GINTSTS_GOUTNakEff, hsotg->regs + S3C_GINTSTS);
2111 if (gintsts & S3C_GINTSTS_GINNakEff) {
2112 dev_info(hsotg->dev, "GINNakEff triggered\n");
2114 s3c_hsotg_dump(hsotg);
2116 writel(S3C_DCTL_CGNPInNAK, hsotg->regs + S3C_DCTL);
2117 writel(S3C_GINTSTS_GINNakEff, hsotg->regs + S3C_GINTSTS);
2120 /* if we've had fifo events, we should try and go around the
2121 * loop again to see if there's any point in returning yet. */
2123 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2130 * s3c_hsotg_ep_enable - enable the given endpoint
2131 * @ep: The USB endpint to configure
2132 * @desc: The USB endpoint descriptor to configure with.
2134 * This is called from the USB gadget code's usb_ep_enable().
2136 static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2137 const struct usb_endpoint_descriptor *desc)
2139 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2140 struct s3c_hsotg *hsotg = hs_ep->parent;
2141 unsigned long flags;
2142 int index = hs_ep->index;
2149 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2150 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2151 desc->wMaxPacketSize, desc->bInterval);
2153 /* not to be called for EP0 */
2154 WARN_ON(index == 0);
2156 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2157 if (dir_in != hs_ep->dir_in) {
2158 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2162 mps = le16_to_cpu(desc->wMaxPacketSize);
2164 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2166 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2167 epctrl = readl(hsotg->regs + epctrl_reg);
2169 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2170 __func__, epctrl, epctrl_reg);
2172 spin_lock_irqsave(&hs_ep->lock, flags);
2174 epctrl &= ~(S3C_DxEPCTL_EPType_MASK | S3C_DxEPCTL_MPS_MASK);
2175 epctrl |= S3C_DxEPCTL_MPS(mps);
2177 /* mark the endpoint as active, otherwise the core may ignore
2178 * transactions entirely for this endpoint */
2179 epctrl |= S3C_DxEPCTL_USBActEp;
2181 /* set the NAK status on the endpoint, otherwise we might try and
2182 * do something with data that we've yet got a request to process
2183 * since the RXFIFO will take data for an endpoint even if the
2184 * size register hasn't been set.
2187 epctrl |= S3C_DxEPCTL_SNAK;
2189 /* update the endpoint state */
2190 hs_ep->ep.maxpacket = mps;
2192 /* default, set to non-periodic */
2193 hs_ep->periodic = 0;
2195 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2196 case USB_ENDPOINT_XFER_ISOC:
2197 dev_err(hsotg->dev, "no current ISOC support\n");
2200 case USB_ENDPOINT_XFER_BULK:
2201 epctrl |= S3C_DxEPCTL_EPType_Bulk;
2204 case USB_ENDPOINT_XFER_INT:
2206 /* Allocate our TxFNum by simply using the index
2207 * of the endpoint for the moment. We could do
2208 * something better if the host indicates how
2209 * many FIFOs we are expecting to use. */
2211 hs_ep->periodic = 1;
2212 epctrl |= S3C_DxEPCTL_TxFNum(index);
2215 epctrl |= S3C_DxEPCTL_EPType_Intterupt;
2218 case USB_ENDPOINT_XFER_CONTROL:
2219 epctrl |= S3C_DxEPCTL_EPType_Control;
2223 /* for non control endpoints, set PID to D0 */
2225 epctrl |= S3C_DxEPCTL_SetD0PID;
2227 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2230 writel(epctrl, hsotg->regs + epctrl_reg);
2231 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2232 __func__, readl(hsotg->regs + epctrl_reg));
2234 /* enable the endpoint interrupt */
2235 s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2237 spin_unlock_irqrestore(&hs_ep->lock, flags);
2241 static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2243 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2244 struct s3c_hsotg *hsotg = hs_ep->parent;
2245 int dir_in = hs_ep->dir_in;
2246 int index = hs_ep->index;
2247 unsigned long flags;
2251 dev_info(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2253 if (ep == &hsotg->eps[0].ep) {
2254 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2258 epctrl_reg = dir_in ? S3C_DIEPCTL(index) : S3C_DOEPCTL(index);
2260 /* terminate all requests with shutdown */
2261 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
2263 spin_lock_irqsave(&hs_ep->lock, flags);
2265 ctrl = readl(hsotg->regs + epctrl_reg);
2266 ctrl &= ~S3C_DxEPCTL_EPEna;
2267 ctrl &= ~S3C_DxEPCTL_USBActEp;
2268 ctrl |= S3C_DxEPCTL_SNAK;
2270 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2271 writel(ctrl, hsotg->regs + epctrl_reg);
2273 /* disable endpoint interrupts */
2274 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2276 spin_unlock_irqrestore(&hs_ep->lock, flags);
2281 * on_list - check request is on the given endpoint
2282 * @ep: The endpoint to check.
2283 * @test: The request to test if it is on the endpoint.
2285 static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2287 struct s3c_hsotg_req *req, *treq;
2289 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2297 static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2299 struct s3c_hsotg_req *hs_req = our_req(req);
2300 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2301 struct s3c_hsotg *hs = hs_ep->parent;
2302 unsigned long flags;
2304 dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2306 if (hs_req == hs_ep->req) {
2307 dev_dbg(hs->dev, "%s: already in progress\n", __func__);
2308 return -EINPROGRESS;
2311 spin_lock_irqsave(&hs_ep->lock, flags);
2313 if (!on_list(hs_ep, hs_req)) {
2314 spin_unlock_irqrestore(&hs_ep->lock, flags);
2318 s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2319 spin_unlock_irqrestore(&hs_ep->lock, flags);
2324 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2326 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2327 struct s3c_hsotg *hs = hs_ep->parent;
2328 int index = hs_ep->index;
2329 unsigned long irqflags;
2333 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2335 spin_lock_irqsave(&hs_ep->lock, irqflags);
2337 /* write both IN and OUT control registers */
2339 epreg = S3C_DIEPCTL(index);
2340 epctl = readl(hs->regs + epreg);
2343 epctl |= S3C_DxEPCTL_Stall;
2345 epctl &= ~S3C_DxEPCTL_Stall;
2347 writel(epctl, hs->regs + epreg);
2349 epreg = S3C_DOEPCTL(index);
2350 epctl = readl(hs->regs + epreg);
2353 epctl |= S3C_DxEPCTL_Stall;
2355 epctl &= ~S3C_DxEPCTL_Stall;
2357 writel(epctl, hs->regs + epreg);
2359 spin_unlock_irqrestore(&hs_ep->lock, irqflags);
2364 static struct usb_ep_ops s3c_hsotg_ep_ops = {
2365 .enable = s3c_hsotg_ep_enable,
2366 .disable = s3c_hsotg_ep_disable,
2367 .alloc_request = s3c_hsotg_ep_alloc_request,
2368 .free_request = s3c_hsotg_ep_free_request,
2369 .queue = s3c_hsotg_ep_queue,
2370 .dequeue = s3c_hsotg_ep_dequeue,
2371 .set_halt = s3c_hsotg_ep_sethalt,
2372 /* note, don't belive we have any call for the fifo routines */
2376 * s3c_hsotg_corereset - issue softreset to the core
2377 * @hsotg: The device state
2379 * Issue a soft reset to the core, and await the core finishing it.
2381 static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2386 dev_dbg(hsotg->dev, "resetting core\n");
2388 /* issue soft reset */
2389 writel(S3C_GRSTCTL_CSftRst, hsotg->regs + S3C_GRSTCTL);
2393 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2394 } while (!(grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0);
2396 if (!(grstctl & S3C_GRSTCTL_CSftRst)) {
2397 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2404 u32 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
2406 if (timeout-- < 0) {
2407 dev_info(hsotg->dev,
2408 "%s: reset failed, GRSTCTL=%08x\n",
2413 if (grstctl & S3C_GRSTCTL_CSftRst)
2416 if (!(grstctl & S3C_GRSTCTL_AHBIdle))
2419 break; /* reset done */
2422 dev_dbg(hsotg->dev, "reset successful\n");
2426 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
2428 struct s3c_hsotg *hsotg = our_hsotg;
2432 printk(KERN_ERR "%s: called with no device\n", __func__);
2437 dev_err(hsotg->dev, "%s: no driver\n", __func__);
2441 if (driver->speed != USB_SPEED_HIGH &&
2442 driver->speed != USB_SPEED_FULL) {
2443 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
2446 if (!driver->bind || !driver->setup) {
2447 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
2451 WARN_ON(hsotg->driver);
2453 driver->driver.bus = NULL;
2454 hsotg->driver = driver;
2455 hsotg->gadget.dev.driver = &driver->driver;
2456 hsotg->gadget.dev.dma_mask = hsotg->dev->dma_mask;
2457 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2459 ret = device_add(&hsotg->gadget.dev);
2461 dev_err(hsotg->dev, "failed to register gadget device\n");
2465 ret = driver->bind(&hsotg->gadget);
2467 dev_err(hsotg->dev, "failed bind %s\n", driver->driver.name);
2469 hsotg->gadget.dev.driver = NULL;
2470 hsotg->driver = NULL;
2474 /* we must now enable ep0 ready for host detection and then
2475 * set configuration. */
2477 s3c_hsotg_corereset(hsotg);
2479 /* set the PLL on, remove the HNP/SRP and set the PHY */
2480 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) |
2481 (0x5 << 10), hsotg->regs + S3C_GUSBCFG);
2483 /* looks like soft-reset changes state of FIFOs */
2484 s3c_hsotg_init_fifo(hsotg);
2486 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2488 writel(1 << 18 | S3C_DCFG_DevSpd_HS, hsotg->regs + S3C_DCFG);
2490 writel(S3C_GINTSTS_DisconnInt | S3C_GINTSTS_SessReqInt |
2491 S3C_GINTSTS_ConIDStsChng | S3C_GINTSTS_USBRst |
2492 S3C_GINTSTS_EnumDone | S3C_GINTSTS_OTGInt |
2493 S3C_GINTSTS_USBSusp | S3C_GINTSTS_WkUpInt |
2494 S3C_GINTSTS_GOUTNakEff | S3C_GINTSTS_GINNakEff |
2495 S3C_GINTSTS_ErlySusp,
2496 hsotg->regs + S3C_GINTMSK);
2498 if (using_dma(hsotg))
2499 writel(S3C_GAHBCFG_GlblIntrEn | S3C_GAHBCFG_DMAEn |
2500 S3C_GAHBCFG_HBstLen_Incr4,
2501 hsotg->regs + S3C_GAHBCFG);
2503 writel(S3C_GAHBCFG_GlblIntrEn, hsotg->regs + S3C_GAHBCFG);
2505 /* Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2506 * up being flooded with interrupts if the host is polling the
2507 * endpoint to try and read data. */
2509 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2510 S3C_DIEPMSK_INTknEPMisMsk |
2511 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
2512 hsotg->regs + S3C_DIEPMSK);
2514 /* don't need XferCompl, we get that from RXFIFO in slave mode. In
2515 * DMA mode we may need this. */
2516 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2517 S3C_DOEPMSK_EPDisbldMsk |
2518 (using_dma(hsotg) ? (S3C_DIEPMSK_XferComplMsk |
2519 S3C_DIEPMSK_TimeOUTMsk) : 0),
2520 hsotg->regs + S3C_DOEPMSK);
2522 writel(0, hsotg->regs + S3C_DAINTMSK);
2524 dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2525 readl(hsotg->regs + S3C_DIEPCTL0),
2526 readl(hsotg->regs + S3C_DOEPCTL0));
2528 /* enable in and out endpoint interrupts */
2529 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt);
2531 /* Enable the RXFIFO when in slave mode, as this is how we collect
2532 * the data. In DMA mode, we get events from the FIFO but also
2533 * things we cannot process, so do not use it. */
2534 if (!using_dma(hsotg))
2535 s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_RxFLvl);
2537 /* Enable interrupts for EP0 in and out */
2538 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2539 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2541 __orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2542 udelay(10); /* see openiboot */
2543 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
2545 dev_info(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + S3C_DCTL));
2547 /* S3C_DxEPCTL_USBActEp says RO in manual, but seems to be set by
2548 writing to the EPCTL register.. */
2550 /* set to read 1 8byte packet */
2551 writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
2552 S3C_DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
2554 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2555 S3C_DxEPCTL_CNAK | S3C_DxEPCTL_EPEna |
2556 S3C_DxEPCTL_USBActEp,
2557 hsotg->regs + S3C_DOEPCTL0);
2559 /* enable, but don't activate EP0in */
2560 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2561 S3C_DxEPCTL_USBActEp, hsotg->regs + S3C_DIEPCTL0);
2563 s3c_hsotg_enqueue_setup(hsotg);
2565 dev_info(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2566 readl(hsotg->regs + S3C_DIEPCTL0),
2567 readl(hsotg->regs + S3C_DOEPCTL0));
2569 /* clear global NAKs */
2570 writel(S3C_DCTL_CGOUTNak | S3C_DCTL_CGNPInNAK,
2571 hsotg->regs + S3C_DCTL);
2573 /* remove the soft-disconnect and let's go */
2574 __bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
2576 /* report to the user, and return */
2578 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
2582 hsotg->driver = NULL;
2583 hsotg->gadget.dev.driver = NULL;
2586 EXPORT_SYMBOL(usb_gadget_register_driver);
2588 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2590 struct s3c_hsotg *hsotg = our_hsotg;
2596 if (!driver || driver != hsotg->driver || !driver->unbind)
2599 /* all endpoints should be shutdown */
2600 for (ep = 0; ep < S3C_HSOTG_EPS; ep++)
2601 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
2603 call_gadget(hsotg, disconnect);
2605 driver->unbind(&hsotg->gadget);
2606 hsotg->driver = NULL;
2607 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
2609 device_del(&hsotg->gadget.dev);
2611 dev_info(hsotg->dev, "unregistered gadget driver '%s'\n",
2612 driver->driver.name);
2616 EXPORT_SYMBOL(usb_gadget_unregister_driver);
2618 static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
2620 return s3c_hsotg_read_frameno(to_hsotg(gadget));
2623 static struct usb_gadget_ops s3c_hsotg_gadget_ops = {
2624 .get_frame = s3c_hsotg_gadget_getframe,
2628 * s3c_hsotg_initep - initialise a single endpoint
2629 * @hsotg: The device state.
2630 * @hs_ep: The endpoint to be initialised.
2631 * @epnum: The endpoint number
2633 * Initialise the given endpoint (as part of the probe and device state
2634 * creation) to give to the gadget driver. Setup the endpoint name, any
2635 * direction information and other state that may be required.
2637 static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg,
2638 struct s3c_hsotg_ep *hs_ep,
2646 else if ((epnum % 2) == 0) {
2653 hs_ep->index = epnum;
2655 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
2657 INIT_LIST_HEAD(&hs_ep->queue);
2658 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
2660 spin_lock_init(&hs_ep->lock);
2662 /* add to the list of endpoints known by the gadget driver */
2664 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
2666 hs_ep->parent = hsotg;
2667 hs_ep->ep.name = hs_ep->name;
2668 hs_ep->ep.maxpacket = epnum ? 512 : EP0_MPS_LIMIT;
2669 hs_ep->ep.ops = &s3c_hsotg_ep_ops;
2671 /* Read the FIFO size for the Periodic TX FIFO, even if we're
2672 * an OUT endpoint, we may as well do this if in future the
2673 * code is changed to make each endpoint's direction changeable.
2676 ptxfifo = readl(hsotg->regs + S3C_DPTXFSIZn(epnum));
2677 hs_ep->fifo_size = S3C_DPTXFSIZn_DPTxFSize_GET(ptxfifo);
2679 /* if we're using dma, we need to set the next-endpoint pointer
2680 * to be something valid.
2683 if (using_dma(hsotg)) {
2684 u32 next = S3C_DxEPCTL_NextEp((epnum + 1) % 15);
2685 writel(next, hsotg->regs + S3C_DIEPCTL(epnum));
2686 writel(next, hsotg->regs + S3C_DOEPCTL(epnum));
2691 * s3c_hsotg_otgreset - reset the OtG phy block
2692 * @hsotg: The host state.
2694 * Power up the phy, set the basic configuration and start the PHY.
2696 static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)
2700 writel(0, S3C_PHYPWR);
2703 osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0;
2705 writel(osc | 0x10, S3C_PHYCLK);
2707 /* issue a full set of resets to the otg and core */
2709 writel(S3C_RSTCON_PHY, S3C_RSTCON);
2710 udelay(20); /* at-least 10uS */
2711 writel(0, S3C_RSTCON);
2715 static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2717 /* unmask subset of endpoint interrupts */
2719 writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
2720 S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
2721 hsotg->regs + S3C_DIEPMSK);
2723 writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
2724 S3C_DOEPMSK_EPDisbldMsk | S3C_DOEPMSK_XferComplMsk,
2725 hsotg->regs + S3C_DOEPMSK);
2727 writel(0, hsotg->regs + S3C_DAINTMSK);
2730 /* post global nak until we're ready */
2731 writel(S3C_DCTL_SGNPInNAK | S3C_DCTL_SGOUTNak,
2732 hsotg->regs + S3C_DCTL);
2737 dev_info(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2738 readl(hsotg->regs + S3C_GRXFSIZ),
2739 readl(hsotg->regs + S3C_GNPTXFSIZ));
2741 s3c_hsotg_init_fifo(hsotg);
2743 /* set the PLL on, remove the HNP/SRP and set the PHY */
2744 writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) | (0x5 << 10),
2745 hsotg->regs + S3C_GUSBCFG);
2747 writel(using_dma(hsotg) ? S3C_GAHBCFG_DMAEn : 0x0,
2748 hsotg->regs + S3C_GAHBCFG);
2751 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
2753 struct device *dev = hsotg->dev;
2754 void __iomem *regs = hsotg->regs;
2758 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
2759 readl(regs + S3C_DCFG), readl(regs + S3C_DCTL),
2760 readl(regs + S3C_DIEPMSK));
2762 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
2763 readl(regs + S3C_GAHBCFG), readl(regs + 0x44));
2765 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2766 readl(regs + S3C_GRXFSIZ), readl(regs + S3C_GNPTXFSIZ));
2768 /* show periodic fifo settings */
2770 for (idx = 1; idx <= 15; idx++) {
2771 val = readl(regs + S3C_DPTXFSIZn(idx));
2772 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
2773 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
2774 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
2777 for (idx = 0; idx < 15; idx++) {
2779 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
2780 readl(regs + S3C_DIEPCTL(idx)),
2781 readl(regs + S3C_DIEPTSIZ(idx)),
2782 readl(regs + S3C_DIEPDMA(idx)));
2784 val = readl(regs + S3C_DOEPCTL(idx));
2786 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
2787 idx, readl(regs + S3C_DOEPCTL(idx)),
2788 readl(regs + S3C_DOEPTSIZ(idx)),
2789 readl(regs + S3C_DOEPDMA(idx)));
2793 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
2794 readl(regs + S3C_DVBUSDIS), readl(regs + S3C_DVBUSPULSE));
2799 * state_show - debugfs: show overall driver and device state.
2800 * @seq: The seq file to write to.
2801 * @v: Unused parameter.
2803 * This debugfs entry shows the overall state of the hardware and
2804 * some general information about each of the endpoints available
2807 static int state_show(struct seq_file *seq, void *v)
2809 struct s3c_hsotg *hsotg = seq->private;
2810 void __iomem *regs = hsotg->regs;
2813 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
2814 readl(regs + S3C_DCFG),
2815 readl(regs + S3C_DCTL),
2816 readl(regs + S3C_DSTS));
2818 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
2819 readl(regs + S3C_DIEPMSK), readl(regs + S3C_DOEPMSK));
2821 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
2822 readl(regs + S3C_GINTMSK),
2823 readl(regs + S3C_GINTSTS));
2825 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
2826 readl(regs + S3C_DAINTMSK),
2827 readl(regs + S3C_DAINT));
2829 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
2830 readl(regs + S3C_GNPTXSTS),
2831 readl(regs + S3C_GRXSTSR));
2833 seq_printf(seq, "\nEndpoint status:\n");
2835 for (idx = 0; idx < 15; idx++) {
2838 in = readl(regs + S3C_DIEPCTL(idx));
2839 out = readl(regs + S3C_DOEPCTL(idx));
2841 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
2844 in = readl(regs + S3C_DIEPTSIZ(idx));
2845 out = readl(regs + S3C_DOEPTSIZ(idx));
2847 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
2850 seq_printf(seq, "\n");
2856 static int state_open(struct inode *inode, struct file *file)
2858 return single_open(file, state_show, inode->i_private);
2861 static const struct file_operations state_fops = {
2862 .owner = THIS_MODULE,
2865 .llseek = seq_lseek,
2866 .release = single_release,
2870 * fifo_show - debugfs: show the fifo information
2871 * @seq: The seq_file to write data to.
2872 * @v: Unused parameter.
2874 * Show the FIFO information for the overall fifo and all the
2875 * periodic transmission FIFOs.
2877 static int fifo_show(struct seq_file *seq, void *v)
2879 struct s3c_hsotg *hsotg = seq->private;
2880 void __iomem *regs = hsotg->regs;
2884 seq_printf(seq, "Non-periodic FIFOs:\n");
2885 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + S3C_GRXFSIZ));
2887 val = readl(regs + S3C_GNPTXFSIZ);
2888 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
2889 val >> S3C_GNPTXFSIZ_NPTxFDep_SHIFT,
2890 val & S3C_GNPTXFSIZ_NPTxFStAddr_MASK);
2892 seq_printf(seq, "\nPeriodic TXFIFOs:\n");
2894 for (idx = 1; idx <= 15; idx++) {
2895 val = readl(regs + S3C_DPTXFSIZn(idx));
2897 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
2898 val >> S3C_DPTXFSIZn_DPTxFSize_SHIFT,
2899 val & S3C_DPTXFSIZn_DPTxFStAddr_MASK);
2905 static int fifo_open(struct inode *inode, struct file *file)
2907 return single_open(file, fifo_show, inode->i_private);
2910 static const struct file_operations fifo_fops = {
2911 .owner = THIS_MODULE,
2914 .llseek = seq_lseek,
2915 .release = single_release,
2919 static const char *decode_direction(int is_in)
2921 return is_in ? "in" : "out";
2925 * ep_show - debugfs: show the state of an endpoint.
2926 * @seq: The seq_file to write data to.
2927 * @v: Unused parameter.
2929 * This debugfs entry shows the state of the given endpoint (one is
2930 * registered for each available).
2932 static int ep_show(struct seq_file *seq, void *v)
2934 struct s3c_hsotg_ep *ep = seq->private;
2935 struct s3c_hsotg *hsotg = ep->parent;
2936 struct s3c_hsotg_req *req;
2937 void __iomem *regs = hsotg->regs;
2938 int index = ep->index;
2939 int show_limit = 15;
2940 unsigned long flags;
2942 seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n",
2943 ep->index, ep->ep.name, decode_direction(ep->dir_in));
2945 /* first show the register state */
2947 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
2948 readl(regs + S3C_DIEPCTL(index)),
2949 readl(regs + S3C_DOEPCTL(index)));
2951 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
2952 readl(regs + S3C_DIEPDMA(index)),
2953 readl(regs + S3C_DOEPDMA(index)));
2955 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
2956 readl(regs + S3C_DIEPINT(index)),
2957 readl(regs + S3C_DOEPINT(index)));
2959 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
2960 readl(regs + S3C_DIEPTSIZ(index)),
2961 readl(regs + S3C_DOEPTSIZ(index)));
2963 seq_printf(seq, "\n");
2964 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
2965 seq_printf(seq, "total_data=%ld\n", ep->total_data);
2967 seq_printf(seq, "request list (%p,%p):\n",
2968 ep->queue.next, ep->queue.prev);
2970 spin_lock_irqsave(&ep->lock, flags);
2972 list_for_each_entry(req, &ep->queue, queue) {
2973 if (--show_limit < 0) {
2974 seq_printf(seq, "not showing more requests...\n");
2978 seq_printf(seq, "%c req %p: %d bytes @%p, ",
2979 req == ep->req ? '*' : ' ',
2980 req, req->req.length, req->req.buf);
2981 seq_printf(seq, "%d done, res %d\n",
2982 req->req.actual, req->req.status);
2985 spin_unlock_irqrestore(&ep->lock, flags);
2990 static int ep_open(struct inode *inode, struct file *file)
2992 return single_open(file, ep_show, inode->i_private);
2995 static const struct file_operations ep_fops = {
2996 .owner = THIS_MODULE,
2999 .llseek = seq_lseek,
3000 .release = single_release,
3004 * s3c_hsotg_create_debug - create debugfs directory and files
3005 * @hsotg: The driver state
3007 * Create the debugfs files to allow the user to get information
3008 * about the state of the system. The directory name is created
3009 * with the same name as the device itself, in case we end up
3010 * with multiple blocks in future systems.
3012 static void __devinit s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
3014 struct dentry *root;
3017 root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
3018 hsotg->debug_root = root;
3020 dev_err(hsotg->dev, "cannot create debug root\n");
3024 /* create general state file */
3026 hsotg->debug_file = debugfs_create_file("state", 0444, root,
3027 hsotg, &state_fops);
3029 if (IS_ERR(hsotg->debug_file))
3030 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3032 hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3035 if (IS_ERR(hsotg->debug_fifo))
3036 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3038 /* create one file for each endpoint */
3040 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3041 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3043 ep->debugfs = debugfs_create_file(ep->name, 0444,
3044 root, ep, &ep_fops);
3046 if (IS_ERR(ep->debugfs))
3047 dev_err(hsotg->dev, "failed to create %s debug file\n",
3053 * s3c_hsotg_delete_debug - cleanup debugfs entries
3054 * @hsotg: The driver state
3056 * Cleanup (remove) the debugfs files for use on module exit.
3058 static void __devexit s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
3062 for (epidx = 0; epidx < S3C_HSOTG_EPS; epidx++) {
3063 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3064 debugfs_remove(ep->debugfs);
3067 debugfs_remove(hsotg->debug_file);
3068 debugfs_remove(hsotg->debug_fifo);
3069 debugfs_remove(hsotg->debug_root);
3073 * s3c_hsotg_gate - set the hardware gate for the block
3074 * @pdev: The device we bound to
3077 * Set the hardware gate setting into the block. If we end up on
3078 * something other than an S3C64XX, then we might need to change this
3079 * to using a platform data callback, or some other mechanism.
3081 static void s3c_hsotg_gate(struct platform_device *pdev, bool on)
3083 unsigned long flags;
3086 local_irq_save(flags);
3088 others = __raw_readl(S3C64XX_OTHERS);
3090 others |= S3C64XX_OTHERS_USBMASK;
3092 others &= ~S3C64XX_OTHERS_USBMASK;
3093 __raw_writel(others, S3C64XX_OTHERS);
3095 local_irq_restore(flags);
3098 static struct s3c_hsotg_plat s3c_hsotg_default_pdata;
3100 static int __devinit s3c_hsotg_probe(struct platform_device *pdev)
3102 struct s3c_hsotg_plat *plat = pdev->dev.platform_data;
3103 struct device *dev = &pdev->dev;
3104 struct s3c_hsotg *hsotg;
3105 struct resource *res;
3110 plat = &s3c_hsotg_default_pdata;
3112 hsotg = kzalloc(sizeof(struct s3c_hsotg) +
3113 sizeof(struct s3c_hsotg_ep) * S3C_HSOTG_EPS,
3116 dev_err(dev, "cannot get memory\n");
3123 platform_set_drvdata(pdev, hsotg);
3125 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3127 dev_err(dev, "cannot find register resource 0\n");
3132 hsotg->regs_res = request_mem_region(res->start, resource_size(res),
3134 if (!hsotg->regs_res) {
3135 dev_err(dev, "cannot reserve registers\n");
3140 hsotg->regs = ioremap(res->start, resource_size(res));
3142 dev_err(dev, "cannot map registers\n");
3147 ret = platform_get_irq(pdev, 0);
3149 dev_err(dev, "cannot find IRQ\n");
3155 ret = request_irq(ret, s3c_hsotg_irq, 0, dev_name(dev), hsotg);
3157 dev_err(dev, "cannot claim IRQ\n");
3161 dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq);
3163 device_initialize(&hsotg->gadget.dev);
3165 dev_set_name(&hsotg->gadget.dev, "gadget");
3167 hsotg->gadget.is_dualspeed = 1;
3168 hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
3169 hsotg->gadget.name = dev_name(dev);
3171 hsotg->gadget.dev.parent = dev;
3172 hsotg->gadget.dev.dma_mask = dev->dma_mask;
3174 /* setup endpoint information */
3176 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3177 hsotg->gadget.ep0 = &hsotg->eps[0].ep;
3179 /* allocate EP0 request */
3181 hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
3183 if (!hsotg->ctrl_req) {
3184 dev_err(dev, "failed to allocate ctrl req\n");
3188 /* reset the system */
3190 s3c_hsotg_gate(pdev, true);
3192 s3c_hsotg_otgreset(hsotg);
3193 s3c_hsotg_corereset(hsotg);
3194 s3c_hsotg_init(hsotg);
3196 /* initialise the endpoints now the core has been initialised */
3197 for (epnum = 0; epnum < S3C_HSOTG_EPS; epnum++)
3198 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
3200 s3c_hsotg_create_debug(hsotg);
3202 s3c_hsotg_dump(hsotg);
3208 iounmap(hsotg->regs);
3211 release_resource(hsotg->regs_res);
3212 kfree(hsotg->regs_res);
3219 static int __devexit s3c_hsotg_remove(struct platform_device *pdev)
3221 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3223 s3c_hsotg_delete_debug(hsotg);
3225 usb_gadget_unregister_driver(hsotg->driver);
3227 free_irq(hsotg->irq, hsotg);
3228 iounmap(hsotg->regs);
3230 release_resource(hsotg->regs_res);
3231 kfree(hsotg->regs_res);
3233 s3c_hsotg_gate(pdev, false);
3240 #define s3c_hsotg_suspend NULL
3241 #define s3c_hsotg_resume NULL
3244 static struct platform_driver s3c_hsotg_driver = {
3246 .name = "s3c-hsotg",
3247 .owner = THIS_MODULE,
3249 .probe = s3c_hsotg_probe,
3250 .remove = __devexit_p(s3c_hsotg_remove),
3251 .suspend = s3c_hsotg_suspend,
3252 .resume = s3c_hsotg_resume,
3255 static int __init s3c_hsotg_modinit(void)
3257 return platform_driver_register(&s3c_hsotg_driver);
3260 static void __exit s3c_hsotg_modexit(void)
3262 platform_driver_unregister(&s3c_hsotg_driver);
3265 module_init(s3c_hsotg_modinit);
3266 module_exit(s3c_hsotg_modexit);
3268 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3269 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3270 MODULE_LICENSE("GPL");
3271 MODULE_ALIAS("platform:s3c-hsotg");