drivers/usb/dwc3/gadget.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/delay.h>
  13 #include <linux/slab.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/list.h>
  20 #include <linux/dma-mapping.h>
  21
  22 #include <linux/usb/ch9.h>
  23 #include <linux/usb/gadget.h>
  24
  25 #include "debug.h"
  26 #include "core.h"
  27 #include "gadget.h"
  28 #include "io.h"
  29
  30 #define DWC3_ALIGN_FRAME(d, n)  (((d)->frame_number + ((d)->interval * (n))) \
  31                                         & ~((d)->interval - 1))
  32
  33 /**
  34  * dwc3_gadget_set_test_mode - enables usb2 test modes
  35  * @dwc: pointer to our context structure
  36  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  37  *
  38  * Caller should take care of locking. This function will return 0 on
  39  * success or -EINVAL if wrong Test Selector is passed.
  40  */
  41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  42 {
  43         u32             reg;
  44
  45         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  46         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  47
  48         switch (mode) {
  49         case USB_TEST_J:
  50         case USB_TEST_K:
  51         case USB_TEST_SE0_NAK:
  52         case USB_TEST_PACKET:
  53         case USB_TEST_FORCE_ENABLE:
  54                 reg |= mode << 1;
  55                 break;
  56         default:
  57                 return -EINVAL;
  58         }
  59
  60         dwc3_gadget_dctl_write_safe(dwc, reg);
  61
  62         return 0;
  63 }
  64
  65 /**
  66  * dwc3_gadget_get_link_state - gets current state of usb link
  67  * @dwc: pointer to our context structure
  68  *
  69  * Caller should take care of locking. This function will
  70  * return the link state on success (>= 0) or -ETIMEDOUT.
  71  */
  72 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  73 {
  74         u32             reg;
  75
  76         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  77
  78         return DWC3_DSTS_USBLNKST(reg);
  79 }
  80
  81 /**
  82  * dwc3_gadget_set_link_state - sets usb link to a particular state
  83  * @dwc: pointer to our context structure
  84  * @state: the state to put link into
  85  *
  86  * Caller should take care of locking. This function will
  87  * return 0 on success or -ETIMEDOUT.
  88  */
  89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  90 {
  91         int             retries = 10000;
  92         u32             reg;
  93
  94         /*
  95          * Wait until device controller is ready. Only applies to 1.94a and
  96          * later RTL.
  97          */
  98         if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) {
  99                 while (--retries) {
 100                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 101                         if (reg & DWC3_DSTS_DCNRD)
 102                                 udelay(5);
 103                         else
 104                                 break;
 105                 }
 106
 107                 if (retries <= 0)
 108                         return -ETIMEDOUT;
 109         }
 110
 111         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 112         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 113
 114         /* set no action before sending new link state change */
 115         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 116
 117         /* set requested state */
 118         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 119         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 120
 121         /*
 122          * The following code is racy when called from dwc3_gadget_wakeup,
 123          * and is not needed, at least on newer versions
 124          */
 125         if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
 126                 return 0;
 127
 128         /* wait for a change in DSTS */
 129         retries = 10000;
 130         while (--retries) {
 131                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 132
 133                 if (DWC3_DSTS_USBLNKST(reg) == state)
 134                         return 0;
 135
 136                 udelay(5);
 137         }
 138
 139         return -ETIMEDOUT;
 140 }
 141
 142 /**
 143  * dwc3_ep_inc_trb - increment a trb index.
 144  * @index: Pointer to the TRB index to increment.
 145  *
 146  * The index should never point to the link TRB. After incrementing,
 147  * if it is point to the link TRB, wrap around to the beginning. The
 148  * link TRB is always at the last TRB entry.
 149  */
 150 static void dwc3_ep_inc_trb(u8 *index)
 151 {
 152         (*index)++;
 153         if (*index == (DWC3_TRB_NUM - 1))
 154                 *index = 0;
 155 }
 156
 157 /**
 158  * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
 159  * @dep: The endpoint whose enqueue pointer we're incrementing
 160  */
 161 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
 162 {
 163         dwc3_ep_inc_trb(&dep->trb_enqueue);
 164 }
 165
 166 /**
 167  * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
 168  * @dep: The endpoint whose enqueue pointer we're incrementing
 169  */
 170 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
 171 {
 172         dwc3_ep_inc_trb(&dep->trb_dequeue);
 173 }
 174
 175 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
 176                 struct dwc3_request *req, int status)
 177 {
 178         struct dwc3                     *dwc = dep->dwc;
 179
 180         list_del(&req->list);
 181         req->remaining = 0;
 182         req->needs_extra_trb = false;
 183
 184         if (req->request.status == -EINPROGRESS)
 185                 req->request.status = status;
 186
 187         if (req->trb)
 188                 usb_gadget_unmap_request_by_dev(dwc->sysdev,
 189                                 &req->request, req->direction);
 190
 191         req->trb = NULL;
 192         trace_dwc3_gadget_giveback(req);
 193
 194         if (dep->number > 1)
 195                 pm_runtime_put(dwc->dev);
 196 }
 197
 198 /**
 199  * dwc3_gadget_giveback - call struct usb_request's ->complete callback
 200  * @dep: The endpoint to whom the request belongs to
 201  * @req: The request we're giving back
 202  * @status: completion code for the request
 203  *
 204  * Must be called with controller's lock held and interrupts disabled. This
 205  * function will unmap @req and call its ->complete() callback to notify upper
 206  * layers that it has completed.
 207  */
 208 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 209                 int status)
 210 {
 211         struct dwc3                     *dwc = dep->dwc;
 212
 213         dwc3_gadget_del_and_unmap_request(dep, req, status);
 214         req->status = DWC3_REQUEST_STATUS_COMPLETED;
 215
 216         spin_unlock(&dwc->lock);
 217         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 218         spin_lock(&dwc->lock);
 219 }
 220
 221 /**
 222  * dwc3_send_gadget_generic_command - issue a generic command for the controller
 223  * @dwc: pointer to the controller context
 224  * @cmd: the command to be issued
 225  * @param: command parameter
 226  *
 227  * Caller should take care of locking. Issue @cmd with a given @param to @dwc
 228  * and wait for its completion.
 229  */
 230 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
 231                 u32 param)
 232 {
 233         u32             timeout = 500;
 234         int             status = 0;
 235         int             ret = 0;
 236         u32             reg;
 237
 238         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 239         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 240
 241         do {
 242                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 243                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 244                         status = DWC3_DGCMD_STATUS(reg);
 245                         if (status)
 246                                 ret = -EINVAL;
 247                         break;
 248                 }
 249         } while (--timeout);
 250
 251         if (!timeout) {
 252                 ret = -ETIMEDOUT;
 253                 status = -ETIMEDOUT;
 254         }
 255
 256         trace_dwc3_gadget_generic_cmd(cmd, param, status);
 257
 258         return ret;
 259 }
 260
 261 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
 262
 263 /**
 264  * dwc3_send_gadget_ep_cmd - issue an endpoint command
 265  * @dep: the endpoint to which the command is going to be issued
 266  * @cmd: the command to be issued
 267  * @params: parameters to the command
 268  *
 269  * Caller should handle locking. This function will issue @cmd with given
 270  * @params to @dep and wait for its completion.
 271  */
 272 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
 273                 struct dwc3_gadget_ep_cmd_params *params)
 274 {
 275         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
 276         struct dwc3             *dwc = dep->dwc;
 277         u32                     timeout = 5000;
 278         u32                     saved_config = 0;
 279         u32                     reg;
 280
 281         int                     cmd_status = 0;
 282         int                     ret = -EINVAL;
 283
 284         /*
 285          * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
 286          * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
 287          * endpoint command.
 288          *
 289          * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
 290          * settings. Restore them after the command is completed.
 291          *
 292          * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
 293          */
 294         if (dwc->gadget->speed <= USB_SPEED_HIGH) {
 295                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 296                 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
 297                         saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
 298                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 299                 }
 300
 301                 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
 302                         saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
 303                         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 304                 }
 305
 306                 if (saved_config)
 307                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 308         }
 309
 310         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
 311                 int link_state;
 312
 313                 link_state = dwc3_gadget_get_link_state(dwc);
 314                 if (link_state == DWC3_LINK_STATE_U1 ||
 315                     link_state == DWC3_LINK_STATE_U2 ||
 316                     link_state == DWC3_LINK_STATE_U3) {
 317                         ret = __dwc3_gadget_wakeup(dwc);
 318                         dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
 319                                         ret);
 320                 }
 321         }
 322
 323         dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
 324         dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
 325         dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
 326
 327         /*
 328          * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
 329          * not relying on XferNotReady, we can make use of a special "No
 330          * Response Update Transfer" command where we should clear both CmdAct
 331          * and CmdIOC bits.
 332          *
 333          * With this, we don't need to wait for command completion and can
 334          * straight away issue further commands to the endpoint.
 335          *
 336          * NOTICE: We're making an assumption that control endpoints will never
 337          * make use of Update Transfer command. This is a safe assumption
 338          * because we can never have more than one request at a time with
 339          * Control Endpoints. If anybody changes that assumption, this chunk
 340          * needs to be updated accordingly.
 341          */
 342         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
 343                         !usb_endpoint_xfer_isoc(desc))
 344                 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
 345         else
 346                 cmd |= DWC3_DEPCMD_CMDACT;
 347
 348         dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
 349         do {
 350                 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
 351                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 352                         cmd_status = DWC3_DEPCMD_STATUS(reg);
 353
 354                         switch (cmd_status) {
 355                         case 0:
 356                                 ret = 0;
 357                                 break;
 358                         case DEPEVT_TRANSFER_NO_RESOURCE:
 359                                 dev_WARN(dwc->dev, "No resource for %s\n",
 360                                          dep->name);
 361                                 ret = -EINVAL;
 362                                 break;
 363                         case DEPEVT_TRANSFER_BUS_EXPIRY:
 364                                 /*
 365                                  * SW issues START TRANSFER command to
 366                                  * isochronous ep with future frame interval. If
 367                                  * future interval time has already passed when
 368                                  * core receives the command, it will respond
 369                                  * with an error status of 'Bus Expiry'.
 370                                  *
 371                                  * Instead of always returning -EINVAL, let's
 372                                  * give a hint to the gadget driver that this is
 373                                  * the case by returning -EAGAIN.
 374                                  */
 375                                 ret = -EAGAIN;
 376                                 break;
 377                         default:
 378                                 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
 379                         }
 380
 381                         break;
 382                 }
 383         } while (--timeout);
 384
 385         if (timeout == 0) {
 386                 ret = -ETIMEDOUT;
 387                 cmd_status = -ETIMEDOUT;
 388         }
 389
 390         trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
 391
 392         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
 393                 if (ret == 0)
 394                         dep->flags |= DWC3_EP_TRANSFER_STARTED;
 395
 396                 if (ret != -ETIMEDOUT)
 397                         dwc3_gadget_ep_get_transfer_index(dep);
 398         }
 399
 400         if (saved_config) {
 401                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 402                 reg |= saved_config;
 403                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 404         }
 405
 406         return ret;
 407 }
 408
 409 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
 410 {
 411         struct dwc3 *dwc = dep->dwc;
 412         struct dwc3_gadget_ep_cmd_params params;
 413         u32 cmd = DWC3_DEPCMD_CLEARSTALL;
 414
 415         /*
 416          * As of core revision 2.60a the recommended programming model
 417          * is to set the ClearPendIN bit when issuing a Clear Stall EP
 418          * command for IN endpoints. This is to prevent an issue where
 419          * some (non-compliant) hosts may not send ACK TPs for pending
 420          * IN transfers due to a mishandled error condition. Synopsys
 421          * STAR 9000614252.
 422          */
 423         if (dep->direction &&
 424             !DWC3_VER_IS_PRIOR(DWC3, 260A) &&
 425             (dwc->gadget->speed >= USB_SPEED_SUPER))
 426                 cmd |= DWC3_DEPCMD_CLEARPENDIN;
 427
 428         memset(&params, 0, sizeof(params));
 429
 430         return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 431 }
 432
 433 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 434                 struct dwc3_trb *trb)
 435 {
 436         u32             offset = (char *) trb - (char *) dep->trb_pool;
 437
 438         return dep->trb_pool_dma + offset;
 439 }
 440
 441 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 442 {
 443         struct dwc3             *dwc = dep->dwc;
 444
 445         if (dep->trb_pool)
 446                 return 0;
 447
 448         dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
 449                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 450                         &dep->trb_pool_dma, GFP_KERNEL);
 451         if (!dep->trb_pool) {
 452                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 453                                 dep->name);
 454                 return -ENOMEM;
 455         }
 456
 457         return 0;
 458 }
 459
 460 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 461 {
 462         struct dwc3             *dwc = dep->dwc;
 463
 464         dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 465                         dep->trb_pool, dep->trb_pool_dma);
 466
 467         dep->trb_pool = NULL;
 468         dep->trb_pool_dma = 0;
 469 }
 470
 471 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
 472 {
 473         struct dwc3_gadget_ep_cmd_params params;
 474
 475         memset(&params, 0x00, sizeof(params));
 476
 477         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 478
 479         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
 480                         &params);
 481 }
 482
 483 /**
 484  * dwc3_gadget_start_config - configure ep resources
 485  * @dep: endpoint that is being enabled
 486  *
 487  * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
 488  * completion, it will set Transfer Resource for all available endpoints.
 489  *
 490  * The assignment of transfer resources cannot perfectly follow the data book
 491  * due to the fact that the controller driver does not have all knowledge of the
 492  * configuration in advance. It is given this information piecemeal by the
 493  * composite gadget framework after every SET_CONFIGURATION and
 494  * SET_INTERFACE. Trying to follow the databook programming model in this
 495  * scenario can cause errors. For two reasons:
 496  *
 497  * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
 498  * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
 499  * incorrect in the scenario of multiple interfaces.
 500  *
 501  * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
 502  * endpoint on alt setting (8.1.6).
 503  *
 504  * The following simplified method is used instead:
 505  *
 506  * All hardware endpoints can be assigned a transfer resource and this setting
 507  * will stay persistent until either a core reset or hibernation. So whenever we
 508  * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
 509  * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
 510  * guaranteed that there are as many transfer resources as endpoints.
 511  *
 512  * This function is called for each endpoint when it is being enabled but is
 513  * triggered only when called for EP0-out, which always happens first, and which
 514  * should only happen in one of the above conditions.
 515  */
 516 static int dwc3_gadget_start_config(struct dwc3_ep *dep)
 517 {
 518         struct dwc3_gadget_ep_cmd_params params;
 519         struct dwc3             *dwc;
 520         u32                     cmd;
 521         int                     i;
 522         int                     ret;
 523
 524         if (dep->number)
 525                 return 0;
 526
 527         memset(&params, 0x00, sizeof(params));
 528         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 529         dwc = dep->dwc;
 530
 531         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 532         if (ret)
 533                 return ret;
 534
 535         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 536                 struct dwc3_ep *dep = dwc->eps[i];
 537
 538                 if (!dep)
 539                         continue;
 540
 541                 ret = dwc3_gadget_set_xfer_resource(dep);
 542                 if (ret)
 543                         return ret;
 544         }
 545
 546         return 0;
 547 }
 548
 549 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
 550 {
 551         const struct usb_ss_ep_comp_descriptor *comp_desc;
 552         const struct usb_endpoint_descriptor *desc;
 553         struct dwc3_gadget_ep_cmd_params params;
 554         struct dwc3 *dwc = dep->dwc;
 555
 556         comp_desc = dep->endpoint.comp_desc;
 557         desc = dep->endpoint.desc;
 558
 559         memset(&params, 0x00, sizeof(params));
 560
 561         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 562                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 563
 564         /* Burst size is only needed in SuperSpeed mode */
 565         if (dwc->gadget->speed >= USB_SPEED_SUPER) {
 566                 u32 burst = dep->endpoint.maxburst;
 567
 568                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
 569         }
 570
 571         params.param0 |= action;
 572         if (action == DWC3_DEPCFG_ACTION_RESTORE)
 573                 params.param2 |= dep->saved_state;
 574
 575         if (usb_endpoint_xfer_control(desc))
 576                 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
 577
 578         if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
 579                 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
 580
 581         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 582                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 583                         | DWC3_DEPCFG_XFER_COMPLETE_EN
 584                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 585                 dep->stream_capable = true;
 586         }
 587
 588         if (!usb_endpoint_xfer_control(desc))
 589                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 590
 591         /*
 592          * We are doing 1:1 mapping for endpoints, meaning
 593          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 594          * so on. We consider the direction bit as part of the physical
 595          * endpoint number. So USB endpoint 0x81 is 0x03.
 596          */
 597         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 598
 599         /*
 600          * We must use the lower 16 TX FIFOs even though
 601          * HW might have more
 602          */
 603         if (dep->direction)
 604                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 605
 606         if (desc->bInterval) {
 607                 u8 bInterval_m1;
 608
 609                 /*
 610                  * Valid range for DEPCFG.bInterval_m1 is from 0 to 13.
 611                  *
 612                  * NOTE: The programming guide incorrectly stated bInterval_m1
 613                  * must be set to 0 when operating in fullspeed. Internally the
 614                  * controller does not have this limitation. See DWC_usb3x
 615                  * programming guide section 3.2.2.1.
 616                  */
 617                 bInterval_m1 = min_t(u8, desc->bInterval - 1, 13);
 618
 619                 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
 620                     dwc->gadget->speed == USB_SPEED_FULL)
 621                         dep->interval = desc->bInterval;
 622                 else
 623                         dep->interval = 1 << (desc->bInterval - 1);
 624
 625                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1);
 626         }
 627
 628         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
 629 }
 630
 631 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
 632                 bool interrupt);
 633
 634 /**
 635  * dwc3_gadget_calc_tx_fifo_size - calculates the txfifo size value
 636  * @dwc: pointer to the DWC3 context
 637  * @nfifos: number of fifos to calculate for
 638  *
 639  * Calculates the size value based on the equation below:
 640  *
 641  * DWC3 revision 280A and prior:
 642  * fifo_size = mult * (max_packet / mdwidth) + 1;
 643  *
 644  * DWC3 revision 290A and onwards:
 645  * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
 646  *
 647  * The max packet size is set to 1024, as the txfifo requirements mainly apply
 648  * to super speed USB use cases.  However, it is safe to overestimate the fifo
 649  * allocations for other scenarios, i.e. high speed USB.
 650  */
 651 static int dwc3_gadget_calc_tx_fifo_size(struct dwc3 *dwc, int mult)
 652 {
 653         int max_packet = 1024;
 654         int fifo_size;
 655         int mdwidth;
 656
 657         mdwidth = dwc3_mdwidth(dwc);
 658
 659         /* MDWIDTH is represented in bits, we need it in bytes */
 660         mdwidth >>= 3;
 661
 662         if (DWC3_VER_IS_PRIOR(DWC3, 290A))
 663                 fifo_size = mult * (max_packet / mdwidth) + 1;
 664         else
 665                 fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1;
 666         return fifo_size;
 667 }
 668
 669 /**
 670  * dwc3_gadget_clear_tx_fifo_size - Clears txfifo allocation
 671  * @dwc: pointer to the DWC3 context
 672  *
 673  * Iterates through all the endpoint registers and clears the previous txfifo
 674  * allocations.
 675  */
 676 void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
 677 {
 678         struct dwc3_ep *dep;
 679         int fifo_depth;
 680         int size;
 681         int num;
 682
 683         if (!dwc->do_fifo_resize)
 684                 return;
 685
 686         /* Read ep0IN related TXFIFO size */
 687         dep = dwc->eps[1];
 688         size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
 689         if (DWC3_IP_IS(DWC3))
 690                 fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
 691         else
 692                 fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
 693
 694         dwc->last_fifo_depth = fifo_depth;
 695         /* Clear existing TXFIFO for all IN eps except ep0 */
 696         for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM);
 697              num += 2) {
 698                 dep = dwc->eps[num];
 699                 /* Don't change TXFRAMNUM on usb31 version */
 700                 size = DWC3_IP_IS(DWC3) ? 0 :
 701                         dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) &
 702                                    DWC31_GTXFIFOSIZ_TXFRAMNUM;
 703
 704                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size);
 705                 dep->flags &= ~DWC3_EP_TXFIFO_RESIZED;
 706         }
 707         dwc->num_ep_resized = 0;
 708 }
 709
 710 /*
 711  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 712  * @dwc: pointer to our context structure
 713  *
 714  * This function will a best effort FIFO allocation in order
 715  * to improve FIFO usage and throughput, while still allowing
 716  * us to enable as many endpoints as possible.
 717  *
 718  * Keep in mind that this operation will be highly dependent
 719  * on the configured size for RAM1 - which contains TxFifo -,
 720  * the amount of endpoints enabled on coreConsultant tool, and
 721  * the width of the Master Bus.
 722  *
 723  * In general, FIFO depths are represented with the following equation:
 724  *
 725  * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
 726  *
 727  * In conjunction with dwc3_gadget_check_config(), this resizing logic will
 728  * ensure that all endpoints will have enough internal memory for one max
 729  * packet per endpoint.
 730  */
 731 static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
 732 {
 733         struct dwc3 *dwc = dep->dwc;
 734         int fifo_0_start;
 735         int ram1_depth;
 736         int fifo_size;
 737         int min_depth;
 738         int num_in_ep;
 739         int remaining;
 740         int num_fifos = 1;
 741         int fifo;
 742         int tmp;
 743
 744         if (!dwc->do_fifo_resize)
 745                 return 0;
 746
 747         /* resize IN endpoints except ep0 */
 748         if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
 749                 return 0;
 750
 751         /* bail if already resized */
 752         if (dep->flags & DWC3_EP_TXFIFO_RESIZED)
 753                 return 0;
 754
 755         ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
 756
 757         if ((dep->endpoint.maxburst > 1 &&
 758              usb_endpoint_xfer_bulk(dep->endpoint.desc)) ||
 759             usb_endpoint_xfer_isoc(dep->endpoint.desc))
 760                 num_fifos = 3;
 761
 762         if (dep->endpoint.maxburst > 6 &&
 763             usb_endpoint_xfer_bulk(dep->endpoint.desc) && DWC3_IP_IS(DWC31))
 764                 num_fifos = dwc->tx_fifo_resize_max_num;
 765
 766         /* FIFO size for a single buffer */
 767         fifo = dwc3_gadget_calc_tx_fifo_size(dwc, 1);
 768
 769         /* Calculate the number of remaining EPs w/o any FIFO */
 770         num_in_ep = dwc->max_cfg_eps;
 771         num_in_ep -= dwc->num_ep_resized;
 772
 773         /* Reserve at least one FIFO for the number of IN EPs */
 774         min_depth = num_in_ep * (fifo + 1);
 775         remaining = ram1_depth - min_depth - dwc->last_fifo_depth;
 776         remaining = max_t(int, 0, remaining);
 777         /*
 778          * We've already reserved 1 FIFO per EP, so check what we can fit in
 779          * addition to it.  If there is not enough remaining space, allocate
 780          * all the remaining space to the EP.
 781          */
 782         fifo_size = (num_fifos - 1) * fifo;
 783         if (remaining < fifo_size)
 784                 fifo_size = remaining;
 785
 786         fifo_size += fifo;
 787         /* Last increment according to the TX FIFO size equation */
 788         fifo_size++;
 789
 790         /* Check if TXFIFOs start at non-zero addr */
 791         tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
 792         fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
 793
 794         fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
 795         if (DWC3_IP_IS(DWC3))
 796                 dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
 797         else
 798                 dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
 799
 800         /* Check fifo size allocation doesn't exceed available RAM size. */
 801         if (dwc->last_fifo_depth >= ram1_depth) {
 802                 dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n",
 803                         dwc->last_fifo_depth, ram1_depth,
 804                         dep->endpoint.name, fifo_size);
 805                 if (DWC3_IP_IS(DWC3))
 806                         fifo_size = DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
 807                 else
 808                         fifo_size = DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
 809
 810                 dwc->last_fifo_depth -= fifo_size;
 811                 return -ENOMEM;
 812         }
 813
 814         dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size);
 815         dep->flags |= DWC3_EP_TXFIFO_RESIZED;
 816         dwc->num_ep_resized++;
 817
 818         return 0;
 819 }
 820
 821 /**
 822  * __dwc3_gadget_ep_enable - initializes a hw endpoint
 823  * @dep: endpoint to be initialized
 824  * @action: one of INIT, MODIFY or RESTORE
 825  *
 826  * Caller should take care of locking. Execute all necessary commands to
 827  * initialize a HW endpoint so it can be used by a gadget driver.
 828  */
 829 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
 830 {
 831         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
 832         struct dwc3             *dwc = dep->dwc;
 833
 834         u32                     reg;
 835         int                     ret;
 836
 837         if (!(dep->flags & DWC3_EP_ENABLED)) {
 838                 ret = dwc3_gadget_resize_tx_fifos(dep);
 839                 if (ret)
 840                         return ret;
 841
 842                 ret = dwc3_gadget_start_config(dep);
 843                 if (ret)
 844                         return ret;
 845         }
 846
 847         ret = dwc3_gadget_set_ep_config(dep, action);
 848         if (ret)
 849                 return ret;
 850
 851         if (!(dep->flags & DWC3_EP_ENABLED)) {
 852                 struct dwc3_trb *trb_st_hw;
 853                 struct dwc3_trb *trb_link;
 854
 855                 dep->type = usb_endpoint_type(desc);
 856                 dep->flags |= DWC3_EP_ENABLED;
 857
 858                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 859                 reg |= DWC3_DALEPENA_EP(dep->number);
 860                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 861
 862                 if (usb_endpoint_xfer_control(desc))
 863                         goto out;
 864
 865                 /* Initialize the TRB ring */
 866                 dep->trb_dequeue = 0;
 867                 dep->trb_enqueue = 0;
 868                 memset(dep->trb_pool, 0,
 869                        sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
 870
 871                 /* Link TRB. The HWO bit is never reset */
 872                 trb_st_hw = &dep->trb_pool[0];
 873
 874                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 875                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 876                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 877                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 878                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 879         }
 880
 881         /*
 882          * Issue StartTransfer here with no-op TRB so we can always rely on No
 883          * Response Update Transfer command.
 884          */
 885         if (usb_endpoint_xfer_bulk(desc) ||
 886                         usb_endpoint_xfer_int(desc)) {
 887                 struct dwc3_gadget_ep_cmd_params params;
 888                 struct dwc3_trb *trb;
 889                 dma_addr_t trb_dma;
 890                 u32 cmd;
 891
 892                 memset(&params, 0, sizeof(params));
 893                 trb = &dep->trb_pool[0];
 894                 trb_dma = dwc3_trb_dma_offset(dep, trb);
 895
 896                 params.param0 = upper_32_bits(trb_dma);
 897                 params.param1 = lower_32_bits(trb_dma);
 898
 899                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 900
 901                 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 902                 if (ret < 0)
 903                         return ret;
 904
 905                 if (dep->stream_capable) {
 906                         /*
 907                          * For streams, at start, there maybe a race where the
 908                          * host primes the endpoint before the function driver
 909                          * queues a request to initiate a stream. In that case,
 910                          * the controller will not see the prime to generate the
 911                          * ERDY and start stream. To workaround this, issue a
 912                          * no-op TRB as normal, but end it immediately. As a
 913                          * result, when the function driver queues the request,
 914                          * the next START_TRANSFER command will cause the
 915                          * controller to generate an ERDY to initiate the
 916                          * stream.
 917                          */
 918                         dwc3_stop_active_transfer(dep, true, true);
 919
 920                         /*
 921                          * All stream eps will reinitiate stream on NoStream
 922                          * rejection until we can determine that the host can
 923                          * prime after the first transfer.
 924                          *
 925                          * However, if the controller is capable of
 926                          * TXF_FLUSH_BYPASS, then IN direction endpoints will
 927                          * automatically restart the stream without the driver
 928                          * initiation.
 929                          */
 930                         if (!dep->direction ||
 931                             !(dwc->hwparams.hwparams9 &
 932                               DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS))
 933                                 dep->flags |= DWC3_EP_FORCE_RESTART_STREAM;
 934                 }
 935         }
 936
 937 out:
 938         trace_dwc3_gadget_ep_enable(dep);
 939
 940         return 0;
 941 }
 942
 943 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 944 {
 945         struct dwc3_request             *req;
 946
 947         dwc3_stop_active_transfer(dep, true, false);
 948
 949         /* - giveback all requests to gadget driver */
 950         while (!list_empty(&dep->started_list)) {
 951                 req = next_request(&dep->started_list);
 952
 953                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 954         }
 955
 956         while (!list_empty(&dep->pending_list)) {
 957                 req = next_request(&dep->pending_list);
 958
 959                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 960         }
 961
 962         while (!list_empty(&dep->cancelled_list)) {
 963                 req = next_request(&dep->cancelled_list);
 964
 965                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 966         }
 967 }
 968
 969 /**
 970  * __dwc3_gadget_ep_disable - disables a hw endpoint
 971  * @dep: the endpoint to disable
 972  *
 973  * This function undoes what __dwc3_gadget_ep_enable did and also removes
 974  * requests which are currently being processed by the hardware and those which
 975  * are not yet scheduled.
 976  *
 977  * Caller should take care of locking.
 978  */
 979 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 980 {
 981         struct dwc3             *dwc = dep->dwc;
 982         u32                     reg;
 983
 984         trace_dwc3_gadget_ep_disable(dep);
 985
 986         /* make sure HW endpoint isn't stalled */
 987         if (dep->flags & DWC3_EP_STALL)
 988                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 989
 990         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 991         reg &= ~DWC3_DALEPENA_EP(dep->number);
 992         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 993
 994         /* Clear out the ep descriptors for non-ep0 */
 995         if (dep->number > 1) {
 996                 dep->endpoint.comp_desc = NULL;
 997                 dep->endpoint.desc = NULL;
 998         }
 999
1000         dwc3_remove_requests(dwc, dep);
1001
1002         dep->stream_capable = false;
1003         dep->type = 0;
1004         dep->flags &= DWC3_EP_TXFIFO_RESIZED;
1005
1006         return 0;
1007 }
1008
1009 /* -------------------------------------------------------------------------- */
1010
1011 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
1012                 const struct usb_endpoint_descriptor *desc)
1013 {
1014         return -EINVAL;
1015 }
1016
1017 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
1018 {
1019         return -EINVAL;
1020 }
1021
1022 /* -------------------------------------------------------------------------- */
1023
1024 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
1025                 const struct usb_endpoint_descriptor *desc)
1026 {
1027         struct dwc3_ep                  *dep;
1028         struct dwc3                     *dwc;
1029         unsigned long                   flags;
1030         int                             ret;
1031
1032         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
1033                 pr_debug("dwc3: invalid parameters\n");
1034                 return -EINVAL;
1035         }
1036
1037         if (!desc->wMaxPacketSize) {
1038                 pr_debug("dwc3: missing wMaxPacketSize\n");
1039                 return -EINVAL;
1040         }
1041
1042         dep = to_dwc3_ep(ep);
1043         dwc = dep->dwc;
1044
1045         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
1046                                         "%s is already enabled\n",
1047                                         dep->name))
1048                 return 0;
1049
1050         spin_lock_irqsave(&dwc->lock, flags);
1051         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1052         spin_unlock_irqrestore(&dwc->lock, flags);
1053
1054         return ret;
1055 }
1056
1057 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
1058 {
1059         struct dwc3_ep                  *dep;
1060         struct dwc3                     *dwc;
1061         unsigned long                   flags;
1062         int                             ret;
1063
1064         if (!ep) {
1065                 pr_debug("dwc3: invalid parameters\n");
1066                 return -EINVAL;
1067         }
1068
1069         dep = to_dwc3_ep(ep);
1070         dwc = dep->dwc;
1071
1072         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
1073                                         "%s is already disabled\n",
1074                                         dep->name))
1075                 return 0;
1076
1077         spin_lock_irqsave(&dwc->lock, flags);
1078         ret = __dwc3_gadget_ep_disable(dep);
1079         spin_unlock_irqrestore(&dwc->lock, flags);
1080
1081         return ret;
1082 }
1083
1084 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
1085                 gfp_t gfp_flags)
1086 {
1087         struct dwc3_request             *req;
1088         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1089
1090         req = kzalloc(sizeof(*req), gfp_flags);
1091         if (!req)
1092                 return NULL;
1093
1094         req->direction  = dep->direction;
1095         req->epnum      = dep->number;
1096         req->dep        = dep;
1097         req->status     = DWC3_REQUEST_STATUS_UNKNOWN;
1098
1099         trace_dwc3_alloc_request(req);
1100
1101         return &req->request;
1102 }
1103
1104 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
1105                 struct usb_request *request)
1106 {
1107         struct dwc3_request             *req = to_dwc3_request(request);
1108
1109         trace_dwc3_free_request(req);
1110         kfree(req);
1111 }
1112
1113 /**
1114  * dwc3_ep_prev_trb - returns the previous TRB in the ring
1115  * @dep: The endpoint with the TRB ring
1116  * @index: The index of the current TRB in the ring
1117  *
1118  * Returns the TRB prior to the one pointed to by the index. If the
1119  * index is 0, we will wrap backwards, skip the link TRB, and return
1120  * the one just before that.
1121  */
1122 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
1123 {
1124         u8 tmp = index;
1125
1126         if (!tmp)
1127                 tmp = DWC3_TRB_NUM - 1;
1128
1129         return &dep->trb_pool[tmp - 1];
1130 }
1131
1132 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
1133 {
1134         u8                      trbs_left;
1135
1136         /*
1137          * If the enqueue & dequeue are equal then the TRB ring is either full
1138          * or empty. It's considered full when there are DWC3_TRB_NUM-1 of TRBs
1139          * pending to be processed by the driver.
1140          */
1141         if (dep->trb_enqueue == dep->trb_dequeue) {
1142                 /*
1143                  * If there is any request remained in the started_list at
1144                  * this point, that means there is no TRB available.
1145                  */
1146                 if (!list_empty(&dep->started_list))
1147                         return 0;
1148
1149                 return DWC3_TRB_NUM - 1;
1150         }
1151
1152         trbs_left = dep->trb_dequeue - dep->trb_enqueue;
1153         trbs_left &= (DWC3_TRB_NUM - 1);
1154
1155         if (dep->trb_dequeue < dep->trb_enqueue)
1156                 trbs_left--;
1157
1158         return trbs_left;
1159 }
1160
1161 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
1162                 dma_addr_t dma, unsigned int length, unsigned int chain,
1163                 unsigned int node, unsigned int stream_id,
1164                 unsigned int short_not_ok, unsigned int no_interrupt,
1165                 unsigned int is_last, bool must_interrupt)
1166 {
1167         struct dwc3             *dwc = dep->dwc;
1168         struct usb_gadget       *gadget = dwc->gadget;
1169         enum usb_device_speed   speed = gadget->speed;
1170
1171         trb->size = DWC3_TRB_SIZE_LENGTH(length);
1172         trb->bpl = lower_32_bits(dma);
1173         trb->bph = upper_32_bits(dma);
1174
1175         switch (usb_endpoint_type(dep->endpoint.desc)) {
1176         case USB_ENDPOINT_XFER_CONTROL:
1177                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
1178                 break;
1179
1180         case USB_ENDPOINT_XFER_ISOC:
1181                 if (!node) {
1182                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
1183
1184                         /*
1185                          * USB Specification 2.0 Section 5.9.2 states that: "If
1186                          * there is only a single transaction in the microframe,
1187                          * only a DATA0 data packet PID is used.  If there are
1188                          * two transactions per microframe, DATA1 is used for
1189                          * the first transaction data packet and DATA0 is used
1190                          * for the second transaction data packet.  If there are
1191                          * three transactions per microframe, DATA2 is used for
1192                          * the first transaction data packet, DATA1 is used for
1193                          * the second, and DATA0 is used for the third."
1194                          *
1195                          * IOW, we should satisfy the following cases:
1196                          *
1197                          * 1) length <= maxpacket
1198                          *      - DATA0
1199                          *
1200                          * 2) maxpacket < length <= (2 * maxpacket)
1201                          *      - DATA1, DATA0
1202                          *
1203                          * 3) (2 * maxpacket) < length <= (3 * maxpacket)
1204                          *      - DATA2, DATA1, DATA0
1205                          */
1206                         if (speed == USB_SPEED_HIGH) {
1207                                 struct usb_ep *ep = &dep->endpoint;
1208                                 unsigned int mult = 2;
1209                                 unsigned int maxp = usb_endpoint_maxp(ep->desc);
1210
1211                                 if (length <= (2 * maxp))
1212                                         mult--;
1213
1214                                 if (length <= maxp)
1215                                         mult--;
1216
1217                                 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
1218                         }
1219                 } else {
1220                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
1221                 }
1222
1223                 /* always enable Interrupt on Missed ISOC */
1224                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1225                 break;
1226
1227         case USB_ENDPOINT_XFER_BULK:
1228         case USB_ENDPOINT_XFER_INT:
1229                 trb->ctrl = DWC3_TRBCTL_NORMAL;
1230                 break;
1231         default:
1232                 /*
1233                  * This is only possible with faulty memory because we
1234                  * checked it already :)
1235                  */
1236                 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
1237                                 usb_endpoint_type(dep->endpoint.desc));
1238         }
1239
1240         /*
1241          * Enable Continue on Short Packet
1242          * when endpoint is not a stream capable
1243          */
1244         if (usb_endpoint_dir_out(dep->endpoint.desc)) {
1245                 if (!dep->stream_capable)
1246                         trb->ctrl |= DWC3_TRB_CTRL_CSP;
1247
1248                 if (short_not_ok)
1249                         trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1250         }
1251
1252         if ((!no_interrupt && !chain) || must_interrupt)
1253                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1254
1255         if (chain)
1256                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1257         else if (dep->stream_capable && is_last)
1258                 trb->ctrl |= DWC3_TRB_CTRL_LST;
1259
1260         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1261                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1262
1263         trb->ctrl |= DWC3_TRB_CTRL_HWO;
1264
1265         dwc3_ep_inc_enq(dep);
1266
1267         trace_dwc3_prepare_trb(dep, trb);
1268 }
1269
1270 /**
1271  * dwc3_prepare_one_trb - setup one TRB from one request
1272  * @dep: endpoint for which this request is prepared
1273  * @req: dwc3_request pointer
1274  * @trb_length: buffer size of the TRB
1275  * @chain: should this TRB be chained to the next?
1276  * @node: only for isochronous endpoints. First TRB needs different type.
1277  * @use_bounce_buffer: set to use bounce buffer
1278  * @must_interrupt: set to interrupt on TRB completion
1279  */
1280 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1281                 struct dwc3_request *req, unsigned int trb_length,
1282                 unsigned int chain, unsigned int node, bool use_bounce_buffer,
1283                 bool must_interrupt)
1284 {
1285         struct dwc3_trb         *trb;
1286         dma_addr_t              dma;
1287         unsigned int            stream_id = req->request.stream_id;
1288         unsigned int            short_not_ok = req->request.short_not_ok;
1289         unsigned int            no_interrupt = req->request.no_interrupt;
1290         unsigned int            is_last = req->request.is_last;
1291
1292         if (use_bounce_buffer)
1293                 dma = dep->dwc->bounce_addr;
1294         else if (req->request.num_sgs > 0)
1295                 dma = sg_dma_address(req->start_sg);
1296         else
1297                 dma = req->request.dma;
1298
1299         trb = &dep->trb_pool[dep->trb_enqueue];
1300
1301         if (!req->trb) {
1302                 dwc3_gadget_move_started_request(req);
1303                 req->trb = trb;
1304                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1305         }
1306
1307         req->num_trbs++;
1308
1309         __dwc3_prepare_one_trb(dep, trb, dma, trb_length, chain, node,
1310                         stream_id, short_not_ok, no_interrupt, is_last,
1311                         must_interrupt);
1312 }
1313
1314 static bool dwc3_needs_extra_trb(struct dwc3_ep *dep, struct dwc3_request *req)
1315 {
1316         unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1317         unsigned int rem = req->request.length % maxp;
1318
1319         if ((req->request.length && req->request.zero && !rem &&
1320                         !usb_endpoint_xfer_isoc(dep->endpoint.desc)) ||
1321                         (!req->direction && rem))
1322                 return true;
1323
1324         return false;
1325 }
1326
1327 /**
1328  * dwc3_prepare_last_sg - prepare TRBs for the last SG entry
1329  * @dep: The endpoint that the request belongs to
1330  * @req: The request to prepare
1331  * @entry_length: The last SG entry size
1332  * @node: Indicates whether this is not the first entry (for isoc only)
1333  *
1334  * Return the number of TRBs prepared.
1335  */
1336 static int dwc3_prepare_last_sg(struct dwc3_ep *dep,
1337                 struct dwc3_request *req, unsigned int entry_length,
1338                 unsigned int node)
1339 {
1340         unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1341         unsigned int rem = req->request.length % maxp;
1342         unsigned int num_trbs = 1;
1343
1344         if (dwc3_needs_extra_trb(dep, req))
1345                 num_trbs++;
1346
1347         if (dwc3_calc_trbs_left(dep) < num_trbs)
1348                 return 0;
1349
1350         req->needs_extra_trb = num_trbs > 1;
1351
1352         /* Prepare a normal TRB */
1353         if (req->direction || req->request.length)
1354                 dwc3_prepare_one_trb(dep, req, entry_length,
1355                                 req->needs_extra_trb, node, false, false);
1356
1357         /* Prepare extra TRBs for ZLP and MPS OUT transfer alignment */
1358         if ((!req->direction && !req->request.length) || req->needs_extra_trb)
1359                 dwc3_prepare_one_trb(dep, req,
1360                                 req->direction ? 0 : maxp - rem,
1361                                 false, 1, true, false);
1362
1363         return num_trbs;
1364 }
1365
1366 static int dwc3_prepare_trbs_sg(struct dwc3_ep *dep,
1367                 struct dwc3_request *req)
1368 {
1369         struct scatterlist *sg = req->start_sg;
1370         struct scatterlist *s;
1371         int             i;
1372         unsigned int length = req->request.length;
1373         unsigned int remaining = req->request.num_mapped_sgs
1374                 - req->num_queued_sgs;
1375         unsigned int num_trbs = req->num_trbs;
1376         bool needs_extra_trb = dwc3_needs_extra_trb(dep, req);
1377
1378         /*
1379          * If we resume preparing the request, then get the remaining length of
1380          * the request and resume where we left off.
1381          */
1382         for_each_sg(req->request.sg, s, req->num_queued_sgs, i)
1383                 length -= sg_dma_len(s);
1384
1385         for_each_sg(sg, s, remaining, i) {
1386                 unsigned int num_trbs_left = dwc3_calc_trbs_left(dep);
1387                 unsigned int trb_length;
1388                 bool must_interrupt = false;
1389                 bool last_sg = false;
1390
1391                 trb_length = min_t(unsigned int, length, sg_dma_len(s));
1392
1393                 length -= trb_length;
1394
1395                 /*
1396                  * IOMMU driver is coalescing the list of sgs which shares a
1397                  * page boundary into one and giving it to USB driver. With
1398                  * this the number of sgs mapped is not equal to the number of
1399                  * sgs passed. So mark the chain bit to false if it isthe last
1400                  * mapped sg.
1401                  */
1402                 if ((i == remaining - 1) || !length)
1403                         last_sg = true;
1404
1405                 if (!num_trbs_left)
1406                         break;
1407
1408                 if (last_sg) {
1409                         if (!dwc3_prepare_last_sg(dep, req, trb_length, i))
1410                                 break;
1411                 } else {
1412                         /*
1413                          * Look ahead to check if we have enough TRBs for the
1414                          * next SG entry. If not, set interrupt on this TRB to
1415                          * resume preparing the next SG entry when more TRBs are
1416                          * free.
1417                          */
1418                         if (num_trbs_left == 1 || (needs_extra_trb &&
1419                                         num_trbs_left <= 2 &&
1420                                         sg_dma_len(sg_next(s)) >= length))
1421                                 must_interrupt = true;
1422
1423                         dwc3_prepare_one_trb(dep, req, trb_length, 1, i, false,
1424                                         must_interrupt);
1425                 }
1426
1427                 /*
1428                  * There can be a situation where all sgs in sglist are not
1429                  * queued because of insufficient trb number. To handle this
1430                  * case, update start_sg to next sg to be queued, so that
1431                  * we have free trbs we can continue queuing from where we
1432                  * previously stopped
1433                  */
1434                 if (!last_sg)
1435                         req->start_sg = sg_next(s);
1436
1437                 req->num_queued_sgs++;
1438                 req->num_pending_sgs--;
1439
1440                 /*
1441                  * The number of pending SG entries may not correspond to the
1442                  * number of mapped SG entries. If all the data are queued, then
1443                  * don't include unused SG entries.
1444                  */
1445                 if (length == 0) {
1446                         req->num_pending_sgs = 0;
1447                         break;
1448                 }
1449
1450                 if (must_interrupt)
1451                         break;
1452         }
1453
1454         return req->num_trbs - num_trbs;
1455 }
1456
1457 static int dwc3_prepare_trbs_linear(struct dwc3_ep *dep,
1458                 struct dwc3_request *req)
1459 {
1460         return dwc3_prepare_last_sg(dep, req, req->request.length, 0);
1461 }
1462
1463 /*
1464  * dwc3_prepare_trbs - setup TRBs from requests
1465  * @dep: endpoint for which requests are being prepared
1466  *
1467  * The function goes through the requests list and sets up TRBs for the
1468  * transfers. The function returns once there are no more TRBs available or
1469  * it runs out of requests.
1470  *
1471  * Returns the number of TRBs prepared or negative errno.
1472  */
1473 static int dwc3_prepare_trbs(struct dwc3_ep *dep)
1474 {
1475         struct dwc3_request     *req, *n;
1476         int                     ret = 0;
1477
1478         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1479
1480         /*
1481          * We can get in a situation where there's a request in the started list
1482          * but there weren't enough TRBs to fully kick it in the first time
1483          * around, so it has been waiting for more TRBs to be freed up.
1484          *
1485          * In that case, we should check if we have a request with pending_sgs
1486          * in the started list and prepare TRBs for that request first,
1487          * otherwise we will prepare TRBs completely out of order and that will
1488          * break things.
1489          */
1490         list_for_each_entry(req, &dep->started_list, list) {
1491                 if (req->num_pending_sgs > 0) {
1492                         ret = dwc3_prepare_trbs_sg(dep, req);
1493                         if (!ret || req->num_pending_sgs)
1494                                 return ret;
1495                 }
1496
1497                 if (!dwc3_calc_trbs_left(dep))
1498                         return ret;
1499
1500                 /*
1501                  * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1502                  * burst capability may try to read and use TRBs beyond the
1503                  * active transfer instead of stopping.
1504                  */
1505                 if (dep->stream_capable && req->request.is_last)
1506                         return ret;
1507         }
1508
1509         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1510                 struct dwc3     *dwc = dep->dwc;
1511
1512                 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1513                                                     dep->direction);
1514                 if (ret)
1515                         return ret;
1516
1517                 req->sg                 = req->request.sg;
1518                 req->start_sg           = req->sg;
1519                 req->num_queued_sgs     = 0;
1520                 req->num_pending_sgs    = req->request.num_mapped_sgs;
1521
1522                 if (req->num_pending_sgs > 0) {
1523                         ret = dwc3_prepare_trbs_sg(dep, req);
1524                         if (req->num_pending_sgs)
1525                                 return ret;
1526                 } else {
1527                         ret = dwc3_prepare_trbs_linear(dep, req);
1528                 }
1529
1530                 if (!ret || !dwc3_calc_trbs_left(dep))
1531                         return ret;
1532
1533                 /*
1534                  * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1535                  * burst capability may try to read and use TRBs beyond the
1536                  * active transfer instead of stopping.
1537                  */
1538                 if (dep->stream_capable && req->request.is_last)
1539                         return ret;
1540         }
1541
1542         return ret;
1543 }
1544
1545 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep);
1546
1547 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1548 {
1549         struct dwc3_gadget_ep_cmd_params params;
1550         struct dwc3_request             *req;
1551         int                             starting;
1552         int                             ret;
1553         u32                             cmd;
1554
1555         /*
1556          * Note that it's normal to have no new TRBs prepared (i.e. ret == 0).
1557          * This happens when we need to stop and restart a transfer such as in
1558          * the case of reinitiating a stream or retrying an isoc transfer.
1559          */
1560         ret = dwc3_prepare_trbs(dep);
1561         if (ret < 0)
1562                 return ret;
1563
1564         starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1565
1566         /*
1567          * If there's no new TRB prepared and we don't need to restart a
1568          * transfer, there's no need to update the transfer.
1569          */
1570         if (!ret && !starting)
1571                 return ret;
1572
1573         req = next_request(&dep->started_list);
1574         if (!req) {
1575                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1576                 return 0;
1577         }
1578
1579         memset(&params, 0, sizeof(params));
1580
1581         if (starting) {
1582                 params.param0 = upper_32_bits(req->trb_dma);
1583                 params.param1 = lower_32_bits(req->trb_dma);
1584                 cmd = DWC3_DEPCMD_STARTTRANSFER;
1585
1586                 if (dep->stream_capable)
1587                         cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1588
1589                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1590                         cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1591         } else {
1592                 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1593                         DWC3_DEPCMD_PARAM(dep->resource_index);
1594         }
1595
1596         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1597         if (ret < 0) {
1598                 struct dwc3_request *tmp;
1599
1600                 if (ret == -EAGAIN)
1601                         return ret;
1602
1603                 dwc3_stop_active_transfer(dep, true, true);
1604
1605                 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1606                         dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_DEQUEUED);
1607
1608                 /* If ep isn't started, then there's no end transfer pending */
1609                 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1610                         dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1611
1612                 return ret;
1613         }
1614
1615         if (dep->stream_capable && req->request.is_last)
1616                 dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE;
1617
1618         return 0;
1619 }
1620
1621 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1622 {
1623         u32                     reg;
1624
1625         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1626         return DWC3_DSTS_SOFFN(reg);
1627 }
1628
1629 /**
1630  * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1631  * @dep: isoc endpoint
1632  *
1633  * This function tests for the correct combination of BIT[15:14] from the 16-bit
1634  * microframe number reported by the XferNotReady event for the future frame
1635  * number to start the isoc transfer.
1636  *
1637  * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1638  * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1639  * XferNotReady event are invalid. The driver uses this number to schedule the
1640  * isochronous transfer and passes it to the START TRANSFER command. Because
1641  * this number is invalid, the command may fail. If BIT[15:14] matches the
1642  * internal 16-bit microframe, the START TRANSFER command will pass and the
1643  * transfer will start at the scheduled time, if it is off by 1, the command
1644  * will still pass, but the transfer will start 2 seconds in the future. For all
1645  * other conditions, the START TRANSFER command will fail with bus-expiry.
1646  *
1647  * In order to workaround this issue, we can test for the correct combination of
1648  * BIT[15:14] by sending START TRANSFER commands with different values of
1649  * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1650  * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1651  * As the result, within the 4 possible combinations for BIT[15:14], there will
1652  * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1653  * command status will result in a 2-second delay start. The smaller BIT[15:14]
1654  * value is the correct combination.
1655  *
1656  * Since there are only 4 outcomes and the results are ordered, we can simply
1657  * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1658  * deduce the smaller successful combination.
1659  *
1660  * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1661  * of BIT[15:14]. The correct combination is as follow:
1662  *
1663  * if test0 fails and test1 passes, BIT[15:14] is 'b01
1664  * if test0 fails and test1 fails, BIT[15:14] is 'b10
1665  * if test0 passes and test1 fails, BIT[15:14] is 'b11
1666  * if test0 passes and test1 passes, BIT[15:14] is 'b00
1667  *
1668  * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1669  * endpoints.
1670  */
1671 static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1672 {
1673         int cmd_status = 0;
1674         bool test0;
1675         bool test1;
1676
1677         while (dep->combo_num < 2) {
1678                 struct dwc3_gadget_ep_cmd_params params;
1679                 u32 test_frame_number;
1680                 u32 cmd;
1681
1682                 /*
1683                  * Check if we can start isoc transfer on the next interval or
1684                  * 4 uframes in the future with BIT[15:14] as dep->combo_num
1685                  */
1686                 test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK;
1687                 test_frame_number |= dep->combo_num << 14;
1688                 test_frame_number += max_t(u32, 4, dep->interval);
1689
1690                 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1691                 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1692
1693                 cmd = DWC3_DEPCMD_STARTTRANSFER;
1694                 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1695                 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1696
1697                 /* Redo if some other failure beside bus-expiry is received */
1698                 if (cmd_status && cmd_status != -EAGAIN) {
1699                         dep->start_cmd_status = 0;
1700                         dep->combo_num = 0;
1701                         return 0;
1702                 }
1703
1704                 /* Store the first test status */
1705                 if (dep->combo_num == 0)
1706                         dep->start_cmd_status = cmd_status;
1707
1708                 dep->combo_num++;
1709
1710                 /*
1711                  * End the transfer if the START_TRANSFER command is successful
1712                  * to wait for the next XferNotReady to test the command again
1713                  */
1714                 if (cmd_status == 0) {
1715                         dwc3_stop_active_transfer(dep, true, true);
1716                         return 0;
1717                 }
1718         }
1719
1720         /* test0 and test1 are both completed at this point */
1721         test0 = (dep->start_cmd_status == 0);
1722         test1 = (cmd_status == 0);
1723
1724         if (!test0 && test1)
1725                 dep->combo_num = 1;
1726         else if (!test0 && !test1)
1727                 dep->combo_num = 2;
1728         else if (test0 && !test1)
1729                 dep->combo_num = 3;
1730         else if (test0 && test1)
1731                 dep->combo_num = 0;
1732
1733         dep->frame_number &= DWC3_FRNUMBER_MASK;
1734         dep->frame_number |= dep->combo_num << 14;
1735         dep->frame_number += max_t(u32, 4, dep->interval);
1736
1737         /* Reinitialize test variables */
1738         dep->start_cmd_status = 0;
1739         dep->combo_num = 0;
1740
1741         return __dwc3_gadget_kick_transfer(dep);
1742 }
1743
1744 static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1745 {
1746         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
1747         struct dwc3 *dwc = dep->dwc;
1748         int ret;
1749         int i;
1750
1751         if (list_empty(&dep->pending_list) &&
1752             list_empty(&dep->started_list)) {
1753                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1754                 return -EAGAIN;
1755         }
1756
1757         if (!dwc->dis_start_transfer_quirk &&
1758             (DWC3_VER_IS_PRIOR(DWC31, 170A) ||
1759              DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) {
1760                 if (dwc->gadget->speed <= USB_SPEED_HIGH && dep->direction)
1761                         return dwc3_gadget_start_isoc_quirk(dep);
1762         }
1763
1764         if (desc->bInterval <= 14 &&
1765             dwc->gadget->speed >= USB_SPEED_HIGH) {
1766                 u32 frame = __dwc3_gadget_get_frame(dwc);
1767                 bool rollover = frame <
1768                                 (dep->frame_number & DWC3_FRNUMBER_MASK);
1769
1770                 /*
1771                  * frame_number is set from XferNotReady and may be already
1772                  * out of date. DSTS only provides the lower 14 bit of the
1773                  * current frame number. So add the upper two bits of
1774                  * frame_number and handle a possible rollover.
1775                  * This will provide the correct frame_number unless more than
1776                  * rollover has happened since XferNotReady.
1777                  */
1778
1779                 dep->frame_number = (dep->frame_number & ~DWC3_FRNUMBER_MASK) |
1780                                      frame;
1781                 if (rollover)
1782                         dep->frame_number += BIT(14);
1783         }
1784
1785         for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1786                 dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1);
1787
1788                 ret = __dwc3_gadget_kick_transfer(dep);
1789                 if (ret != -EAGAIN)
1790                         break;
1791         }
1792
1793         /*
1794          * After a number of unsuccessful start attempts due to bus-expiry
1795          * status, issue END_TRANSFER command and retry on the next XferNotReady
1796          * event.
1797          */
1798         if (ret == -EAGAIN) {
1799                 struct dwc3_gadget_ep_cmd_params params;
1800                 u32 cmd;
1801
1802                 cmd = DWC3_DEPCMD_ENDTRANSFER |
1803                         DWC3_DEPCMD_CMDIOC |
1804                         DWC3_DEPCMD_PARAM(dep->resource_index);
1805
1806                 dep->resource_index = 0;
1807                 memset(&params, 0, sizeof(params));
1808
1809                 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1810                 if (!ret)
1811                         dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
1812         }
1813
1814         return ret;
1815 }
1816
1817 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1818 {
1819         struct dwc3             *dwc = dep->dwc;
1820
1821         if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
1822                 dev_dbg(dwc->dev, "%s: can't queue to disabled endpoint\n",
1823                                 dep->name);
1824                 return -ESHUTDOWN;
1825         }
1826
1827         if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1828                                 &req->request, req->dep->name))
1829                 return -EINVAL;
1830
1831         if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1832                                 "%s: request %pK already in flight\n",
1833                                 dep->name, &req->request))
1834                 return -EINVAL;
1835
1836         pm_runtime_get(dwc->dev);
1837
1838         req->request.actual     = 0;
1839         req->request.status     = -EINPROGRESS;
1840
1841         trace_dwc3_ep_queue(req);
1842
1843         list_add_tail(&req->list, &dep->pending_list);
1844         req->status = DWC3_REQUEST_STATUS_QUEUED;
1845
1846         if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)
1847                 return 0;
1848
1849         /*
1850          * Start the transfer only after the END_TRANSFER is completed
1851          * and endpoint STALL is cleared.
1852          */
1853         if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
1854             (dep->flags & DWC3_EP_WEDGE) ||
1855             (dep->flags & DWC3_EP_STALL)) {
1856                 dep->flags |= DWC3_EP_DELAY_START;
1857                 return 0;
1858         }
1859
1860         /*
1861          * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1862          * wait for a XferNotReady event so we will know what's the current
1863          * (micro-)frame number.
1864          *
1865          * Without this trick, we are very, very likely gonna get Bus Expiry
1866          * errors which will force us issue EndTransfer command.
1867          */
1868         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1869                 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1870                                 !(dep->flags & DWC3_EP_TRANSFER_STARTED))
1871                         return 0;
1872
1873                 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1874                         if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
1875                                 return __dwc3_gadget_start_isoc(dep);
1876                 }
1877         }
1878
1879         __dwc3_gadget_kick_transfer(dep);
1880
1881         return 0;
1882 }
1883
1884 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1885         gfp_t gfp_flags)
1886 {
1887         struct dwc3_request             *req = to_dwc3_request(request);
1888         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1889         struct dwc3                     *dwc = dep->dwc;
1890
1891         unsigned long                   flags;
1892
1893         int                             ret;
1894
1895         spin_lock_irqsave(&dwc->lock, flags);
1896         ret = __dwc3_gadget_ep_queue(dep, req);
1897         spin_unlock_irqrestore(&dwc->lock, flags);
1898
1899         return ret;
1900 }
1901
1902 static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
1903 {
1904         int i;
1905
1906         /* If req->trb is not set, then the request has not started */
1907         if (!req->trb)
1908                 return;
1909
1910         /*
1911          * If request was already started, this means we had to
1912          * stop the transfer. With that we also need to ignore
1913          * all TRBs used by the request, however TRBs can only
1914          * be modified after completion of END_TRANSFER
1915          * command. So what we do here is that we wait for
1916          * END_TRANSFER completion and only after that, we jump
1917          * over TRBs by clearing HWO and incrementing dequeue
1918          * pointer.
1919          */
1920         for (i = 0; i < req->num_trbs; i++) {
1921                 struct dwc3_trb *trb;
1922
1923                 trb = &dep->trb_pool[dep->trb_dequeue];
1924                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1925                 dwc3_ep_inc_deq(dep);
1926         }
1927
1928         req->num_trbs = 0;
1929 }
1930
1931 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
1932 {
1933         struct dwc3_request             *req;
1934         struct dwc3_request             *tmp;
1935         struct dwc3                     *dwc = dep->dwc;
1936
1937         list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) {
1938                 dwc3_gadget_ep_skip_trbs(dep, req);
1939                 switch (req->status) {
1940                 case DWC3_REQUEST_STATUS_DISCONNECTED:
1941                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
1942                         break;
1943                 case DWC3_REQUEST_STATUS_DEQUEUED:
1944                         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1945                         break;
1946                 case DWC3_REQUEST_STATUS_STALLED:
1947                         dwc3_gadget_giveback(dep, req, -EPIPE);
1948                         break;
1949                 default:
1950                         dev_err(dwc->dev, "request cancelled with wrong reason:%d\n", req->status);
1951                         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1952                         break;
1953                 }
1954         }
1955 }
1956
1957 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1958                 struct usb_request *request)
1959 {
1960         struct dwc3_request             *req = to_dwc3_request(request);
1961         struct dwc3_request             *r = NULL;
1962
1963         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1964         struct dwc3                     *dwc = dep->dwc;
1965
1966         unsigned long                   flags;
1967         int                             ret = 0;
1968
1969         trace_dwc3_ep_dequeue(req);
1970
1971         spin_lock_irqsave(&dwc->lock, flags);
1972
1973         list_for_each_entry(r, &dep->cancelled_list, list) {
1974                 if (r == req)
1975                         goto out;
1976         }
1977
1978         list_for_each_entry(r, &dep->pending_list, list) {
1979                 if (r == req) {
1980                         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1981                         goto out;
1982                 }
1983         }
1984
1985         list_for_each_entry(r, &dep->started_list, list) {
1986                 if (r == req) {
1987                         struct dwc3_request *t;
1988
1989                         /* wait until it is processed */
1990                         dwc3_stop_active_transfer(dep, true, true);
1991
1992                         /*
1993                          * Remove any started request if the transfer is
1994                          * cancelled.
1995                          */
1996                         list_for_each_entry_safe(r, t, &dep->started_list, list)
1997                                 dwc3_gadget_move_cancelled_request(r,
1998                                                 DWC3_REQUEST_STATUS_DEQUEUED);
1999
2000                         dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
2001
2002                         goto out;
2003                 }
2004         }
2005
2006         dev_err(dwc->dev, "request %pK was not queued to %s\n",
2007                 request, ep->name);
2008         ret = -EINVAL;
2009 out:
2010         spin_unlock_irqrestore(&dwc->lock, flags);
2011
2012         return ret;
2013 }
2014
2015 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
2016 {
2017         struct dwc3_gadget_ep_cmd_params        params;
2018         struct dwc3                             *dwc = dep->dwc;
2019         struct dwc3_request                     *req;
2020         struct dwc3_request                     *tmp;
2021         int                                     ret;
2022
2023         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2024                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
2025                 return -EINVAL;
2026         }
2027
2028         memset(&params, 0x00, sizeof(params));
2029
2030         if (value) {
2031                 struct dwc3_trb *trb;
2032
2033                 unsigned int transfer_in_flight;
2034                 unsigned int started;
2035
2036                 if (dep->number > 1)
2037                         trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
2038                 else
2039                         trb = &dwc->ep0_trb[dep->trb_enqueue];
2040
2041                 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
2042                 started = !list_empty(&dep->started_list);
2043
2044                 if (!protocol && ((dep->direction && transfer_in_flight) ||
2045                                 (!dep->direction && started))) {
2046                         return -EAGAIN;
2047                 }
2048
2049                 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
2050                                 &params);
2051                 if (ret)
2052                         dev_err(dwc->dev, "failed to set STALL on %s\n",
2053                                         dep->name);
2054                 else
2055                         dep->flags |= DWC3_EP_STALL;
2056         } else {
2057                 /*
2058                  * Don't issue CLEAR_STALL command to control endpoints. The
2059                  * controller automatically clears the STALL when it receives
2060                  * the SETUP token.
2061                  */
2062                 if (dep->number <= 1) {
2063                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2064                         return 0;
2065                 }
2066
2067                 dwc3_stop_active_transfer(dep, true, true);
2068
2069                 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
2070                         dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_STALLED);
2071
2072                 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) {
2073                         dep->flags |= DWC3_EP_PENDING_CLEAR_STALL;
2074                         return 0;
2075                 }
2076
2077                 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2078
2079                 ret = dwc3_send_clear_stall_ep_cmd(dep);
2080                 if (ret) {
2081                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
2082                                         dep->name);
2083                         return ret;
2084                 }
2085
2086                 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2087
2088                 if ((dep->flags & DWC3_EP_DELAY_START) &&
2089                     !usb_endpoint_xfer_isoc(dep->endpoint.desc))
2090                         __dwc3_gadget_kick_transfer(dep);
2091
2092                 dep->flags &= ~DWC3_EP_DELAY_START;
2093         }
2094
2095         return ret;
2096 }
2097
2098 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
2099 {
2100         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
2101         struct dwc3                     *dwc = dep->dwc;
2102
2103         unsigned long                   flags;
2104
2105         int                             ret;
2106
2107         spin_lock_irqsave(&dwc->lock, flags);
2108         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
2109         spin_unlock_irqrestore(&dwc->lock, flags);
2110
2111         return ret;
2112 }
2113
2114 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
2115 {
2116         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
2117         struct dwc3                     *dwc = dep->dwc;
2118         unsigned long                   flags;
2119         int                             ret;
2120
2121         spin_lock_irqsave(&dwc->lock, flags);
2122         dep->flags |= DWC3_EP_WEDGE;
2123
2124         if (dep->number == 0 || dep->number == 1)
2125                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
2126         else
2127                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
2128         spin_unlock_irqrestore(&dwc->lock, flags);
2129
2130         return ret;
2131 }
2132
2133 /* -------------------------------------------------------------------------- */
2134
2135 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
2136         .bLength        = USB_DT_ENDPOINT_SIZE,
2137         .bDescriptorType = USB_DT_ENDPOINT,
2138         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
2139 };
2140
2141 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
2142         .enable         = dwc3_gadget_ep0_enable,
2143         .disable        = dwc3_gadget_ep0_disable,
2144         .alloc_request  = dwc3_gadget_ep_alloc_request,
2145         .free_request   = dwc3_gadget_ep_free_request,
2146         .queue          = dwc3_gadget_ep0_queue,
2147         .dequeue        = dwc3_gadget_ep_dequeue,
2148         .set_halt       = dwc3_gadget_ep0_set_halt,
2149         .set_wedge      = dwc3_gadget_ep_set_wedge,
2150 };
2151
2152 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
2153         .enable         = dwc3_gadget_ep_enable,
2154         .disable        = dwc3_gadget_ep_disable,
2155         .alloc_request  = dwc3_gadget_ep_alloc_request,
2156         .free_request   = dwc3_gadget_ep_free_request,
2157         .queue          = dwc3_gadget_ep_queue,
2158         .dequeue        = dwc3_gadget_ep_dequeue,
2159         .set_halt       = dwc3_gadget_ep_set_halt,
2160         .set_wedge      = dwc3_gadget_ep_set_wedge,
2161 };
2162
2163 /* -------------------------------------------------------------------------- */
2164
2165 static int dwc3_gadget_get_frame(struct usb_gadget *g)
2166 {
2167         struct dwc3             *dwc = gadget_to_dwc(g);
2168
2169         return __dwc3_gadget_get_frame(dwc);
2170 }
2171
2172 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
2173 {
2174         int                     retries;
2175
2176         int                     ret;
2177         u32                     reg;
2178
2179         u8                      link_state;
2180
2181         /*
2182          * According to the Databook Remote wakeup request should
2183          * be issued only when the device is in early suspend state.
2184          *
2185          * We can check that via USB Link State bits in DSTS register.
2186          */
2187         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2188
2189         link_state = DWC3_DSTS_USBLNKST(reg);
2190
2191         switch (link_state) {
2192         case DWC3_LINK_STATE_RESET:
2193         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
2194         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
2195         case DWC3_LINK_STATE_U2:        /* in HS, means Sleep (L1) */
2196         case DWC3_LINK_STATE_U1:
2197         case DWC3_LINK_STATE_RESUME:
2198                 break;
2199         default:
2200                 return -EINVAL;
2201         }
2202
2203         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
2204         if (ret < 0) {
2205                 dev_err(dwc->dev, "failed to put link in Recovery\n");
2206                 return ret;
2207         }
2208
2209         /* Recent versions do this automatically */
2210         if (DWC3_VER_IS_PRIOR(DWC3, 194A)) {
2211                 /* write zeroes to Link Change Request */
2212                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2213                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
2214                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2215         }
2216
2217         /* poll until Link State changes to ON */
2218         retries = 20000;
2219
2220         while (retries--) {
2221                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2222
2223                 /* in HS, means ON */
2224                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
2225                         break;
2226         }
2227
2228         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
2229                 dev_err(dwc->dev, "failed to send remote wakeup\n");
2230                 return -EINVAL;
2231         }
2232
2233         return 0;
2234 }
2235
2236 static int dwc3_gadget_wakeup(struct usb_gadget *g)
2237 {
2238         struct dwc3             *dwc = gadget_to_dwc(g);
2239         unsigned long           flags;
2240         int                     ret;
2241
2242         spin_lock_irqsave(&dwc->lock, flags);
2243         ret = __dwc3_gadget_wakeup(dwc);
2244         spin_unlock_irqrestore(&dwc->lock, flags);
2245
2246         return ret;
2247 }
2248
2249 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
2250                 int is_selfpowered)
2251 {
2252         struct dwc3             *dwc = gadget_to_dwc(g);
2253         unsigned long           flags;
2254
2255         spin_lock_irqsave(&dwc->lock, flags);
2256         g->is_selfpowered = !!is_selfpowered;
2257         spin_unlock_irqrestore(&dwc->lock, flags);
2258
2259         return 0;
2260 }
2261
2262 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2263 {
2264         u32 epnum;
2265
2266         for (epnum = 2; epnum < dwc->num_eps; epnum++) {
2267                 struct dwc3_ep *dep;
2268
2269                 dep = dwc->eps[epnum];
2270                 if (!dep)
2271                         continue;
2272
2273                 dwc3_remove_requests(dwc, dep);
2274         }
2275 }
2276
2277 static void __dwc3_gadget_set_ssp_rate(struct dwc3 *dwc)
2278 {
2279         enum usb_ssp_rate       ssp_rate = dwc->gadget_ssp_rate;
2280         u32                     reg;
2281
2282         if (ssp_rate == USB_SSP_GEN_UNKNOWN)
2283                 ssp_rate = dwc->max_ssp_rate;
2284
2285         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2286         reg &= ~DWC3_DCFG_SPEED_MASK;
2287         reg &= ~DWC3_DCFG_NUMLANES(~0);
2288
2289         if (ssp_rate == USB_SSP_GEN_1x2)
2290                 reg |= DWC3_DCFG_SUPERSPEED;
2291         else if (dwc->max_ssp_rate != USB_SSP_GEN_1x2)
2292                 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2293
2294         if (ssp_rate != USB_SSP_GEN_2x1 &&
2295             dwc->max_ssp_rate != USB_SSP_GEN_2x1)
2296                 reg |= DWC3_DCFG_NUMLANES(1);
2297
2298         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2299 }
2300
2301 static void __dwc3_gadget_set_speed(struct dwc3 *dwc)
2302 {
2303         enum usb_device_speed   speed;
2304         u32                     reg;
2305
2306         speed = dwc->gadget_max_speed;
2307         if (speed == USB_SPEED_UNKNOWN || speed > dwc->maximum_speed)
2308                 speed = dwc->maximum_speed;
2309
2310         if (speed == USB_SPEED_SUPER_PLUS &&
2311             DWC3_IP_IS(DWC32)) {
2312                 __dwc3_gadget_set_ssp_rate(dwc);
2313                 return;
2314         }
2315
2316         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2317         reg &= ~(DWC3_DCFG_SPEED_MASK);
2318
2319         /*
2320          * WORKAROUND: DWC3 revision < 2.20a have an issue
2321          * which would cause metastability state on Run/Stop
2322          * bit if we try to force the IP to USB2-only mode.
2323          *
2324          * Because of that, we cannot configure the IP to any
2325          * speed other than the SuperSpeed
2326          *
2327          * Refers to:
2328          *
2329          * STAR#9000525659: Clock Domain Crossing on DCTL in
2330          * USB 2.0 Mode
2331          */
2332         if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
2333             !dwc->dis_metastability_quirk) {
2334                 reg |= DWC3_DCFG_SUPERSPEED;
2335         } else {
2336                 switch (speed) {
2337                 case USB_SPEED_FULL:
2338                         reg |= DWC3_DCFG_FULLSPEED;
2339                         break;
2340                 case USB_SPEED_HIGH:
2341                         reg |= DWC3_DCFG_HIGHSPEED;
2342                         break;
2343                 case USB_SPEED_SUPER:
2344                         reg |= DWC3_DCFG_SUPERSPEED;
2345                         break;
2346                 case USB_SPEED_SUPER_PLUS:
2347                         if (DWC3_IP_IS(DWC3))
2348                                 reg |= DWC3_DCFG_SUPERSPEED;
2349                         else
2350                                 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2351                         break;
2352                 default:
2353                         dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2354
2355                         if (DWC3_IP_IS(DWC3))
2356                                 reg |= DWC3_DCFG_SUPERSPEED;
2357                         else
2358                                 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2359                 }
2360         }
2361
2362         if (DWC3_IP_IS(DWC32) &&
2363             speed > USB_SPEED_UNKNOWN &&
2364             speed < USB_SPEED_SUPER_PLUS)
2365                 reg &= ~DWC3_DCFG_NUMLANES(~0);
2366
2367         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2368 }
2369
2370 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
2371 {
2372         u32                     reg;
2373         u32                     timeout = 500;
2374
2375         if (pm_runtime_suspended(dwc->dev))
2376                 return 0;
2377
2378         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2379         if (is_on) {
2380                 if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) {
2381                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
2382                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
2383                 }
2384
2385                 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
2386                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
2387                 reg |= DWC3_DCTL_RUN_STOP;
2388
2389                 if (dwc->has_hibernation)
2390                         reg |= DWC3_DCTL_KEEP_CONNECT;
2391
2392                 __dwc3_gadget_set_speed(dwc);
2393                 dwc->pullups_connected = true;
2394         } else {
2395                 reg &= ~DWC3_DCTL_RUN_STOP;
2396
2397                 if (dwc->has_hibernation && !suspend)
2398                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
2399
2400                 dwc->pullups_connected = false;
2401         }
2402
2403         dwc3_gadget_dctl_write_safe(dwc, reg);
2404
2405         do {
2406                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2407                 reg &= DWC3_DSTS_DEVCTRLHLT;
2408         } while (--timeout && !(!is_on ^ !reg));
2409
2410         if (!timeout)
2411                 return -ETIMEDOUT;
2412
2413         return 0;
2414 }
2415
2416 static void dwc3_gadget_disable_irq(struct dwc3 *dwc);
2417 static void __dwc3_gadget_stop(struct dwc3 *dwc);
2418 static int __dwc3_gadget_start(struct dwc3 *dwc);
2419
2420 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
2421 {
2422         struct dwc3             *dwc = gadget_to_dwc(g);
2423         unsigned long           flags;
2424         int                     ret;
2425
2426         is_on = !!is_on;
2427         dwc->softconnect = is_on;
2428         /*
2429          * Per databook, when we want to stop the gadget, if a control transfer
2430          * is still in process, complete it and get the core into setup phase.
2431          */
2432         if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
2433                 reinit_completion(&dwc->ep0_in_setup);
2434
2435                 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
2436                                 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
2437                 if (ret == 0)
2438                         dev_warn(dwc->dev, "timed out waiting for SETUP phase\n");
2439         }
2440
2441         /*
2442          * Avoid issuing a runtime resume if the device is already in the
2443          * suspended state during gadget disconnect.  DWC3 gadget was already
2444          * halted/stopped during runtime suspend.
2445          */
2446         if (!is_on) {
2447                 pm_runtime_barrier(dwc->dev);
2448                 if (pm_runtime_suspended(dwc->dev))
2449                         return 0;
2450         }
2451
2452         /*
2453          * Check the return value for successful resume, or error.  For a
2454          * successful resume, the DWC3 runtime PM resume routine will handle
2455          * the run stop sequence, so avoid duplicate operations here.
2456          */
2457         ret = pm_runtime_get_sync(dwc->dev);
2458         if (!ret || ret < 0) {
2459                 pm_runtime_put(dwc->dev);
2460                 return 0;
2461         }
2462
2463         /*
2464          * Synchronize and disable any further event handling while controller
2465          * is being enabled/disabled.
2466          */
2467         disable_irq(dwc->irq_gadget);
2468
2469         spin_lock_irqsave(&dwc->lock, flags);
2470
2471         if (!is_on) {
2472                 u32 count;
2473
2474                 dwc->connected = false;
2475                 /*
2476                  * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
2477                  * Section 4.1.8 Table 4-7, it states that for a device-initiated
2478                  * disconnect, the SW needs to ensure that it sends "a DEPENDXFER
2479                  * command for any active transfers" before clearing the RunStop
2480                  * bit.
2481                  */
2482                 dwc3_stop_active_transfers(dwc);
2483                 __dwc3_gadget_stop(dwc);
2484
2485                 /*
2486                  * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
2487                  * Section 1.3.4, it mentions that for the DEVCTRLHLT bit, the
2488                  * "software needs to acknowledge the events that are generated
2489                  * (by writing to GEVNTCOUNTn) while it is waiting for this bit
2490                  * to be set to '1'."
2491                  */
2492                 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2493                 count &= DWC3_GEVNTCOUNT_MASK;
2494                 if (count > 0) {
2495                         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
2496                         dwc->ev_buf->lpos = (dwc->ev_buf->lpos + count) %
2497                                                 dwc->ev_buf->length;
2498                 }
2499         } else {
2500                 __dwc3_gadget_start(dwc);
2501         }
2502
2503         ret = dwc3_gadget_run_stop(dwc, is_on, false);
2504         spin_unlock_irqrestore(&dwc->lock, flags);
2505         enable_irq(dwc->irq_gadget);
2506
2507         pm_runtime_put(dwc->dev);
2508
2509         return ret;
2510 }
2511
2512 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
2513 {
2514         u32                     reg;
2515
2516         /* Enable all but Start and End of Frame IRQs */
2517         reg = (DWC3_DEVTEN_EVNTOVERFLOWEN |
2518                         DWC3_DEVTEN_CMDCMPLTEN |
2519                         DWC3_DEVTEN_ERRTICERREN |
2520                         DWC3_DEVTEN_WKUPEVTEN |
2521                         DWC3_DEVTEN_CONNECTDONEEN |
2522                         DWC3_DEVTEN_USBRSTEN |
2523                         DWC3_DEVTEN_DISCONNEVTEN);
2524
2525         if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2526                 reg |= DWC3_DEVTEN_ULSTCNGEN;
2527
2528         /* On 2.30a and above this bit enables U3/L2-L1 Suspend Events */
2529         if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
2530                 reg |= DWC3_DEVTEN_U3L2L1SUSPEN;
2531
2532         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2533 }
2534
2535 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
2536 {
2537         /* mask all interrupts */
2538         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2539 }
2540
2541 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
2542 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
2543
2544 /**
2545  * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
2546  * @dwc: pointer to our context structure
2547  *
2548  * The following looks like complex but it's actually very simple. In order to
2549  * calculate the number of packets we can burst at once on OUT transfers, we're
2550  * gonna use RxFIFO size.
2551  *
2552  * To calculate RxFIFO size we need two numbers:
2553  * MDWIDTH = size, in bits, of the internal memory bus
2554  * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
2555  *
2556  * Given these two numbers, the formula is simple:
2557  *
2558  * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
2559  *
2560  * 24 bytes is for 3x SETUP packets
2561  * 16 bytes is a clock domain crossing tolerance
2562  *
2563  * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
2564  */
2565 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
2566 {
2567         u32 ram2_depth;
2568         u32 mdwidth;
2569         u32 nump;
2570         u32 reg;
2571
2572         ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
2573         mdwidth = dwc3_mdwidth(dwc);
2574
2575         nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
2576         nump = min_t(u32, nump, 16);
2577
2578         /* update NumP */
2579         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2580         reg &= ~DWC3_DCFG_NUMP_MASK;
2581         reg |= nump << DWC3_DCFG_NUMP_SHIFT;
2582         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2583 }
2584
2585 static int __dwc3_gadget_start(struct dwc3 *dwc)
2586 {
2587         struct dwc3_ep          *dep;
2588         int                     ret = 0;
2589         u32                     reg;
2590
2591         /*
2592          * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
2593          * the core supports IMOD, disable it.
2594          */
2595         if (dwc->imod_interval) {
2596                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2597                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2598         } else if (dwc3_has_imod(dwc)) {
2599                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
2600         }
2601
2602         /*
2603          * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
2604          * field instead of letting dwc3 itself calculate that automatically.
2605          *
2606          * This way, we maximize the chances that we'll be able to get several
2607          * bursts of data without going through any sort of endpoint throttling.
2608          */
2609         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
2610         if (DWC3_IP_IS(DWC3))
2611                 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
2612         else
2613                 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
2614
2615         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
2616
2617         dwc3_gadget_setup_nump(dwc);
2618
2619         /*
2620          * Currently the controller handles single stream only. So, Ignore
2621          * Packet Pending bit for stream selection and don't search for another
2622          * stream if the host sends Data Packet with PP=0 (for OUT direction) or
2623          * ACK with NumP=0 and PP=0 (for IN direction). This slightly improves
2624          * the stream performance.
2625          */
2626         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2627         reg |= DWC3_DCFG_IGNSTRMPP;
2628         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2629
2630         /* Start with SuperSpeed Default */
2631         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2632
2633         dep = dwc->eps[0];
2634         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2635         if (ret) {
2636                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2637                 goto err0;
2638         }
2639
2640         dep = dwc->eps[1];
2641         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2642         if (ret) {
2643                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2644                 goto err1;
2645         }
2646
2647         /* begin to receive SETUP packets */
2648         dwc->ep0state = EP0_SETUP_PHASE;
2649         dwc->link_state = DWC3_LINK_STATE_SS_DIS;
2650         dwc->delayed_status = false;
2651         dwc3_ep0_out_start(dwc);
2652
2653         dwc3_gadget_enable_irq(dwc);
2654
2655         return 0;
2656
2657 err1:
2658         __dwc3_gadget_ep_disable(dwc->eps[0]);
2659
2660 err0:
2661         return ret;
2662 }
2663
2664 static int dwc3_gadget_start(struct usb_gadget *g,
2665                 struct usb_gadget_driver *driver)
2666 {
2667         struct dwc3             *dwc = gadget_to_dwc(g);
2668         unsigned long           flags;
2669         int                     ret;
2670         int                     irq;
2671
2672         irq = dwc->irq_gadget;
2673         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2674                         IRQF_SHARED, "dwc3", dwc->ev_buf);
2675         if (ret) {
2676                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2677                                 irq, ret);
2678                 return ret;
2679         }
2680
2681         spin_lock_irqsave(&dwc->lock, flags);
2682         dwc->gadget_driver      = driver;
2683         spin_unlock_irqrestore(&dwc->lock, flags);
2684
2685         return 0;
2686 }
2687
2688 static void __dwc3_gadget_stop(struct dwc3 *dwc)
2689 {
2690         dwc3_gadget_disable_irq(dwc);
2691         __dwc3_gadget_ep_disable(dwc->eps[0]);
2692         __dwc3_gadget_ep_disable(dwc->eps[1]);
2693 }
2694
2695 static int dwc3_gadget_stop(struct usb_gadget *g)
2696 {
2697         struct dwc3             *dwc = gadget_to_dwc(g);
2698         unsigned long           flags;
2699
2700         spin_lock_irqsave(&dwc->lock, flags);
2701         dwc->gadget_driver      = NULL;
2702         dwc->max_cfg_eps = 0;
2703         spin_unlock_irqrestore(&dwc->lock, flags);
2704
2705         free_irq(dwc->irq_gadget, dwc->ev_buf);
2706
2707         return 0;
2708 }
2709
2710 static void dwc3_gadget_config_params(struct usb_gadget *g,
2711                                       struct usb_dcd_config_params *params)
2712 {
2713         struct dwc3             *dwc = gadget_to_dwc(g);
2714
2715         params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
2716         params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
2717
2718         /* Recommended BESL */
2719         if (!dwc->dis_enblslpm_quirk) {
2720                 /*
2721                  * If the recommended BESL baseline is 0 or if the BESL deep is
2722                  * less than 2, Microsoft's Windows 10 host usb stack will issue
2723                  * a usb reset immediately after it receives the extended BOS
2724                  * descriptor and the enumeration will fail. To maintain
2725                  * compatibility with the Windows' usb stack, let's set the
2726                  * recommended BESL baseline to 1 and clamp the BESL deep to be
2727                  * within 2 to 15.
2728                  */
2729                 params->besl_baseline = 1;
2730                 if (dwc->is_utmi_l1_suspend)
2731                         params->besl_deep =
2732                                 clamp_t(u8, dwc->hird_threshold, 2, 15);
2733         }
2734
2735         /* U1 Device exit Latency */
2736         if (dwc->dis_u1_entry_quirk)
2737                 params->bU1devExitLat = 0;
2738         else
2739                 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
2740
2741         /* U2 Device exit Latency */
2742         if (dwc->dis_u2_entry_quirk)
2743                 params->bU2DevExitLat = 0;
2744         else
2745                 params->bU2DevExitLat =
2746                                 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
2747 }
2748
2749 static void dwc3_gadget_set_speed(struct usb_gadget *g,
2750                                   enum usb_device_speed speed)
2751 {
2752         struct dwc3             *dwc = gadget_to_dwc(g);
2753         unsigned long           flags;
2754
2755         spin_lock_irqsave(&dwc->lock, flags);
2756         dwc->gadget_max_speed = speed;
2757         spin_unlock_irqrestore(&dwc->lock, flags);
2758 }
2759
2760 static void dwc3_gadget_set_ssp_rate(struct usb_gadget *g,
2761                                      enum usb_ssp_rate rate)
2762 {
2763         struct dwc3             *dwc = gadget_to_dwc(g);
2764         unsigned long           flags;
2765
2766         spin_lock_irqsave(&dwc->lock, flags);
2767         dwc->gadget_max_speed = USB_SPEED_SUPER_PLUS;
2768         dwc->gadget_ssp_rate = rate;
2769         spin_unlock_irqrestore(&dwc->lock, flags);
2770 }
2771
2772 static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA)
2773 {
2774         struct dwc3             *dwc = gadget_to_dwc(g);
2775         union power_supply_propval      val = {0};
2776         int                             ret;
2777
2778         if (dwc->usb2_phy)
2779                 return usb_phy_set_power(dwc->usb2_phy, mA);
2780
2781         if (!dwc->usb_psy)
2782                 return -EOPNOTSUPP;
2783
2784         val.intval = 1000 * mA;
2785         ret = power_supply_set_property(dwc->usb_psy, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val);
2786
2787         return ret;
2788 }
2789
2790 /**
2791  * dwc3_gadget_check_config - ensure dwc3 can support the USB configuration
2792  * @g: pointer to the USB gadget
2793  *
2794  * Used to record the maximum number of endpoints being used in a USB composite
2795  * device. (across all configurations)  This is to be used in the calculation
2796  * of the TXFIFO sizes when resizing internal memory for individual endpoints.
2797  * It will help ensured that the resizing logic reserves enough space for at
2798  * least one max packet.
2799  */
2800 static int dwc3_gadget_check_config(struct usb_gadget *g)
2801 {
2802         struct dwc3 *dwc = gadget_to_dwc(g);
2803         struct usb_ep *ep;
2804         int fifo_size = 0;
2805         int ram1_depth;
2806         int ep_num = 0;
2807
2808         if (!dwc->do_fifo_resize)
2809                 return 0;
2810
2811         list_for_each_entry(ep, &g->ep_list, ep_list) {
2812                 /* Only interested in the IN endpoints */
2813                 if (ep->claimed && (ep->address & USB_DIR_IN))
2814                         ep_num++;
2815         }
2816
2817         if (ep_num <= dwc->max_cfg_eps)
2818                 return 0;
2819
2820         /* Update the max number of eps in the composition */
2821         dwc->max_cfg_eps = ep_num;
2822
2823         fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps);
2824         /* Based on the equation, increment by one for every ep */
2825         fifo_size += dwc->max_cfg_eps;
2826
2827         /* Check if we can fit a single fifo per endpoint */
2828         ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
2829         if (fifo_size > ram1_depth)
2830                 return -ENOMEM;
2831
2832         return 0;
2833 }
2834
2835 static void dwc3_gadget_async_callbacks(struct usb_gadget *g, bool enable)
2836 {
2837         struct dwc3             *dwc = gadget_to_dwc(g);
2838         unsigned long           flags;
2839
2840         spin_lock_irqsave(&dwc->lock, flags);
2841         dwc->async_callbacks = enable;
2842         spin_unlock_irqrestore(&dwc->lock, flags);
2843 }
2844
2845 static const struct usb_gadget_ops dwc3_gadget_ops = {
2846         .get_frame              = dwc3_gadget_get_frame,
2847         .wakeup                 = dwc3_gadget_wakeup,
2848         .set_selfpowered        = dwc3_gadget_set_selfpowered,
2849         .pullup                 = dwc3_gadget_pullup,
2850         .udc_start              = dwc3_gadget_start,
2851         .udc_stop               = dwc3_gadget_stop,
2852         .udc_set_speed          = dwc3_gadget_set_speed,
2853         .udc_set_ssp_rate       = dwc3_gadget_set_ssp_rate,
2854         .get_config_params      = dwc3_gadget_config_params,
2855         .vbus_draw              = dwc3_gadget_vbus_draw,
2856         .check_config           = dwc3_gadget_check_config,
2857         .udc_async_callbacks    = dwc3_gadget_async_callbacks,
2858 };
2859
2860 /* -------------------------------------------------------------------------- */
2861
2862 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2863 {
2864         struct dwc3 *dwc = dep->dwc;
2865
2866         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2867         dep->endpoint.maxburst = 1;
2868         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2869         if (!dep->direction)
2870                 dwc->gadget->ep0 = &dep->endpoint;
2871
2872         dep->endpoint.caps.type_control = true;
2873
2874         return 0;
2875 }
2876
2877 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2878 {
2879         struct dwc3 *dwc = dep->dwc;
2880         u32 mdwidth;
2881         int size;
2882
2883         mdwidth = dwc3_mdwidth(dwc);
2884
2885         /* MDWIDTH is represented in bits, we need it in bytes */
2886         mdwidth /= 8;
2887
2888         size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2889         if (DWC3_IP_IS(DWC3))
2890                 size = DWC3_GTXFIFOSIZ_TXFDEP(size);
2891         else
2892                 size = DWC31_GTXFIFOSIZ_TXFDEP(size);
2893
2894         /* FIFO Depth is in MDWDITH bytes. Multiply */
2895         size *= mdwidth;
2896
2897         /*
2898          * To meet performance requirement, a minimum TxFIFO size of 3x
2899          * MaxPacketSize is recommended for endpoints that support burst and a
2900          * minimum TxFIFO size of 2x MaxPacketSize for endpoints that don't
2901          * support burst. Use those numbers and we can calculate the max packet
2902          * limit as below.
2903          */
2904         if (dwc->maximum_speed >= USB_SPEED_SUPER)
2905                 size /= 3;
2906         else
2907                 size /= 2;
2908
2909         usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2910
2911         dep->endpoint.max_streams = 16;
2912         dep->endpoint.ops = &dwc3_gadget_ep_ops;
2913         list_add_tail(&dep->endpoint.ep_list,
2914                         &dwc->gadget->ep_list);
2915         dep->endpoint.caps.type_iso = true;
2916         dep->endpoint.caps.type_bulk = true;
2917         dep->endpoint.caps.type_int = true;
2918
2919         return dwc3_alloc_trb_pool(dep);
2920 }
2921
2922 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2923 {
2924         struct dwc3 *dwc = dep->dwc;
2925         u32 mdwidth;
2926         int size;
2927
2928         mdwidth = dwc3_mdwidth(dwc);
2929
2930         /* MDWIDTH is represented in bits, convert to bytes */
2931         mdwidth /= 8;
2932
2933         /* All OUT endpoints share a single RxFIFO space */
2934         size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0));
2935         if (DWC3_IP_IS(DWC3))
2936                 size = DWC3_GRXFIFOSIZ_RXFDEP(size);
2937         else
2938                 size = DWC31_GRXFIFOSIZ_RXFDEP(size);
2939
2940         /* FIFO depth is in MDWDITH bytes */
2941         size *= mdwidth;
2942
2943         /*
2944          * To meet performance requirement, a minimum recommended RxFIFO size
2945          * is defined as follow:
2946          * RxFIFO size >= (3 x MaxPacketSize) +
2947          * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin)
2948          *
2949          * Then calculate the max packet limit as below.
2950          */
2951         size -= (3 * 8) + 16;
2952         if (size < 0)
2953                 size = 0;
2954         else
2955                 size /= 3;
2956
2957         usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2958         dep->endpoint.max_streams = 16;
2959         dep->endpoint.ops = &dwc3_gadget_ep_ops;
2960         list_add_tail(&dep->endpoint.ep_list,
2961                         &dwc->gadget->ep_list);
2962         dep->endpoint.caps.type_iso = true;
2963         dep->endpoint.caps.type_bulk = true;
2964         dep->endpoint.caps.type_int = true;
2965
2966         return dwc3_alloc_trb_pool(dep);
2967 }
2968
2969 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
2970 {
2971         struct dwc3_ep                  *dep;
2972         bool                            direction = epnum & 1;
2973         int                             ret;
2974         u8                              num = epnum >> 1;
2975
2976         dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2977         if (!dep)
2978                 return -ENOMEM;
2979
2980         dep->dwc = dwc;
2981         dep->number = epnum;
2982         dep->direction = direction;
2983         dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2984         dwc->eps[epnum] = dep;
2985         dep->combo_num = 0;
2986         dep->start_cmd_status = 0;
2987
2988         snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2989                         direction ? "in" : "out");
2990
2991         dep->endpoint.name = dep->name;
2992
2993         if (!(dep->number > 1)) {
2994                 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2995                 dep->endpoint.comp_desc = NULL;
2996         }
2997
2998         if (num == 0)
2999                 ret = dwc3_gadget_init_control_endpoint(dep);
3000         else if (direction)
3001                 ret = dwc3_gadget_init_in_endpoint(dep);
3002         else
3003                 ret = dwc3_gadget_init_out_endpoint(dep);
3004
3005         if (ret)
3006                 return ret;
3007
3008         dep->endpoint.caps.dir_in = direction;
3009         dep->endpoint.caps.dir_out = !direction;
3010
3011         INIT_LIST_HEAD(&dep->pending_list);
3012         INIT_LIST_HEAD(&dep->started_list);
3013         INIT_LIST_HEAD(&dep->cancelled_list);
3014
3015         dwc3_debugfs_create_endpoint_dir(dep);
3016
3017         return 0;
3018 }
3019
3020 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
3021 {
3022         u8                              epnum;
3023
3024         INIT_LIST_HEAD(&dwc->gadget->ep_list);
3025
3026         for (epnum = 0; epnum < total; epnum++) {
3027                 int                     ret;
3028
3029                 ret = dwc3_gadget_init_endpoint(dwc, epnum);
3030                 if (ret)
3031                         return ret;
3032         }
3033
3034         return 0;
3035 }
3036
3037 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
3038 {
3039         struct dwc3_ep                  *dep;
3040         u8                              epnum;
3041
3042         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3043                 dep = dwc->eps[epnum];
3044                 if (!dep)
3045                         continue;
3046                 /*
3047                  * Physical endpoints 0 and 1 are special; they form the
3048                  * bi-directional USB endpoint 0.
3049                  *
3050                  * For those two physical endpoints, we don't allocate a TRB
3051                  * pool nor do we add them the endpoints list. Due to that, we
3052                  * shouldn't do these two operations otherwise we would end up
3053                  * with all sorts of bugs when removing dwc3.ko.
3054                  */
3055                 if (epnum != 0 && epnum != 1) {
3056                         dwc3_free_trb_pool(dep);
3057                         list_del(&dep->endpoint.ep_list);
3058                 }
3059
3060                 debugfs_remove_recursive(debugfs_lookup(dep->name,
3061                                 debugfs_lookup(dev_name(dep->dwc->dev),
3062                                                usb_debug_root)));
3063                 kfree(dep);
3064         }
3065 }
3066
3067 /* -------------------------------------------------------------------------- */
3068
3069 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
3070                 struct dwc3_request *req, struct dwc3_trb *trb,
3071                 const struct dwc3_event_depevt *event, int status, int chain)
3072 {
3073         unsigned int            count;
3074
3075         dwc3_ep_inc_deq(dep);
3076
3077         trace_dwc3_complete_trb(dep, trb);
3078         req->num_trbs--;
3079
3080         /*
3081          * If we're in the middle of series of chained TRBs and we
3082          * receive a short transfer along the way, DWC3 will skip
3083          * through all TRBs including the last TRB in the chain (the
3084          * where CHN bit is zero. DWC3 will also avoid clearing HWO
3085          * bit and SW has to do it manually.
3086          *
3087          * We're going to do that here to avoid problems of HW trying
3088          * to use bogus TRBs for transfers.
3089          */
3090         if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
3091                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3092
3093         /*
3094          * For isochronous transfers, the first TRB in a service interval must
3095          * have the Isoc-First type. Track and report its interval frame number.
3096          */
3097         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3098             (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
3099                 unsigned int frame_number;
3100
3101                 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
3102                 frame_number &= ~(dep->interval - 1);
3103                 req->request.frame_number = frame_number;
3104         }
3105
3106         /*
3107          * We use bounce buffer for requests that needs extra TRB or OUT ZLP. If
3108          * this TRB points to the bounce buffer address, it's a MPS alignment
3109          * TRB. Don't add it to req->remaining calculation.
3110          */
3111         if (trb->bpl == lower_32_bits(dep->dwc->bounce_addr) &&
3112             trb->bph == upper_32_bits(dep->dwc->bounce_addr)) {
3113                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3114                 return 1;
3115         }
3116
3117         count = trb->size & DWC3_TRB_SIZE_MASK;
3118         req->remaining += count;
3119
3120         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
3121                 return 1;
3122
3123         if (event->status & DEPEVT_STATUS_SHORT && !chain)
3124                 return 1;
3125
3126         if ((trb->ctrl & DWC3_TRB_CTRL_IOC) ||
3127             (trb->ctrl & DWC3_TRB_CTRL_LST))
3128                 return 1;
3129
3130         return 0;
3131 }
3132
3133 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
3134                 struct dwc3_request *req, const struct dwc3_event_depevt *event,
3135                 int status)
3136 {
3137         struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
3138         struct scatterlist *sg = req->sg;
3139         struct scatterlist *s;
3140         unsigned int num_queued = req->num_queued_sgs;
3141         unsigned int i;
3142         int ret = 0;
3143
3144         for_each_sg(sg, s, num_queued, i) {
3145                 trb = &dep->trb_pool[dep->trb_dequeue];
3146
3147                 req->sg = sg_next(s);
3148                 req->num_queued_sgs--;
3149
3150                 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
3151                                 trb, event, status, true);
3152                 if (ret)
3153                         break;
3154         }
3155
3156         return ret;
3157 }
3158
3159 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
3160                 struct dwc3_request *req, const struct dwc3_event_depevt *event,
3161                 int status)
3162 {
3163         struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
3164
3165         return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
3166                         event, status, false);
3167 }
3168
3169 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
3170 {
3171         return req->num_pending_sgs == 0 && req->num_queued_sgs == 0;
3172 }
3173
3174 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
3175                 const struct dwc3_event_depevt *event,
3176                 struct dwc3_request *req, int status)
3177 {
3178         int ret;
3179
3180         if (req->request.num_mapped_sgs)
3181                 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
3182                                 status);
3183         else
3184                 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
3185                                 status);
3186
3187         req->request.actual = req->request.length - req->remaining;
3188
3189         if (!dwc3_gadget_ep_request_completed(req))
3190                 goto out;
3191
3192         if (req->needs_extra_trb) {
3193                 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
3194                                 status);
3195                 req->needs_extra_trb = false;
3196         }
3197
3198         dwc3_gadget_giveback(dep, req, status);
3199
3200 out:
3201         return ret;
3202 }
3203
3204 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
3205                 const struct dwc3_event_depevt *event, int status)
3206 {
3207         struct dwc3_request     *req;
3208         struct dwc3_request     *tmp;
3209
3210         list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
3211                 int ret;
3212
3213                 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
3214                                 req, status);
3215                 if (ret)
3216                         break;
3217         }
3218 }
3219
3220 static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep)
3221 {
3222         struct dwc3_request     *req;
3223         struct dwc3             *dwc = dep->dwc;
3224
3225         if (!dep->endpoint.desc || !dwc->pullups_connected ||
3226             !dwc->connected)
3227                 return false;
3228
3229         if (!list_empty(&dep->pending_list))
3230                 return true;
3231
3232         /*
3233          * We only need to check the first entry of the started list. We can
3234          * assume the completed requests are removed from the started list.
3235          */
3236         req = next_request(&dep->started_list);
3237         if (!req)
3238                 return false;
3239
3240         return !dwc3_gadget_ep_request_completed(req);
3241 }
3242
3243 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
3244                 const struct dwc3_event_depevt *event)
3245 {
3246         dep->frame_number = event->parameters;
3247 }
3248
3249 static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep,
3250                 const struct dwc3_event_depevt *event, int status)
3251 {
3252         struct dwc3             *dwc = dep->dwc;
3253         bool                    no_started_trb = true;
3254
3255         dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
3256
3257         if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3258                 goto out;
3259
3260         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3261                 list_empty(&dep->started_list) &&
3262                 (list_empty(&dep->pending_list) || status == -EXDEV))
3263                 dwc3_stop_active_transfer(dep, true, true);
3264         else if (dwc3_gadget_ep_should_continue(dep))
3265                 if (__dwc3_gadget_kick_transfer(dep) == 0)
3266                         no_started_trb = false;
3267
3268 out:
3269         /*
3270          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
3271          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
3272          */
3273         if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3274                 u32             reg;
3275                 int             i;
3276
3277                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
3278                         dep = dwc->eps[i];
3279
3280                         if (!(dep->flags & DWC3_EP_ENABLED))
3281                                 continue;
3282
3283                         if (!list_empty(&dep->started_list))
3284                                 return no_started_trb;
3285                 }
3286
3287                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3288                 reg |= dwc->u1u2;
3289                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3290
3291                 dwc->u1u2 = 0;
3292         }
3293
3294         return no_started_trb;
3295 }
3296
3297 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
3298                 const struct dwc3_event_depevt *event)
3299 {
3300         int status = 0;
3301
3302         if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
3303                 dwc3_gadget_endpoint_frame_from_event(dep, event);
3304
3305         if (event->status & DEPEVT_STATUS_BUSERR)
3306                 status = -ECONNRESET;
3307
3308         if (event->status & DEPEVT_STATUS_MISSED_ISOC)
3309                 status = -EXDEV;
3310
3311         dwc3_gadget_endpoint_trbs_complete(dep, event, status);
3312 }
3313
3314 static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep,
3315                 const struct dwc3_event_depevt *event)
3316 {
3317         int status = 0;
3318
3319         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3320
3321         if (event->status & DEPEVT_STATUS_BUSERR)
3322                 status = -ECONNRESET;
3323
3324         if (dwc3_gadget_endpoint_trbs_complete(dep, event, status))
3325                 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
3326 }
3327
3328 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
3329                 const struct dwc3_event_depevt *event)
3330 {
3331         dwc3_gadget_endpoint_frame_from_event(dep, event);
3332
3333         /*
3334          * The XferNotReady event is generated only once before the endpoint
3335          * starts. It will be generated again when END_TRANSFER command is
3336          * issued. For some controller versions, the XferNotReady event may be
3337          * generated while the END_TRANSFER command is still in process. Ignore
3338          * it and wait for the next XferNotReady event after the command is
3339          * completed.
3340          */
3341         if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3342                 return;
3343
3344         (void) __dwc3_gadget_start_isoc(dep);
3345 }
3346
3347 static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep *dep,
3348                 const struct dwc3_event_depevt *event)
3349 {
3350         u8 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
3351
3352         if (cmd != DWC3_DEPCMD_ENDTRANSFER)
3353                 return;
3354
3355         dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
3356         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3357         dwc3_gadget_ep_cleanup_cancelled_requests(dep);
3358
3359         if (dep->flags & DWC3_EP_PENDING_CLEAR_STALL) {
3360                 struct dwc3 *dwc = dep->dwc;
3361
3362                 dep->flags &= ~DWC3_EP_PENDING_CLEAR_STALL;
3363                 if (dwc3_send_clear_stall_ep_cmd(dep)) {
3364                         struct usb_ep *ep0 = &dwc->eps[0]->endpoint;
3365
3366                         dev_err(dwc->dev, "failed to clear STALL on %s\n", dep->name);
3367                         if (dwc->delayed_status)
3368                                 __dwc3_gadget_ep0_set_halt(ep0, 1);
3369                         return;
3370                 }
3371
3372                 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
3373                 if (dwc->delayed_status)
3374                         dwc3_ep0_send_delayed_status(dwc);
3375         }
3376
3377         if ((dep->flags & DWC3_EP_DELAY_START) &&
3378             !usb_endpoint_xfer_isoc(dep->endpoint.desc))
3379                 __dwc3_gadget_kick_transfer(dep);
3380
3381         dep->flags &= ~DWC3_EP_DELAY_START;
3382 }
3383
3384 static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep,
3385                 const struct dwc3_event_depevt *event)
3386 {
3387         struct dwc3 *dwc = dep->dwc;
3388
3389         if (event->status == DEPEVT_STREAMEVT_FOUND) {
3390                 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3391                 goto out;
3392         }
3393
3394         /* Note: NoStream rejection event param value is 0 and not 0xFFFF */
3395         switch (event->parameters) {
3396         case DEPEVT_STREAM_PRIME:
3397                 /*
3398                  * If the host can properly transition the endpoint state from
3399                  * idle to prime after a NoStream rejection, there's no need to
3400                  * force restarting the endpoint to reinitiate the stream. To
3401                  * simplify the check, assume the host follows the USB spec if
3402                  * it primed the endpoint more than once.
3403                  */
3404                 if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) {
3405                         if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED)
3406                                 dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM;
3407                         else
3408                                 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3409                 }
3410
3411                 break;
3412         case DEPEVT_STREAM_NOSTREAM:
3413                 if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) ||
3414                     !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) ||
3415                     !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE))
3416                         break;
3417
3418                 /*
3419                  * If the host rejects a stream due to no active stream, by the
3420                  * USB and xHCI spec, the endpoint will be put back to idle
3421                  * state. When the host is ready (buffer added/updated), it will
3422                  * prime the endpoint to inform the usb device controller. This
3423                  * triggers the device controller to issue ERDY to restart the
3424                  * stream. However, some hosts don't follow this and keep the
3425                  * endpoint in the idle state. No prime will come despite host
3426                  * streams are updated, and the device controller will not be
3427                  * triggered to generate ERDY to move the next stream data. To
3428                  * workaround this and maintain compatibility with various
3429                  * hosts, force to reinitate the stream until the host is ready
3430                  * instead of waiting for the host to prime the endpoint.
3431                  */
3432                 if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) {
3433                         unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME;
3434
3435                         dwc3_send_gadget_generic_command(dwc, cmd, dep->number);
3436                 } else {
3437                         dep->flags |= DWC3_EP_DELAY_START;
3438                         dwc3_stop_active_transfer(dep, true, true);
3439                         return;
3440                 }
3441                 break;
3442         }
3443
3444 out:
3445         dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM;
3446 }
3447
3448 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
3449                 const struct dwc3_event_depevt *event)
3450 {
3451         struct dwc3_ep          *dep;
3452         u8                      epnum = event->endpoint_number;
3453
3454         dep = dwc->eps[epnum];
3455
3456         if (!(dep->flags & DWC3_EP_ENABLED)) {
3457                 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
3458                         return;
3459
3460                 /* Handle only EPCMDCMPLT when EP disabled */
3461                 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
3462                         return;
3463         }
3464
3465         if (epnum == 0 || epnum == 1) {
3466                 dwc3_ep0_interrupt(dwc, event);
3467                 return;
3468         }
3469
3470         switch (event->endpoint_event) {
3471         case DWC3_DEPEVT_XFERINPROGRESS:
3472                 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
3473                 break;
3474         case DWC3_DEPEVT_XFERNOTREADY:
3475                 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
3476                 break;
3477         case DWC3_DEPEVT_EPCMDCMPLT:
3478                 dwc3_gadget_endpoint_command_complete(dep, event);
3479                 break;
3480         case DWC3_DEPEVT_XFERCOMPLETE:
3481                 dwc3_gadget_endpoint_transfer_complete(dep, event);
3482                 break;
3483         case DWC3_DEPEVT_STREAMEVT:
3484                 dwc3_gadget_endpoint_stream_event(dep, event);
3485                 break;
3486         case DWC3_DEPEVT_RXTXFIFOEVT:
3487                 break;
3488         }
3489 }
3490
3491 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
3492 {
3493         if (dwc->async_callbacks && dwc->gadget_driver->disconnect) {
3494                 spin_unlock(&dwc->lock);
3495                 dwc->gadget_driver->disconnect(dwc->gadget);
3496                 spin_lock(&dwc->lock);
3497         }
3498 }
3499
3500 static void dwc3_suspend_gadget(struct dwc3 *dwc)
3501 {
3502         if (dwc->async_callbacks && dwc->gadget_driver->suspend) {
3503                 spin_unlock(&dwc->lock);
3504                 dwc->gadget_driver->suspend(dwc->gadget);
3505                 spin_lock(&dwc->lock);
3506         }
3507 }
3508
3509 static void dwc3_resume_gadget(struct dwc3 *dwc)
3510 {
3511         if (dwc->async_callbacks && dwc->gadget_driver->resume) {
3512                 spin_unlock(&dwc->lock);
3513                 dwc->gadget_driver->resume(dwc->gadget);
3514                 spin_lock(&dwc->lock);
3515         }
3516 }
3517
3518 static void dwc3_reset_gadget(struct dwc3 *dwc)
3519 {
3520         if (!dwc->gadget_driver)
3521                 return;
3522
3523         if (dwc->async_callbacks && dwc->gadget->speed != USB_SPEED_UNKNOWN) {
3524                 spin_unlock(&dwc->lock);
3525                 usb_gadget_udc_reset(dwc->gadget, dwc->gadget_driver);
3526                 spin_lock(&dwc->lock);
3527         }
3528 }
3529
3530 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
3531         bool interrupt)
3532 {
3533         struct dwc3_gadget_ep_cmd_params params;
3534         u32 cmd;
3535         int ret;
3536
3537         if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) ||
3538             (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
3539                 return;
3540
3541         /*
3542          * NOTICE: We are violating what the Databook says about the
3543          * EndTransfer command. Ideally we would _always_ wait for the
3544          * EndTransfer Command Completion IRQ, but that's causing too
3545          * much trouble synchronizing between us and gadget driver.
3546          *
3547          * We have discussed this with the IP Provider and it was
3548          * suggested to giveback all requests here.
3549          *
3550          * Note also that a similar handling was tested by Synopsys
3551          * (thanks a lot Paul) and nothing bad has come out of it.
3552          * In short, what we're doing is issuing EndTransfer with
3553          * CMDIOC bit set and delay kicking transfer until the
3554          * EndTransfer command had completed.
3555          *
3556          * As of IP version 3.10a of the DWC_usb3 IP, the controller
3557          * supports a mode to work around the above limitation. The
3558          * software can poll the CMDACT bit in the DEPCMD register
3559          * after issuing a EndTransfer command. This mode is enabled
3560          * by writing GUCTL2[14]. This polling is already done in the
3561          * dwc3_send_gadget_ep_cmd() function so if the mode is
3562          * enabled, the EndTransfer command will have completed upon
3563          * returning from this function.
3564          *
3565          * This mode is NOT available on the DWC_usb31 IP.
3566          */
3567
3568         cmd = DWC3_DEPCMD_ENDTRANSFER;
3569         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
3570         cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
3571         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3572         memset(&params, 0, sizeof(params));
3573         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
3574         WARN_ON_ONCE(ret);
3575         dep->resource_index = 0;
3576
3577         /*
3578          * The END_TRANSFER command will cause the controller to generate a
3579          * NoStream Event, and it's not due to the host DP NoStream rejection.
3580          * Ignore the next NoStream event.
3581          */
3582         if (dep->stream_capable)
3583                 dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM;
3584
3585         if (!interrupt)
3586                 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3587         else
3588                 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
3589 }
3590
3591 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
3592 {
3593         u32 epnum;
3594
3595         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3596                 struct dwc3_ep *dep;
3597                 int ret;
3598
3599                 dep = dwc->eps[epnum];
3600                 if (!dep)
3601                         continue;
3602
3603                 if (!(dep->flags & DWC3_EP_STALL))
3604                         continue;
3605
3606                 dep->flags &= ~DWC3_EP_STALL;
3607
3608                 ret = dwc3_send_clear_stall_ep_cmd(dep);
3609                 WARN_ON_ONCE(ret);
3610         }
3611 }
3612
3613 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
3614 {
3615         int                     reg;
3616
3617         dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET);
3618
3619         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3620         reg &= ~DWC3_DCTL_INITU1ENA;
3621         reg &= ~DWC3_DCTL_INITU2ENA;
3622         dwc3_gadget_dctl_write_safe(dwc, reg);
3623
3624         dwc3_disconnect_gadget(dwc);
3625
3626         dwc->gadget->speed = USB_SPEED_UNKNOWN;
3627         dwc->setup_packet_pending = false;
3628         usb_gadget_set_state(dwc->gadget, USB_STATE_NOTATTACHED);
3629
3630         dwc->connected = false;
3631 }
3632
3633 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
3634 {
3635         u32                     reg;
3636
3637         /*
3638          * Ideally, dwc3_reset_gadget() would trigger the function
3639          * drivers to stop any active transfers through ep disable.
3640          * However, for functions which defer ep disable, such as mass
3641          * storage, we will need to rely on the call to stop active
3642          * transfers here, and avoid allowing of request queuing.
3643          */
3644         dwc->connected = false;
3645
3646         /*
3647          * WORKAROUND: DWC3 revisions <1.88a have an issue which
3648          * would cause a missing Disconnect Event if there's a
3649          * pending Setup Packet in the FIFO.
3650          *
3651          * There's no suggested workaround on the official Bug
3652          * report, which states that "unless the driver/application
3653          * is doing any special handling of a disconnect event,
3654          * there is no functional issue".
3655          *
3656          * Unfortunately, it turns out that we _do_ some special
3657          * handling of a disconnect event, namely complete all
3658          * pending transfers, notify gadget driver of the
3659          * disconnection, and so on.
3660          *
3661          * Our suggested workaround is to follow the Disconnect
3662          * Event steps here, instead, based on a setup_packet_pending
3663          * flag. Such flag gets set whenever we have a SETUP_PENDING
3664          * status for EP0 TRBs and gets cleared on XferComplete for the
3665          * same endpoint.
3666          *
3667          * Refers to:
3668          *
3669          * STAR#9000466709: RTL: Device : Disconnect event not
3670          * generated if setup packet pending in FIFO
3671          */
3672         if (DWC3_VER_IS_PRIOR(DWC3, 188A)) {
3673                 if (dwc->setup_packet_pending)
3674                         dwc3_gadget_disconnect_interrupt(dwc);
3675         }
3676
3677         dwc3_reset_gadget(dwc);
3678         /*
3679          * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
3680          * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW
3681          * needs to ensure that it sends "a DEPENDXFER command for any active
3682          * transfers."
3683          */
3684         dwc3_stop_active_transfers(dwc);
3685         dwc->connected = true;
3686
3687         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3688         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
3689         dwc3_gadget_dctl_write_safe(dwc, reg);
3690         dwc->test_mode = false;
3691         dwc3_clear_stall_all_ep(dwc);
3692
3693         /* Reset device address to zero */
3694         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3695         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
3696         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3697 }
3698
3699 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
3700 {
3701         struct dwc3_ep          *dep;
3702         int                     ret;
3703         u32                     reg;
3704         u8                      lanes = 1;
3705         u8                      speed;
3706
3707         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
3708         speed = reg & DWC3_DSTS_CONNECTSPD;
3709         dwc->speed = speed;
3710
3711         if (DWC3_IP_IS(DWC32))
3712                 lanes = DWC3_DSTS_CONNLANES(reg) + 1;
3713
3714         dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
3715
3716         /*
3717          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
3718          * each time on Connect Done.
3719          *
3720          * Currently we always use the reset value. If any platform
3721          * wants to set this to a different value, we need to add a
3722          * setting and update GCTL.RAMCLKSEL here.
3723          */
3724
3725         switch (speed) {
3726         case DWC3_DSTS_SUPERSPEED_PLUS:
3727                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3728                 dwc->gadget->ep0->maxpacket = 512;
3729                 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
3730
3731                 if (lanes > 1)
3732                         dwc->gadget->ssp_rate = USB_SSP_GEN_2x2;
3733                 else
3734                         dwc->gadget->ssp_rate = USB_SSP_GEN_2x1;
3735                 break;
3736         case DWC3_DSTS_SUPERSPEED:
3737                 /*
3738                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
3739                  * would cause a missing USB3 Reset event.
3740                  *
3741                  * In such situations, we should force a USB3 Reset
3742                  * event by calling our dwc3_gadget_reset_interrupt()
3743                  * routine.
3744                  *
3745                  * Refers to:
3746                  *
3747                  * STAR#9000483510: RTL: SS : USB3 reset event may
3748                  * not be generated always when the link enters poll
3749                  */
3750                 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
3751                         dwc3_gadget_reset_interrupt(dwc);
3752
3753                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3754                 dwc->gadget->ep0->maxpacket = 512;
3755                 dwc->gadget->speed = USB_SPEED_SUPER;
3756
3757                 if (lanes > 1) {
3758                         dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
3759                         dwc->gadget->ssp_rate = USB_SSP_GEN_1x2;
3760                 }
3761                 break;
3762         case DWC3_DSTS_HIGHSPEED:
3763                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3764                 dwc->gadget->ep0->maxpacket = 64;
3765                 dwc->gadget->speed = USB_SPEED_HIGH;
3766                 break;
3767         case DWC3_DSTS_FULLSPEED:
3768                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3769                 dwc->gadget->ep0->maxpacket = 64;
3770                 dwc->gadget->speed = USB_SPEED_FULL;
3771                 break;
3772         }
3773
3774         dwc->eps[1]->endpoint.maxpacket = dwc->gadget->ep0->maxpacket;
3775
3776         /* Enable USB2 LPM Capability */
3777
3778         if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) &&
3779             !dwc->usb2_gadget_lpm_disable &&
3780             (speed != DWC3_DSTS_SUPERSPEED) &&
3781             (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
3782                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3783                 reg |= DWC3_DCFG_LPM_CAP;
3784                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3785
3786                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3787                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
3788
3789                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
3790                                             (dwc->is_utmi_l1_suspend << 4));
3791
3792                 /*
3793                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
3794                  * DCFG.LPMCap is set, core responses with an ACK and the
3795                  * BESL value in the LPM token is less than or equal to LPM
3796                  * NYET threshold.
3797                  */
3798                 WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum,
3799                                 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
3800
3801                 if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A))
3802                         reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
3803
3804                 dwc3_gadget_dctl_write_safe(dwc, reg);
3805         } else {
3806                 if (dwc->usb2_gadget_lpm_disable) {
3807                         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3808                         reg &= ~DWC3_DCFG_LPM_CAP;
3809                         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3810                 }
3811
3812                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3813                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
3814                 dwc3_gadget_dctl_write_safe(dwc, reg);
3815         }
3816
3817         dep = dwc->eps[0];
3818         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3819         if (ret) {
3820                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3821                 return;
3822         }
3823
3824         dep = dwc->eps[1];
3825         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3826         if (ret) {
3827                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3828                 return;
3829         }
3830
3831         /*
3832          * Configure PHY via GUSB3PIPECTLn if required.
3833          *
3834          * Update GTXFIFOSIZn
3835          *
3836          * In both cases reset values should be sufficient.
3837          */
3838 }
3839
3840 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
3841 {
3842         /*
3843          * TODO take core out of low power mode when that's
3844          * implemented.
3845          */
3846
3847         if (dwc->async_callbacks && dwc->gadget_driver->resume) {
3848                 spin_unlock(&dwc->lock);
3849                 dwc->gadget_driver->resume(dwc->gadget);
3850                 spin_lock(&dwc->lock);
3851         }
3852 }
3853
3854 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
3855                 unsigned int evtinfo)
3856 {
3857         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
3858         unsigned int            pwropt;
3859
3860         /*
3861          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
3862          * Hibernation mode enabled which would show up when device detects
3863          * host-initiated U3 exit.
3864          *
3865          * In that case, device will generate a Link State Change Interrupt
3866          * from U3 to RESUME which is only necessary if Hibernation is
3867          * configured in.
3868          *
3869          * There are no functional changes due to such spurious event and we
3870          * just need to ignore it.
3871          *
3872          * Refers to:
3873          *
3874          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
3875          * operational mode
3876          */
3877         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
3878         if (DWC3_VER_IS_PRIOR(DWC3, 250A) &&
3879                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
3880                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
3881                                 (next == DWC3_LINK_STATE_RESUME)) {
3882                         return;
3883                 }
3884         }
3885
3886         /*
3887          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
3888          * on the link partner, the USB session might do multiple entry/exit
3889          * of low power states before a transfer takes place.
3890          *
3891          * Due to this problem, we might experience lower throughput. The
3892          * suggested workaround is to disable DCTL[12:9] bits if we're
3893          * transitioning from U1/U2 to U0 and enable those bits again
3894          * after a transfer completes and there are no pending transfers
3895          * on any of the enabled endpoints.
3896          *
3897          * This is the first half of that workaround.
3898          *
3899          * Refers to:
3900          *
3901          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
3902          * core send LGO_Ux entering U0
3903          */
3904         if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3905                 if (next == DWC3_LINK_STATE_U0) {
3906                         u32     u1u2;
3907                         u32     reg;
3908
3909                         switch (dwc->link_state) {
3910                         case DWC3_LINK_STATE_U1:
3911                         case DWC3_LINK_STATE_U2:
3912                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3913                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
3914                                                 | DWC3_DCTL_ACCEPTU2ENA
3915                                                 | DWC3_DCTL_INITU1ENA
3916                                                 | DWC3_DCTL_ACCEPTU1ENA);
3917
3918                                 if (!dwc->u1u2)
3919                                         dwc->u1u2 = reg & u1u2;
3920
3921                                 reg &= ~u1u2;
3922
3923                                 dwc3_gadget_dctl_write_safe(dwc, reg);
3924                                 break;
3925                         default:
3926                                 /* do nothing */
3927                                 break;
3928                         }
3929                 }
3930         }
3931
3932         switch (next) {
3933         case DWC3_LINK_STATE_U1:
3934                 if (dwc->speed == USB_SPEED_SUPER)
3935                         dwc3_suspend_gadget(dwc);
3936                 break;
3937         case DWC3_LINK_STATE_U2:
3938         case DWC3_LINK_STATE_U3:
3939                 dwc3_suspend_gadget(dwc);
3940                 break;
3941         case DWC3_LINK_STATE_RESUME:
3942                 dwc3_resume_gadget(dwc);
3943                 break;
3944         default:
3945                 /* do nothing */
3946                 break;
3947         }
3948
3949         dwc->link_state = next;
3950 }
3951
3952 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
3953                                           unsigned int evtinfo)
3954 {
3955         enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3956
3957         if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
3958                 dwc3_suspend_gadget(dwc);
3959
3960         dwc->link_state = next;
3961 }
3962
3963 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
3964                 unsigned int evtinfo)
3965 {
3966         unsigned int is_ss = evtinfo & BIT(4);
3967
3968         /*
3969          * WORKAROUND: DWC3 revison 2.20a with hibernation support
3970          * have a known issue which can cause USB CV TD.9.23 to fail
3971          * randomly.
3972          *
3973          * Because of this issue, core could generate bogus hibernation
3974          * events which SW needs to ignore.
3975          *
3976          * Refers to:
3977          *
3978          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3979          * Device Fallback from SuperSpeed
3980          */
3981         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
3982                 return;
3983
3984         /* enter hibernation here */
3985 }
3986
3987 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
3988                 const struct dwc3_event_devt *event)
3989 {
3990         switch (event->type) {
3991         case DWC3_DEVICE_EVENT_DISCONNECT:
3992                 dwc3_gadget_disconnect_interrupt(dwc);
3993                 break;
3994         case DWC3_DEVICE_EVENT_RESET:
3995                 dwc3_gadget_reset_interrupt(dwc);
3996                 break;
3997         case DWC3_DEVICE_EVENT_CONNECT_DONE:
3998                 dwc3_gadget_conndone_interrupt(dwc);
3999                 break;
4000         case DWC3_DEVICE_EVENT_WAKEUP:
4001                 dwc3_gadget_wakeup_interrupt(dwc);
4002                 break;
4003         case DWC3_DEVICE_EVENT_HIBER_REQ:
4004                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
4005                                         "unexpected hibernation event\n"))
4006                         break;
4007
4008                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
4009                 break;
4010         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
4011                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
4012                 break;
4013         case DWC3_DEVICE_EVENT_SUSPEND:
4014                 /* It changed to be suspend event for version 2.30a and above */
4015                 if (!DWC3_VER_IS_PRIOR(DWC3, 230A)) {
4016                         /*
4017                          * Ignore suspend event until the gadget enters into
4018                          * USB_STATE_CONFIGURED state.
4019                          */
4020                         if (dwc->gadget->state >= USB_STATE_CONFIGURED)
4021                                 dwc3_gadget_suspend_interrupt(dwc,
4022                                                 event->event_info);
4023                 }
4024                 break;
4025         case DWC3_DEVICE_EVENT_SOF:
4026         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
4027         case DWC3_DEVICE_EVENT_CMD_CMPL:
4028         case DWC3_DEVICE_EVENT_OVERFLOW:
4029                 break;
4030         default:
4031                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
4032         }
4033 }
4034
4035 static void dwc3_process_event_entry(struct dwc3 *dwc,
4036                 const union dwc3_event *event)
4037 {
4038         trace_dwc3_event(event->raw, dwc);
4039
4040         if (!event->type.is_devspec)
4041                 dwc3_endpoint_interrupt(dwc, &event->depevt);
4042         else if (event->type.type == DWC3_EVENT_TYPE_DEV)
4043                 dwc3_gadget_interrupt(dwc, &event->devt);
4044         else
4045                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
4046 }
4047
4048 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
4049 {
4050         struct dwc3 *dwc = evt->dwc;
4051         irqreturn_t ret = IRQ_NONE;
4052         int left;
4053         u32 reg;
4054
4055         left = evt->count;
4056
4057         if (!(evt->flags & DWC3_EVENT_PENDING))
4058                 return IRQ_NONE;
4059
4060         while (left > 0) {
4061                 union dwc3_event event;
4062
4063                 event.raw = *(u32 *) (evt->cache + evt->lpos);
4064
4065                 dwc3_process_event_entry(dwc, &event);
4066
4067                 /*
4068                  * FIXME we wrap around correctly to the next entry as
4069                  * almost all entries are 4 bytes in size. There is one
4070                  * entry which has 12 bytes which is a regular entry
4071                  * followed by 8 bytes data. ATM I don't know how
4072                  * things are organized if we get next to the a
4073                  * boundary so I worry about that once we try to handle
4074                  * that.
4075                  */
4076                 evt->lpos = (evt->lpos + 4) % evt->length;
4077                 left -= 4;
4078         }
4079
4080         evt->count = 0;
4081         evt->flags &= ~DWC3_EVENT_PENDING;
4082         ret = IRQ_HANDLED;
4083
4084         /* Unmask interrupt */
4085         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
4086         reg &= ~DWC3_GEVNTSIZ_INTMASK;
4087         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
4088
4089         if (dwc->imod_interval) {
4090                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
4091                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
4092         }
4093
4094         return ret;
4095 }
4096
4097 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
4098 {
4099         struct dwc3_event_buffer *evt = _evt;
4100         struct dwc3 *dwc = evt->dwc;
4101         unsigned long flags;
4102         irqreturn_t ret = IRQ_NONE;
4103
4104         spin_lock_irqsave(&dwc->lock, flags);
4105         ret = dwc3_process_event_buf(evt);
4106         spin_unlock_irqrestore(&dwc->lock, flags);
4107
4108         return ret;
4109 }
4110
4111 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
4112 {
4113         struct dwc3 *dwc = evt->dwc;
4114         u32 amount;
4115         u32 count;
4116         u32 reg;
4117
4118         if (pm_runtime_suspended(dwc->dev)) {
4119                 pm_runtime_get(dwc->dev);
4120                 disable_irq_nosync(dwc->irq_gadget);
4121                 dwc->pending_events = true;
4122                 return IRQ_HANDLED;
4123         }
4124
4125         /*
4126          * With PCIe legacy interrupt, test shows that top-half irq handler can
4127          * be called again after HW interrupt deassertion. Check if bottom-half
4128          * irq event handler completes before caching new event to prevent
4129          * losing events.
4130          */
4131         if (evt->flags & DWC3_EVENT_PENDING)
4132                 return IRQ_HANDLED;
4133
4134         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
4135         count &= DWC3_GEVNTCOUNT_MASK;
4136         if (!count)
4137                 return IRQ_NONE;
4138
4139         evt->count = count;
4140         evt->flags |= DWC3_EVENT_PENDING;
4141
4142         /* Mask interrupt */
4143         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
4144         reg |= DWC3_GEVNTSIZ_INTMASK;
4145         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
4146
4147         amount = min(count, evt->length - evt->lpos);
4148         memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
4149
4150         if (amount < count)
4151                 memcpy(evt->cache, evt->buf, count - amount);
4152
4153         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
4154
4155         return IRQ_WAKE_THREAD;
4156 }
4157
4158 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
4159 {
4160         struct dwc3_event_buffer        *evt = _evt;
4161
4162         return dwc3_check_event_buf(evt);
4163 }
4164
4165 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
4166 {
4167         struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
4168         int irq;
4169
4170         irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
4171         if (irq > 0)
4172                 goto out;
4173
4174         if (irq == -EPROBE_DEFER)
4175                 goto out;
4176
4177         irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
4178         if (irq > 0)
4179                 goto out;
4180
4181         if (irq == -EPROBE_DEFER)
4182                 goto out;
4183
4184         irq = platform_get_irq(dwc3_pdev, 0);
4185         if (irq > 0)
4186                 goto out;
4187
4188         if (!irq)
4189                 irq = -EINVAL;
4190
4191 out:
4192         return irq;
4193 }
4194
4195 static void dwc_gadget_release(struct device *dev)
4196 {
4197         struct usb_gadget *gadget = container_of(dev, struct usb_gadget, dev);
4198
4199         kfree(gadget);
4200 }
4201
4202 /**
4203  * dwc3_gadget_init - initializes gadget related registers
4204  * @dwc: pointer to our controller context structure
4205  *
4206  * Returns 0 on success otherwise negative errno.
4207  */
4208 int dwc3_gadget_init(struct dwc3 *dwc)
4209 {
4210         int ret;
4211         int irq;
4212         struct device *dev;
4213
4214         irq = dwc3_gadget_get_irq(dwc);
4215         if (irq < 0) {
4216                 ret = irq;
4217                 goto err0;
4218         }
4219
4220         dwc->irq_gadget = irq;
4221
4222         dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
4223                                           sizeof(*dwc->ep0_trb) * 2,
4224                                           &dwc->ep0_trb_addr, GFP_KERNEL);
4225         if (!dwc->ep0_trb) {
4226                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
4227                 ret = -ENOMEM;
4228                 goto err0;
4229         }
4230
4231         dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
4232         if (!dwc->setup_buf) {
4233                 ret = -ENOMEM;
4234                 goto err1;
4235         }
4236
4237         dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
4238                         &dwc->bounce_addr, GFP_KERNEL);
4239         if (!dwc->bounce) {
4240                 ret = -ENOMEM;
4241                 goto err2;
4242         }
4243
4244         init_completion(&dwc->ep0_in_setup);
4245         dwc->gadget = kzalloc(sizeof(struct usb_gadget), GFP_KERNEL);
4246         if (!dwc->gadget) {
4247                 ret = -ENOMEM;
4248                 goto err3;
4249         }
4250
4251
4252         usb_initialize_gadget(dwc->dev, dwc->gadget, dwc_gadget_release);
4253         dev                             = &dwc->gadget->dev;
4254         dev->platform_data              = dwc;
4255         dwc->gadget->ops                = &dwc3_gadget_ops;
4256         dwc->gadget->speed              = USB_SPEED_UNKNOWN;
4257         dwc->gadget->ssp_rate           = USB_SSP_GEN_UNKNOWN;
4258         dwc->gadget->sg_supported       = true;
4259         dwc->gadget->name               = "dwc3-gadget";
4260         dwc->gadget->lpm_capable        = !dwc->usb2_gadget_lpm_disable;
4261
4262         /*
4263          * FIXME We might be setting max_speed to <SUPER, however versions
4264          * <2.20a of dwc3 have an issue with metastability (documented
4265          * elsewhere in this driver) which tells us we can't set max speed to
4266          * anything lower than SUPER.
4267          *
4268          * Because gadget.max_speed is only used by composite.c and function
4269          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
4270          * to happen so we avoid sending SuperSpeed Capability descriptor
4271          * together with our BOS descriptor as that could confuse host into
4272          * thinking we can handle super speed.
4273          *
4274          * Note that, in fact, we won't even support GetBOS requests when speed
4275          * is less than super speed because we don't have means, yet, to tell
4276          * composite.c that we are USB 2.0 + LPM ECN.
4277          */
4278         if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
4279             !dwc->dis_metastability_quirk)
4280                 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
4281                                 dwc->revision);
4282
4283         dwc->gadget->max_speed          = dwc->maximum_speed;
4284         dwc->gadget->max_ssp_rate       = dwc->max_ssp_rate;
4285
4286         /*
4287          * REVISIT: Here we should clear all pending IRQs to be
4288          * sure we're starting from a well known location.
4289          */
4290
4291         ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
4292         if (ret)
4293                 goto err4;
4294
4295         ret = usb_add_gadget(dwc->gadget);
4296         if (ret) {
4297                 dev_err(dwc->dev, "failed to add gadget\n");
4298                 goto err5;
4299         }
4300
4301         if (DWC3_IP_IS(DWC32) && dwc->maximum_speed == USB_SPEED_SUPER_PLUS)
4302                 dwc3_gadget_set_ssp_rate(dwc->gadget, dwc->max_ssp_rate);
4303         else
4304                 dwc3_gadget_set_speed(dwc->gadget, dwc->maximum_speed);
4305
4306         return 0;
4307
4308 err5:
4309         dwc3_gadget_free_endpoints(dwc);
4310 err4:
4311         usb_put_gadget(dwc->gadget);
4312         dwc->gadget = NULL;
4313 err3:
4314         dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4315                         dwc->bounce_addr);
4316
4317 err2:
4318         kfree(dwc->setup_buf);
4319
4320 err1:
4321         dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4322                         dwc->ep0_trb, dwc->ep0_trb_addr);
4323
4324 err0:
4325         return ret;
4326 }
4327
4328 /* -------------------------------------------------------------------------- */
4329
4330 void dwc3_gadget_exit(struct dwc3 *dwc)
4331 {
4332         if (!dwc->gadget)
4333                 return;
4334
4335         usb_del_gadget(dwc->gadget);
4336         dwc3_gadget_free_endpoints(dwc);
4337         usb_put_gadget(dwc->gadget);
4338         dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4339                           dwc->bounce_addr);
4340         kfree(dwc->setup_buf);
4341         dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4342                           dwc->ep0_trb, dwc->ep0_trb_addr);
4343 }
4344
4345 int dwc3_gadget_suspend(struct dwc3 *dwc)
4346 {
4347         if (!dwc->gadget_driver)
4348                 return 0;
4349
4350         dwc3_gadget_run_stop(dwc, false, false);
4351         dwc3_disconnect_gadget(dwc);
4352         __dwc3_gadget_stop(dwc);
4353
4354         return 0;
4355 }
4356
4357 int dwc3_gadget_resume(struct dwc3 *dwc)
4358 {
4359         int                     ret;
4360
4361         if (!dwc->gadget_driver || !dwc->softconnect)
4362                 return 0;
4363
4364         ret = __dwc3_gadget_start(dwc);
4365         if (ret < 0)
4366                 goto err0;
4367
4368         ret = dwc3_gadget_run_stop(dwc, true, false);
4369         if (ret < 0)
4370                 goto err1;
4371
4372         return 0;
4373
4374 err1:
4375         __dwc3_gadget_stop(dwc);
4376
4377 err0:
4378         return ret;
4379 }
4380
4381 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
4382 {
4383         if (dwc->pending_events) {
4384                 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
4385                 dwc->pending_events = false;
4386                 enable_irq(dwc->irq_gadget);
4387         }
4388 }