1 // SPDX-License-Identifier: GPL-2.0
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
19 #include <linux/list.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
30 #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
51 case USB_TEST_SE0_NAK:
53 case USB_TEST_FORCE_ENABLE:
60 dwc3_gadget_dctl_write_safe(dwc, reg);
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
78 return DWC3_DSTS_USBLNKST(reg);
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
95 * Wait until device controller is ready. Only applies to 1.94a and
98 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
114 /* set no action before sending new link state change */
115 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
117 /* set requested state */
118 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
119 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
122 * The following code is racy when called from dwc3_gadget_wakeup,
123 * and is not needed, at least on newer versions
125 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
128 /* wait for a change in DSTS */
131 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
133 if (DWC3_DSTS_USBLNKST(reg) == state)
143 * dwc3_ep_inc_trb - increment a trb index.
144 * @index: Pointer to the TRB index to increment.
146 * The index should never point to the link TRB. After incrementing,
147 * if it is point to the link TRB, wrap around to the beginning. The
148 * link TRB is always at the last TRB entry.
150 static void dwc3_ep_inc_trb(u8 *index)
153 if (*index == (DWC3_TRB_NUM - 1))
158 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
159 * @dep: The endpoint whose enqueue pointer we're incrementing
161 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
163 dwc3_ep_inc_trb(&dep->trb_enqueue);
167 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
168 * @dep: The endpoint whose enqueue pointer we're incrementing
170 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
172 dwc3_ep_inc_trb(&dep->trb_dequeue);
175 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
176 struct dwc3_request *req, int status)
178 struct dwc3 *dwc = dep->dwc;
180 list_del(&req->list);
182 req->needs_extra_trb = false;
184 if (req->request.status == -EINPROGRESS)
185 req->request.status = status;
188 usb_gadget_unmap_request_by_dev(dwc->sysdev,
189 &req->request, req->direction);
192 trace_dwc3_gadget_giveback(req);
195 pm_runtime_put(dwc->dev);
199 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
200 * @dep: The endpoint to whom the request belongs to
201 * @req: The request we're giving back
202 * @status: completion code for the request
204 * Must be called with controller's lock held and interrupts disabled. This
205 * function will unmap @req and call its ->complete() callback to notify upper
206 * layers that it has completed.
208 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
211 struct dwc3 *dwc = dep->dwc;
213 dwc3_gadget_del_and_unmap_request(dep, req, status);
214 req->status = DWC3_REQUEST_STATUS_COMPLETED;
216 spin_unlock(&dwc->lock);
217 usb_gadget_giveback_request(&dep->endpoint, &req->request);
218 spin_lock(&dwc->lock);
222 * dwc3_send_gadget_generic_command - issue a generic command for the controller
223 * @dwc: pointer to the controller context
224 * @cmd: the command to be issued
225 * @param: command parameter
227 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
228 * and wait for its completion.
230 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
238 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
239 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
242 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
243 if (!(reg & DWC3_DGCMD_CMDACT)) {
244 status = DWC3_DGCMD_STATUS(reg);
256 trace_dwc3_gadget_generic_cmd(cmd, param, status);
261 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
264 * dwc3_send_gadget_ep_cmd - issue an endpoint command
265 * @dep: the endpoint to which the command is going to be issued
266 * @cmd: the command to be issued
267 * @params: parameters to the command
269 * Caller should handle locking. This function will issue @cmd with given
270 * @params to @dep and wait for its completion.
272 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
273 struct dwc3_gadget_ep_cmd_params *params)
275 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
276 struct dwc3 *dwc = dep->dwc;
278 u32 saved_config = 0;
285 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
286 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
289 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
290 * settings. Restore them after the command is completed.
292 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
294 if (dwc->gadget->speed <= USB_SPEED_HIGH) {
295 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
296 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
297 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
298 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
301 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
302 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
303 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
307 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
310 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
313 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
314 dwc->link_state == DWC3_LINK_STATE_U2 ||
315 dwc->link_state == DWC3_LINK_STATE_U3);
317 if (unlikely(needs_wakeup)) {
318 ret = __dwc3_gadget_wakeup(dwc);
319 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
324 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
325 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
326 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
329 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
330 * not relying on XferNotReady, we can make use of a special "No
331 * Response Update Transfer" command where we should clear both CmdAct
334 * With this, we don't need to wait for command completion and can
335 * straight away issue further commands to the endpoint.
337 * NOTICE: We're making an assumption that control endpoints will never
338 * make use of Update Transfer command. This is a safe assumption
339 * because we can never have more than one request at a time with
340 * Control Endpoints. If anybody changes that assumption, this chunk
341 * needs to be updated accordingly.
343 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
344 !usb_endpoint_xfer_isoc(desc))
345 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
347 cmd |= DWC3_DEPCMD_CMDACT;
349 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
351 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
352 if (!(reg & DWC3_DEPCMD_CMDACT)) {
353 cmd_status = DWC3_DEPCMD_STATUS(reg);
355 switch (cmd_status) {
359 case DEPEVT_TRANSFER_NO_RESOURCE:
360 dev_WARN(dwc->dev, "No resource for %s\n",
364 case DEPEVT_TRANSFER_BUS_EXPIRY:
366 * SW issues START TRANSFER command to
367 * isochronous ep with future frame interval. If
368 * future interval time has already passed when
369 * core receives the command, it will respond
370 * with an error status of 'Bus Expiry'.
372 * Instead of always returning -EINVAL, let's
373 * give a hint to the gadget driver that this is
374 * the case by returning -EAGAIN.
379 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
388 cmd_status = -ETIMEDOUT;
391 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
393 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
395 dep->flags |= DWC3_EP_TRANSFER_STARTED;
397 if (ret != -ETIMEDOUT)
398 dwc3_gadget_ep_get_transfer_index(dep);
402 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
404 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
410 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
412 struct dwc3 *dwc = dep->dwc;
413 struct dwc3_gadget_ep_cmd_params params;
414 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
417 * As of core revision 2.60a the recommended programming model
418 * is to set the ClearPendIN bit when issuing a Clear Stall EP
419 * command for IN endpoints. This is to prevent an issue where
420 * some (non-compliant) hosts may not send ACK TPs for pending
421 * IN transfers due to a mishandled error condition. Synopsys
424 if (dep->direction &&
425 !DWC3_VER_IS_PRIOR(DWC3, 260A) &&
426 (dwc->gadget->speed >= USB_SPEED_SUPER))
427 cmd |= DWC3_DEPCMD_CLEARPENDIN;
429 memset(¶ms, 0, sizeof(params));
431 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
434 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
435 struct dwc3_trb *trb)
437 u32 offset = (char *) trb - (char *) dep->trb_pool;
439 return dep->trb_pool_dma + offset;
442 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
444 struct dwc3 *dwc = dep->dwc;
449 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
450 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
451 &dep->trb_pool_dma, GFP_KERNEL);
452 if (!dep->trb_pool) {
453 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
461 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
463 struct dwc3 *dwc = dep->dwc;
465 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
466 dep->trb_pool, dep->trb_pool_dma);
468 dep->trb_pool = NULL;
469 dep->trb_pool_dma = 0;
472 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
474 struct dwc3_gadget_ep_cmd_params params;
476 memset(¶ms, 0x00, sizeof(params));
478 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
480 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
485 * dwc3_gadget_start_config - configure ep resources
486 * @dep: endpoint that is being enabled
488 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
489 * completion, it will set Transfer Resource for all available endpoints.
491 * The assignment of transfer resources cannot perfectly follow the data book
492 * due to the fact that the controller driver does not have all knowledge of the
493 * configuration in advance. It is given this information piecemeal by the
494 * composite gadget framework after every SET_CONFIGURATION and
495 * SET_INTERFACE. Trying to follow the databook programming model in this
496 * scenario can cause errors. For two reasons:
498 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
499 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
500 * incorrect in the scenario of multiple interfaces.
502 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
503 * endpoint on alt setting (8.1.6).
505 * The following simplified method is used instead:
507 * All hardware endpoints can be assigned a transfer resource and this setting
508 * will stay persistent until either a core reset or hibernation. So whenever we
509 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
510 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
511 * guaranteed that there are as many transfer resources as endpoints.
513 * This function is called for each endpoint when it is being enabled but is
514 * triggered only when called for EP0-out, which always happens first, and which
515 * should only happen in one of the above conditions.
517 static int dwc3_gadget_start_config(struct dwc3_ep *dep)
519 struct dwc3_gadget_ep_cmd_params params;
528 memset(¶ms, 0x00, sizeof(params));
529 cmd = DWC3_DEPCMD_DEPSTARTCFG;
532 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
536 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
537 struct dwc3_ep *dep = dwc->eps[i];
542 ret = dwc3_gadget_set_xfer_resource(dep);
550 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
552 const struct usb_ss_ep_comp_descriptor *comp_desc;
553 const struct usb_endpoint_descriptor *desc;
554 struct dwc3_gadget_ep_cmd_params params;
555 struct dwc3 *dwc = dep->dwc;
557 comp_desc = dep->endpoint.comp_desc;
558 desc = dep->endpoint.desc;
560 memset(¶ms, 0x00, sizeof(params));
562 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
563 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
565 /* Burst size is only needed in SuperSpeed mode */
566 if (dwc->gadget->speed >= USB_SPEED_SUPER) {
567 u32 burst = dep->endpoint.maxburst;
569 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
572 params.param0 |= action;
573 if (action == DWC3_DEPCFG_ACTION_RESTORE)
574 params.param2 |= dep->saved_state;
576 if (usb_endpoint_xfer_control(desc))
577 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
579 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
580 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
582 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
583 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
584 | DWC3_DEPCFG_XFER_COMPLETE_EN
585 | DWC3_DEPCFG_STREAM_EVENT_EN;
586 dep->stream_capable = true;
589 if (!usb_endpoint_xfer_control(desc))
590 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
593 * We are doing 1:1 mapping for endpoints, meaning
594 * Physical Endpoints 2 maps to Logical Endpoint 2 and
595 * so on. We consider the direction bit as part of the physical
596 * endpoint number. So USB endpoint 0x81 is 0x03.
598 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
601 * We must use the lower 16 TX FIFOs even though
605 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
607 if (desc->bInterval) {
608 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
609 dep->interval = 1 << (desc->bInterval - 1);
612 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
615 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
619 * __dwc3_gadget_ep_enable - initializes a hw endpoint
620 * @dep: endpoint to be initialized
621 * @action: one of INIT, MODIFY or RESTORE
623 * Caller should take care of locking. Execute all necessary commands to
624 * initialize a HW endpoint so it can be used by a gadget driver.
626 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
628 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
629 struct dwc3 *dwc = dep->dwc;
634 if (!(dep->flags & DWC3_EP_ENABLED)) {
635 ret = dwc3_gadget_start_config(dep);
640 ret = dwc3_gadget_set_ep_config(dep, action);
644 if (!(dep->flags & DWC3_EP_ENABLED)) {
645 struct dwc3_trb *trb_st_hw;
646 struct dwc3_trb *trb_link;
648 dep->type = usb_endpoint_type(desc);
649 dep->flags |= DWC3_EP_ENABLED;
651 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
652 reg |= DWC3_DALEPENA_EP(dep->number);
653 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
655 if (usb_endpoint_xfer_control(desc))
658 /* Initialize the TRB ring */
659 dep->trb_dequeue = 0;
660 dep->trb_enqueue = 0;
661 memset(dep->trb_pool, 0,
662 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
664 /* Link TRB. The HWO bit is never reset */
665 trb_st_hw = &dep->trb_pool[0];
667 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
668 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
669 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
670 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
671 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
675 * Issue StartTransfer here with no-op TRB so we can always rely on No
676 * Response Update Transfer command.
678 if (usb_endpoint_xfer_bulk(desc) ||
679 usb_endpoint_xfer_int(desc)) {
680 struct dwc3_gadget_ep_cmd_params params;
681 struct dwc3_trb *trb;
685 memset(¶ms, 0, sizeof(params));
686 trb = &dep->trb_pool[0];
687 trb_dma = dwc3_trb_dma_offset(dep, trb);
689 params.param0 = upper_32_bits(trb_dma);
690 params.param1 = lower_32_bits(trb_dma);
692 cmd = DWC3_DEPCMD_STARTTRANSFER;
694 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
698 if (dep->stream_capable) {
700 * For streams, at start, there maybe a race where the
701 * host primes the endpoint before the function driver
702 * queues a request to initiate a stream. In that case,
703 * the controller will not see the prime to generate the
704 * ERDY and start stream. To workaround this, issue a
705 * no-op TRB as normal, but end it immediately. As a
706 * result, when the function driver queues the request,
707 * the next START_TRANSFER command will cause the
708 * controller to generate an ERDY to initiate the
711 dwc3_stop_active_transfer(dep, true, true);
714 * All stream eps will reinitiate stream on NoStream
715 * rejection until we can determine that the host can
716 * prime after the first transfer.
718 dep->flags |= DWC3_EP_FORCE_RESTART_STREAM;
723 trace_dwc3_gadget_ep_enable(dep);
728 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
730 struct dwc3_request *req;
732 dwc3_stop_active_transfer(dep, true, false);
734 /* - giveback all requests to gadget driver */
735 while (!list_empty(&dep->started_list)) {
736 req = next_request(&dep->started_list);
738 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
741 while (!list_empty(&dep->pending_list)) {
742 req = next_request(&dep->pending_list);
744 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
747 while (!list_empty(&dep->cancelled_list)) {
748 req = next_request(&dep->cancelled_list);
750 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
755 * __dwc3_gadget_ep_disable - disables a hw endpoint
756 * @dep: the endpoint to disable
758 * This function undoes what __dwc3_gadget_ep_enable did and also removes
759 * requests which are currently being processed by the hardware and those which
760 * are not yet scheduled.
762 * Caller should take care of locking.
764 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
766 struct dwc3 *dwc = dep->dwc;
769 trace_dwc3_gadget_ep_disable(dep);
771 dwc3_remove_requests(dwc, dep);
773 /* make sure HW endpoint isn't stalled */
774 if (dep->flags & DWC3_EP_STALL)
775 __dwc3_gadget_ep_set_halt(dep, 0, false);
777 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
778 reg &= ~DWC3_DALEPENA_EP(dep->number);
779 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
781 dep->stream_capable = false;
785 /* Clear out the ep descriptors for non-ep0 */
786 if (dep->number > 1) {
787 dep->endpoint.comp_desc = NULL;
788 dep->endpoint.desc = NULL;
794 /* -------------------------------------------------------------------------- */
796 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
797 const struct usb_endpoint_descriptor *desc)
802 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
807 /* -------------------------------------------------------------------------- */
809 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
810 const struct usb_endpoint_descriptor *desc)
817 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
818 pr_debug("dwc3: invalid parameters\n");
822 if (!desc->wMaxPacketSize) {
823 pr_debug("dwc3: missing wMaxPacketSize\n");
827 dep = to_dwc3_ep(ep);
830 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
831 "%s is already enabled\n",
835 spin_lock_irqsave(&dwc->lock, flags);
836 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
837 spin_unlock_irqrestore(&dwc->lock, flags);
842 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
850 pr_debug("dwc3: invalid parameters\n");
854 dep = to_dwc3_ep(ep);
857 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
858 "%s is already disabled\n",
862 spin_lock_irqsave(&dwc->lock, flags);
863 ret = __dwc3_gadget_ep_disable(dep);
864 spin_unlock_irqrestore(&dwc->lock, flags);
869 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
872 struct dwc3_request *req;
873 struct dwc3_ep *dep = to_dwc3_ep(ep);
875 req = kzalloc(sizeof(*req), gfp_flags);
879 req->direction = dep->direction;
880 req->epnum = dep->number;
882 req->status = DWC3_REQUEST_STATUS_UNKNOWN;
884 trace_dwc3_alloc_request(req);
886 return &req->request;
889 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
890 struct usb_request *request)
892 struct dwc3_request *req = to_dwc3_request(request);
894 trace_dwc3_free_request(req);
899 * dwc3_ep_prev_trb - returns the previous TRB in the ring
900 * @dep: The endpoint with the TRB ring
901 * @index: The index of the current TRB in the ring
903 * Returns the TRB prior to the one pointed to by the index. If the
904 * index is 0, we will wrap backwards, skip the link TRB, and return
905 * the one just before that.
907 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
912 tmp = DWC3_TRB_NUM - 1;
914 return &dep->trb_pool[tmp - 1];
917 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
919 struct dwc3_trb *tmp;
923 * If enqueue & dequeue are equal than it is either full or empty.
925 * One way to know for sure is if the TRB right before us has HWO bit
926 * set or not. If it has, then we're definitely full and can't fit any
927 * more transfers in our ring.
929 if (dep->trb_enqueue == dep->trb_dequeue) {
930 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
931 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
934 return DWC3_TRB_NUM - 1;
937 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
938 trbs_left &= (DWC3_TRB_NUM - 1);
940 if (dep->trb_dequeue < dep->trb_enqueue)
946 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
947 dma_addr_t dma, unsigned int length, unsigned int chain,
948 unsigned int node, unsigned int stream_id,
949 unsigned int short_not_ok, unsigned int no_interrupt,
950 unsigned int is_last, bool must_interrupt)
952 struct dwc3 *dwc = dep->dwc;
953 struct usb_gadget *gadget = dwc->gadget;
954 enum usb_device_speed speed = gadget->speed;
956 trb->size = DWC3_TRB_SIZE_LENGTH(length);
957 trb->bpl = lower_32_bits(dma);
958 trb->bph = upper_32_bits(dma);
960 switch (usb_endpoint_type(dep->endpoint.desc)) {
961 case USB_ENDPOINT_XFER_CONTROL:
962 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
965 case USB_ENDPOINT_XFER_ISOC:
967 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
970 * USB Specification 2.0 Section 5.9.2 states that: "If
971 * there is only a single transaction in the microframe,
972 * only a DATA0 data packet PID is used. If there are
973 * two transactions per microframe, DATA1 is used for
974 * the first transaction data packet and DATA0 is used
975 * for the second transaction data packet. If there are
976 * three transactions per microframe, DATA2 is used for
977 * the first transaction data packet, DATA1 is used for
978 * the second, and DATA0 is used for the third."
980 * IOW, we should satisfy the following cases:
982 * 1) length <= maxpacket
985 * 2) maxpacket < length <= (2 * maxpacket)
988 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
989 * - DATA2, DATA1, DATA0
991 if (speed == USB_SPEED_HIGH) {
992 struct usb_ep *ep = &dep->endpoint;
993 unsigned int mult = 2;
994 unsigned int maxp = usb_endpoint_maxp(ep->desc);
996 if (length <= (2 * maxp))
1002 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
1005 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
1008 /* always enable Interrupt on Missed ISOC */
1009 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1012 case USB_ENDPOINT_XFER_BULK:
1013 case USB_ENDPOINT_XFER_INT:
1014 trb->ctrl = DWC3_TRBCTL_NORMAL;
1018 * This is only possible with faulty memory because we
1019 * checked it already :)
1021 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
1022 usb_endpoint_type(dep->endpoint.desc));
1026 * Enable Continue on Short Packet
1027 * when endpoint is not a stream capable
1029 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
1030 if (!dep->stream_capable)
1031 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1034 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1037 if ((!no_interrupt && !chain) || must_interrupt)
1038 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1041 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1042 else if (dep->stream_capable && is_last)
1043 trb->ctrl |= DWC3_TRB_CTRL_LST;
1045 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1046 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1048 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1050 dwc3_ep_inc_enq(dep);
1052 trace_dwc3_prepare_trb(dep, trb);
1056 * dwc3_prepare_one_trb - setup one TRB from one request
1057 * @dep: endpoint for which this request is prepared
1058 * @req: dwc3_request pointer
1059 * @trb_length: buffer size of the TRB
1060 * @chain: should this TRB be chained to the next?
1061 * @node: only for isochronous endpoints. First TRB needs different type.
1062 * @use_bounce_buffer: set to use bounce buffer
1063 * @must_interrupt: set to interrupt on TRB completion
1065 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1066 struct dwc3_request *req, unsigned int trb_length,
1067 unsigned int chain, unsigned int node, bool use_bounce_buffer,
1068 bool must_interrupt)
1070 struct dwc3_trb *trb;
1072 unsigned int stream_id = req->request.stream_id;
1073 unsigned int short_not_ok = req->request.short_not_ok;
1074 unsigned int no_interrupt = req->request.no_interrupt;
1075 unsigned int is_last = req->request.is_last;
1077 if (use_bounce_buffer)
1078 dma = dep->dwc->bounce_addr;
1079 else if (req->request.num_sgs > 0)
1080 dma = sg_dma_address(req->start_sg);
1082 dma = req->request.dma;
1084 trb = &dep->trb_pool[dep->trb_enqueue];
1087 dwc3_gadget_move_started_request(req);
1089 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1094 __dwc3_prepare_one_trb(dep, trb, dma, trb_length, chain, node,
1095 stream_id, short_not_ok, no_interrupt, is_last,
1099 static bool dwc3_needs_extra_trb(struct dwc3_ep *dep, struct dwc3_request *req)
1101 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1102 unsigned int rem = req->request.length % maxp;
1104 if ((req->request.length && req->request.zero && !rem &&
1105 !usb_endpoint_xfer_isoc(dep->endpoint.desc)) ||
1106 (!req->direction && rem))
1113 * dwc3_prepare_last_sg - prepare TRBs for the last SG entry
1114 * @dep: The endpoint that the request belongs to
1115 * @req: The request to prepare
1116 * @entry_length: The last SG entry size
1117 * @node: Indicates whether this is not the first entry (for isoc only)
1119 * Return the number of TRBs prepared.
1121 static int dwc3_prepare_last_sg(struct dwc3_ep *dep,
1122 struct dwc3_request *req, unsigned int entry_length,
1125 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1126 unsigned int rem = req->request.length % maxp;
1127 unsigned int num_trbs = 1;
1129 if (dwc3_needs_extra_trb(dep, req))
1132 if (dwc3_calc_trbs_left(dep) < num_trbs)
1135 req->needs_extra_trb = num_trbs > 1;
1137 /* Prepare a normal TRB */
1138 if (req->direction || req->request.length)
1139 dwc3_prepare_one_trb(dep, req, entry_length,
1140 req->needs_extra_trb, node, false, false);
1142 /* Prepare extra TRBs for ZLP and MPS OUT transfer alignment */
1143 if ((!req->direction && !req->request.length) || req->needs_extra_trb)
1144 dwc3_prepare_one_trb(dep, req,
1145 req->direction ? 0 : maxp - rem,
1146 false, 1, true, false);
1151 static int dwc3_prepare_trbs_sg(struct dwc3_ep *dep,
1152 struct dwc3_request *req)
1154 struct scatterlist *sg = req->start_sg;
1155 struct scatterlist *s;
1157 unsigned int length = req->request.length;
1158 unsigned int remaining = req->request.num_mapped_sgs
1159 - req->num_queued_sgs;
1160 unsigned int num_trbs = req->num_trbs;
1161 bool needs_extra_trb = dwc3_needs_extra_trb(dep, req);
1164 * If we resume preparing the request, then get the remaining length of
1165 * the request and resume where we left off.
1167 for_each_sg(req->request.sg, s, req->num_queued_sgs, i)
1168 length -= sg_dma_len(s);
1170 for_each_sg(sg, s, remaining, i) {
1171 unsigned int num_trbs_left = dwc3_calc_trbs_left(dep);
1172 unsigned int trb_length;
1173 bool must_interrupt = false;
1174 bool last_sg = false;
1176 trb_length = min_t(unsigned int, length, sg_dma_len(s));
1178 length -= trb_length;
1181 * IOMMU driver is coalescing the list of sgs which shares a
1182 * page boundary into one and giving it to USB driver. With
1183 * this the number of sgs mapped is not equal to the number of
1184 * sgs passed. So mark the chain bit to false if it isthe last
1187 if ((i == remaining - 1) || !length)
1194 if (!dwc3_prepare_last_sg(dep, req, trb_length, i))
1198 * Look ahead to check if we have enough TRBs for the
1199 * next SG entry. If not, set interrupt on this TRB to
1200 * resume preparing the next SG entry when more TRBs are
1203 if (num_trbs_left == 1 || (needs_extra_trb &&
1204 num_trbs_left <= 2 &&
1205 sg_dma_len(sg_next(s)) >= length))
1206 must_interrupt = true;
1208 dwc3_prepare_one_trb(dep, req, trb_length, 1, i, false,
1213 * There can be a situation where all sgs in sglist are not
1214 * queued because of insufficient trb number. To handle this
1215 * case, update start_sg to next sg to be queued, so that
1216 * we have free trbs we can continue queuing from where we
1217 * previously stopped
1220 req->start_sg = sg_next(s);
1222 req->num_queued_sgs++;
1225 * The number of pending SG entries may not correspond to the
1226 * number of mapped SG entries. If all the data are queued, then
1227 * don't include unused SG entries.
1230 req->num_pending_sgs -= req->request.num_mapped_sgs - req->num_queued_sgs;
1238 return req->num_trbs - num_trbs;
1241 static int dwc3_prepare_trbs_linear(struct dwc3_ep *dep,
1242 struct dwc3_request *req)
1244 return dwc3_prepare_last_sg(dep, req, req->request.length, 0);
1248 * dwc3_prepare_trbs - setup TRBs from requests
1249 * @dep: endpoint for which requests are being prepared
1251 * The function goes through the requests list and sets up TRBs for the
1252 * transfers. The function returns once there are no more TRBs available or
1253 * it runs out of requests.
1255 * Returns the number of TRBs prepared or negative errno.
1257 static int dwc3_prepare_trbs(struct dwc3_ep *dep)
1259 struct dwc3_request *req, *n;
1262 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1265 * We can get in a situation where there's a request in the started list
1266 * but there weren't enough TRBs to fully kick it in the first time
1267 * around, so it has been waiting for more TRBs to be freed up.
1269 * In that case, we should check if we have a request with pending_sgs
1270 * in the started list and prepare TRBs for that request first,
1271 * otherwise we will prepare TRBs completely out of order and that will
1274 list_for_each_entry(req, &dep->started_list, list) {
1275 if (req->num_pending_sgs > 0) {
1276 ret = dwc3_prepare_trbs_sg(dep, req);
1277 if (!ret || req->num_pending_sgs)
1281 if (!dwc3_calc_trbs_left(dep))
1285 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1286 * burst capability may try to read and use TRBs beyond the
1287 * active transfer instead of stopping.
1289 if (dep->stream_capable && req->request.is_last)
1293 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1294 struct dwc3 *dwc = dep->dwc;
1296 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1301 req->sg = req->request.sg;
1302 req->start_sg = req->sg;
1303 req->num_queued_sgs = 0;
1304 req->num_pending_sgs = req->request.num_mapped_sgs;
1306 if (req->num_pending_sgs > 0) {
1307 ret = dwc3_prepare_trbs_sg(dep, req);
1308 if (req->num_pending_sgs)
1311 ret = dwc3_prepare_trbs_linear(dep, req);
1314 if (!ret || !dwc3_calc_trbs_left(dep))
1318 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1319 * burst capability may try to read and use TRBs beyond the
1320 * active transfer instead of stopping.
1322 if (dep->stream_capable && req->request.is_last)
1329 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep);
1331 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1333 struct dwc3_gadget_ep_cmd_params params;
1334 struct dwc3_request *req;
1340 * Note that it's normal to have no new TRBs prepared (i.e. ret == 0).
1341 * This happens when we need to stop and restart a transfer such as in
1342 * the case of reinitiating a stream or retrying an isoc transfer.
1344 ret = dwc3_prepare_trbs(dep);
1348 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1351 * If there's no new TRB prepared and we don't need to restart a
1352 * transfer, there's no need to update the transfer.
1354 if (!ret && !starting)
1357 req = next_request(&dep->started_list);
1359 dep->flags |= DWC3_EP_PENDING_REQUEST;
1363 memset(¶ms, 0, sizeof(params));
1366 params.param0 = upper_32_bits(req->trb_dma);
1367 params.param1 = lower_32_bits(req->trb_dma);
1368 cmd = DWC3_DEPCMD_STARTTRANSFER;
1370 if (dep->stream_capable)
1371 cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1373 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1374 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1376 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1377 DWC3_DEPCMD_PARAM(dep->resource_index);
1380 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1382 struct dwc3_request *tmp;
1387 dwc3_stop_active_transfer(dep, true, true);
1389 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1390 dwc3_gadget_move_cancelled_request(req);
1392 /* If ep isn't started, then there's no end transfer pending */
1393 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1394 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1399 if (dep->stream_capable && req->request.is_last)
1400 dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE;
1405 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1409 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1410 return DWC3_DSTS_SOFFN(reg);
1414 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1415 * @dep: isoc endpoint
1417 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1418 * microframe number reported by the XferNotReady event for the future frame
1419 * number to start the isoc transfer.
1421 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1422 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1423 * XferNotReady event are invalid. The driver uses this number to schedule the
1424 * isochronous transfer and passes it to the START TRANSFER command. Because
1425 * this number is invalid, the command may fail. If BIT[15:14] matches the
1426 * internal 16-bit microframe, the START TRANSFER command will pass and the
1427 * transfer will start at the scheduled time, if it is off by 1, the command
1428 * will still pass, but the transfer will start 2 seconds in the future. For all
1429 * other conditions, the START TRANSFER command will fail with bus-expiry.
1431 * In order to workaround this issue, we can test for the correct combination of
1432 * BIT[15:14] by sending START TRANSFER commands with different values of
1433 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1434 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1435 * As the result, within the 4 possible combinations for BIT[15:14], there will
1436 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1437 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1438 * value is the correct combination.
1440 * Since there are only 4 outcomes and the results are ordered, we can simply
1441 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1442 * deduce the smaller successful combination.
1444 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1445 * of BIT[15:14]. The correct combination is as follow:
1447 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1448 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1449 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1450 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1452 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1455 static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1461 while (dep->combo_num < 2) {
1462 struct dwc3_gadget_ep_cmd_params params;
1463 u32 test_frame_number;
1467 * Check if we can start isoc transfer on the next interval or
1468 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1470 test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK;
1471 test_frame_number |= dep->combo_num << 14;
1472 test_frame_number += max_t(u32, 4, dep->interval);
1474 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1475 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1477 cmd = DWC3_DEPCMD_STARTTRANSFER;
1478 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1479 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1481 /* Redo if some other failure beside bus-expiry is received */
1482 if (cmd_status && cmd_status != -EAGAIN) {
1483 dep->start_cmd_status = 0;
1488 /* Store the first test status */
1489 if (dep->combo_num == 0)
1490 dep->start_cmd_status = cmd_status;
1495 * End the transfer if the START_TRANSFER command is successful
1496 * to wait for the next XferNotReady to test the command again
1498 if (cmd_status == 0) {
1499 dwc3_stop_active_transfer(dep, true, true);
1504 /* test0 and test1 are both completed at this point */
1505 test0 = (dep->start_cmd_status == 0);
1506 test1 = (cmd_status == 0);
1508 if (!test0 && test1)
1510 else if (!test0 && !test1)
1512 else if (test0 && !test1)
1514 else if (test0 && test1)
1517 dep->frame_number &= DWC3_FRNUMBER_MASK;
1518 dep->frame_number |= dep->combo_num << 14;
1519 dep->frame_number += max_t(u32, 4, dep->interval);
1521 /* Reinitialize test variables */
1522 dep->start_cmd_status = 0;
1525 return __dwc3_gadget_kick_transfer(dep);
1528 static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1530 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
1531 struct dwc3 *dwc = dep->dwc;
1535 if (list_empty(&dep->pending_list) &&
1536 list_empty(&dep->started_list)) {
1537 dep->flags |= DWC3_EP_PENDING_REQUEST;
1541 if (!dwc->dis_start_transfer_quirk &&
1542 (DWC3_VER_IS_PRIOR(DWC31, 170A) ||
1543 DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) {
1544 if (dwc->gadget->speed <= USB_SPEED_HIGH && dep->direction)
1545 return dwc3_gadget_start_isoc_quirk(dep);
1548 if (desc->bInterval <= 14 &&
1549 dwc->gadget->speed >= USB_SPEED_HIGH) {
1550 u32 frame = __dwc3_gadget_get_frame(dwc);
1551 bool rollover = frame <
1552 (dep->frame_number & DWC3_FRNUMBER_MASK);
1555 * frame_number is set from XferNotReady and may be already
1556 * out of date. DSTS only provides the lower 14 bit of the
1557 * current frame number. So add the upper two bits of
1558 * frame_number and handle a possible rollover.
1559 * This will provide the correct frame_number unless more than
1560 * rollover has happened since XferNotReady.
1563 dep->frame_number = (dep->frame_number & ~DWC3_FRNUMBER_MASK) |
1566 dep->frame_number += BIT(14);
1569 for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1570 dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1);
1572 ret = __dwc3_gadget_kick_transfer(dep);
1578 * After a number of unsuccessful start attempts due to bus-expiry
1579 * status, issue END_TRANSFER command and retry on the next XferNotReady
1582 if (ret == -EAGAIN) {
1583 struct dwc3_gadget_ep_cmd_params params;
1586 cmd = DWC3_DEPCMD_ENDTRANSFER |
1587 DWC3_DEPCMD_CMDIOC |
1588 DWC3_DEPCMD_PARAM(dep->resource_index);
1590 dep->resource_index = 0;
1591 memset(¶ms, 0, sizeof(params));
1593 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1595 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
1601 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1603 struct dwc3 *dwc = dep->dwc;
1605 if (!dep->endpoint.desc || !dwc->pullups_connected) {
1606 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1611 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1612 &req->request, req->dep->name))
1615 if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1616 "%s: request %pK already in flight\n",
1617 dep->name, &req->request))
1620 pm_runtime_get(dwc->dev);
1622 req->request.actual = 0;
1623 req->request.status = -EINPROGRESS;
1625 trace_dwc3_ep_queue(req);
1627 list_add_tail(&req->list, &dep->pending_list);
1628 req->status = DWC3_REQUEST_STATUS_QUEUED;
1630 if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)
1634 * Start the transfer only after the END_TRANSFER is completed
1635 * and endpoint STALL is cleared.
1637 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
1638 (dep->flags & DWC3_EP_WEDGE) ||
1639 (dep->flags & DWC3_EP_STALL)) {
1640 dep->flags |= DWC3_EP_DELAY_START;
1645 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1646 * wait for a XferNotReady event so we will know what's the current
1647 * (micro-)frame number.
1649 * Without this trick, we are very, very likely gonna get Bus Expiry
1650 * errors which will force us issue EndTransfer command.
1652 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1653 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1654 !(dep->flags & DWC3_EP_TRANSFER_STARTED))
1657 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1658 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
1659 return __dwc3_gadget_start_isoc(dep);
1663 return __dwc3_gadget_kick_transfer(dep);
1666 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1669 struct dwc3_request *req = to_dwc3_request(request);
1670 struct dwc3_ep *dep = to_dwc3_ep(ep);
1671 struct dwc3 *dwc = dep->dwc;
1673 unsigned long flags;
1677 spin_lock_irqsave(&dwc->lock, flags);
1678 ret = __dwc3_gadget_ep_queue(dep, req);
1679 spin_unlock_irqrestore(&dwc->lock, flags);
1684 static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
1688 /* If req->trb is not set, then the request has not started */
1693 * If request was already started, this means we had to
1694 * stop the transfer. With that we also need to ignore
1695 * all TRBs used by the request, however TRBs can only
1696 * be modified after completion of END_TRANSFER
1697 * command. So what we do here is that we wait for
1698 * END_TRANSFER completion and only after that, we jump
1699 * over TRBs by clearing HWO and incrementing dequeue
1702 for (i = 0; i < req->num_trbs; i++) {
1703 struct dwc3_trb *trb;
1705 trb = &dep->trb_pool[dep->trb_dequeue];
1706 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1707 dwc3_ep_inc_deq(dep);
1713 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
1715 struct dwc3_request *req;
1716 struct dwc3_request *tmp;
1718 list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) {
1719 dwc3_gadget_ep_skip_trbs(dep, req);
1720 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1724 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1725 struct usb_request *request)
1727 struct dwc3_request *req = to_dwc3_request(request);
1728 struct dwc3_request *r = NULL;
1730 struct dwc3_ep *dep = to_dwc3_ep(ep);
1731 struct dwc3 *dwc = dep->dwc;
1733 unsigned long flags;
1736 trace_dwc3_ep_dequeue(req);
1738 spin_lock_irqsave(&dwc->lock, flags);
1740 list_for_each_entry(r, &dep->cancelled_list, list) {
1745 list_for_each_entry(r, &dep->pending_list, list) {
1747 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1752 list_for_each_entry(r, &dep->started_list, list) {
1754 struct dwc3_request *t;
1756 /* wait until it is processed */
1757 dwc3_stop_active_transfer(dep, true, true);
1760 * Remove any started request if the transfer is
1763 list_for_each_entry_safe(r, t, &dep->started_list, list)
1764 dwc3_gadget_move_cancelled_request(r);
1766 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
1772 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1776 spin_unlock_irqrestore(&dwc->lock, flags);
1781 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1783 struct dwc3_gadget_ep_cmd_params params;
1784 struct dwc3 *dwc = dep->dwc;
1785 struct dwc3_request *req;
1786 struct dwc3_request *tmp;
1789 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1790 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1794 memset(¶ms, 0x00, sizeof(params));
1797 struct dwc3_trb *trb;
1799 unsigned int transfer_in_flight;
1800 unsigned int started;
1802 if (dep->number > 1)
1803 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1805 trb = &dwc->ep0_trb[dep->trb_enqueue];
1807 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1808 started = !list_empty(&dep->started_list);
1810 if (!protocol && ((dep->direction && transfer_in_flight) ||
1811 (!dep->direction && started))) {
1815 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1818 dev_err(dwc->dev, "failed to set STALL on %s\n",
1821 dep->flags |= DWC3_EP_STALL;
1824 * Don't issue CLEAR_STALL command to control endpoints. The
1825 * controller automatically clears the STALL when it receives
1828 if (dep->number <= 1) {
1829 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1833 dwc3_stop_active_transfer(dep, true, true);
1835 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1836 dwc3_gadget_move_cancelled_request(req);
1838 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) {
1839 dep->flags |= DWC3_EP_PENDING_CLEAR_STALL;
1843 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1845 ret = dwc3_send_clear_stall_ep_cmd(dep);
1847 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1852 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1854 if ((dep->flags & DWC3_EP_DELAY_START) &&
1855 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
1856 __dwc3_gadget_kick_transfer(dep);
1858 dep->flags &= ~DWC3_EP_DELAY_START;
1864 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1866 struct dwc3_ep *dep = to_dwc3_ep(ep);
1867 struct dwc3 *dwc = dep->dwc;
1869 unsigned long flags;
1873 spin_lock_irqsave(&dwc->lock, flags);
1874 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1875 spin_unlock_irqrestore(&dwc->lock, flags);
1880 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1882 struct dwc3_ep *dep = to_dwc3_ep(ep);
1883 struct dwc3 *dwc = dep->dwc;
1884 unsigned long flags;
1887 spin_lock_irqsave(&dwc->lock, flags);
1888 dep->flags |= DWC3_EP_WEDGE;
1890 if (dep->number == 0 || dep->number == 1)
1891 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1893 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1894 spin_unlock_irqrestore(&dwc->lock, flags);
1899 /* -------------------------------------------------------------------------- */
1901 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1902 .bLength = USB_DT_ENDPOINT_SIZE,
1903 .bDescriptorType = USB_DT_ENDPOINT,
1904 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1907 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1908 .enable = dwc3_gadget_ep0_enable,
1909 .disable = dwc3_gadget_ep0_disable,
1910 .alloc_request = dwc3_gadget_ep_alloc_request,
1911 .free_request = dwc3_gadget_ep_free_request,
1912 .queue = dwc3_gadget_ep0_queue,
1913 .dequeue = dwc3_gadget_ep_dequeue,
1914 .set_halt = dwc3_gadget_ep0_set_halt,
1915 .set_wedge = dwc3_gadget_ep_set_wedge,
1918 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1919 .enable = dwc3_gadget_ep_enable,
1920 .disable = dwc3_gadget_ep_disable,
1921 .alloc_request = dwc3_gadget_ep_alloc_request,
1922 .free_request = dwc3_gadget_ep_free_request,
1923 .queue = dwc3_gadget_ep_queue,
1924 .dequeue = dwc3_gadget_ep_dequeue,
1925 .set_halt = dwc3_gadget_ep_set_halt,
1926 .set_wedge = dwc3_gadget_ep_set_wedge,
1929 /* -------------------------------------------------------------------------- */
1931 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1933 struct dwc3 *dwc = gadget_to_dwc(g);
1935 return __dwc3_gadget_get_frame(dwc);
1938 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1948 * According to the Databook Remote wakeup request should
1949 * be issued only when the device is in early suspend state.
1951 * We can check that via USB Link State bits in DSTS register.
1953 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1955 link_state = DWC3_DSTS_USBLNKST(reg);
1957 switch (link_state) {
1958 case DWC3_LINK_STATE_RESET:
1959 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1960 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1961 case DWC3_LINK_STATE_RESUME:
1967 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1969 dev_err(dwc->dev, "failed to put link in Recovery\n");
1973 /* Recent versions do this automatically */
1974 if (DWC3_VER_IS_PRIOR(DWC3, 194A)) {
1975 /* write zeroes to Link Change Request */
1976 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1977 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1978 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1981 /* poll until Link State changes to ON */
1985 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1987 /* in HS, means ON */
1988 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1992 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1993 dev_err(dwc->dev, "failed to send remote wakeup\n");
2000 static int dwc3_gadget_wakeup(struct usb_gadget *g)
2002 struct dwc3 *dwc = gadget_to_dwc(g);
2003 unsigned long flags;
2006 spin_lock_irqsave(&dwc->lock, flags);
2007 ret = __dwc3_gadget_wakeup(dwc);
2008 spin_unlock_irqrestore(&dwc->lock, flags);
2013 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
2016 struct dwc3 *dwc = gadget_to_dwc(g);
2017 unsigned long flags;
2019 spin_lock_irqsave(&dwc->lock, flags);
2020 g->is_selfpowered = !!is_selfpowered;
2021 spin_unlock_irqrestore(&dwc->lock, flags);
2026 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2030 for (epnum = 2; epnum < dwc->num_eps; epnum++) {
2031 struct dwc3_ep *dep;
2033 dep = dwc->eps[epnum];
2037 dwc3_remove_requests(dwc, dep);
2041 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
2046 if (pm_runtime_suspended(dwc->dev))
2049 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2051 if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) {
2052 reg &= ~DWC3_DCTL_TRGTULST_MASK;
2053 reg |= DWC3_DCTL_TRGTULST_RX_DET;
2056 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
2057 reg &= ~DWC3_DCTL_KEEP_CONNECT;
2058 reg |= DWC3_DCTL_RUN_STOP;
2060 if (dwc->has_hibernation)
2061 reg |= DWC3_DCTL_KEEP_CONNECT;
2063 dwc->pullups_connected = true;
2065 reg &= ~DWC3_DCTL_RUN_STOP;
2067 if (dwc->has_hibernation && !suspend)
2068 reg &= ~DWC3_DCTL_KEEP_CONNECT;
2070 dwc->pullups_connected = false;
2073 dwc3_gadget_dctl_write_safe(dwc, reg);
2076 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2077 reg &= DWC3_DSTS_DEVCTRLHLT;
2078 } while (--timeout && !(!is_on ^ !reg));
2086 static void dwc3_gadget_disable_irq(struct dwc3 *dwc);
2087 static void __dwc3_gadget_stop(struct dwc3 *dwc);
2088 static int __dwc3_gadget_start(struct dwc3 *dwc);
2090 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
2092 struct dwc3 *dwc = gadget_to_dwc(g);
2093 unsigned long flags;
2099 * Per databook, when we want to stop the gadget, if a control transfer
2100 * is still in process, complete it and get the core into setup phase.
2102 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
2103 reinit_completion(&dwc->ep0_in_setup);
2105 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
2106 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
2108 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
2114 * Synchronize any pending event handling before executing the controller
2118 dwc3_gadget_disable_irq(dwc);
2119 synchronize_irq(dwc->irq_gadget);
2122 spin_lock_irqsave(&dwc->lock, flags);
2128 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
2129 * Section 4.1.8 Table 4-7, it states that for a device-initiated
2130 * disconnect, the SW needs to ensure that it sends "a DEPENDXFER
2131 * command for any active transfers" before clearing the RunStop
2134 dwc3_stop_active_transfers(dwc);
2135 __dwc3_gadget_stop(dwc);
2138 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
2139 * Section 1.3.4, it mentions that for the DEVCTRLHLT bit, the
2140 * "software needs to acknowledge the events that are generated
2141 * (by writing to GEVNTCOUNTn) while it is waiting for this bit
2142 * to be set to '1'."
2144 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2145 count &= DWC3_GEVNTCOUNT_MASK;
2147 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
2148 dwc->ev_buf->lpos = (dwc->ev_buf->lpos + count) %
2149 dwc->ev_buf->length;
2152 __dwc3_gadget_start(dwc);
2155 ret = dwc3_gadget_run_stop(dwc, is_on, false);
2156 spin_unlock_irqrestore(&dwc->lock, flags);
2161 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
2165 /* Enable all but Start and End of Frame IRQs */
2166 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2167 DWC3_DEVTEN_EVNTOVERFLOWEN |
2168 DWC3_DEVTEN_CMDCMPLTEN |
2169 DWC3_DEVTEN_ERRTICERREN |
2170 DWC3_DEVTEN_WKUPEVTEN |
2171 DWC3_DEVTEN_CONNECTDONEEN |
2172 DWC3_DEVTEN_USBRSTEN |
2173 DWC3_DEVTEN_DISCONNEVTEN);
2175 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2176 reg |= DWC3_DEVTEN_ULSTCNGEN;
2178 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2181 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
2183 /* mask all interrupts */
2184 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2187 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
2188 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
2191 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
2192 * @dwc: pointer to our context structure
2194 * The following looks like complex but it's actually very simple. In order to
2195 * calculate the number of packets we can burst at once on OUT transfers, we're
2196 * gonna use RxFIFO size.
2198 * To calculate RxFIFO size we need two numbers:
2199 * MDWIDTH = size, in bits, of the internal memory bus
2200 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
2202 * Given these two numbers, the formula is simple:
2204 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
2206 * 24 bytes is for 3x SETUP packets
2207 * 16 bytes is a clock domain crossing tolerance
2209 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
2211 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
2218 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
2219 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
2220 if (DWC3_IP_IS(DWC32))
2221 mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6);
2223 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
2224 nump = min_t(u32, nump, 16);
2227 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2228 reg &= ~DWC3_DCFG_NUMP_MASK;
2229 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
2230 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2233 static int __dwc3_gadget_start(struct dwc3 *dwc)
2235 struct dwc3_ep *dep;
2240 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
2241 * the core supports IMOD, disable it.
2243 if (dwc->imod_interval) {
2244 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2245 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2246 } else if (dwc3_has_imod(dwc)) {
2247 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
2251 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
2252 * field instead of letting dwc3 itself calculate that automatically.
2254 * This way, we maximize the chances that we'll be able to get several
2255 * bursts of data without going through any sort of endpoint throttling.
2257 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
2258 if (DWC3_IP_IS(DWC3))
2259 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
2261 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
2263 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
2265 dwc3_gadget_setup_nump(dwc);
2267 /* Start with SuperSpeed Default */
2268 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2271 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2273 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2278 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2280 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2284 /* begin to receive SETUP packets */
2285 dwc->ep0state = EP0_SETUP_PHASE;
2286 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
2287 dwc3_ep0_out_start(dwc);
2289 dwc3_gadget_enable_irq(dwc);
2294 __dwc3_gadget_ep_disable(dwc->eps[0]);
2300 static int dwc3_gadget_start(struct usb_gadget *g,
2301 struct usb_gadget_driver *driver)
2303 struct dwc3 *dwc = gadget_to_dwc(g);
2304 unsigned long flags;
2308 irq = dwc->irq_gadget;
2309 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2310 IRQF_SHARED, "dwc3", dwc->ev_buf);
2312 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2317 spin_lock_irqsave(&dwc->lock, flags);
2318 if (dwc->gadget_driver) {
2319 dev_err(dwc->dev, "%s is already bound to %s\n",
2321 dwc->gadget_driver->driver.name);
2326 dwc->gadget_driver = driver;
2327 spin_unlock_irqrestore(&dwc->lock, flags);
2332 spin_unlock_irqrestore(&dwc->lock, flags);
2339 static void __dwc3_gadget_stop(struct dwc3 *dwc)
2341 dwc3_gadget_disable_irq(dwc);
2342 __dwc3_gadget_ep_disable(dwc->eps[0]);
2343 __dwc3_gadget_ep_disable(dwc->eps[1]);
2346 static int dwc3_gadget_stop(struct usb_gadget *g)
2348 struct dwc3 *dwc = gadget_to_dwc(g);
2349 unsigned long flags;
2351 spin_lock_irqsave(&dwc->lock, flags);
2352 dwc->gadget_driver = NULL;
2353 spin_unlock_irqrestore(&dwc->lock, flags);
2355 free_irq(dwc->irq_gadget, dwc->ev_buf);
2360 static void dwc3_gadget_config_params(struct usb_gadget *g,
2361 struct usb_dcd_config_params *params)
2363 struct dwc3 *dwc = gadget_to_dwc(g);
2365 params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
2366 params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
2368 /* Recommended BESL */
2369 if (!dwc->dis_enblslpm_quirk) {
2371 * If the recommended BESL baseline is 0 or if the BESL deep is
2372 * less than 2, Microsoft's Windows 10 host usb stack will issue
2373 * a usb reset immediately after it receives the extended BOS
2374 * descriptor and the enumeration will fail. To maintain
2375 * compatibility with the Windows' usb stack, let's set the
2376 * recommended BESL baseline to 1 and clamp the BESL deep to be
2379 params->besl_baseline = 1;
2380 if (dwc->is_utmi_l1_suspend)
2382 clamp_t(u8, dwc->hird_threshold, 2, 15);
2385 /* U1 Device exit Latency */
2386 if (dwc->dis_u1_entry_quirk)
2387 params->bU1devExitLat = 0;
2389 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
2391 /* U2 Device exit Latency */
2392 if (dwc->dis_u2_entry_quirk)
2393 params->bU2DevExitLat = 0;
2395 params->bU2DevExitLat =
2396 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
2399 static void dwc3_gadget_set_speed(struct usb_gadget *g,
2400 enum usb_device_speed speed)
2402 struct dwc3 *dwc = gadget_to_dwc(g);
2403 unsigned long flags;
2406 spin_lock_irqsave(&dwc->lock, flags);
2407 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2408 reg &= ~(DWC3_DCFG_SPEED_MASK);
2411 * WORKAROUND: DWC3 revision < 2.20a have an issue
2412 * which would cause metastability state on Run/Stop
2413 * bit if we try to force the IP to USB2-only mode.
2415 * Because of that, we cannot configure the IP to any
2416 * speed other than the SuperSpeed
2420 * STAR#9000525659: Clock Domain Crossing on DCTL in
2423 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
2424 !dwc->dis_metastability_quirk) {
2425 reg |= DWC3_DCFG_SUPERSPEED;
2429 reg |= DWC3_DCFG_LOWSPEED;
2431 case USB_SPEED_FULL:
2432 reg |= DWC3_DCFG_FULLSPEED;
2434 case USB_SPEED_HIGH:
2435 reg |= DWC3_DCFG_HIGHSPEED;
2437 case USB_SPEED_SUPER:
2438 reg |= DWC3_DCFG_SUPERSPEED;
2440 case USB_SPEED_SUPER_PLUS:
2441 if (DWC3_IP_IS(DWC3))
2442 reg |= DWC3_DCFG_SUPERSPEED;
2444 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2447 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2449 if (DWC3_IP_IS(DWC3))
2450 reg |= DWC3_DCFG_SUPERSPEED;
2452 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2455 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2457 spin_unlock_irqrestore(&dwc->lock, flags);
2460 static const struct usb_gadget_ops dwc3_gadget_ops = {
2461 .get_frame = dwc3_gadget_get_frame,
2462 .wakeup = dwc3_gadget_wakeup,
2463 .set_selfpowered = dwc3_gadget_set_selfpowered,
2464 .pullup = dwc3_gadget_pullup,
2465 .udc_start = dwc3_gadget_start,
2466 .udc_stop = dwc3_gadget_stop,
2467 .udc_set_speed = dwc3_gadget_set_speed,
2468 .get_config_params = dwc3_gadget_config_params,
2471 /* -------------------------------------------------------------------------- */
2473 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2475 struct dwc3 *dwc = dep->dwc;
2477 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2478 dep->endpoint.maxburst = 1;
2479 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2480 if (!dep->direction)
2481 dwc->gadget->ep0 = &dep->endpoint;
2483 dep->endpoint.caps.type_control = true;
2488 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2490 struct dwc3 *dwc = dep->dwc;
2494 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2495 if (DWC3_IP_IS(DWC32))
2496 mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6);
2498 /* MDWIDTH is represented in bits, we need it in bytes */
2501 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2502 if (DWC3_IP_IS(DWC3))
2503 size = DWC3_GTXFIFOSIZ_TXFDEP(size);
2505 size = DWC31_GTXFIFOSIZ_TXFDEP(size);
2507 /* FIFO Depth is in MDWDITH bytes. Multiply */
2511 * To meet performance requirement, a minimum TxFIFO size of 3x
2512 * MaxPacketSize is recommended for endpoints that support burst and a
2513 * minimum TxFIFO size of 2x MaxPacketSize for endpoints that don't
2514 * support burst. Use those numbers and we can calculate the max packet
2517 if (dwc->maximum_speed >= USB_SPEED_SUPER)
2522 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2524 dep->endpoint.max_streams = 16;
2525 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2526 list_add_tail(&dep->endpoint.ep_list,
2527 &dwc->gadget->ep_list);
2528 dep->endpoint.caps.type_iso = true;
2529 dep->endpoint.caps.type_bulk = true;
2530 dep->endpoint.caps.type_int = true;
2532 return dwc3_alloc_trb_pool(dep);
2535 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2537 struct dwc3 *dwc = dep->dwc;
2541 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2542 if (DWC3_IP_IS(DWC32))
2543 mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6);
2545 /* MDWIDTH is represented in bits, convert to bytes */
2548 /* All OUT endpoints share a single RxFIFO space */
2549 size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0));
2550 if (DWC3_IP_IS(DWC3))
2551 size = DWC3_GRXFIFOSIZ_RXFDEP(size);
2553 size = DWC31_GRXFIFOSIZ_RXFDEP(size);
2555 /* FIFO depth is in MDWDITH bytes */
2559 * To meet performance requirement, a minimum recommended RxFIFO size
2560 * is defined as follow:
2561 * RxFIFO size >= (3 x MaxPacketSize) +
2562 * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin)
2564 * Then calculate the max packet limit as below.
2566 size -= (3 * 8) + 16;
2572 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2573 dep->endpoint.max_streams = 16;
2574 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2575 list_add_tail(&dep->endpoint.ep_list,
2576 &dwc->gadget->ep_list);
2577 dep->endpoint.caps.type_iso = true;
2578 dep->endpoint.caps.type_bulk = true;
2579 dep->endpoint.caps.type_int = true;
2581 return dwc3_alloc_trb_pool(dep);
2584 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
2586 struct dwc3_ep *dep;
2587 bool direction = epnum & 1;
2589 u8 num = epnum >> 1;
2591 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2596 dep->number = epnum;
2597 dep->direction = direction;
2598 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2599 dwc->eps[epnum] = dep;
2601 dep->start_cmd_status = 0;
2603 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2604 direction ? "in" : "out");
2606 dep->endpoint.name = dep->name;
2608 if (!(dep->number > 1)) {
2609 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2610 dep->endpoint.comp_desc = NULL;
2614 ret = dwc3_gadget_init_control_endpoint(dep);
2616 ret = dwc3_gadget_init_in_endpoint(dep);
2618 ret = dwc3_gadget_init_out_endpoint(dep);
2623 dep->endpoint.caps.dir_in = direction;
2624 dep->endpoint.caps.dir_out = !direction;
2626 INIT_LIST_HEAD(&dep->pending_list);
2627 INIT_LIST_HEAD(&dep->started_list);
2628 INIT_LIST_HEAD(&dep->cancelled_list);
2633 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2637 INIT_LIST_HEAD(&dwc->gadget->ep_list);
2639 for (epnum = 0; epnum < total; epnum++) {
2642 ret = dwc3_gadget_init_endpoint(dwc, epnum);
2650 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2652 struct dwc3_ep *dep;
2655 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2656 dep = dwc->eps[epnum];
2660 * Physical endpoints 0 and 1 are special; they form the
2661 * bi-directional USB endpoint 0.
2663 * For those two physical endpoints, we don't allocate a TRB
2664 * pool nor do we add them the endpoints list. Due to that, we
2665 * shouldn't do these two operations otherwise we would end up
2666 * with all sorts of bugs when removing dwc3.ko.
2668 if (epnum != 0 && epnum != 1) {
2669 dwc3_free_trb_pool(dep);
2670 list_del(&dep->endpoint.ep_list);
2677 /* -------------------------------------------------------------------------- */
2679 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
2680 struct dwc3_request *req, struct dwc3_trb *trb,
2681 const struct dwc3_event_depevt *event, int status, int chain)
2685 dwc3_ep_inc_deq(dep);
2687 trace_dwc3_complete_trb(dep, trb);
2691 * If we're in the middle of series of chained TRBs and we
2692 * receive a short transfer along the way, DWC3 will skip
2693 * through all TRBs including the last TRB in the chain (the
2694 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2695 * bit and SW has to do it manually.
2697 * We're going to do that here to avoid problems of HW trying
2698 * to use bogus TRBs for transfers.
2700 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2701 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2704 * For isochronous transfers, the first TRB in a service interval must
2705 * have the Isoc-First type. Track and report its interval frame number.
2707 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2708 (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
2709 unsigned int frame_number;
2711 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
2712 frame_number &= ~(dep->interval - 1);
2713 req->request.frame_number = frame_number;
2717 * We use bounce buffer for requests that needs extra TRB or OUT ZLP. If
2718 * this TRB points to the bounce buffer address, it's a MPS alignment
2719 * TRB. Don't add it to req->remaining calculation.
2721 if (trb->bpl == lower_32_bits(dep->dwc->bounce_addr) &&
2722 trb->bph == upper_32_bits(dep->dwc->bounce_addr)) {
2723 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2727 count = trb->size & DWC3_TRB_SIZE_MASK;
2728 req->remaining += count;
2730 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2733 if (event->status & DEPEVT_STATUS_SHORT && !chain)
2736 if ((trb->ctrl & DWC3_TRB_CTRL_IOC) ||
2737 (trb->ctrl & DWC3_TRB_CTRL_LST))
2743 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
2744 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2747 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2748 struct scatterlist *sg = req->sg;
2749 struct scatterlist *s;
2750 unsigned int pending = req->num_pending_sgs;
2754 for_each_sg(sg, s, pending, i) {
2755 trb = &dep->trb_pool[dep->trb_dequeue];
2757 req->sg = sg_next(s);
2758 req->num_pending_sgs--;
2760 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
2761 trb, event, status, true);
2769 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
2770 struct dwc3_request *req, const struct dwc3_event_depevt *event,
2773 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2775 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
2776 event, status, false);
2779 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
2781 return req->num_pending_sgs == 0;
2784 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
2785 const struct dwc3_event_depevt *event,
2786 struct dwc3_request *req, int status)
2790 if (req->num_pending_sgs)
2791 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
2794 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2797 req->request.actual = req->request.length - req->remaining;
2799 if (!dwc3_gadget_ep_request_completed(req))
2802 if (req->needs_extra_trb) {
2803 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2805 req->needs_extra_trb = false;
2808 dwc3_gadget_giveback(dep, req, status);
2814 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
2815 const struct dwc3_event_depevt *event, int status)
2817 struct dwc3_request *req;
2818 struct dwc3_request *tmp;
2820 list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
2823 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
2830 static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep)
2832 struct dwc3_request *req;
2834 if (!list_empty(&dep->pending_list))
2838 * We only need to check the first entry of the started list. We can
2839 * assume the completed requests are removed from the started list.
2841 req = next_request(&dep->started_list);
2845 return !dwc3_gadget_ep_request_completed(req);
2848 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
2849 const struct dwc3_event_depevt *event)
2851 dep->frame_number = event->parameters;
2854 static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep,
2855 const struct dwc3_event_depevt *event, int status)
2857 struct dwc3 *dwc = dep->dwc;
2858 bool no_started_trb = true;
2860 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
2862 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
2865 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2866 list_empty(&dep->started_list) &&
2867 (list_empty(&dep->pending_list) || status == -EXDEV))
2868 dwc3_stop_active_transfer(dep, true, true);
2869 else if (dwc3_gadget_ep_should_continue(dep))
2870 if (__dwc3_gadget_kick_transfer(dep) == 0)
2871 no_started_trb = false;
2875 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2876 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2878 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
2882 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2885 if (!(dep->flags & DWC3_EP_ENABLED))
2888 if (!list_empty(&dep->started_list))
2889 return no_started_trb;
2892 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2894 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2899 return no_started_trb;
2902 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
2903 const struct dwc3_event_depevt *event)
2907 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
2908 dwc3_gadget_endpoint_frame_from_event(dep, event);
2910 if (event->status & DEPEVT_STATUS_BUSERR)
2911 status = -ECONNRESET;
2913 if (event->status & DEPEVT_STATUS_MISSED_ISOC)
2916 dwc3_gadget_endpoint_trbs_complete(dep, event, status);
2919 static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep,
2920 const struct dwc3_event_depevt *event)
2924 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
2926 if (event->status & DEPEVT_STATUS_BUSERR)
2927 status = -ECONNRESET;
2929 if (dwc3_gadget_endpoint_trbs_complete(dep, event, status))
2930 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
2933 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
2934 const struct dwc3_event_depevt *event)
2936 dwc3_gadget_endpoint_frame_from_event(dep, event);
2939 * The XferNotReady event is generated only once before the endpoint
2940 * starts. It will be generated again when END_TRANSFER command is
2941 * issued. For some controller versions, the XferNotReady event may be
2942 * generated while the END_TRANSFER command is still in process. Ignore
2943 * it and wait for the next XferNotReady event after the command is
2946 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
2949 (void) __dwc3_gadget_start_isoc(dep);
2952 static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep *dep,
2953 const struct dwc3_event_depevt *event)
2955 u8 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2957 if (cmd != DWC3_DEPCMD_ENDTRANSFER)
2960 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2961 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
2962 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2964 if (dep->flags & DWC3_EP_PENDING_CLEAR_STALL) {
2965 struct dwc3 *dwc = dep->dwc;
2967 dep->flags &= ~DWC3_EP_PENDING_CLEAR_STALL;
2968 if (dwc3_send_clear_stall_ep_cmd(dep)) {
2969 struct usb_ep *ep0 = &dwc->eps[0]->endpoint;
2971 dev_err(dwc->dev, "failed to clear STALL on %s\n", dep->name);
2972 if (dwc->delayed_status)
2973 __dwc3_gadget_ep0_set_halt(ep0, 1);
2977 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2978 if (dwc->delayed_status)
2979 dwc3_ep0_send_delayed_status(dwc);
2982 if ((dep->flags & DWC3_EP_DELAY_START) &&
2983 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
2984 __dwc3_gadget_kick_transfer(dep);
2986 dep->flags &= ~DWC3_EP_DELAY_START;
2989 static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep,
2990 const struct dwc3_event_depevt *event)
2992 struct dwc3 *dwc = dep->dwc;
2994 if (event->status == DEPEVT_STREAMEVT_FOUND) {
2995 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
2999 /* Note: NoStream rejection event param value is 0 and not 0xFFFF */
3000 switch (event->parameters) {
3001 case DEPEVT_STREAM_PRIME:
3003 * If the host can properly transition the endpoint state from
3004 * idle to prime after a NoStream rejection, there's no need to
3005 * force restarting the endpoint to reinitiate the stream. To
3006 * simplify the check, assume the host follows the USB spec if
3007 * it primed the endpoint more than once.
3009 if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) {
3010 if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED)
3011 dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM;
3013 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3017 case DEPEVT_STREAM_NOSTREAM:
3018 if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) ||
3019 !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) ||
3020 !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE))
3024 * If the host rejects a stream due to no active stream, by the
3025 * USB and xHCI spec, the endpoint will be put back to idle
3026 * state. When the host is ready (buffer added/updated), it will
3027 * prime the endpoint to inform the usb device controller. This
3028 * triggers the device controller to issue ERDY to restart the
3029 * stream. However, some hosts don't follow this and keep the
3030 * endpoint in the idle state. No prime will come despite host
3031 * streams are updated, and the device controller will not be
3032 * triggered to generate ERDY to move the next stream data. To
3033 * workaround this and maintain compatibility with various
3034 * hosts, force to reinitate the stream until the host is ready
3035 * instead of waiting for the host to prime the endpoint.
3037 if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) {
3038 unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME;
3040 dwc3_send_gadget_generic_command(dwc, cmd, dep->number);
3042 dep->flags |= DWC3_EP_DELAY_START;
3043 dwc3_stop_active_transfer(dep, true, true);
3050 dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM;
3053 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
3054 const struct dwc3_event_depevt *event)
3056 struct dwc3_ep *dep;
3057 u8 epnum = event->endpoint_number;
3059 dep = dwc->eps[epnum];
3061 if (!(dep->flags & DWC3_EP_ENABLED)) {
3062 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
3065 /* Handle only EPCMDCMPLT when EP disabled */
3066 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
3070 if (epnum == 0 || epnum == 1) {
3071 dwc3_ep0_interrupt(dwc, event);
3075 switch (event->endpoint_event) {
3076 case DWC3_DEPEVT_XFERINPROGRESS:
3077 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
3079 case DWC3_DEPEVT_XFERNOTREADY:
3080 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
3082 case DWC3_DEPEVT_EPCMDCMPLT:
3083 dwc3_gadget_endpoint_command_complete(dep, event);
3085 case DWC3_DEPEVT_XFERCOMPLETE:
3086 dwc3_gadget_endpoint_transfer_complete(dep, event);
3088 case DWC3_DEPEVT_STREAMEVT:
3089 dwc3_gadget_endpoint_stream_event(dep, event);
3091 case DWC3_DEPEVT_RXTXFIFOEVT:
3096 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
3098 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
3099 spin_unlock(&dwc->lock);
3100 dwc->gadget_driver->disconnect(dwc->gadget);
3101 spin_lock(&dwc->lock);
3105 static void dwc3_suspend_gadget(struct dwc3 *dwc)
3107 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
3108 spin_unlock(&dwc->lock);
3109 dwc->gadget_driver->suspend(dwc->gadget);
3110 spin_lock(&dwc->lock);
3114 static void dwc3_resume_gadget(struct dwc3 *dwc)
3116 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
3117 spin_unlock(&dwc->lock);
3118 dwc->gadget_driver->resume(dwc->gadget);
3119 spin_lock(&dwc->lock);
3123 static void dwc3_reset_gadget(struct dwc3 *dwc)
3125 if (!dwc->gadget_driver)
3128 if (dwc->gadget->speed != USB_SPEED_UNKNOWN) {
3129 spin_unlock(&dwc->lock);
3130 usb_gadget_udc_reset(dwc->gadget, dwc->gadget_driver);
3131 spin_lock(&dwc->lock);
3135 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
3138 struct dwc3_gadget_ep_cmd_params params;
3142 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) ||
3143 (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
3147 * NOTICE: We are violating what the Databook says about the
3148 * EndTransfer command. Ideally we would _always_ wait for the
3149 * EndTransfer Command Completion IRQ, but that's causing too
3150 * much trouble synchronizing between us and gadget driver.
3152 * We have discussed this with the IP Provider and it was
3153 * suggested to giveback all requests here.
3155 * Note also that a similar handling was tested by Synopsys
3156 * (thanks a lot Paul) and nothing bad has come out of it.
3157 * In short, what we're doing is issuing EndTransfer with
3158 * CMDIOC bit set and delay kicking transfer until the
3159 * EndTransfer command had completed.
3161 * As of IP version 3.10a of the DWC_usb3 IP, the controller
3162 * supports a mode to work around the above limitation. The
3163 * software can poll the CMDACT bit in the DEPCMD register
3164 * after issuing a EndTransfer command. This mode is enabled
3165 * by writing GUCTL2[14]. This polling is already done in the
3166 * dwc3_send_gadget_ep_cmd() function so if the mode is
3167 * enabled, the EndTransfer command will have completed upon
3168 * returning from this function.
3170 * This mode is NOT available on the DWC_usb31 IP.
3173 cmd = DWC3_DEPCMD_ENDTRANSFER;
3174 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
3175 cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
3176 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3177 memset(¶ms, 0, sizeof(params));
3178 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
3180 dep->resource_index = 0;
3183 * The END_TRANSFER command will cause the controller to generate a
3184 * NoStream Event, and it's not due to the host DP NoStream rejection.
3185 * Ignore the next NoStream event.
3187 if (dep->stream_capable)
3188 dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM;
3191 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3193 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
3196 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
3200 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3201 struct dwc3_ep *dep;
3204 dep = dwc->eps[epnum];
3208 if (!(dep->flags & DWC3_EP_STALL))
3211 dep->flags &= ~DWC3_EP_STALL;
3213 ret = dwc3_send_clear_stall_ep_cmd(dep);
3218 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
3222 dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET);
3224 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3225 reg &= ~DWC3_DCTL_INITU1ENA;
3226 reg &= ~DWC3_DCTL_INITU2ENA;
3227 dwc3_gadget_dctl_write_safe(dwc, reg);
3229 dwc3_disconnect_gadget(dwc);
3231 dwc->gadget->speed = USB_SPEED_UNKNOWN;
3232 dwc->setup_packet_pending = false;
3233 usb_gadget_set_state(dwc->gadget, USB_STATE_NOTATTACHED);
3235 dwc->connected = false;
3238 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
3242 dwc->connected = true;
3245 * WORKAROUND: DWC3 revisions <1.88a have an issue which
3246 * would cause a missing Disconnect Event if there's a
3247 * pending Setup Packet in the FIFO.
3249 * There's no suggested workaround on the official Bug
3250 * report, which states that "unless the driver/application
3251 * is doing any special handling of a disconnect event,
3252 * there is no functional issue".
3254 * Unfortunately, it turns out that we _do_ some special
3255 * handling of a disconnect event, namely complete all
3256 * pending transfers, notify gadget driver of the
3257 * disconnection, and so on.
3259 * Our suggested workaround is to follow the Disconnect
3260 * Event steps here, instead, based on a setup_packet_pending
3261 * flag. Such flag gets set whenever we have a SETUP_PENDING
3262 * status for EP0 TRBs and gets cleared on XferComplete for the
3267 * STAR#9000466709: RTL: Device : Disconnect event not
3268 * generated if setup packet pending in FIFO
3270 if (DWC3_VER_IS_PRIOR(DWC3, 188A)) {
3271 if (dwc->setup_packet_pending)
3272 dwc3_gadget_disconnect_interrupt(dwc);
3275 dwc3_reset_gadget(dwc);
3277 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
3278 * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW
3279 * needs to ensure that it sends "a DEPENDXFER command for any active
3282 dwc3_stop_active_transfers(dwc);
3284 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3285 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
3286 dwc3_gadget_dctl_write_safe(dwc, reg);
3287 dwc->test_mode = false;
3288 dwc3_clear_stall_all_ep(dwc);
3290 /* Reset device address to zero */
3291 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3292 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
3293 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3296 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
3298 struct dwc3_ep *dep;
3303 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
3304 speed = reg & DWC3_DSTS_CONNECTSPD;
3308 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
3309 * each time on Connect Done.
3311 * Currently we always use the reset value. If any platform
3312 * wants to set this to a different value, we need to add a
3313 * setting and update GCTL.RAMCLKSEL here.
3317 case DWC3_DSTS_SUPERSPEED_PLUS:
3318 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3319 dwc->gadget->ep0->maxpacket = 512;
3320 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
3322 case DWC3_DSTS_SUPERSPEED:
3324 * WORKAROUND: DWC3 revisions <1.90a have an issue which
3325 * would cause a missing USB3 Reset event.
3327 * In such situations, we should force a USB3 Reset
3328 * event by calling our dwc3_gadget_reset_interrupt()
3333 * STAR#9000483510: RTL: SS : USB3 reset event may
3334 * not be generated always when the link enters poll
3336 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
3337 dwc3_gadget_reset_interrupt(dwc);
3339 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3340 dwc->gadget->ep0->maxpacket = 512;
3341 dwc->gadget->speed = USB_SPEED_SUPER;
3343 case DWC3_DSTS_HIGHSPEED:
3344 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3345 dwc->gadget->ep0->maxpacket = 64;
3346 dwc->gadget->speed = USB_SPEED_HIGH;
3348 case DWC3_DSTS_FULLSPEED:
3349 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3350 dwc->gadget->ep0->maxpacket = 64;
3351 dwc->gadget->speed = USB_SPEED_FULL;
3353 case DWC3_DSTS_LOWSPEED:
3354 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
3355 dwc->gadget->ep0->maxpacket = 8;
3356 dwc->gadget->speed = USB_SPEED_LOW;
3360 dwc->eps[1]->endpoint.maxpacket = dwc->gadget->ep0->maxpacket;
3362 /* Enable USB2 LPM Capability */
3364 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) &&
3365 (speed != DWC3_DSTS_SUPERSPEED) &&
3366 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
3367 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3368 reg |= DWC3_DCFG_LPM_CAP;
3369 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3371 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3372 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
3374 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
3375 (dwc->is_utmi_l1_suspend << 4));
3378 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
3379 * DCFG.LPMCap is set, core responses with an ACK and the
3380 * BESL value in the LPM token is less than or equal to LPM
3383 WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum,
3384 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
3386 if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A))
3387 reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
3389 dwc3_gadget_dctl_write_safe(dwc, reg);
3391 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3392 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
3393 dwc3_gadget_dctl_write_safe(dwc, reg);
3397 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3399 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3404 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3406 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3411 * Configure PHY via GUSB3PIPECTLn if required.
3413 * Update GTXFIFOSIZn
3415 * In both cases reset values should be sufficient.
3419 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
3422 * TODO take core out of low power mode when that's
3426 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
3427 spin_unlock(&dwc->lock);
3428 dwc->gadget_driver->resume(dwc->gadget);
3429 spin_lock(&dwc->lock);
3433 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
3434 unsigned int evtinfo)
3436 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3437 unsigned int pwropt;
3440 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
3441 * Hibernation mode enabled which would show up when device detects
3442 * host-initiated U3 exit.
3444 * In that case, device will generate a Link State Change Interrupt
3445 * from U3 to RESUME which is only necessary if Hibernation is
3448 * There are no functional changes due to such spurious event and we
3449 * just need to ignore it.
3453 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
3456 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
3457 if (DWC3_VER_IS_PRIOR(DWC3, 250A) &&
3458 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
3459 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
3460 (next == DWC3_LINK_STATE_RESUME)) {
3466 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
3467 * on the link partner, the USB session might do multiple entry/exit
3468 * of low power states before a transfer takes place.
3470 * Due to this problem, we might experience lower throughput. The
3471 * suggested workaround is to disable DCTL[12:9] bits if we're
3472 * transitioning from U1/U2 to U0 and enable those bits again
3473 * after a transfer completes and there are no pending transfers
3474 * on any of the enabled endpoints.
3476 * This is the first half of that workaround.
3480 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
3481 * core send LGO_Ux entering U0
3483 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3484 if (next == DWC3_LINK_STATE_U0) {
3488 switch (dwc->link_state) {
3489 case DWC3_LINK_STATE_U1:
3490 case DWC3_LINK_STATE_U2:
3491 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3492 u1u2 = reg & (DWC3_DCTL_INITU2ENA
3493 | DWC3_DCTL_ACCEPTU2ENA
3494 | DWC3_DCTL_INITU1ENA
3495 | DWC3_DCTL_ACCEPTU1ENA);
3498 dwc->u1u2 = reg & u1u2;
3502 dwc3_gadget_dctl_write_safe(dwc, reg);
3512 case DWC3_LINK_STATE_U1:
3513 if (dwc->speed == USB_SPEED_SUPER)
3514 dwc3_suspend_gadget(dwc);
3516 case DWC3_LINK_STATE_U2:
3517 case DWC3_LINK_STATE_U3:
3518 dwc3_suspend_gadget(dwc);
3520 case DWC3_LINK_STATE_RESUME:
3521 dwc3_resume_gadget(dwc);
3528 dwc->link_state = next;
3531 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
3532 unsigned int evtinfo)
3534 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3536 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
3537 dwc3_suspend_gadget(dwc);
3539 dwc->link_state = next;
3542 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
3543 unsigned int evtinfo)
3545 unsigned int is_ss = evtinfo & BIT(4);
3548 * WORKAROUND: DWC3 revison 2.20a with hibernation support
3549 * have a known issue which can cause USB CV TD.9.23 to fail
3552 * Because of this issue, core could generate bogus hibernation
3553 * events which SW needs to ignore.
3557 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3558 * Device Fallback from SuperSpeed
3560 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
3563 /* enter hibernation here */
3566 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
3567 const struct dwc3_event_devt *event)
3569 switch (event->type) {
3570 case DWC3_DEVICE_EVENT_DISCONNECT:
3571 dwc3_gadget_disconnect_interrupt(dwc);
3573 case DWC3_DEVICE_EVENT_RESET:
3574 dwc3_gadget_reset_interrupt(dwc);
3576 case DWC3_DEVICE_EVENT_CONNECT_DONE:
3577 dwc3_gadget_conndone_interrupt(dwc);
3579 case DWC3_DEVICE_EVENT_WAKEUP:
3580 dwc3_gadget_wakeup_interrupt(dwc);
3582 case DWC3_DEVICE_EVENT_HIBER_REQ:
3583 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3584 "unexpected hibernation event\n"))
3587 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3589 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3590 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3592 case DWC3_DEVICE_EVENT_EOPF:
3593 /* It changed to be suspend event for version 2.30a and above */
3594 if (!DWC3_VER_IS_PRIOR(DWC3, 230A)) {
3596 * Ignore suspend event until the gadget enters into
3597 * USB_STATE_CONFIGURED state.
3599 if (dwc->gadget->state >= USB_STATE_CONFIGURED)
3600 dwc3_gadget_suspend_interrupt(dwc,
3604 case DWC3_DEVICE_EVENT_SOF:
3605 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
3606 case DWC3_DEVICE_EVENT_CMD_CMPL:
3607 case DWC3_DEVICE_EVENT_OVERFLOW:
3610 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3614 static void dwc3_process_event_entry(struct dwc3 *dwc,
3615 const union dwc3_event *event)
3617 trace_dwc3_event(event->raw, dwc);
3619 if (!event->type.is_devspec)
3620 dwc3_endpoint_interrupt(dwc, &event->depevt);
3621 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3622 dwc3_gadget_interrupt(dwc, &event->devt);
3624 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3627 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3629 struct dwc3 *dwc = evt->dwc;
3630 irqreturn_t ret = IRQ_NONE;
3636 if (!(evt->flags & DWC3_EVENT_PENDING))
3640 union dwc3_event event;
3642 event.raw = *(u32 *) (evt->cache + evt->lpos);
3644 dwc3_process_event_entry(dwc, &event);
3647 * FIXME we wrap around correctly to the next entry as
3648 * almost all entries are 4 bytes in size. There is one
3649 * entry which has 12 bytes which is a regular entry
3650 * followed by 8 bytes data. ATM I don't know how
3651 * things are organized if we get next to the a
3652 * boundary so I worry about that once we try to handle
3655 evt->lpos = (evt->lpos + 4) % evt->length;
3660 evt->flags &= ~DWC3_EVENT_PENDING;
3663 /* Unmask interrupt */
3664 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3665 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3666 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3668 if (dwc->imod_interval) {
3669 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3670 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3676 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3678 struct dwc3_event_buffer *evt = _evt;
3679 struct dwc3 *dwc = evt->dwc;
3680 unsigned long flags;
3681 irqreturn_t ret = IRQ_NONE;
3683 spin_lock_irqsave(&dwc->lock, flags);
3684 ret = dwc3_process_event_buf(evt);
3685 spin_unlock_irqrestore(&dwc->lock, flags);
3690 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3692 struct dwc3 *dwc = evt->dwc;
3697 if (pm_runtime_suspended(dwc->dev)) {
3698 pm_runtime_get(dwc->dev);
3699 disable_irq_nosync(dwc->irq_gadget);
3700 dwc->pending_events = true;
3705 * With PCIe legacy interrupt, test shows that top-half irq handler can
3706 * be called again after HW interrupt deassertion. Check if bottom-half
3707 * irq event handler completes before caching new event to prevent
3710 if (evt->flags & DWC3_EVENT_PENDING)
3713 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3714 count &= DWC3_GEVNTCOUNT_MASK;
3719 evt->flags |= DWC3_EVENT_PENDING;
3721 /* Mask interrupt */
3722 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3723 reg |= DWC3_GEVNTSIZ_INTMASK;
3724 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3726 amount = min(count, evt->length - evt->lpos);
3727 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3730 memcpy(evt->cache, evt->buf, count - amount);
3732 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3734 return IRQ_WAKE_THREAD;
3737 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3739 struct dwc3_event_buffer *evt = _evt;
3741 return dwc3_check_event_buf(evt);
3744 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3746 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3749 irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
3753 if (irq == -EPROBE_DEFER)
3756 irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
3760 if (irq == -EPROBE_DEFER)
3763 irq = platform_get_irq(dwc3_pdev, 0);
3774 static void dwc_gadget_release(struct device *dev)
3776 struct usb_gadget *gadget = container_of(dev, struct usb_gadget, dev);
3782 * dwc3_gadget_init - initializes gadget related registers
3783 * @dwc: pointer to our controller context structure
3785 * Returns 0 on success otherwise negative errno.
3787 int dwc3_gadget_init(struct dwc3 *dwc)
3793 irq = dwc3_gadget_get_irq(dwc);
3799 dwc->irq_gadget = irq;
3801 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3802 sizeof(*dwc->ep0_trb) * 2,
3803 &dwc->ep0_trb_addr, GFP_KERNEL);
3804 if (!dwc->ep0_trb) {
3805 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3810 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3811 if (!dwc->setup_buf) {
3816 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3817 &dwc->bounce_addr, GFP_KERNEL);
3823 init_completion(&dwc->ep0_in_setup);
3824 dwc->gadget = kzalloc(sizeof(struct usb_gadget), GFP_KERNEL);
3831 usb_initialize_gadget(dwc->dev, dwc->gadget, dwc_gadget_release);
3832 dev = &dwc->gadget->dev;
3833 dev->platform_data = dwc;
3834 dwc->gadget->ops = &dwc3_gadget_ops;
3835 dwc->gadget->speed = USB_SPEED_UNKNOWN;
3836 dwc->gadget->sg_supported = true;
3837 dwc->gadget->name = "dwc3-gadget";
3838 dwc->gadget->lpm_capable = true;
3841 * FIXME We might be setting max_speed to <SUPER, however versions
3842 * <2.20a of dwc3 have an issue with metastability (documented
3843 * elsewhere in this driver) which tells us we can't set max speed to
3844 * anything lower than SUPER.
3846 * Because gadget.max_speed is only used by composite.c and function
3847 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3848 * to happen so we avoid sending SuperSpeed Capability descriptor
3849 * together with our BOS descriptor as that could confuse host into
3850 * thinking we can handle super speed.
3852 * Note that, in fact, we won't even support GetBOS requests when speed
3853 * is less than super speed because we don't have means, yet, to tell
3854 * composite.c that we are USB 2.0 + LPM ECN.
3856 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
3857 !dwc->dis_metastability_quirk)
3858 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3861 dwc->gadget->max_speed = dwc->maximum_speed;
3864 * REVISIT: Here we should clear all pending IRQs to be
3865 * sure we're starting from a well known location.
3868 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3872 ret = usb_add_gadget(dwc->gadget);
3874 dev_err(dwc->dev, "failed to add gadget\n");
3878 dwc3_gadget_set_speed(dwc->gadget, dwc->maximum_speed);
3883 dwc3_gadget_free_endpoints(dwc);
3885 usb_put_gadget(dwc->gadget);
3887 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3891 kfree(dwc->setup_buf);
3894 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3895 dwc->ep0_trb, dwc->ep0_trb_addr);
3901 /* -------------------------------------------------------------------------- */
3903 void dwc3_gadget_exit(struct dwc3 *dwc)
3905 usb_del_gadget_udc(dwc->gadget);
3906 dwc3_gadget_free_endpoints(dwc);
3907 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3909 kfree(dwc->setup_buf);
3910 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3911 dwc->ep0_trb, dwc->ep0_trb_addr);
3914 int dwc3_gadget_suspend(struct dwc3 *dwc)
3916 if (!dwc->gadget_driver)
3919 dwc3_gadget_run_stop(dwc, false, false);
3920 dwc3_disconnect_gadget(dwc);
3921 __dwc3_gadget_stop(dwc);
3926 int dwc3_gadget_resume(struct dwc3 *dwc)
3930 if (!dwc->gadget_driver)
3933 ret = __dwc3_gadget_start(dwc);
3937 ret = dwc3_gadget_run_stop(dwc, true, false);
3944 __dwc3_gadget_stop(dwc);
3950 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3952 if (dwc->pending_events) {
3953 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3954 dwc->pending_events = false;
3955 enable_irq(dwc->irq_gadget);