fb5a09ffebb00915913feb8bc77e087452155627
[linux-2.6-microblaze.git] / drivers / usb / dwc3 / gadget.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4  *
5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6  *
7  * Authors: Felipe Balbi <balbi@ti.com>,
8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9  */
10
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/list.h>
20 #include <linux/dma-mapping.h>
21
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
24
25 #include "debug.h"
26 #include "core.h"
27 #include "gadget.h"
28 #include "io.h"
29
30 #define DWC3_ALIGN_FRAME(d, n)  (((d)->frame_number + ((d)->interval * (n))) \
31                                         & ~((d)->interval - 1))
32
33 /**
34  * dwc3_gadget_set_test_mode - enables usb2 test modes
35  * @dwc: pointer to our context structure
36  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
37  *
38  * Caller should take care of locking. This function will return 0 on
39  * success or -EINVAL if wrong Test Selector is passed.
40  */
41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
42 {
43         u32             reg;
44
45         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
47
48         switch (mode) {
49         case USB_TEST_J:
50         case USB_TEST_K:
51         case USB_TEST_SE0_NAK:
52         case USB_TEST_PACKET:
53         case USB_TEST_FORCE_ENABLE:
54                 reg |= mode << 1;
55                 break;
56         default:
57                 return -EINVAL;
58         }
59
60         dwc3_gadget_dctl_write_safe(dwc, reg);
61
62         return 0;
63 }
64
65 /**
66  * dwc3_gadget_get_link_state - gets current state of usb link
67  * @dwc: pointer to our context structure
68  *
69  * Caller should take care of locking. This function will
70  * return the link state on success (>= 0) or -ETIMEDOUT.
71  */
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
73 {
74         u32             reg;
75
76         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
77
78         return DWC3_DSTS_USBLNKST(reg);
79 }
80
81 /**
82  * dwc3_gadget_set_link_state - sets usb link to a particular state
83  * @dwc: pointer to our context structure
84  * @state: the state to put link into
85  *
86  * Caller should take care of locking. This function will
87  * return 0 on success or -ETIMEDOUT.
88  */
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
90 {
91         int             retries = 10000;
92         u32             reg;
93
94         /*
95          * Wait until device controller is ready. Only applies to 1.94a and
96          * later RTL.
97          */
98         if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) {
99                 while (--retries) {
100                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101                         if (reg & DWC3_DSTS_DCNRD)
102                                 udelay(5);
103                         else
104                                 break;
105                 }
106
107                 if (retries <= 0)
108                         return -ETIMEDOUT;
109         }
110
111         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
113
114         /* set no action before sending new link state change */
115         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
116
117         /* set requested state */
118         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
119         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
120
121         /*
122          * The following code is racy when called from dwc3_gadget_wakeup,
123          * and is not needed, at least on newer versions
124          */
125         if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
126                 return 0;
127
128         /* wait for a change in DSTS */
129         retries = 10000;
130         while (--retries) {
131                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
132
133                 if (DWC3_DSTS_USBLNKST(reg) == state)
134                         return 0;
135
136                 udelay(5);
137         }
138
139         return -ETIMEDOUT;
140 }
141
142 /**
143  * dwc3_ep_inc_trb - increment a trb index.
144  * @index: Pointer to the TRB index to increment.
145  *
146  * The index should never point to the link TRB. After incrementing,
147  * if it is point to the link TRB, wrap around to the beginning. The
148  * link TRB is always at the last TRB entry.
149  */
150 static void dwc3_ep_inc_trb(u8 *index)
151 {
152         (*index)++;
153         if (*index == (DWC3_TRB_NUM - 1))
154                 *index = 0;
155 }
156
157 /**
158  * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
159  * @dep: The endpoint whose enqueue pointer we're incrementing
160  */
161 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
162 {
163         dwc3_ep_inc_trb(&dep->trb_enqueue);
164 }
165
166 /**
167  * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
168  * @dep: The endpoint whose enqueue pointer we're incrementing
169  */
170 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
171 {
172         dwc3_ep_inc_trb(&dep->trb_dequeue);
173 }
174
175 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
176                 struct dwc3_request *req, int status)
177 {
178         struct dwc3                     *dwc = dep->dwc;
179
180         list_del(&req->list);
181         req->remaining = 0;
182         req->needs_extra_trb = false;
183
184         if (req->request.status == -EINPROGRESS)
185                 req->request.status = status;
186
187         if (req->trb)
188                 usb_gadget_unmap_request_by_dev(dwc->sysdev,
189                                 &req->request, req->direction);
190
191         req->trb = NULL;
192         trace_dwc3_gadget_giveback(req);
193
194         if (dep->number > 1)
195                 pm_runtime_put(dwc->dev);
196 }
197
198 /**
199  * dwc3_gadget_giveback - call struct usb_request's ->complete callback
200  * @dep: The endpoint to whom the request belongs to
201  * @req: The request we're giving back
202  * @status: completion code for the request
203  *
204  * Must be called with controller's lock held and interrupts disabled. This
205  * function will unmap @req and call its ->complete() callback to notify upper
206  * layers that it has completed.
207  */
208 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
209                 int status)
210 {
211         struct dwc3                     *dwc = dep->dwc;
212
213         dwc3_gadget_del_and_unmap_request(dep, req, status);
214         req->status = DWC3_REQUEST_STATUS_COMPLETED;
215
216         spin_unlock(&dwc->lock);
217         usb_gadget_giveback_request(&dep->endpoint, &req->request);
218         spin_lock(&dwc->lock);
219 }
220
221 /**
222  * dwc3_send_gadget_generic_command - issue a generic command for the controller
223  * @dwc: pointer to the controller context
224  * @cmd: the command to be issued
225  * @param: command parameter
226  *
227  * Caller should take care of locking. Issue @cmd with a given @param to @dwc
228  * and wait for its completion.
229  */
230 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
231                 u32 param)
232 {
233         u32             timeout = 500;
234         int             status = 0;
235         int             ret = 0;
236         u32             reg;
237
238         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
239         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
240
241         do {
242                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
243                 if (!(reg & DWC3_DGCMD_CMDACT)) {
244                         status = DWC3_DGCMD_STATUS(reg);
245                         if (status)
246                                 ret = -EINVAL;
247                         break;
248                 }
249         } while (--timeout);
250
251         if (!timeout) {
252                 ret = -ETIMEDOUT;
253                 status = -ETIMEDOUT;
254         }
255
256         trace_dwc3_gadget_generic_cmd(cmd, param, status);
257
258         return ret;
259 }
260
261 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
262
263 /**
264  * dwc3_send_gadget_ep_cmd - issue an endpoint command
265  * @dep: the endpoint to which the command is going to be issued
266  * @cmd: the command to be issued
267  * @params: parameters to the command
268  *
269  * Caller should handle locking. This function will issue @cmd with given
270  * @params to @dep and wait for its completion.
271  */
272 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
273                 struct dwc3_gadget_ep_cmd_params *params)
274 {
275         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
276         struct dwc3             *dwc = dep->dwc;
277         u32                     timeout = 5000;
278         u32                     saved_config = 0;
279         u32                     reg;
280
281         int                     cmd_status = 0;
282         int                     ret = -EINVAL;
283
284         /*
285          * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
286          * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
287          * endpoint command.
288          *
289          * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
290          * settings. Restore them after the command is completed.
291          *
292          * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
293          */
294         if (dwc->gadget->speed <= USB_SPEED_HIGH) {
295                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
296                 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
297                         saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
298                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
299                 }
300
301                 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
302                         saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
303                         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
304                 }
305
306                 if (saved_config)
307                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
308         }
309
310         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
311                 int link_state;
312
313                 link_state = dwc3_gadget_get_link_state(dwc);
314                 if (link_state == DWC3_LINK_STATE_U1 ||
315                     link_state == DWC3_LINK_STATE_U2 ||
316                     link_state == DWC3_LINK_STATE_U3) {
317                         ret = __dwc3_gadget_wakeup(dwc);
318                         dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
319                                         ret);
320                 }
321         }
322
323         dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
324         dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
325         dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
326
327         /*
328          * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
329          * not relying on XferNotReady, we can make use of a special "No
330          * Response Update Transfer" command where we should clear both CmdAct
331          * and CmdIOC bits.
332          *
333          * With this, we don't need to wait for command completion and can
334          * straight away issue further commands to the endpoint.
335          *
336          * NOTICE: We're making an assumption that control endpoints will never
337          * make use of Update Transfer command. This is a safe assumption
338          * because we can never have more than one request at a time with
339          * Control Endpoints. If anybody changes that assumption, this chunk
340          * needs to be updated accordingly.
341          */
342         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
343                         !usb_endpoint_xfer_isoc(desc))
344                 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
345         else
346                 cmd |= DWC3_DEPCMD_CMDACT;
347
348         dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
349         do {
350                 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
351                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
352                         cmd_status = DWC3_DEPCMD_STATUS(reg);
353
354                         switch (cmd_status) {
355                         case 0:
356                                 ret = 0;
357                                 break;
358                         case DEPEVT_TRANSFER_NO_RESOURCE:
359                                 dev_WARN(dwc->dev, "No resource for %s\n",
360                                          dep->name);
361                                 ret = -EINVAL;
362                                 break;
363                         case DEPEVT_TRANSFER_BUS_EXPIRY:
364                                 /*
365                                  * SW issues START TRANSFER command to
366                                  * isochronous ep with future frame interval. If
367                                  * future interval time has already passed when
368                                  * core receives the command, it will respond
369                                  * with an error status of 'Bus Expiry'.
370                                  *
371                                  * Instead of always returning -EINVAL, let's
372                                  * give a hint to the gadget driver that this is
373                                  * the case by returning -EAGAIN.
374                                  */
375                                 ret = -EAGAIN;
376                                 break;
377                         default:
378                                 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
379                         }
380
381                         break;
382                 }
383         } while (--timeout);
384
385         if (timeout == 0) {
386                 ret = -ETIMEDOUT;
387                 cmd_status = -ETIMEDOUT;
388         }
389
390         trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
391
392         if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
393                 if (ret == 0)
394                         dep->flags |= DWC3_EP_TRANSFER_STARTED;
395
396                 if (ret != -ETIMEDOUT)
397                         dwc3_gadget_ep_get_transfer_index(dep);
398         }
399
400         if (saved_config) {
401                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
402                 reg |= saved_config;
403                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
404         }
405
406         return ret;
407 }
408
409 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
410 {
411         struct dwc3 *dwc = dep->dwc;
412         struct dwc3_gadget_ep_cmd_params params;
413         u32 cmd = DWC3_DEPCMD_CLEARSTALL;
414
415         /*
416          * As of core revision 2.60a the recommended programming model
417          * is to set the ClearPendIN bit when issuing a Clear Stall EP
418          * command for IN endpoints. This is to prevent an issue where
419          * some (non-compliant) hosts may not send ACK TPs for pending
420          * IN transfers due to a mishandled error condition. Synopsys
421          * STAR 9000614252.
422          */
423         if (dep->direction &&
424             !DWC3_VER_IS_PRIOR(DWC3, 260A) &&
425             (dwc->gadget->speed >= USB_SPEED_SUPER))
426                 cmd |= DWC3_DEPCMD_CLEARPENDIN;
427
428         memset(&params, 0, sizeof(params));
429
430         return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
431 }
432
433 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
434                 struct dwc3_trb *trb)
435 {
436         u32             offset = (char *) trb - (char *) dep->trb_pool;
437
438         return dep->trb_pool_dma + offset;
439 }
440
441 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
442 {
443         struct dwc3             *dwc = dep->dwc;
444
445         if (dep->trb_pool)
446                 return 0;
447
448         dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
449                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
450                         &dep->trb_pool_dma, GFP_KERNEL);
451         if (!dep->trb_pool) {
452                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
453                                 dep->name);
454                 return -ENOMEM;
455         }
456
457         return 0;
458 }
459
460 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
461 {
462         struct dwc3             *dwc = dep->dwc;
463
464         dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
465                         dep->trb_pool, dep->trb_pool_dma);
466
467         dep->trb_pool = NULL;
468         dep->trb_pool_dma = 0;
469 }
470
471 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
472 {
473         struct dwc3_gadget_ep_cmd_params params;
474
475         memset(&params, 0x00, sizeof(params));
476
477         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
478
479         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
480                         &params);
481 }
482
483 /**
484  * dwc3_gadget_start_config - configure ep resources
485  * @dep: endpoint that is being enabled
486  *
487  * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
488  * completion, it will set Transfer Resource for all available endpoints.
489  *
490  * The assignment of transfer resources cannot perfectly follow the data book
491  * due to the fact that the controller driver does not have all knowledge of the
492  * configuration in advance. It is given this information piecemeal by the
493  * composite gadget framework after every SET_CONFIGURATION and
494  * SET_INTERFACE. Trying to follow the databook programming model in this
495  * scenario can cause errors. For two reasons:
496  *
497  * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
498  * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
499  * incorrect in the scenario of multiple interfaces.
500  *
501  * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
502  * endpoint on alt setting (8.1.6).
503  *
504  * The following simplified method is used instead:
505  *
506  * All hardware endpoints can be assigned a transfer resource and this setting
507  * will stay persistent until either a core reset or hibernation. So whenever we
508  * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
509  * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
510  * guaranteed that there are as many transfer resources as endpoints.
511  *
512  * This function is called for each endpoint when it is being enabled but is
513  * triggered only when called for EP0-out, which always happens first, and which
514  * should only happen in one of the above conditions.
515  */
516 static int dwc3_gadget_start_config(struct dwc3_ep *dep)
517 {
518         struct dwc3_gadget_ep_cmd_params params;
519         struct dwc3             *dwc;
520         u32                     cmd;
521         int                     i;
522         int                     ret;
523
524         if (dep->number)
525                 return 0;
526
527         memset(&params, 0x00, sizeof(params));
528         cmd = DWC3_DEPCMD_DEPSTARTCFG;
529         dwc = dep->dwc;
530
531         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
532         if (ret)
533                 return ret;
534
535         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
536                 struct dwc3_ep *dep = dwc->eps[i];
537
538                 if (!dep)
539                         continue;
540
541                 ret = dwc3_gadget_set_xfer_resource(dep);
542                 if (ret)
543                         return ret;
544         }
545
546         return 0;
547 }
548
549 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
550 {
551         const struct usb_ss_ep_comp_descriptor *comp_desc;
552         const struct usb_endpoint_descriptor *desc;
553         struct dwc3_gadget_ep_cmd_params params;
554         struct dwc3 *dwc = dep->dwc;
555
556         comp_desc = dep->endpoint.comp_desc;
557         desc = dep->endpoint.desc;
558
559         memset(&params, 0x00, sizeof(params));
560
561         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
562                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
563
564         /* Burst size is only needed in SuperSpeed mode */
565         if (dwc->gadget->speed >= USB_SPEED_SUPER) {
566                 u32 burst = dep->endpoint.maxburst;
567
568                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
569         }
570
571         params.param0 |= action;
572         if (action == DWC3_DEPCFG_ACTION_RESTORE)
573                 params.param2 |= dep->saved_state;
574
575         if (usb_endpoint_xfer_control(desc))
576                 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
577
578         if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
579                 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
580
581         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
582                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
583                         | DWC3_DEPCFG_XFER_COMPLETE_EN
584                         | DWC3_DEPCFG_STREAM_EVENT_EN;
585                 dep->stream_capable = true;
586         }
587
588         if (!usb_endpoint_xfer_control(desc))
589                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
590
591         /*
592          * We are doing 1:1 mapping for endpoints, meaning
593          * Physical Endpoints 2 maps to Logical Endpoint 2 and
594          * so on. We consider the direction bit as part of the physical
595          * endpoint number. So USB endpoint 0x81 is 0x03.
596          */
597         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
598
599         /*
600          * We must use the lower 16 TX FIFOs even though
601          * HW might have more
602          */
603         if (dep->direction)
604                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
605
606         if (desc->bInterval) {
607                 u8 bInterval_m1;
608
609                 /*
610                  * Valid range for DEPCFG.bInterval_m1 is from 0 to 13.
611                  *
612                  * NOTE: The programming guide incorrectly stated bInterval_m1
613                  * must be set to 0 when operating in fullspeed. Internally the
614                  * controller does not have this limitation. See DWC_usb3x
615                  * programming guide section 3.2.2.1.
616                  */
617                 bInterval_m1 = min_t(u8, desc->bInterval - 1, 13);
618
619                 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
620                     dwc->gadget->speed == USB_SPEED_FULL)
621                         dep->interval = desc->bInterval;
622                 else
623                         dep->interval = 1 << (desc->bInterval - 1);
624
625                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1);
626         }
627
628         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
629 }
630
631 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
632                 bool interrupt);
633
634 /**
635  * dwc3_gadget_calc_tx_fifo_size - calculates the txfifo size value
636  * @dwc: pointer to the DWC3 context
637  * @nfifos: number of fifos to calculate for
638  *
639  * Calculates the size value based on the equation below:
640  *
641  * DWC3 revision 280A and prior:
642  * fifo_size = mult * (max_packet / mdwidth) + 1;
643  *
644  * DWC3 revision 290A and onwards:
645  * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
646  *
647  * The max packet size is set to 1024, as the txfifo requirements mainly apply
648  * to super speed USB use cases.  However, it is safe to overestimate the fifo
649  * allocations for other scenarios, i.e. high speed USB.
650  */
651 static int dwc3_gadget_calc_tx_fifo_size(struct dwc3 *dwc, int mult)
652 {
653         int max_packet = 1024;
654         int fifo_size;
655         int mdwidth;
656
657         mdwidth = dwc3_mdwidth(dwc);
658
659         /* MDWIDTH is represented in bits, we need it in bytes */
660         mdwidth >>= 3;
661
662         if (DWC3_VER_IS_PRIOR(DWC3, 290A))
663                 fifo_size = mult * (max_packet / mdwidth) + 1;
664         else
665                 fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1;
666         return fifo_size;
667 }
668
669 /**
670  * dwc3_gadget_clear_tx_fifo_size - Clears txfifo allocation
671  * @dwc: pointer to the DWC3 context
672  *
673  * Iterates through all the endpoint registers and clears the previous txfifo
674  * allocations.
675  */
676 void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
677 {
678         struct dwc3_ep *dep;
679         int fifo_depth;
680         int size;
681         int num;
682
683         if (!dwc->do_fifo_resize)
684                 return;
685
686         /* Read ep0IN related TXFIFO size */
687         dep = dwc->eps[1];
688         size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
689         if (DWC3_IP_IS(DWC3))
690                 fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
691         else
692                 fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
693
694         dwc->last_fifo_depth = fifo_depth;
695         /* Clear existing TXFIFO for all IN eps except ep0 */
696         for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM);
697              num += 2) {
698                 dep = dwc->eps[num];
699                 /* Don't change TXFRAMNUM on usb31 version */
700                 size = DWC3_IP_IS(DWC3) ? 0 :
701                         dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) &
702                                    DWC31_GTXFIFOSIZ_TXFRAMNUM;
703
704                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size);
705         }
706         dwc->num_ep_resized = 0;
707 }
708
709 /*
710  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
711  * @dwc: pointer to our context structure
712  *
713  * This function will a best effort FIFO allocation in order
714  * to improve FIFO usage and throughput, while still allowing
715  * us to enable as many endpoints as possible.
716  *
717  * Keep in mind that this operation will be highly dependent
718  * on the configured size for RAM1 - which contains TxFifo -,
719  * the amount of endpoints enabled on coreConsultant tool, and
720  * the width of the Master Bus.
721  *
722  * In general, FIFO depths are represented with the following equation:
723  *
724  * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
725  *
726  * In conjunction with dwc3_gadget_check_config(), this resizing logic will
727  * ensure that all endpoints will have enough internal memory for one max
728  * packet per endpoint.
729  */
730 static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
731 {
732         struct dwc3 *dwc = dep->dwc;
733         int fifo_0_start;
734         int ram1_depth;
735         int fifo_size;
736         int min_depth;
737         int num_in_ep;
738         int remaining;
739         int num_fifos = 1;
740         int fifo;
741         int tmp;
742
743         if (!dwc->do_fifo_resize)
744                 return 0;
745
746         /* resize IN endpoints except ep0 */
747         if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
748                 return 0;
749
750         ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
751
752         if ((dep->endpoint.maxburst > 1 &&
753              usb_endpoint_xfer_bulk(dep->endpoint.desc)) ||
754             usb_endpoint_xfer_isoc(dep->endpoint.desc))
755                 num_fifos = 3;
756
757         if (dep->endpoint.maxburst > 6 &&
758             usb_endpoint_xfer_bulk(dep->endpoint.desc) && DWC3_IP_IS(DWC31))
759                 num_fifos = dwc->tx_fifo_resize_max_num;
760
761         /* FIFO size for a single buffer */
762         fifo = dwc3_gadget_calc_tx_fifo_size(dwc, 1);
763
764         /* Calculate the number of remaining EPs w/o any FIFO */
765         num_in_ep = dwc->max_cfg_eps;
766         num_in_ep -= dwc->num_ep_resized;
767
768         /* Reserve at least one FIFO for the number of IN EPs */
769         min_depth = num_in_ep * (fifo + 1);
770         remaining = ram1_depth - min_depth - dwc->last_fifo_depth;
771         remaining = max_t(int, 0, remaining);
772         /*
773          * We've already reserved 1 FIFO per EP, so check what we can fit in
774          * addition to it.  If there is not enough remaining space, allocate
775          * all the remaining space to the EP.
776          */
777         fifo_size = (num_fifos - 1) * fifo;
778         if (remaining < fifo_size)
779                 fifo_size = remaining;
780
781         fifo_size += fifo;
782         /* Last increment according to the TX FIFO size equation */
783         fifo_size++;
784
785         /* Check if TXFIFOs start at non-zero addr */
786         tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
787         fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
788
789         fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
790         if (DWC3_IP_IS(DWC3))
791                 dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
792         else
793                 dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
794
795         /* Check fifo size allocation doesn't exceed available RAM size. */
796         if (dwc->last_fifo_depth >= ram1_depth) {
797                 dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n",
798                         dwc->last_fifo_depth, ram1_depth,
799                         dep->endpoint.name, fifo_size);
800                 if (DWC3_IP_IS(DWC3))
801                         fifo_size = DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
802                 else
803                         fifo_size = DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
804
805                 dwc->last_fifo_depth -= fifo_size;
806                 return -ENOMEM;
807         }
808
809         dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size);
810         dwc->num_ep_resized++;
811
812         return 0;
813 }
814
815 /**
816  * __dwc3_gadget_ep_enable - initializes a hw endpoint
817  * @dep: endpoint to be initialized
818  * @action: one of INIT, MODIFY or RESTORE
819  *
820  * Caller should take care of locking. Execute all necessary commands to
821  * initialize a HW endpoint so it can be used by a gadget driver.
822  */
823 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
824 {
825         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
826         struct dwc3             *dwc = dep->dwc;
827
828         u32                     reg;
829         int                     ret;
830
831         if (!(dep->flags & DWC3_EP_ENABLED)) {
832                 ret = dwc3_gadget_resize_tx_fifos(dep);
833                 if (ret)
834                         return ret;
835
836                 ret = dwc3_gadget_start_config(dep);
837                 if (ret)
838                         return ret;
839         }
840
841         ret = dwc3_gadget_set_ep_config(dep, action);
842         if (ret)
843                 return ret;
844
845         if (!(dep->flags & DWC3_EP_ENABLED)) {
846                 struct dwc3_trb *trb_st_hw;
847                 struct dwc3_trb *trb_link;
848
849                 dep->type = usb_endpoint_type(desc);
850                 dep->flags |= DWC3_EP_ENABLED;
851
852                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
853                 reg |= DWC3_DALEPENA_EP(dep->number);
854                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
855
856                 if (usb_endpoint_xfer_control(desc))
857                         goto out;
858
859                 /* Initialize the TRB ring */
860                 dep->trb_dequeue = 0;
861                 dep->trb_enqueue = 0;
862                 memset(dep->trb_pool, 0,
863                        sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
864
865                 /* Link TRB. The HWO bit is never reset */
866                 trb_st_hw = &dep->trb_pool[0];
867
868                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
869                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
870                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
871                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
872                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
873         }
874
875         /*
876          * Issue StartTransfer here with no-op TRB so we can always rely on No
877          * Response Update Transfer command.
878          */
879         if (usb_endpoint_xfer_bulk(desc) ||
880                         usb_endpoint_xfer_int(desc)) {
881                 struct dwc3_gadget_ep_cmd_params params;
882                 struct dwc3_trb *trb;
883                 dma_addr_t trb_dma;
884                 u32 cmd;
885
886                 memset(&params, 0, sizeof(params));
887                 trb = &dep->trb_pool[0];
888                 trb_dma = dwc3_trb_dma_offset(dep, trb);
889
890                 params.param0 = upper_32_bits(trb_dma);
891                 params.param1 = lower_32_bits(trb_dma);
892
893                 cmd = DWC3_DEPCMD_STARTTRANSFER;
894
895                 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
896                 if (ret < 0)
897                         return ret;
898
899                 if (dep->stream_capable) {
900                         /*
901                          * For streams, at start, there maybe a race where the
902                          * host primes the endpoint before the function driver
903                          * queues a request to initiate a stream. In that case,
904                          * the controller will not see the prime to generate the
905                          * ERDY and start stream. To workaround this, issue a
906                          * no-op TRB as normal, but end it immediately. As a
907                          * result, when the function driver queues the request,
908                          * the next START_TRANSFER command will cause the
909                          * controller to generate an ERDY to initiate the
910                          * stream.
911                          */
912                         dwc3_stop_active_transfer(dep, true, true);
913
914                         /*
915                          * All stream eps will reinitiate stream on NoStream
916                          * rejection until we can determine that the host can
917                          * prime after the first transfer.
918                          *
919                          * However, if the controller is capable of
920                          * TXF_FLUSH_BYPASS, then IN direction endpoints will
921                          * automatically restart the stream without the driver
922                          * initiation.
923                          */
924                         if (!dep->direction ||
925                             !(dwc->hwparams.hwparams9 &
926                               DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS))
927                                 dep->flags |= DWC3_EP_FORCE_RESTART_STREAM;
928                 }
929         }
930
931 out:
932         trace_dwc3_gadget_ep_enable(dep);
933
934         return 0;
935 }
936
937 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
938 {
939         struct dwc3_request             *req;
940
941         dwc3_stop_active_transfer(dep, true, false);
942
943         /* - giveback all requests to gadget driver */
944         while (!list_empty(&dep->started_list)) {
945                 req = next_request(&dep->started_list);
946
947                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
948         }
949
950         while (!list_empty(&dep->pending_list)) {
951                 req = next_request(&dep->pending_list);
952
953                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
954         }
955
956         while (!list_empty(&dep->cancelled_list)) {
957                 req = next_request(&dep->cancelled_list);
958
959                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
960         }
961 }
962
963 /**
964  * __dwc3_gadget_ep_disable - disables a hw endpoint
965  * @dep: the endpoint to disable
966  *
967  * This function undoes what __dwc3_gadget_ep_enable did and also removes
968  * requests which are currently being processed by the hardware and those which
969  * are not yet scheduled.
970  *
971  * Caller should take care of locking.
972  */
973 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
974 {
975         struct dwc3             *dwc = dep->dwc;
976         u32                     reg;
977
978         trace_dwc3_gadget_ep_disable(dep);
979
980         /* make sure HW endpoint isn't stalled */
981         if (dep->flags & DWC3_EP_STALL)
982                 __dwc3_gadget_ep_set_halt(dep, 0, false);
983
984         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
985         reg &= ~DWC3_DALEPENA_EP(dep->number);
986         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
987
988         /* Clear out the ep descriptors for non-ep0 */
989         if (dep->number > 1) {
990                 dep->endpoint.comp_desc = NULL;
991                 dep->endpoint.desc = NULL;
992         }
993
994         dwc3_remove_requests(dwc, dep);
995
996         dep->stream_capable = false;
997         dep->type = 0;
998         dep->flags = 0;
999
1000         return 0;
1001 }
1002
1003 /* -------------------------------------------------------------------------- */
1004
1005 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
1006                 const struct usb_endpoint_descriptor *desc)
1007 {
1008         return -EINVAL;
1009 }
1010
1011 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
1012 {
1013         return -EINVAL;
1014 }
1015
1016 /* -------------------------------------------------------------------------- */
1017
1018 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
1019                 const struct usb_endpoint_descriptor *desc)
1020 {
1021         struct dwc3_ep                  *dep;
1022         struct dwc3                     *dwc;
1023         unsigned long                   flags;
1024         int                             ret;
1025
1026         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
1027                 pr_debug("dwc3: invalid parameters\n");
1028                 return -EINVAL;
1029         }
1030
1031         if (!desc->wMaxPacketSize) {
1032                 pr_debug("dwc3: missing wMaxPacketSize\n");
1033                 return -EINVAL;
1034         }
1035
1036         dep = to_dwc3_ep(ep);
1037         dwc = dep->dwc;
1038
1039         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
1040                                         "%s is already enabled\n",
1041                                         dep->name))
1042                 return 0;
1043
1044         spin_lock_irqsave(&dwc->lock, flags);
1045         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1046         spin_unlock_irqrestore(&dwc->lock, flags);
1047
1048         return ret;
1049 }
1050
1051 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
1052 {
1053         struct dwc3_ep                  *dep;
1054         struct dwc3                     *dwc;
1055         unsigned long                   flags;
1056         int                             ret;
1057
1058         if (!ep) {
1059                 pr_debug("dwc3: invalid parameters\n");
1060                 return -EINVAL;
1061         }
1062
1063         dep = to_dwc3_ep(ep);
1064         dwc = dep->dwc;
1065
1066         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
1067                                         "%s is already disabled\n",
1068                                         dep->name))
1069                 return 0;
1070
1071         spin_lock_irqsave(&dwc->lock, flags);
1072         ret = __dwc3_gadget_ep_disable(dep);
1073         spin_unlock_irqrestore(&dwc->lock, flags);
1074
1075         return ret;
1076 }
1077
1078 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
1079                 gfp_t gfp_flags)
1080 {
1081         struct dwc3_request             *req;
1082         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1083
1084         req = kzalloc(sizeof(*req), gfp_flags);
1085         if (!req)
1086                 return NULL;
1087
1088         req->direction  = dep->direction;
1089         req->epnum      = dep->number;
1090         req->dep        = dep;
1091         req->status     = DWC3_REQUEST_STATUS_UNKNOWN;
1092
1093         trace_dwc3_alloc_request(req);
1094
1095         return &req->request;
1096 }
1097
1098 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
1099                 struct usb_request *request)
1100 {
1101         struct dwc3_request             *req = to_dwc3_request(request);
1102
1103         trace_dwc3_free_request(req);
1104         kfree(req);
1105 }
1106
1107 /**
1108  * dwc3_ep_prev_trb - returns the previous TRB in the ring
1109  * @dep: The endpoint with the TRB ring
1110  * @index: The index of the current TRB in the ring
1111  *
1112  * Returns the TRB prior to the one pointed to by the index. If the
1113  * index is 0, we will wrap backwards, skip the link TRB, and return
1114  * the one just before that.
1115  */
1116 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
1117 {
1118         u8 tmp = index;
1119
1120         if (!tmp)
1121                 tmp = DWC3_TRB_NUM - 1;
1122
1123         return &dep->trb_pool[tmp - 1];
1124 }
1125
1126 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
1127 {
1128         struct dwc3_trb         *tmp;
1129         u8                      trbs_left;
1130
1131         /*
1132          * If enqueue & dequeue are equal than it is either full or empty.
1133          *
1134          * One way to know for sure is if the TRB right before us has HWO bit
1135          * set or not. If it has, then we're definitely full and can't fit any
1136          * more transfers in our ring.
1137          */
1138         if (dep->trb_enqueue == dep->trb_dequeue) {
1139                 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1140                 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
1141                         return 0;
1142
1143                 return DWC3_TRB_NUM - 1;
1144         }
1145
1146         trbs_left = dep->trb_dequeue - dep->trb_enqueue;
1147         trbs_left &= (DWC3_TRB_NUM - 1);
1148
1149         if (dep->trb_dequeue < dep->trb_enqueue)
1150                 trbs_left--;
1151
1152         return trbs_left;
1153 }
1154
1155 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
1156                 dma_addr_t dma, unsigned int length, unsigned int chain,
1157                 unsigned int node, unsigned int stream_id,
1158                 unsigned int short_not_ok, unsigned int no_interrupt,
1159                 unsigned int is_last, bool must_interrupt)
1160 {
1161         struct dwc3             *dwc = dep->dwc;
1162         struct usb_gadget       *gadget = dwc->gadget;
1163         enum usb_device_speed   speed = gadget->speed;
1164
1165         trb->size = DWC3_TRB_SIZE_LENGTH(length);
1166         trb->bpl = lower_32_bits(dma);
1167         trb->bph = upper_32_bits(dma);
1168
1169         switch (usb_endpoint_type(dep->endpoint.desc)) {
1170         case USB_ENDPOINT_XFER_CONTROL:
1171                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
1172                 break;
1173
1174         case USB_ENDPOINT_XFER_ISOC:
1175                 if (!node) {
1176                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
1177
1178                         /*
1179                          * USB Specification 2.0 Section 5.9.2 states that: "If
1180                          * there is only a single transaction in the microframe,
1181                          * only a DATA0 data packet PID is used.  If there are
1182                          * two transactions per microframe, DATA1 is used for
1183                          * the first transaction data packet and DATA0 is used
1184                          * for the second transaction data packet.  If there are
1185                          * three transactions per microframe, DATA2 is used for
1186                          * the first transaction data packet, DATA1 is used for
1187                          * the second, and DATA0 is used for the third."
1188                          *
1189                          * IOW, we should satisfy the following cases:
1190                          *
1191                          * 1) length <= maxpacket
1192                          *      - DATA0
1193                          *
1194                          * 2) maxpacket < length <= (2 * maxpacket)
1195                          *      - DATA1, DATA0
1196                          *
1197                          * 3) (2 * maxpacket) < length <= (3 * maxpacket)
1198                          *      - DATA2, DATA1, DATA0
1199                          */
1200                         if (speed == USB_SPEED_HIGH) {
1201                                 struct usb_ep *ep = &dep->endpoint;
1202                                 unsigned int mult = 2;
1203                                 unsigned int maxp = usb_endpoint_maxp(ep->desc);
1204
1205                                 if (length <= (2 * maxp))
1206                                         mult--;
1207
1208                                 if (length <= maxp)
1209                                         mult--;
1210
1211                                 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
1212                         }
1213                 } else {
1214                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
1215                 }
1216
1217                 /* always enable Interrupt on Missed ISOC */
1218                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1219                 break;
1220
1221         case USB_ENDPOINT_XFER_BULK:
1222         case USB_ENDPOINT_XFER_INT:
1223                 trb->ctrl = DWC3_TRBCTL_NORMAL;
1224                 break;
1225         default:
1226                 /*
1227                  * This is only possible with faulty memory because we
1228                  * checked it already :)
1229                  */
1230                 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
1231                                 usb_endpoint_type(dep->endpoint.desc));
1232         }
1233
1234         /*
1235          * Enable Continue on Short Packet
1236          * when endpoint is not a stream capable
1237          */
1238         if (usb_endpoint_dir_out(dep->endpoint.desc)) {
1239                 if (!dep->stream_capable)
1240                         trb->ctrl |= DWC3_TRB_CTRL_CSP;
1241
1242                 if (short_not_ok)
1243                         trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1244         }
1245
1246         if ((!no_interrupt && !chain) || must_interrupt)
1247                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1248
1249         if (chain)
1250                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1251         else if (dep->stream_capable && is_last)
1252                 trb->ctrl |= DWC3_TRB_CTRL_LST;
1253
1254         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1255                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1256
1257         trb->ctrl |= DWC3_TRB_CTRL_HWO;
1258
1259         dwc3_ep_inc_enq(dep);
1260
1261         trace_dwc3_prepare_trb(dep, trb);
1262 }
1263
1264 /**
1265  * dwc3_prepare_one_trb - setup one TRB from one request
1266  * @dep: endpoint for which this request is prepared
1267  * @req: dwc3_request pointer
1268  * @trb_length: buffer size of the TRB
1269  * @chain: should this TRB be chained to the next?
1270  * @node: only for isochronous endpoints. First TRB needs different type.
1271  * @use_bounce_buffer: set to use bounce buffer
1272  * @must_interrupt: set to interrupt on TRB completion
1273  */
1274 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1275                 struct dwc3_request *req, unsigned int trb_length,
1276                 unsigned int chain, unsigned int node, bool use_bounce_buffer,
1277                 bool must_interrupt)
1278 {
1279         struct dwc3_trb         *trb;
1280         dma_addr_t              dma;
1281         unsigned int            stream_id = req->request.stream_id;
1282         unsigned int            short_not_ok = req->request.short_not_ok;
1283         unsigned int            no_interrupt = req->request.no_interrupt;
1284         unsigned int            is_last = req->request.is_last;
1285
1286         if (use_bounce_buffer)
1287                 dma = dep->dwc->bounce_addr;
1288         else if (req->request.num_sgs > 0)
1289                 dma = sg_dma_address(req->start_sg);
1290         else
1291                 dma = req->request.dma;
1292
1293         trb = &dep->trb_pool[dep->trb_enqueue];
1294
1295         if (!req->trb) {
1296                 dwc3_gadget_move_started_request(req);
1297                 req->trb = trb;
1298                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1299         }
1300
1301         req->num_trbs++;
1302
1303         __dwc3_prepare_one_trb(dep, trb, dma, trb_length, chain, node,
1304                         stream_id, short_not_ok, no_interrupt, is_last,
1305                         must_interrupt);
1306 }
1307
1308 static bool dwc3_needs_extra_trb(struct dwc3_ep *dep, struct dwc3_request *req)
1309 {
1310         unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1311         unsigned int rem = req->request.length % maxp;
1312
1313         if ((req->request.length && req->request.zero && !rem &&
1314                         !usb_endpoint_xfer_isoc(dep->endpoint.desc)) ||
1315                         (!req->direction && rem))
1316                 return true;
1317
1318         return false;
1319 }
1320
1321 /**
1322  * dwc3_prepare_last_sg - prepare TRBs for the last SG entry
1323  * @dep: The endpoint that the request belongs to
1324  * @req: The request to prepare
1325  * @entry_length: The last SG entry size
1326  * @node: Indicates whether this is not the first entry (for isoc only)
1327  *
1328  * Return the number of TRBs prepared.
1329  */
1330 static int dwc3_prepare_last_sg(struct dwc3_ep *dep,
1331                 struct dwc3_request *req, unsigned int entry_length,
1332                 unsigned int node)
1333 {
1334         unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1335         unsigned int rem = req->request.length % maxp;
1336         unsigned int num_trbs = 1;
1337
1338         if (dwc3_needs_extra_trb(dep, req))
1339                 num_trbs++;
1340
1341         if (dwc3_calc_trbs_left(dep) < num_trbs)
1342                 return 0;
1343
1344         req->needs_extra_trb = num_trbs > 1;
1345
1346         /* Prepare a normal TRB */
1347         if (req->direction || req->request.length)
1348                 dwc3_prepare_one_trb(dep, req, entry_length,
1349                                 req->needs_extra_trb, node, false, false);
1350
1351         /* Prepare extra TRBs for ZLP and MPS OUT transfer alignment */
1352         if ((!req->direction && !req->request.length) || req->needs_extra_trb)
1353                 dwc3_prepare_one_trb(dep, req,
1354                                 req->direction ? 0 : maxp - rem,
1355                                 false, 1, true, false);
1356
1357         return num_trbs;
1358 }
1359
1360 static int dwc3_prepare_trbs_sg(struct dwc3_ep *dep,
1361                 struct dwc3_request *req)
1362 {
1363         struct scatterlist *sg = req->start_sg;
1364         struct scatterlist *s;
1365         int             i;
1366         unsigned int length = req->request.length;
1367         unsigned int remaining = req->request.num_mapped_sgs
1368                 - req->num_queued_sgs;
1369         unsigned int num_trbs = req->num_trbs;
1370         bool needs_extra_trb = dwc3_needs_extra_trb(dep, req);
1371
1372         /*
1373          * If we resume preparing the request, then get the remaining length of
1374          * the request and resume where we left off.
1375          */
1376         for_each_sg(req->request.sg, s, req->num_queued_sgs, i)
1377                 length -= sg_dma_len(s);
1378
1379         for_each_sg(sg, s, remaining, i) {
1380                 unsigned int num_trbs_left = dwc3_calc_trbs_left(dep);
1381                 unsigned int trb_length;
1382                 bool must_interrupt = false;
1383                 bool last_sg = false;
1384
1385                 trb_length = min_t(unsigned int, length, sg_dma_len(s));
1386
1387                 length -= trb_length;
1388
1389                 /*
1390                  * IOMMU driver is coalescing the list of sgs which shares a
1391                  * page boundary into one and giving it to USB driver. With
1392                  * this the number of sgs mapped is not equal to the number of
1393                  * sgs passed. So mark the chain bit to false if it isthe last
1394                  * mapped sg.
1395                  */
1396                 if ((i == remaining - 1) || !length)
1397                         last_sg = true;
1398
1399                 if (!num_trbs_left)
1400                         break;
1401
1402                 if (last_sg) {
1403                         if (!dwc3_prepare_last_sg(dep, req, trb_length, i))
1404                                 break;
1405                 } else {
1406                         /*
1407                          * Look ahead to check if we have enough TRBs for the
1408                          * next SG entry. If not, set interrupt on this TRB to
1409                          * resume preparing the next SG entry when more TRBs are
1410                          * free.
1411                          */
1412                         if (num_trbs_left == 1 || (needs_extra_trb &&
1413                                         num_trbs_left <= 2 &&
1414                                         sg_dma_len(sg_next(s)) >= length))
1415                                 must_interrupt = true;
1416
1417                         dwc3_prepare_one_trb(dep, req, trb_length, 1, i, false,
1418                                         must_interrupt);
1419                 }
1420
1421                 /*
1422                  * There can be a situation where all sgs in sglist are not
1423                  * queued because of insufficient trb number. To handle this
1424                  * case, update start_sg to next sg to be queued, so that
1425                  * we have free trbs we can continue queuing from where we
1426                  * previously stopped
1427                  */
1428                 if (!last_sg)
1429                         req->start_sg = sg_next(s);
1430
1431                 req->num_queued_sgs++;
1432                 req->num_pending_sgs--;
1433
1434                 /*
1435                  * The number of pending SG entries may not correspond to the
1436                  * number of mapped SG entries. If all the data are queued, then
1437                  * don't include unused SG entries.
1438                  */
1439                 if (length == 0) {
1440                         req->num_pending_sgs = 0;
1441                         break;
1442                 }
1443
1444                 if (must_interrupt)
1445                         break;
1446         }
1447
1448         return req->num_trbs - num_trbs;
1449 }
1450
1451 static int dwc3_prepare_trbs_linear(struct dwc3_ep *dep,
1452                 struct dwc3_request *req)
1453 {
1454         return dwc3_prepare_last_sg(dep, req, req->request.length, 0);
1455 }
1456
1457 /*
1458  * dwc3_prepare_trbs - setup TRBs from requests
1459  * @dep: endpoint for which requests are being prepared
1460  *
1461  * The function goes through the requests list and sets up TRBs for the
1462  * transfers. The function returns once there are no more TRBs available or
1463  * it runs out of requests.
1464  *
1465  * Returns the number of TRBs prepared or negative errno.
1466  */
1467 static int dwc3_prepare_trbs(struct dwc3_ep *dep)
1468 {
1469         struct dwc3_request     *req, *n;
1470         int                     ret = 0;
1471
1472         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1473
1474         /*
1475          * We can get in a situation where there's a request in the started list
1476          * but there weren't enough TRBs to fully kick it in the first time
1477          * around, so it has been waiting for more TRBs to be freed up.
1478          *
1479          * In that case, we should check if we have a request with pending_sgs
1480          * in the started list and prepare TRBs for that request first,
1481          * otherwise we will prepare TRBs completely out of order and that will
1482          * break things.
1483          */
1484         list_for_each_entry(req, &dep->started_list, list) {
1485                 if (req->num_pending_sgs > 0) {
1486                         ret = dwc3_prepare_trbs_sg(dep, req);
1487                         if (!ret || req->num_pending_sgs)
1488                                 return ret;
1489                 }
1490
1491                 if (!dwc3_calc_trbs_left(dep))
1492                         return ret;
1493
1494                 /*
1495                  * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1496                  * burst capability may try to read and use TRBs beyond the
1497                  * active transfer instead of stopping.
1498                  */
1499                 if (dep->stream_capable && req->request.is_last)
1500                         return ret;
1501         }
1502
1503         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1504                 struct dwc3     *dwc = dep->dwc;
1505
1506                 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1507                                                     dep->direction);
1508                 if (ret)
1509                         return ret;
1510
1511                 req->sg                 = req->request.sg;
1512                 req->start_sg           = req->sg;
1513                 req->num_queued_sgs     = 0;
1514                 req->num_pending_sgs    = req->request.num_mapped_sgs;
1515
1516                 if (req->num_pending_sgs > 0) {
1517                         ret = dwc3_prepare_trbs_sg(dep, req);
1518                         if (req->num_pending_sgs)
1519                                 return ret;
1520                 } else {
1521                         ret = dwc3_prepare_trbs_linear(dep, req);
1522                 }
1523
1524                 if (!ret || !dwc3_calc_trbs_left(dep))
1525                         return ret;
1526
1527                 /*
1528                  * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1529                  * burst capability may try to read and use TRBs beyond the
1530                  * active transfer instead of stopping.
1531                  */
1532                 if (dep->stream_capable && req->request.is_last)
1533                         return ret;
1534         }
1535
1536         return ret;
1537 }
1538
1539 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep);
1540
1541 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1542 {
1543         struct dwc3_gadget_ep_cmd_params params;
1544         struct dwc3_request             *req;
1545         int                             starting;
1546         int                             ret;
1547         u32                             cmd;
1548
1549         /*
1550          * Note that it's normal to have no new TRBs prepared (i.e. ret == 0).
1551          * This happens when we need to stop and restart a transfer such as in
1552          * the case of reinitiating a stream or retrying an isoc transfer.
1553          */
1554         ret = dwc3_prepare_trbs(dep);
1555         if (ret < 0)
1556                 return ret;
1557
1558         starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1559
1560         /*
1561          * If there's no new TRB prepared and we don't need to restart a
1562          * transfer, there's no need to update the transfer.
1563          */
1564         if (!ret && !starting)
1565                 return ret;
1566
1567         req = next_request(&dep->started_list);
1568         if (!req) {
1569                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1570                 return 0;
1571         }
1572
1573         memset(&params, 0, sizeof(params));
1574
1575         if (starting) {
1576                 params.param0 = upper_32_bits(req->trb_dma);
1577                 params.param1 = lower_32_bits(req->trb_dma);
1578                 cmd = DWC3_DEPCMD_STARTTRANSFER;
1579
1580                 if (dep->stream_capable)
1581                         cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1582
1583                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1584                         cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1585         } else {
1586                 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1587                         DWC3_DEPCMD_PARAM(dep->resource_index);
1588         }
1589
1590         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1591         if (ret < 0) {
1592                 struct dwc3_request *tmp;
1593
1594                 if (ret == -EAGAIN)
1595                         return ret;
1596
1597                 dwc3_stop_active_transfer(dep, true, true);
1598
1599                 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1600                         dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_DEQUEUED);
1601
1602                 /* If ep isn't started, then there's no end transfer pending */
1603                 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1604                         dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1605
1606                 return ret;
1607         }
1608
1609         if (dep->stream_capable && req->request.is_last)
1610                 dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE;
1611
1612         return 0;
1613 }
1614
1615 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1616 {
1617         u32                     reg;
1618
1619         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1620         return DWC3_DSTS_SOFFN(reg);
1621 }
1622
1623 /**
1624  * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1625  * @dep: isoc endpoint
1626  *
1627  * This function tests for the correct combination of BIT[15:14] from the 16-bit
1628  * microframe number reported by the XferNotReady event for the future frame
1629  * number to start the isoc transfer.
1630  *
1631  * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1632  * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1633  * XferNotReady event are invalid. The driver uses this number to schedule the
1634  * isochronous transfer and passes it to the START TRANSFER command. Because
1635  * this number is invalid, the command may fail. If BIT[15:14] matches the
1636  * internal 16-bit microframe, the START TRANSFER command will pass and the
1637  * transfer will start at the scheduled time, if it is off by 1, the command
1638  * will still pass, but the transfer will start 2 seconds in the future. For all
1639  * other conditions, the START TRANSFER command will fail with bus-expiry.
1640  *
1641  * In order to workaround this issue, we can test for the correct combination of
1642  * BIT[15:14] by sending START TRANSFER commands with different values of
1643  * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1644  * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1645  * As the result, within the 4 possible combinations for BIT[15:14], there will
1646  * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1647  * command status will result in a 2-second delay start. The smaller BIT[15:14]
1648  * value is the correct combination.
1649  *
1650  * Since there are only 4 outcomes and the results are ordered, we can simply
1651  * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1652  * deduce the smaller successful combination.
1653  *
1654  * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1655  * of BIT[15:14]. The correct combination is as follow:
1656  *
1657  * if test0 fails and test1 passes, BIT[15:14] is 'b01
1658  * if test0 fails and test1 fails, BIT[15:14] is 'b10
1659  * if test0 passes and test1 fails, BIT[15:14] is 'b11
1660  * if test0 passes and test1 passes, BIT[15:14] is 'b00
1661  *
1662  * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1663  * endpoints.
1664  */
1665 static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1666 {
1667         int cmd_status = 0;
1668         bool test0;
1669         bool test1;
1670
1671         while (dep->combo_num < 2) {
1672                 struct dwc3_gadget_ep_cmd_params params;
1673                 u32 test_frame_number;
1674                 u32 cmd;
1675
1676                 /*
1677                  * Check if we can start isoc transfer on the next interval or
1678                  * 4 uframes in the future with BIT[15:14] as dep->combo_num
1679                  */
1680                 test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK;
1681                 test_frame_number |= dep->combo_num << 14;
1682                 test_frame_number += max_t(u32, 4, dep->interval);
1683
1684                 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1685                 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1686
1687                 cmd = DWC3_DEPCMD_STARTTRANSFER;
1688                 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1689                 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1690
1691                 /* Redo if some other failure beside bus-expiry is received */
1692                 if (cmd_status && cmd_status != -EAGAIN) {
1693                         dep->start_cmd_status = 0;
1694                         dep->combo_num = 0;
1695                         return 0;
1696                 }
1697
1698                 /* Store the first test status */
1699                 if (dep->combo_num == 0)
1700                         dep->start_cmd_status = cmd_status;
1701
1702                 dep->combo_num++;
1703
1704                 /*
1705                  * End the transfer if the START_TRANSFER command is successful
1706                  * to wait for the next XferNotReady to test the command again
1707                  */
1708                 if (cmd_status == 0) {
1709                         dwc3_stop_active_transfer(dep, true, true);
1710                         return 0;
1711                 }
1712         }
1713
1714         /* test0 and test1 are both completed at this point */
1715         test0 = (dep->start_cmd_status == 0);
1716         test1 = (cmd_status == 0);
1717
1718         if (!test0 && test1)
1719                 dep->combo_num = 1;
1720         else if (!test0 && !test1)
1721                 dep->combo_num = 2;
1722         else if (test0 && !test1)
1723                 dep->combo_num = 3;
1724         else if (test0 && test1)
1725                 dep->combo_num = 0;
1726
1727         dep->frame_number &= DWC3_FRNUMBER_MASK;
1728         dep->frame_number |= dep->combo_num << 14;
1729         dep->frame_number += max_t(u32, 4, dep->interval);
1730
1731         /* Reinitialize test variables */
1732         dep->start_cmd_status = 0;
1733         dep->combo_num = 0;
1734
1735         return __dwc3_gadget_kick_transfer(dep);
1736 }
1737
1738 static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1739 {
1740         const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
1741         struct dwc3 *dwc = dep->dwc;
1742         int ret;
1743         int i;
1744
1745         if (list_empty(&dep->pending_list) &&
1746             list_empty(&dep->started_list)) {
1747                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1748                 return -EAGAIN;
1749         }
1750
1751         if (!dwc->dis_start_transfer_quirk &&
1752             (DWC3_VER_IS_PRIOR(DWC31, 170A) ||
1753              DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) {
1754                 if (dwc->gadget->speed <= USB_SPEED_HIGH && dep->direction)
1755                         return dwc3_gadget_start_isoc_quirk(dep);
1756         }
1757
1758         if (desc->bInterval <= 14 &&
1759             dwc->gadget->speed >= USB_SPEED_HIGH) {
1760                 u32 frame = __dwc3_gadget_get_frame(dwc);
1761                 bool rollover = frame <
1762                                 (dep->frame_number & DWC3_FRNUMBER_MASK);
1763
1764                 /*
1765                  * frame_number is set from XferNotReady and may be already
1766                  * out of date. DSTS only provides the lower 14 bit of the
1767                  * current frame number. So add the upper two bits of
1768                  * frame_number and handle a possible rollover.
1769                  * This will provide the correct frame_number unless more than
1770                  * rollover has happened since XferNotReady.
1771                  */
1772
1773                 dep->frame_number = (dep->frame_number & ~DWC3_FRNUMBER_MASK) |
1774                                      frame;
1775                 if (rollover)
1776                         dep->frame_number += BIT(14);
1777         }
1778
1779         for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1780                 dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1);
1781
1782                 ret = __dwc3_gadget_kick_transfer(dep);
1783                 if (ret != -EAGAIN)
1784                         break;
1785         }
1786
1787         /*
1788          * After a number of unsuccessful start attempts due to bus-expiry
1789          * status, issue END_TRANSFER command and retry on the next XferNotReady
1790          * event.
1791          */
1792         if (ret == -EAGAIN) {
1793                 struct dwc3_gadget_ep_cmd_params params;
1794                 u32 cmd;
1795
1796                 cmd = DWC3_DEPCMD_ENDTRANSFER |
1797                         DWC3_DEPCMD_CMDIOC |
1798                         DWC3_DEPCMD_PARAM(dep->resource_index);
1799
1800                 dep->resource_index = 0;
1801                 memset(&params, 0, sizeof(params));
1802
1803                 ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1804                 if (!ret)
1805                         dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
1806         }
1807
1808         return ret;
1809 }
1810
1811 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1812 {
1813         struct dwc3             *dwc = dep->dwc;
1814
1815         if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
1816                 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1817                                 dep->name);
1818                 return -ESHUTDOWN;
1819         }
1820
1821         if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1822                                 &req->request, req->dep->name))
1823                 return -EINVAL;
1824
1825         if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1826                                 "%s: request %pK already in flight\n",
1827                                 dep->name, &req->request))
1828                 return -EINVAL;
1829
1830         pm_runtime_get(dwc->dev);
1831
1832         req->request.actual     = 0;
1833         req->request.status     = -EINPROGRESS;
1834
1835         trace_dwc3_ep_queue(req);
1836
1837         list_add_tail(&req->list, &dep->pending_list);
1838         req->status = DWC3_REQUEST_STATUS_QUEUED;
1839
1840         if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)
1841                 return 0;
1842
1843         /*
1844          * Start the transfer only after the END_TRANSFER is completed
1845          * and endpoint STALL is cleared.
1846          */
1847         if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
1848             (dep->flags & DWC3_EP_WEDGE) ||
1849             (dep->flags & DWC3_EP_STALL)) {
1850                 dep->flags |= DWC3_EP_DELAY_START;
1851                 return 0;
1852         }
1853
1854         /*
1855          * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1856          * wait for a XferNotReady event so we will know what's the current
1857          * (micro-)frame number.
1858          *
1859          * Without this trick, we are very, very likely gonna get Bus Expiry
1860          * errors which will force us issue EndTransfer command.
1861          */
1862         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1863                 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1864                                 !(dep->flags & DWC3_EP_TRANSFER_STARTED))
1865                         return 0;
1866
1867                 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1868                         if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
1869                                 return __dwc3_gadget_start_isoc(dep);
1870                 }
1871         }
1872
1873         __dwc3_gadget_kick_transfer(dep);
1874
1875         return 0;
1876 }
1877
1878 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1879         gfp_t gfp_flags)
1880 {
1881         struct dwc3_request             *req = to_dwc3_request(request);
1882         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1883         struct dwc3                     *dwc = dep->dwc;
1884
1885         unsigned long                   flags;
1886
1887         int                             ret;
1888
1889         spin_lock_irqsave(&dwc->lock, flags);
1890         ret = __dwc3_gadget_ep_queue(dep, req);
1891         spin_unlock_irqrestore(&dwc->lock, flags);
1892
1893         return ret;
1894 }
1895
1896 static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
1897 {
1898         int i;
1899
1900         /* If req->trb is not set, then the request has not started */
1901         if (!req->trb)
1902                 return;
1903
1904         /*
1905          * If request was already started, this means we had to
1906          * stop the transfer. With that we also need to ignore
1907          * all TRBs used by the request, however TRBs can only
1908          * be modified after completion of END_TRANSFER
1909          * command. So what we do here is that we wait for
1910          * END_TRANSFER completion and only after that, we jump
1911          * over TRBs by clearing HWO and incrementing dequeue
1912          * pointer.
1913          */
1914         for (i = 0; i < req->num_trbs; i++) {
1915                 struct dwc3_trb *trb;
1916
1917                 trb = &dep->trb_pool[dep->trb_dequeue];
1918                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1919                 dwc3_ep_inc_deq(dep);
1920         }
1921
1922         req->num_trbs = 0;
1923 }
1924
1925 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
1926 {
1927         struct dwc3_request             *req;
1928         struct dwc3_request             *tmp;
1929         struct dwc3                     *dwc = dep->dwc;
1930
1931         list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) {
1932                 dwc3_gadget_ep_skip_trbs(dep, req);
1933                 switch (req->status) {
1934                 case DWC3_REQUEST_STATUS_DISCONNECTED:
1935                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
1936                         break;
1937                 case DWC3_REQUEST_STATUS_DEQUEUED:
1938                         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1939                         break;
1940                 case DWC3_REQUEST_STATUS_STALLED:
1941                         dwc3_gadget_giveback(dep, req, -EPIPE);
1942                         break;
1943                 default:
1944                         dev_err(dwc->dev, "request cancelled with wrong reason:%d\n", req->status);
1945                         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1946                         break;
1947                 }
1948         }
1949 }
1950
1951 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1952                 struct usb_request *request)
1953 {
1954         struct dwc3_request             *req = to_dwc3_request(request);
1955         struct dwc3_request             *r = NULL;
1956
1957         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1958         struct dwc3                     *dwc = dep->dwc;
1959
1960         unsigned long                   flags;
1961         int                             ret = 0;
1962
1963         trace_dwc3_ep_dequeue(req);
1964
1965         spin_lock_irqsave(&dwc->lock, flags);
1966
1967         list_for_each_entry(r, &dep->cancelled_list, list) {
1968                 if (r == req)
1969                         goto out;
1970         }
1971
1972         list_for_each_entry(r, &dep->pending_list, list) {
1973                 if (r == req) {
1974                         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1975                         goto out;
1976                 }
1977         }
1978
1979         list_for_each_entry(r, &dep->started_list, list) {
1980                 if (r == req) {
1981                         struct dwc3_request *t;
1982
1983                         /* wait until it is processed */
1984                         dwc3_stop_active_transfer(dep, true, true);
1985
1986                         /*
1987                          * Remove any started request if the transfer is
1988                          * cancelled.
1989                          */
1990                         list_for_each_entry_safe(r, t, &dep->started_list, list)
1991                                 dwc3_gadget_move_cancelled_request(r,
1992                                                 DWC3_REQUEST_STATUS_DEQUEUED);
1993
1994                         dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
1995
1996                         goto out;
1997                 }
1998         }
1999
2000         dev_err(dwc->dev, "request %pK was not queued to %s\n",
2001                 request, ep->name);
2002         ret = -EINVAL;
2003 out:
2004         spin_unlock_irqrestore(&dwc->lock, flags);
2005
2006         return ret;
2007 }
2008
2009 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
2010 {
2011         struct dwc3_gadget_ep_cmd_params        params;
2012         struct dwc3                             *dwc = dep->dwc;
2013         struct dwc3_request                     *req;
2014         struct dwc3_request                     *tmp;
2015         int                                     ret;
2016
2017         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2018                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
2019                 return -EINVAL;
2020         }
2021
2022         memset(&params, 0x00, sizeof(params));
2023
2024         if (value) {
2025                 struct dwc3_trb *trb;
2026
2027                 unsigned int transfer_in_flight;
2028                 unsigned int started;
2029
2030                 if (dep->number > 1)
2031                         trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
2032                 else
2033                         trb = &dwc->ep0_trb[dep->trb_enqueue];
2034
2035                 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
2036                 started = !list_empty(&dep->started_list);
2037
2038                 if (!protocol && ((dep->direction && transfer_in_flight) ||
2039                                 (!dep->direction && started))) {
2040                         return -EAGAIN;
2041                 }
2042
2043                 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
2044                                 &params);
2045                 if (ret)
2046                         dev_err(dwc->dev, "failed to set STALL on %s\n",
2047                                         dep->name);
2048                 else
2049                         dep->flags |= DWC3_EP_STALL;
2050         } else {
2051                 /*
2052                  * Don't issue CLEAR_STALL command to control endpoints. The
2053                  * controller automatically clears the STALL when it receives
2054                  * the SETUP token.
2055                  */
2056                 if (dep->number <= 1) {
2057                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2058                         return 0;
2059                 }
2060
2061                 dwc3_stop_active_transfer(dep, true, true);
2062
2063                 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
2064                         dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_STALLED);
2065
2066                 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING) {
2067                         dep->flags |= DWC3_EP_PENDING_CLEAR_STALL;
2068                         return 0;
2069                 }
2070
2071                 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2072
2073                 ret = dwc3_send_clear_stall_ep_cmd(dep);
2074                 if (ret) {
2075                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
2076                                         dep->name);
2077                         return ret;
2078                 }
2079
2080                 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2081
2082                 if ((dep->flags & DWC3_EP_DELAY_START) &&
2083                     !usb_endpoint_xfer_isoc(dep->endpoint.desc))
2084                         __dwc3_gadget_kick_transfer(dep);
2085
2086                 dep->flags &= ~DWC3_EP_DELAY_START;
2087         }
2088
2089         return ret;
2090 }
2091
2092 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
2093 {
2094         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
2095         struct dwc3                     *dwc = dep->dwc;
2096
2097         unsigned long                   flags;
2098
2099         int                             ret;
2100
2101         spin_lock_irqsave(&dwc->lock, flags);
2102         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
2103         spin_unlock_irqrestore(&dwc->lock, flags);
2104
2105         return ret;
2106 }
2107
2108 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
2109 {
2110         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
2111         struct dwc3                     *dwc = dep->dwc;
2112         unsigned long                   flags;
2113         int                             ret;
2114
2115         spin_lock_irqsave(&dwc->lock, flags);
2116         dep->flags |= DWC3_EP_WEDGE;
2117
2118         if (dep->number == 0 || dep->number == 1)
2119                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
2120         else
2121                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
2122         spin_unlock_irqrestore(&dwc->lock, flags);
2123
2124         return ret;
2125 }
2126
2127 /* -------------------------------------------------------------------------- */
2128
2129 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
2130         .bLength        = USB_DT_ENDPOINT_SIZE,
2131         .bDescriptorType = USB_DT_ENDPOINT,
2132         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
2133 };
2134
2135 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
2136         .enable         = dwc3_gadget_ep0_enable,
2137         .disable        = dwc3_gadget_ep0_disable,
2138         .alloc_request  = dwc3_gadget_ep_alloc_request,
2139         .free_request   = dwc3_gadget_ep_free_request,
2140         .queue          = dwc3_gadget_ep0_queue,
2141         .dequeue        = dwc3_gadget_ep_dequeue,
2142         .set_halt       = dwc3_gadget_ep0_set_halt,
2143         .set_wedge      = dwc3_gadget_ep_set_wedge,
2144 };
2145
2146 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
2147         .enable         = dwc3_gadget_ep_enable,
2148         .disable        = dwc3_gadget_ep_disable,
2149         .alloc_request  = dwc3_gadget_ep_alloc_request,
2150         .free_request   = dwc3_gadget_ep_free_request,
2151         .queue          = dwc3_gadget_ep_queue,
2152         .dequeue        = dwc3_gadget_ep_dequeue,
2153         .set_halt       = dwc3_gadget_ep_set_halt,
2154         .set_wedge      = dwc3_gadget_ep_set_wedge,
2155 };
2156
2157 /* -------------------------------------------------------------------------- */
2158
2159 static int dwc3_gadget_get_frame(struct usb_gadget *g)
2160 {
2161         struct dwc3             *dwc = gadget_to_dwc(g);
2162
2163         return __dwc3_gadget_get_frame(dwc);
2164 }
2165
2166 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
2167 {
2168         int                     retries;
2169
2170         int                     ret;
2171         u32                     reg;
2172
2173         u8                      link_state;
2174
2175         /*
2176          * According to the Databook Remote wakeup request should
2177          * be issued only when the device is in early suspend state.
2178          *
2179          * We can check that via USB Link State bits in DSTS register.
2180          */
2181         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2182
2183         link_state = DWC3_DSTS_USBLNKST(reg);
2184
2185         switch (link_state) {
2186         case DWC3_LINK_STATE_RESET:
2187         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
2188         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
2189         case DWC3_LINK_STATE_U2:        /* in HS, means Sleep (L1) */
2190         case DWC3_LINK_STATE_U1:
2191         case DWC3_LINK_STATE_RESUME:
2192                 break;
2193         default:
2194                 return -EINVAL;
2195         }
2196
2197         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
2198         if (ret < 0) {
2199                 dev_err(dwc->dev, "failed to put link in Recovery\n");
2200                 return ret;
2201         }
2202
2203         /* Recent versions do this automatically */
2204         if (DWC3_VER_IS_PRIOR(DWC3, 194A)) {
2205                 /* write zeroes to Link Change Request */
2206                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2207                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
2208                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2209         }
2210
2211         /* poll until Link State changes to ON */
2212         retries = 20000;
2213
2214         while (retries--) {
2215                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2216
2217                 /* in HS, means ON */
2218                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
2219                         break;
2220         }
2221
2222         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
2223                 dev_err(dwc->dev, "failed to send remote wakeup\n");
2224                 return -EINVAL;
2225         }
2226
2227         return 0;
2228 }
2229
2230 static int dwc3_gadget_wakeup(struct usb_gadget *g)
2231 {
2232         struct dwc3             *dwc = gadget_to_dwc(g);
2233         unsigned long           flags;
2234         int                     ret;
2235
2236         spin_lock_irqsave(&dwc->lock, flags);
2237         ret = __dwc3_gadget_wakeup(dwc);
2238         spin_unlock_irqrestore(&dwc->lock, flags);
2239
2240         return ret;
2241 }
2242
2243 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
2244                 int is_selfpowered)
2245 {
2246         struct dwc3             *dwc = gadget_to_dwc(g);
2247         unsigned long           flags;
2248
2249         spin_lock_irqsave(&dwc->lock, flags);
2250         g->is_selfpowered = !!is_selfpowered;
2251         spin_unlock_irqrestore(&dwc->lock, flags);
2252
2253         return 0;
2254 }
2255
2256 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2257 {
2258         u32 epnum;
2259
2260         for (epnum = 2; epnum < dwc->num_eps; epnum++) {
2261                 struct dwc3_ep *dep;
2262
2263                 dep = dwc->eps[epnum];
2264                 if (!dep)
2265                         continue;
2266
2267                 dwc3_remove_requests(dwc, dep);
2268         }
2269 }
2270
2271 static void __dwc3_gadget_set_ssp_rate(struct dwc3 *dwc)
2272 {
2273         enum usb_ssp_rate       ssp_rate = dwc->gadget_ssp_rate;
2274         u32                     reg;
2275
2276         if (ssp_rate == USB_SSP_GEN_UNKNOWN)
2277                 ssp_rate = dwc->max_ssp_rate;
2278
2279         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2280         reg &= ~DWC3_DCFG_SPEED_MASK;
2281         reg &= ~DWC3_DCFG_NUMLANES(~0);
2282
2283         if (ssp_rate == USB_SSP_GEN_1x2)
2284                 reg |= DWC3_DCFG_SUPERSPEED;
2285         else if (dwc->max_ssp_rate != USB_SSP_GEN_1x2)
2286                 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2287
2288         if (ssp_rate != USB_SSP_GEN_2x1 &&
2289             dwc->max_ssp_rate != USB_SSP_GEN_2x1)
2290                 reg |= DWC3_DCFG_NUMLANES(1);
2291
2292         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2293 }
2294
2295 static void __dwc3_gadget_set_speed(struct dwc3 *dwc)
2296 {
2297         enum usb_device_speed   speed;
2298         u32                     reg;
2299
2300         speed = dwc->gadget_max_speed;
2301         if (speed == USB_SPEED_UNKNOWN || speed > dwc->maximum_speed)
2302                 speed = dwc->maximum_speed;
2303
2304         if (speed == USB_SPEED_SUPER_PLUS &&
2305             DWC3_IP_IS(DWC32)) {
2306                 __dwc3_gadget_set_ssp_rate(dwc);
2307                 return;
2308         }
2309
2310         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2311         reg &= ~(DWC3_DCFG_SPEED_MASK);
2312
2313         /*
2314          * WORKAROUND: DWC3 revision < 2.20a have an issue
2315          * which would cause metastability state on Run/Stop
2316          * bit if we try to force the IP to USB2-only mode.
2317          *
2318          * Because of that, we cannot configure the IP to any
2319          * speed other than the SuperSpeed
2320          *
2321          * Refers to:
2322          *
2323          * STAR#9000525659: Clock Domain Crossing on DCTL in
2324          * USB 2.0 Mode
2325          */
2326         if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
2327             !dwc->dis_metastability_quirk) {
2328                 reg |= DWC3_DCFG_SUPERSPEED;
2329         } else {
2330                 switch (speed) {
2331                 case USB_SPEED_FULL:
2332                         reg |= DWC3_DCFG_FULLSPEED;
2333                         break;
2334                 case USB_SPEED_HIGH:
2335                         reg |= DWC3_DCFG_HIGHSPEED;
2336                         break;
2337                 case USB_SPEED_SUPER:
2338                         reg |= DWC3_DCFG_SUPERSPEED;
2339                         break;
2340                 case USB_SPEED_SUPER_PLUS:
2341                         if (DWC3_IP_IS(DWC3))
2342                                 reg |= DWC3_DCFG_SUPERSPEED;
2343                         else
2344                                 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2345                         break;
2346                 default:
2347                         dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2348
2349                         if (DWC3_IP_IS(DWC3))
2350                                 reg |= DWC3_DCFG_SUPERSPEED;
2351                         else
2352                                 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2353                 }
2354         }
2355
2356         if (DWC3_IP_IS(DWC32) &&
2357             speed > USB_SPEED_UNKNOWN &&
2358             speed < USB_SPEED_SUPER_PLUS)
2359                 reg &= ~DWC3_DCFG_NUMLANES(~0);
2360
2361         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2362 }
2363
2364 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
2365 {
2366         u32                     reg;
2367         u32                     timeout = 500;
2368
2369         if (pm_runtime_suspended(dwc->dev))
2370                 return 0;
2371
2372         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2373         if (is_on) {
2374                 if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) {
2375                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
2376                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
2377                 }
2378
2379                 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
2380                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
2381                 reg |= DWC3_DCTL_RUN_STOP;
2382
2383                 if (dwc->has_hibernation)
2384                         reg |= DWC3_DCTL_KEEP_CONNECT;
2385
2386                 __dwc3_gadget_set_speed(dwc);
2387                 dwc->pullups_connected = true;
2388         } else {
2389                 reg &= ~DWC3_DCTL_RUN_STOP;
2390
2391                 if (dwc->has_hibernation && !suspend)
2392                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
2393
2394                 dwc->pullups_connected = false;
2395         }
2396
2397         dwc3_gadget_dctl_write_safe(dwc, reg);
2398
2399         do {
2400                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2401                 reg &= DWC3_DSTS_DEVCTRLHLT;
2402         } while (--timeout && !(!is_on ^ !reg));
2403
2404         if (!timeout)
2405                 return -ETIMEDOUT;
2406
2407         return 0;
2408 }
2409
2410 static void dwc3_gadget_disable_irq(struct dwc3 *dwc);
2411 static void __dwc3_gadget_stop(struct dwc3 *dwc);
2412 static int __dwc3_gadget_start(struct dwc3 *dwc);
2413
2414 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
2415 {
2416         struct dwc3             *dwc = gadget_to_dwc(g);
2417         unsigned long           flags;
2418         int                     ret;
2419
2420         is_on = !!is_on;
2421
2422         /*
2423          * Per databook, when we want to stop the gadget, if a control transfer
2424          * is still in process, complete it and get the core into setup phase.
2425          */
2426         if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
2427                 reinit_completion(&dwc->ep0_in_setup);
2428
2429                 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
2430                                 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
2431                 if (ret == 0) {
2432                         dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
2433                         return -ETIMEDOUT;
2434                 }
2435         }
2436
2437         /*
2438          * Check the return value for successful resume, or error.  For a
2439          * successful resume, the DWC3 runtime PM resume routine will handle
2440          * the run stop sequence, so avoid duplicate operations here.
2441          */
2442         ret = pm_runtime_get_sync(dwc->dev);
2443         if (!ret || ret < 0) {
2444                 pm_runtime_put(dwc->dev);
2445                 return 0;
2446         }
2447
2448         /*
2449          * Synchronize and disable any further event handling while controller
2450          * is being enabled/disabled.
2451          */
2452         disable_irq(dwc->irq_gadget);
2453
2454         spin_lock_irqsave(&dwc->lock, flags);
2455
2456         if (!is_on) {
2457                 u32 count;
2458
2459                 dwc->connected = false;
2460                 /*
2461                  * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
2462                  * Section 4.1.8 Table 4-7, it states that for a device-initiated
2463                  * disconnect, the SW needs to ensure that it sends "a DEPENDXFER
2464                  * command for any active transfers" before clearing the RunStop
2465                  * bit.
2466                  */
2467                 dwc3_stop_active_transfers(dwc);
2468                 __dwc3_gadget_stop(dwc);
2469
2470                 /*
2471                  * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
2472                  * Section 1.3.4, it mentions that for the DEVCTRLHLT bit, the
2473                  * "software needs to acknowledge the events that are generated
2474                  * (by writing to GEVNTCOUNTn) while it is waiting for this bit
2475                  * to be set to '1'."
2476                  */
2477                 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2478                 count &= DWC3_GEVNTCOUNT_MASK;
2479                 if (count > 0) {
2480                         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
2481                         dwc->ev_buf->lpos = (dwc->ev_buf->lpos + count) %
2482                                                 dwc->ev_buf->length;
2483                 }
2484         } else {
2485                 __dwc3_gadget_start(dwc);
2486         }
2487
2488         ret = dwc3_gadget_run_stop(dwc, is_on, false);
2489         spin_unlock_irqrestore(&dwc->lock, flags);
2490         enable_irq(dwc->irq_gadget);
2491
2492         pm_runtime_put(dwc->dev);
2493
2494         return ret;
2495 }
2496
2497 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
2498 {
2499         u32                     reg;
2500
2501         /* Enable all but Start and End of Frame IRQs */
2502         reg = (DWC3_DEVTEN_EVNTOVERFLOWEN |
2503                         DWC3_DEVTEN_CMDCMPLTEN |
2504                         DWC3_DEVTEN_ERRTICERREN |
2505                         DWC3_DEVTEN_WKUPEVTEN |
2506                         DWC3_DEVTEN_CONNECTDONEEN |
2507                         DWC3_DEVTEN_USBRSTEN |
2508                         DWC3_DEVTEN_DISCONNEVTEN);
2509
2510         if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2511                 reg |= DWC3_DEVTEN_ULSTCNGEN;
2512
2513         /* On 2.30a and above this bit enables U3/L2-L1 Suspend Events */
2514         if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
2515                 reg |= DWC3_DEVTEN_U3L2L1SUSPEN;
2516
2517         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2518 }
2519
2520 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
2521 {
2522         /* mask all interrupts */
2523         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2524 }
2525
2526 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
2527 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
2528
2529 /**
2530  * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
2531  * @dwc: pointer to our context structure
2532  *
2533  * The following looks like complex but it's actually very simple. In order to
2534  * calculate the number of packets we can burst at once on OUT transfers, we're
2535  * gonna use RxFIFO size.
2536  *
2537  * To calculate RxFIFO size we need two numbers:
2538  * MDWIDTH = size, in bits, of the internal memory bus
2539  * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
2540  *
2541  * Given these two numbers, the formula is simple:
2542  *
2543  * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
2544  *
2545  * 24 bytes is for 3x SETUP packets
2546  * 16 bytes is a clock domain crossing tolerance
2547  *
2548  * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
2549  */
2550 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
2551 {
2552         u32 ram2_depth;
2553         u32 mdwidth;
2554         u32 nump;
2555         u32 reg;
2556
2557         ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
2558         mdwidth = dwc3_mdwidth(dwc);
2559
2560         nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
2561         nump = min_t(u32, nump, 16);
2562
2563         /* update NumP */
2564         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2565         reg &= ~DWC3_DCFG_NUMP_MASK;
2566         reg |= nump << DWC3_DCFG_NUMP_SHIFT;
2567         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2568 }
2569
2570 static int __dwc3_gadget_start(struct dwc3 *dwc)
2571 {
2572         struct dwc3_ep          *dep;
2573         int                     ret = 0;
2574         u32                     reg;
2575
2576         /*
2577          * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
2578          * the core supports IMOD, disable it.
2579          */
2580         if (dwc->imod_interval) {
2581                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2582                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2583         } else if (dwc3_has_imod(dwc)) {
2584                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
2585         }
2586
2587         /*
2588          * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
2589          * field instead of letting dwc3 itself calculate that automatically.
2590          *
2591          * This way, we maximize the chances that we'll be able to get several
2592          * bursts of data without going through any sort of endpoint throttling.
2593          */
2594         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
2595         if (DWC3_IP_IS(DWC3))
2596                 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
2597         else
2598                 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
2599
2600         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
2601
2602         dwc3_gadget_setup_nump(dwc);
2603
2604         /*
2605          * Currently the controller handles single stream only. So, Ignore
2606          * Packet Pending bit for stream selection and don't search for another
2607          * stream if the host sends Data Packet with PP=0 (for OUT direction) or
2608          * ACK with NumP=0 and PP=0 (for IN direction). This slightly improves
2609          * the stream performance.
2610          */
2611         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2612         reg |= DWC3_DCFG_IGNSTRMPP;
2613         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2614
2615         /* Start with SuperSpeed Default */
2616         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2617
2618         dep = dwc->eps[0];
2619         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2620         if (ret) {
2621                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2622                 goto err0;
2623         }
2624
2625         dep = dwc->eps[1];
2626         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2627         if (ret) {
2628                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2629                 goto err1;
2630         }
2631
2632         /* begin to receive SETUP packets */
2633         dwc->ep0state = EP0_SETUP_PHASE;
2634         dwc->link_state = DWC3_LINK_STATE_SS_DIS;
2635         dwc3_ep0_out_start(dwc);
2636
2637         dwc3_gadget_enable_irq(dwc);
2638
2639         return 0;
2640
2641 err1:
2642         __dwc3_gadget_ep_disable(dwc->eps[0]);
2643
2644 err0:
2645         return ret;
2646 }
2647
2648 static int dwc3_gadget_start(struct usb_gadget *g,
2649                 struct usb_gadget_driver *driver)
2650 {
2651         struct dwc3             *dwc = gadget_to_dwc(g);
2652         unsigned long           flags;
2653         int                     ret;
2654         int                     irq;
2655
2656         irq = dwc->irq_gadget;
2657         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2658                         IRQF_SHARED, "dwc3", dwc->ev_buf);
2659         if (ret) {
2660                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2661                                 irq, ret);
2662                 return ret;
2663         }
2664
2665         spin_lock_irqsave(&dwc->lock, flags);
2666         dwc->gadget_driver      = driver;
2667         spin_unlock_irqrestore(&dwc->lock, flags);
2668
2669         return 0;
2670 }
2671
2672 static void __dwc3_gadget_stop(struct dwc3 *dwc)
2673 {
2674         dwc3_gadget_disable_irq(dwc);
2675         __dwc3_gadget_ep_disable(dwc->eps[0]);
2676         __dwc3_gadget_ep_disable(dwc->eps[1]);
2677 }
2678
2679 static int dwc3_gadget_stop(struct usb_gadget *g)
2680 {
2681         struct dwc3             *dwc = gadget_to_dwc(g);
2682         unsigned long           flags;
2683
2684         spin_lock_irqsave(&dwc->lock, flags);
2685         dwc->gadget_driver      = NULL;
2686         dwc->max_cfg_eps = 0;
2687         spin_unlock_irqrestore(&dwc->lock, flags);
2688
2689         free_irq(dwc->irq_gadget, dwc->ev_buf);
2690
2691         return 0;
2692 }
2693
2694 static void dwc3_gadget_config_params(struct usb_gadget *g,
2695                                       struct usb_dcd_config_params *params)
2696 {
2697         struct dwc3             *dwc = gadget_to_dwc(g);
2698
2699         params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
2700         params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
2701
2702         /* Recommended BESL */
2703         if (!dwc->dis_enblslpm_quirk) {
2704                 /*
2705                  * If the recommended BESL baseline is 0 or if the BESL deep is
2706                  * less than 2, Microsoft's Windows 10 host usb stack will issue
2707                  * a usb reset immediately after it receives the extended BOS
2708                  * descriptor and the enumeration will fail. To maintain
2709                  * compatibility with the Windows' usb stack, let's set the
2710                  * recommended BESL baseline to 1 and clamp the BESL deep to be
2711                  * within 2 to 15.
2712                  */
2713                 params->besl_baseline = 1;
2714                 if (dwc->is_utmi_l1_suspend)
2715                         params->besl_deep =
2716                                 clamp_t(u8, dwc->hird_threshold, 2, 15);
2717         }
2718
2719         /* U1 Device exit Latency */
2720         if (dwc->dis_u1_entry_quirk)
2721                 params->bU1devExitLat = 0;
2722         else
2723                 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
2724
2725         /* U2 Device exit Latency */
2726         if (dwc->dis_u2_entry_quirk)
2727                 params->bU2DevExitLat = 0;
2728         else
2729                 params->bU2DevExitLat =
2730                                 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
2731 }
2732
2733 static void dwc3_gadget_set_speed(struct usb_gadget *g,
2734                                   enum usb_device_speed speed)
2735 {
2736         struct dwc3             *dwc = gadget_to_dwc(g);
2737         unsigned long           flags;
2738
2739         spin_lock_irqsave(&dwc->lock, flags);
2740         dwc->gadget_max_speed = speed;
2741         spin_unlock_irqrestore(&dwc->lock, flags);
2742 }
2743
2744 static void dwc3_gadget_set_ssp_rate(struct usb_gadget *g,
2745                                      enum usb_ssp_rate rate)
2746 {
2747         struct dwc3             *dwc = gadget_to_dwc(g);
2748         unsigned long           flags;
2749
2750         spin_lock_irqsave(&dwc->lock, flags);
2751         dwc->gadget_max_speed = USB_SPEED_SUPER_PLUS;
2752         dwc->gadget_ssp_rate = rate;
2753         spin_unlock_irqrestore(&dwc->lock, flags);
2754 }
2755
2756 static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA)
2757 {
2758         struct dwc3             *dwc = gadget_to_dwc(g);
2759         union power_supply_propval      val = {0};
2760         int                             ret;
2761
2762         if (dwc->usb2_phy)
2763                 return usb_phy_set_power(dwc->usb2_phy, mA);
2764
2765         if (!dwc->usb_psy)
2766                 return -EOPNOTSUPP;
2767
2768         val.intval = 1000 * mA;
2769         ret = power_supply_set_property(dwc->usb_psy, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val);
2770
2771         return ret;
2772 }
2773
2774 /**
2775  * dwc3_gadget_check_config - ensure dwc3 can support the USB configuration
2776  * @g: pointer to the USB gadget
2777  *
2778  * Used to record the maximum number of endpoints being used in a USB composite
2779  * device. (across all configurations)  This is to be used in the calculation
2780  * of the TXFIFO sizes when resizing internal memory for individual endpoints.
2781  * It will help ensured that the resizing logic reserves enough space for at
2782  * least one max packet.
2783  */
2784 static int dwc3_gadget_check_config(struct usb_gadget *g)
2785 {
2786         struct dwc3 *dwc = gadget_to_dwc(g);
2787         struct usb_ep *ep;
2788         int fifo_size = 0;
2789         int ram1_depth;
2790         int ep_num = 0;
2791
2792         if (!dwc->do_fifo_resize)
2793                 return 0;
2794
2795         list_for_each_entry(ep, &g->ep_list, ep_list) {
2796                 /* Only interested in the IN endpoints */
2797                 if (ep->claimed && (ep->address & USB_DIR_IN))
2798                         ep_num++;
2799         }
2800
2801         if (ep_num <= dwc->max_cfg_eps)
2802                 return 0;
2803
2804         /* Update the max number of eps in the composition */
2805         dwc->max_cfg_eps = ep_num;
2806
2807         fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps);
2808         /* Based on the equation, increment by one for every ep */
2809         fifo_size += dwc->max_cfg_eps;
2810
2811         /* Check if we can fit a single fifo per endpoint */
2812         ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
2813         if (fifo_size > ram1_depth)
2814                 return -ENOMEM;
2815
2816         return 0;
2817 }
2818
2819 static void dwc3_gadget_async_callbacks(struct usb_gadget *g, bool enable)
2820 {
2821         struct dwc3             *dwc = gadget_to_dwc(g);
2822         unsigned long           flags;
2823
2824         spin_lock_irqsave(&dwc->lock, flags);
2825         dwc->async_callbacks = enable;
2826         spin_unlock_irqrestore(&dwc->lock, flags);
2827 }
2828
2829 static const struct usb_gadget_ops dwc3_gadget_ops = {
2830         .get_frame              = dwc3_gadget_get_frame,
2831         .wakeup                 = dwc3_gadget_wakeup,
2832         .set_selfpowered        = dwc3_gadget_set_selfpowered,
2833         .pullup                 = dwc3_gadget_pullup,
2834         .udc_start              = dwc3_gadget_start,
2835         .udc_stop               = dwc3_gadget_stop,
2836         .udc_set_speed          = dwc3_gadget_set_speed,
2837         .udc_set_ssp_rate       = dwc3_gadget_set_ssp_rate,
2838         .get_config_params      = dwc3_gadget_config_params,
2839         .vbus_draw              = dwc3_gadget_vbus_draw,
2840         .check_config           = dwc3_gadget_check_config,
2841         .udc_async_callbacks    = dwc3_gadget_async_callbacks,
2842 };
2843
2844 /* -------------------------------------------------------------------------- */
2845
2846 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2847 {
2848         struct dwc3 *dwc = dep->dwc;
2849
2850         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2851         dep->endpoint.maxburst = 1;
2852         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2853         if (!dep->direction)
2854                 dwc->gadget->ep0 = &dep->endpoint;
2855
2856         dep->endpoint.caps.type_control = true;
2857
2858         return 0;
2859 }
2860
2861 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2862 {
2863         struct dwc3 *dwc = dep->dwc;
2864         u32 mdwidth;
2865         int size;
2866
2867         mdwidth = dwc3_mdwidth(dwc);
2868
2869         /* MDWIDTH is represented in bits, we need it in bytes */
2870         mdwidth /= 8;
2871
2872         size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2873         if (DWC3_IP_IS(DWC3))
2874                 size = DWC3_GTXFIFOSIZ_TXFDEP(size);
2875         else
2876                 size = DWC31_GTXFIFOSIZ_TXFDEP(size);
2877
2878         /* FIFO Depth is in MDWDITH bytes. Multiply */
2879         size *= mdwidth;
2880
2881         /*
2882          * To meet performance requirement, a minimum TxFIFO size of 3x
2883          * MaxPacketSize is recommended for endpoints that support burst and a
2884          * minimum TxFIFO size of 2x MaxPacketSize for endpoints that don't
2885          * support burst. Use those numbers and we can calculate the max packet
2886          * limit as below.
2887          */
2888         if (dwc->maximum_speed >= USB_SPEED_SUPER)
2889                 size /= 3;
2890         else
2891                 size /= 2;
2892
2893         usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2894
2895         dep->endpoint.max_streams = 16;
2896         dep->endpoint.ops = &dwc3_gadget_ep_ops;
2897         list_add_tail(&dep->endpoint.ep_list,
2898                         &dwc->gadget->ep_list);
2899         dep->endpoint.caps.type_iso = true;
2900         dep->endpoint.caps.type_bulk = true;
2901         dep->endpoint.caps.type_int = true;
2902
2903         return dwc3_alloc_trb_pool(dep);
2904 }
2905
2906 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2907 {
2908         struct dwc3 *dwc = dep->dwc;
2909         u32 mdwidth;
2910         int size;
2911
2912         mdwidth = dwc3_mdwidth(dwc);
2913
2914         /* MDWIDTH is represented in bits, convert to bytes */
2915         mdwidth /= 8;
2916
2917         /* All OUT endpoints share a single RxFIFO space */
2918         size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0));
2919         if (DWC3_IP_IS(DWC3))
2920                 size = DWC3_GRXFIFOSIZ_RXFDEP(size);
2921         else
2922                 size = DWC31_GRXFIFOSIZ_RXFDEP(size);
2923
2924         /* FIFO depth is in MDWDITH bytes */
2925         size *= mdwidth;
2926
2927         /*
2928          * To meet performance requirement, a minimum recommended RxFIFO size
2929          * is defined as follow:
2930          * RxFIFO size >= (3 x MaxPacketSize) +
2931          * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin)
2932          *
2933          * Then calculate the max packet limit as below.
2934          */
2935         size -= (3 * 8) + 16;
2936         if (size < 0)
2937                 size = 0;
2938         else
2939                 size /= 3;
2940
2941         usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2942         dep->endpoint.max_streams = 16;
2943         dep->endpoint.ops = &dwc3_gadget_ep_ops;
2944         list_add_tail(&dep->endpoint.ep_list,
2945                         &dwc->gadget->ep_list);
2946         dep->endpoint.caps.type_iso = true;
2947         dep->endpoint.caps.type_bulk = true;
2948         dep->endpoint.caps.type_int = true;
2949
2950         return dwc3_alloc_trb_pool(dep);
2951 }
2952
2953 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
2954 {
2955         struct dwc3_ep                  *dep;
2956         bool                            direction = epnum & 1;
2957         int                             ret;
2958         u8                              num = epnum >> 1;
2959
2960         dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2961         if (!dep)
2962                 return -ENOMEM;
2963
2964         dep->dwc = dwc;
2965         dep->number = epnum;
2966         dep->direction = direction;
2967         dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2968         dwc->eps[epnum] = dep;
2969         dep->combo_num = 0;
2970         dep->start_cmd_status = 0;
2971
2972         snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2973                         direction ? "in" : "out");
2974
2975         dep->endpoint.name = dep->name;
2976
2977         if (!(dep->number > 1)) {
2978                 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2979                 dep->endpoint.comp_desc = NULL;
2980         }
2981
2982         if (num == 0)
2983                 ret = dwc3_gadget_init_control_endpoint(dep);
2984         else if (direction)
2985                 ret = dwc3_gadget_init_in_endpoint(dep);
2986         else
2987                 ret = dwc3_gadget_init_out_endpoint(dep);
2988
2989         if (ret)
2990                 return ret;
2991
2992         dep->endpoint.caps.dir_in = direction;
2993         dep->endpoint.caps.dir_out = !direction;
2994
2995         INIT_LIST_HEAD(&dep->pending_list);
2996         INIT_LIST_HEAD(&dep->started_list);
2997         INIT_LIST_HEAD(&dep->cancelled_list);
2998
2999         dwc3_debugfs_create_endpoint_dir(dep);
3000
3001         return 0;
3002 }
3003
3004 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
3005 {
3006         u8                              epnum;
3007
3008         INIT_LIST_HEAD(&dwc->gadget->ep_list);
3009
3010         for (epnum = 0; epnum < total; epnum++) {
3011                 int                     ret;
3012
3013                 ret = dwc3_gadget_init_endpoint(dwc, epnum);
3014                 if (ret)
3015                         return ret;
3016         }
3017
3018         return 0;
3019 }
3020
3021 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
3022 {
3023         struct dwc3_ep                  *dep;
3024         u8                              epnum;
3025
3026         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3027                 dep = dwc->eps[epnum];
3028                 if (!dep)
3029                         continue;
3030                 /*
3031                  * Physical endpoints 0 and 1 are special; they form the
3032                  * bi-directional USB endpoint 0.
3033                  *
3034                  * For those two physical endpoints, we don't allocate a TRB
3035                  * pool nor do we add them the endpoints list. Due to that, we
3036                  * shouldn't do these two operations otherwise we would end up
3037                  * with all sorts of bugs when removing dwc3.ko.
3038                  */
3039                 if (epnum != 0 && epnum != 1) {
3040                         dwc3_free_trb_pool(dep);
3041                         list_del(&dep->endpoint.ep_list);
3042                 }
3043
3044                 debugfs_remove_recursive(debugfs_lookup(dep->name,
3045                                 debugfs_lookup(dev_name(dep->dwc->dev),
3046                                                usb_debug_root)));
3047                 kfree(dep);
3048         }
3049 }
3050
3051 /* -------------------------------------------------------------------------- */
3052
3053 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
3054                 struct dwc3_request *req, struct dwc3_trb *trb,
3055                 const struct dwc3_event_depevt *event, int status, int chain)
3056 {
3057         unsigned int            count;
3058
3059         dwc3_ep_inc_deq(dep);
3060
3061         trace_dwc3_complete_trb(dep, trb);
3062         req->num_trbs--;
3063
3064         /*
3065          * If we're in the middle of series of chained TRBs and we
3066          * receive a short transfer along the way, DWC3 will skip
3067          * through all TRBs including the last TRB in the chain (the
3068          * where CHN bit is zero. DWC3 will also avoid clearing HWO
3069          * bit and SW has to do it manually.
3070          *
3071          * We're going to do that here to avoid problems of HW trying
3072          * to use bogus TRBs for transfers.
3073          */
3074         if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
3075                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3076
3077         /*
3078          * For isochronous transfers, the first TRB in a service interval must
3079          * have the Isoc-First type. Track and report its interval frame number.
3080          */
3081         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3082             (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
3083                 unsigned int frame_number;
3084
3085                 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
3086                 frame_number &= ~(dep->interval - 1);
3087                 req->request.frame_number = frame_number;
3088         }
3089
3090         /*
3091          * We use bounce buffer for requests that needs extra TRB or OUT ZLP. If
3092          * this TRB points to the bounce buffer address, it's a MPS alignment
3093          * TRB. Don't add it to req->remaining calculation.
3094          */
3095         if (trb->bpl == lower_32_bits(dep->dwc->bounce_addr) &&
3096             trb->bph == upper_32_bits(dep->dwc->bounce_addr)) {
3097                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3098                 return 1;
3099         }
3100
3101         count = trb->size & DWC3_TRB_SIZE_MASK;
3102         req->remaining += count;
3103
3104         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
3105                 return 1;
3106
3107         if (event->status & DEPEVT_STATUS_SHORT && !chain)
3108                 return 1;
3109
3110         if ((trb->ctrl & DWC3_TRB_CTRL_IOC) ||
3111             (trb->ctrl & DWC3_TRB_CTRL_LST))
3112                 return 1;
3113
3114         return 0;
3115 }
3116
3117 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
3118                 struct dwc3_request *req, const struct dwc3_event_depevt *event,
3119                 int status)
3120 {
3121         struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
3122         struct scatterlist *sg = req->sg;
3123         struct scatterlist *s;
3124         unsigned int num_queued = req->num_queued_sgs;
3125         unsigned int i;
3126         int ret = 0;
3127
3128         for_each_sg(sg, s, num_queued, i) {
3129                 trb = &dep->trb_pool[dep->trb_dequeue];
3130
3131                 req->sg = sg_next(s);
3132                 req->num_queued_sgs--;
3133
3134                 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
3135                                 trb, event, status, true);
3136                 if (ret)
3137                         break;
3138         }
3139
3140         return ret;
3141 }
3142
3143 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
3144                 struct dwc3_request *req, const struct dwc3_event_depevt *event,
3145                 int status)
3146 {
3147         struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
3148
3149         return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
3150                         event, status, false);
3151 }
3152
3153 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
3154 {
3155         return req->num_pending_sgs == 0 && req->num_queued_sgs == 0;
3156 }
3157
3158 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
3159                 const struct dwc3_event_depevt *event,
3160                 struct dwc3_request *req, int status)
3161 {
3162         int ret;
3163
3164         if (req->request.num_mapped_sgs)
3165                 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
3166                                 status);
3167         else
3168                 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
3169                                 status);
3170
3171         req->request.actual = req->request.length - req->remaining;
3172
3173         if (!dwc3_gadget_ep_request_completed(req))
3174                 goto out;
3175
3176         if (req->needs_extra_trb) {
3177                 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
3178                                 status);
3179                 req->needs_extra_trb = false;
3180         }
3181
3182         dwc3_gadget_giveback(dep, req, status);
3183
3184 out:
3185         return ret;
3186 }
3187
3188 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
3189                 const struct dwc3_event_depevt *event, int status)
3190 {
3191         struct dwc3_request     *req;
3192         struct dwc3_request     *tmp;
3193
3194         list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
3195                 int ret;
3196
3197                 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
3198                                 req, status);
3199                 if (ret)
3200                         break;
3201         }
3202 }
3203
3204 static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep)
3205 {
3206         struct dwc3_request     *req;
3207         struct dwc3             *dwc = dep->dwc;
3208
3209         if (!dep->endpoint.desc || !dwc->pullups_connected ||
3210             !dwc->connected)
3211                 return false;
3212
3213         if (!list_empty(&dep->pending_list))
3214                 return true;
3215
3216         /*
3217          * We only need to check the first entry of the started list. We can
3218          * assume the completed requests are removed from the started list.
3219          */
3220         req = next_request(&dep->started_list);
3221         if (!req)
3222                 return false;
3223
3224         return !dwc3_gadget_ep_request_completed(req);
3225 }
3226
3227 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
3228                 const struct dwc3_event_depevt *event)
3229 {
3230         dep->frame_number = event->parameters;
3231 }
3232
3233 static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep,
3234                 const struct dwc3_event_depevt *event, int status)
3235 {
3236         struct dwc3             *dwc = dep->dwc;
3237         bool                    no_started_trb = true;
3238
3239         dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
3240
3241         if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3242                 goto out;
3243
3244         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3245                 list_empty(&dep->started_list) &&
3246                 (list_empty(&dep->pending_list) || status == -EXDEV))
3247                 dwc3_stop_active_transfer(dep, true, true);
3248         else if (dwc3_gadget_ep_should_continue(dep))
3249                 if (__dwc3_gadget_kick_transfer(dep) == 0)
3250                         no_started_trb = false;
3251
3252 out:
3253         /*
3254          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
3255          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
3256          */
3257         if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3258                 u32             reg;
3259                 int             i;
3260
3261                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
3262                         dep = dwc->eps[i];
3263
3264                         if (!(dep->flags & DWC3_EP_ENABLED))
3265                                 continue;
3266
3267                         if (!list_empty(&dep->started_list))
3268                                 return no_started_trb;
3269                 }
3270
3271                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3272                 reg |= dwc->u1u2;
3273                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3274
3275                 dwc->u1u2 = 0;
3276         }
3277
3278         return no_started_trb;
3279 }
3280
3281 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
3282                 const struct dwc3_event_depevt *event)
3283 {
3284         int status = 0;
3285
3286         if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
3287                 dwc3_gadget_endpoint_frame_from_event(dep, event);
3288
3289         if (event->status & DEPEVT_STATUS_BUSERR)
3290                 status = -ECONNRESET;
3291
3292         if (event->status & DEPEVT_STATUS_MISSED_ISOC)
3293                 status = -EXDEV;
3294
3295         dwc3_gadget_endpoint_trbs_complete(dep, event, status);
3296 }
3297
3298 static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep,
3299                 const struct dwc3_event_depevt *event)
3300 {
3301         int status = 0;
3302
3303         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3304
3305         if (event->status & DEPEVT_STATUS_BUSERR)
3306                 status = -ECONNRESET;
3307
3308         if (dwc3_gadget_endpoint_trbs_complete(dep, event, status))
3309                 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
3310 }
3311
3312 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
3313                 const struct dwc3_event_depevt *event)
3314 {
3315         dwc3_gadget_endpoint_frame_from_event(dep, event);
3316
3317         /*
3318          * The XferNotReady event is generated only once before the endpoint
3319          * starts. It will be generated again when END_TRANSFER command is
3320          * issued. For some controller versions, the XferNotReady event may be
3321          * generated while the END_TRANSFER command is still in process. Ignore
3322          * it and wait for the next XferNotReady event after the command is
3323          * completed.
3324          */
3325         if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3326                 return;
3327
3328         (void) __dwc3_gadget_start_isoc(dep);
3329 }
3330
3331 static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep *dep,
3332                 const struct dwc3_event_depevt *event)
3333 {
3334         u8 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
3335
3336         if (cmd != DWC3_DEPCMD_ENDTRANSFER)
3337                 return;
3338
3339         dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
3340         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3341         dwc3_gadget_ep_cleanup_cancelled_requests(dep);
3342
3343         if (dep->flags & DWC3_EP_PENDING_CLEAR_STALL) {
3344                 struct dwc3 *dwc = dep->dwc;
3345
3346                 dep->flags &= ~DWC3_EP_PENDING_CLEAR_STALL;
3347                 if (dwc3_send_clear_stall_ep_cmd(dep)) {
3348                         struct usb_ep *ep0 = &dwc->eps[0]->endpoint;
3349
3350                         dev_err(dwc->dev, "failed to clear STALL on %s\n", dep->name);
3351                         if (dwc->delayed_status)
3352                                 __dwc3_gadget_ep0_set_halt(ep0, 1);
3353                         return;
3354                 }
3355
3356                 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
3357                 if (dwc->delayed_status)
3358                         dwc3_ep0_send_delayed_status(dwc);
3359         }
3360
3361         if ((dep->flags & DWC3_EP_DELAY_START) &&
3362             !usb_endpoint_xfer_isoc(dep->endpoint.desc))
3363                 __dwc3_gadget_kick_transfer(dep);
3364
3365         dep->flags &= ~DWC3_EP_DELAY_START;
3366 }
3367
3368 static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep,
3369                 const struct dwc3_event_depevt *event)
3370 {
3371         struct dwc3 *dwc = dep->dwc;
3372
3373         if (event->status == DEPEVT_STREAMEVT_FOUND) {
3374                 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3375                 goto out;
3376         }
3377
3378         /* Note: NoStream rejection event param value is 0 and not 0xFFFF */
3379         switch (event->parameters) {
3380         case DEPEVT_STREAM_PRIME:
3381                 /*
3382                  * If the host can properly transition the endpoint state from
3383                  * idle to prime after a NoStream rejection, there's no need to
3384                  * force restarting the endpoint to reinitiate the stream. To
3385                  * simplify the check, assume the host follows the USB spec if
3386                  * it primed the endpoint more than once.
3387                  */
3388                 if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) {
3389                         if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED)
3390                                 dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM;
3391                         else
3392                                 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3393                 }
3394
3395                 break;
3396         case DEPEVT_STREAM_NOSTREAM:
3397                 if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) ||
3398                     !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) ||
3399                     !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE))
3400                         break;
3401
3402                 /*
3403                  * If the host rejects a stream due to no active stream, by the
3404                  * USB and xHCI spec, the endpoint will be put back to idle
3405                  * state. When the host is ready (buffer added/updated), it will
3406                  * prime the endpoint to inform the usb device controller. This
3407                  * triggers the device controller to issue ERDY to restart the
3408                  * stream. However, some hosts don't follow this and keep the
3409                  * endpoint in the idle state. No prime will come despite host
3410                  * streams are updated, and the device controller will not be
3411                  * triggered to generate ERDY to move the next stream data. To
3412                  * workaround this and maintain compatibility with various
3413                  * hosts, force to reinitate the stream until the host is ready
3414                  * instead of waiting for the host to prime the endpoint.
3415                  */
3416                 if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) {
3417                         unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME;
3418
3419                         dwc3_send_gadget_generic_command(dwc, cmd, dep->number);
3420                 } else {
3421                         dep->flags |= DWC3_EP_DELAY_START;
3422                         dwc3_stop_active_transfer(dep, true, true);
3423                         return;
3424                 }
3425                 break;
3426         }
3427
3428 out:
3429         dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM;
3430 }
3431
3432 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
3433                 const struct dwc3_event_depevt *event)
3434 {
3435         struct dwc3_ep          *dep;
3436         u8                      epnum = event->endpoint_number;
3437
3438         dep = dwc->eps[epnum];
3439
3440         if (!(dep->flags & DWC3_EP_ENABLED)) {
3441                 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
3442                         return;
3443
3444                 /* Handle only EPCMDCMPLT when EP disabled */
3445                 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
3446                         return;
3447         }
3448
3449         if (epnum == 0 || epnum == 1) {
3450                 dwc3_ep0_interrupt(dwc, event);
3451                 return;
3452         }
3453
3454         switch (event->endpoint_event) {
3455         case DWC3_DEPEVT_XFERINPROGRESS:
3456                 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
3457                 break;
3458         case DWC3_DEPEVT_XFERNOTREADY:
3459                 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
3460                 break;
3461         case DWC3_DEPEVT_EPCMDCMPLT:
3462                 dwc3_gadget_endpoint_command_complete(dep, event);
3463                 break;
3464         case DWC3_DEPEVT_XFERCOMPLETE:
3465                 dwc3_gadget_endpoint_transfer_complete(dep, event);
3466                 break;
3467         case DWC3_DEPEVT_STREAMEVT:
3468                 dwc3_gadget_endpoint_stream_event(dep, event);
3469                 break;
3470         case DWC3_DEPEVT_RXTXFIFOEVT:
3471                 break;
3472         }
3473 }
3474
3475 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
3476 {
3477         if (dwc->async_callbacks && dwc->gadget_driver->disconnect) {
3478                 spin_unlock(&dwc->lock);
3479                 dwc->gadget_driver->disconnect(dwc->gadget);
3480                 spin_lock(&dwc->lock);
3481         }
3482 }
3483
3484 static void dwc3_suspend_gadget(struct dwc3 *dwc)
3485 {
3486         if (dwc->async_callbacks && dwc->gadget_driver->suspend) {
3487                 spin_unlock(&dwc->lock);
3488                 dwc->gadget_driver->suspend(dwc->gadget);
3489                 spin_lock(&dwc->lock);
3490         }
3491 }
3492
3493 static void dwc3_resume_gadget(struct dwc3 *dwc)
3494 {
3495         if (dwc->async_callbacks && dwc->gadget_driver->resume) {
3496                 spin_unlock(&dwc->lock);
3497                 dwc->gadget_driver->resume(dwc->gadget);
3498                 spin_lock(&dwc->lock);
3499         }
3500 }
3501
3502 static void dwc3_reset_gadget(struct dwc3 *dwc)
3503 {
3504         if (!dwc->gadget_driver)
3505                 return;
3506
3507         if (dwc->async_callbacks && dwc->gadget->speed != USB_SPEED_UNKNOWN) {
3508                 spin_unlock(&dwc->lock);
3509                 usb_gadget_udc_reset(dwc->gadget, dwc->gadget_driver);
3510                 spin_lock(&dwc->lock);
3511         }
3512 }
3513
3514 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
3515         bool interrupt)
3516 {
3517         struct dwc3_gadget_ep_cmd_params params;
3518         u32 cmd;
3519         int ret;
3520
3521         if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) ||
3522             (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
3523                 return;
3524
3525         /*
3526          * NOTICE: We are violating what the Databook says about the
3527          * EndTransfer command. Ideally we would _always_ wait for the
3528          * EndTransfer Command Completion IRQ, but that's causing too
3529          * much trouble synchronizing between us and gadget driver.
3530          *
3531          * We have discussed this with the IP Provider and it was
3532          * suggested to giveback all requests here.
3533          *
3534          * Note also that a similar handling was tested by Synopsys
3535          * (thanks a lot Paul) and nothing bad has come out of it.
3536          * In short, what we're doing is issuing EndTransfer with
3537          * CMDIOC bit set and delay kicking transfer until the
3538          * EndTransfer command had completed.
3539          *
3540          * As of IP version 3.10a of the DWC_usb3 IP, the controller
3541          * supports a mode to work around the above limitation. The
3542          * software can poll the CMDACT bit in the DEPCMD register
3543          * after issuing a EndTransfer command. This mode is enabled
3544          * by writing GUCTL2[14]. This polling is already done in the
3545          * dwc3_send_gadget_ep_cmd() function so if the mode is
3546          * enabled, the EndTransfer command will have completed upon
3547          * returning from this function.
3548          *
3549          * This mode is NOT available on the DWC_usb31 IP.
3550          */
3551
3552         cmd = DWC3_DEPCMD_ENDTRANSFER;
3553         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
3554         cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
3555         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3556         memset(&params, 0, sizeof(params));
3557         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
3558         WARN_ON_ONCE(ret);
3559         dep->resource_index = 0;
3560
3561         /*
3562          * The END_TRANSFER command will cause the controller to generate a
3563          * NoStream Event, and it's not due to the host DP NoStream rejection.
3564          * Ignore the next NoStream event.
3565          */
3566         if (dep->stream_capable)
3567                 dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM;
3568
3569         if (!interrupt)
3570                 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3571         else
3572                 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
3573 }
3574
3575 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
3576 {
3577         u32 epnum;
3578
3579         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3580                 struct dwc3_ep *dep;
3581                 int ret;
3582
3583                 dep = dwc->eps[epnum];
3584                 if (!dep)
3585                         continue;
3586
3587                 if (!(dep->flags & DWC3_EP_STALL))
3588                         continue;
3589
3590                 dep->flags &= ~DWC3_EP_STALL;
3591
3592                 ret = dwc3_send_clear_stall_ep_cmd(dep);
3593                 WARN_ON_ONCE(ret);
3594         }
3595 }
3596
3597 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
3598 {
3599         int                     reg;
3600
3601         dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET);
3602
3603         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3604         reg &= ~DWC3_DCTL_INITU1ENA;
3605         reg &= ~DWC3_DCTL_INITU2ENA;
3606         dwc3_gadget_dctl_write_safe(dwc, reg);
3607
3608         dwc3_disconnect_gadget(dwc);
3609
3610         dwc->gadget->speed = USB_SPEED_UNKNOWN;
3611         dwc->setup_packet_pending = false;
3612         usb_gadget_set_state(dwc->gadget, USB_STATE_NOTATTACHED);
3613
3614         dwc->connected = false;
3615 }
3616
3617 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
3618 {
3619         u32                     reg;
3620
3621         /*
3622          * Ideally, dwc3_reset_gadget() would trigger the function
3623          * drivers to stop any active transfers through ep disable.
3624          * However, for functions which defer ep disable, such as mass
3625          * storage, we will need to rely on the call to stop active
3626          * transfers here, and avoid allowing of request queuing.
3627          */
3628         dwc->connected = false;
3629
3630         /*
3631          * WORKAROUND: DWC3 revisions <1.88a have an issue which
3632          * would cause a missing Disconnect Event if there's a
3633          * pending Setup Packet in the FIFO.
3634          *
3635          * There's no suggested workaround on the official Bug
3636          * report, which states that "unless the driver/application
3637          * is doing any special handling of a disconnect event,
3638          * there is no functional issue".
3639          *
3640          * Unfortunately, it turns out that we _do_ some special
3641          * handling of a disconnect event, namely complete all
3642          * pending transfers, notify gadget driver of the
3643          * disconnection, and so on.
3644          *
3645          * Our suggested workaround is to follow the Disconnect
3646          * Event steps here, instead, based on a setup_packet_pending
3647          * flag. Such flag gets set whenever we have a SETUP_PENDING
3648          * status for EP0 TRBs and gets cleared on XferComplete for the
3649          * same endpoint.
3650          *
3651          * Refers to:
3652          *
3653          * STAR#9000466709: RTL: Device : Disconnect event not
3654          * generated if setup packet pending in FIFO
3655          */
3656         if (DWC3_VER_IS_PRIOR(DWC3, 188A)) {
3657                 if (dwc->setup_packet_pending)
3658                         dwc3_gadget_disconnect_interrupt(dwc);
3659         }
3660
3661         dwc3_reset_gadget(dwc);
3662         /*
3663          * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
3664          * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW
3665          * needs to ensure that it sends "a DEPENDXFER command for any active
3666          * transfers."
3667          */
3668         dwc3_stop_active_transfers(dwc);
3669         dwc->connected = true;
3670
3671         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3672         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
3673         dwc3_gadget_dctl_write_safe(dwc, reg);
3674         dwc->test_mode = false;
3675         dwc3_clear_stall_all_ep(dwc);
3676
3677         /* Reset device address to zero */
3678         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3679         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
3680         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3681 }
3682
3683 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
3684 {
3685         struct dwc3_ep          *dep;
3686         int                     ret;
3687         u32                     reg;
3688         u8                      lanes = 1;
3689         u8                      speed;
3690
3691         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
3692         speed = reg & DWC3_DSTS_CONNECTSPD;
3693         dwc->speed = speed;
3694
3695         if (DWC3_IP_IS(DWC32))
3696                 lanes = DWC3_DSTS_CONNLANES(reg) + 1;
3697
3698         dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
3699
3700         /*
3701          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
3702          * each time on Connect Done.
3703          *
3704          * Currently we always use the reset value. If any platform
3705          * wants to set this to a different value, we need to add a
3706          * setting and update GCTL.RAMCLKSEL here.
3707          */
3708
3709         switch (speed) {
3710         case DWC3_DSTS_SUPERSPEED_PLUS:
3711                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3712                 dwc->gadget->ep0->maxpacket = 512;
3713                 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
3714
3715                 if (lanes > 1)
3716                         dwc->gadget->ssp_rate = USB_SSP_GEN_2x2;
3717                 else
3718                         dwc->gadget->ssp_rate = USB_SSP_GEN_2x1;
3719                 break;
3720         case DWC3_DSTS_SUPERSPEED:
3721                 /*
3722                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
3723                  * would cause a missing USB3 Reset event.
3724                  *
3725                  * In such situations, we should force a USB3 Reset
3726                  * event by calling our dwc3_gadget_reset_interrupt()
3727                  * routine.
3728                  *
3729                  * Refers to:
3730                  *
3731                  * STAR#9000483510: RTL: SS : USB3 reset event may
3732                  * not be generated always when the link enters poll
3733                  */
3734                 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
3735                         dwc3_gadget_reset_interrupt(dwc);
3736
3737                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3738                 dwc->gadget->ep0->maxpacket = 512;
3739                 dwc->gadget->speed = USB_SPEED_SUPER;
3740
3741                 if (lanes > 1) {
3742                         dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
3743                         dwc->gadget->ssp_rate = USB_SSP_GEN_1x2;
3744                 }
3745                 break;
3746         case DWC3_DSTS_HIGHSPEED:
3747                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3748                 dwc->gadget->ep0->maxpacket = 64;
3749                 dwc->gadget->speed = USB_SPEED_HIGH;
3750                 break;
3751         case DWC3_DSTS_FULLSPEED:
3752                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
3753                 dwc->gadget->ep0->maxpacket = 64;
3754                 dwc->gadget->speed = USB_SPEED_FULL;
3755                 break;
3756         }
3757
3758         dwc->eps[1]->endpoint.maxpacket = dwc->gadget->ep0->maxpacket;
3759
3760         /* Enable USB2 LPM Capability */
3761
3762         if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) &&
3763             !dwc->usb2_gadget_lpm_disable &&
3764             (speed != DWC3_DSTS_SUPERSPEED) &&
3765             (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
3766                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3767                 reg |= DWC3_DCFG_LPM_CAP;
3768                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3769
3770                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3771                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
3772
3773                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
3774                                             (dwc->is_utmi_l1_suspend << 4));
3775
3776                 /*
3777                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
3778                  * DCFG.LPMCap is set, core responses with an ACK and the
3779                  * BESL value in the LPM token is less than or equal to LPM
3780                  * NYET threshold.
3781                  */
3782                 WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum,
3783                                 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
3784
3785                 if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A))
3786                         reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
3787
3788                 dwc3_gadget_dctl_write_safe(dwc, reg);
3789         } else {
3790                 if (dwc->usb2_gadget_lpm_disable) {
3791                         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3792                         reg &= ~DWC3_DCFG_LPM_CAP;
3793                         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3794                 }
3795
3796                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3797                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
3798                 dwc3_gadget_dctl_write_safe(dwc, reg);
3799         }
3800
3801         dep = dwc->eps[0];
3802         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3803         if (ret) {
3804                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3805                 return;
3806         }
3807
3808         dep = dwc->eps[1];
3809         ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
3810         if (ret) {
3811                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3812                 return;
3813         }
3814
3815         /*
3816          * Configure PHY via GUSB3PIPECTLn if required.
3817          *
3818          * Update GTXFIFOSIZn
3819          *
3820          * In both cases reset values should be sufficient.
3821          */
3822 }
3823
3824 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
3825 {
3826         /*
3827          * TODO take core out of low power mode when that's
3828          * implemented.
3829          */
3830
3831         if (dwc->async_callbacks && dwc->gadget_driver->resume) {
3832                 spin_unlock(&dwc->lock);
3833                 dwc->gadget_driver->resume(dwc->gadget);
3834                 spin_lock(&dwc->lock);
3835         }
3836 }
3837
3838 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
3839                 unsigned int evtinfo)
3840 {
3841         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
3842         unsigned int            pwropt;
3843
3844         /*
3845          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
3846          * Hibernation mode enabled which would show up when device detects
3847          * host-initiated U3 exit.
3848          *
3849          * In that case, device will generate a Link State Change Interrupt
3850          * from U3 to RESUME which is only necessary if Hibernation is
3851          * configured in.
3852          *
3853          * There are no functional changes due to such spurious event and we
3854          * just need to ignore it.
3855          *
3856          * Refers to:
3857          *
3858          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
3859          * operational mode
3860          */
3861         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
3862         if (DWC3_VER_IS_PRIOR(DWC3, 250A) &&
3863                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
3864                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
3865                                 (next == DWC3_LINK_STATE_RESUME)) {
3866                         return;
3867                 }
3868         }
3869
3870         /*
3871          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
3872          * on the link partner, the USB session might do multiple entry/exit
3873          * of low power states before a transfer takes place.
3874          *
3875          * Due to this problem, we might experience lower throughput. The
3876          * suggested workaround is to disable DCTL[12:9] bits if we're
3877          * transitioning from U1/U2 to U0 and enable those bits again
3878          * after a transfer completes and there are no pending transfers
3879          * on any of the enabled endpoints.
3880          *
3881          * This is the first half of that workaround.
3882          *
3883          * Refers to:
3884          *
3885          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
3886          * core send LGO_Ux entering U0
3887          */
3888         if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3889                 if (next == DWC3_LINK_STATE_U0) {
3890                         u32     u1u2;
3891                         u32     reg;
3892
3893                         switch (dwc->link_state) {
3894                         case DWC3_LINK_STATE_U1:
3895                         case DWC3_LINK_STATE_U2:
3896                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3897                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
3898                                                 | DWC3_DCTL_ACCEPTU2ENA
3899                                                 | DWC3_DCTL_INITU1ENA
3900                                                 | DWC3_DCTL_ACCEPTU1ENA);
3901
3902                                 if (!dwc->u1u2)
3903                                         dwc->u1u2 = reg & u1u2;
3904
3905                                 reg &= ~u1u2;
3906
3907                                 dwc3_gadget_dctl_write_safe(dwc, reg);
3908                                 break;
3909                         default:
3910                                 /* do nothing */
3911                                 break;
3912                         }
3913                 }
3914         }
3915
3916         switch (next) {
3917         case DWC3_LINK_STATE_U1:
3918                 if (dwc->speed == USB_SPEED_SUPER)
3919                         dwc3_suspend_gadget(dwc);
3920                 break;
3921         case DWC3_LINK_STATE_U2:
3922         case DWC3_LINK_STATE_U3:
3923                 dwc3_suspend_gadget(dwc);
3924                 break;
3925         case DWC3_LINK_STATE_RESUME:
3926                 dwc3_resume_gadget(dwc);
3927                 break;
3928         default:
3929                 /* do nothing */
3930                 break;
3931         }
3932
3933         dwc->link_state = next;
3934 }
3935
3936 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
3937                                           unsigned int evtinfo)
3938 {
3939         enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3940
3941         if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
3942                 dwc3_suspend_gadget(dwc);
3943
3944         dwc->link_state = next;
3945 }
3946
3947 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
3948                 unsigned int evtinfo)
3949 {
3950         unsigned int is_ss = evtinfo & BIT(4);
3951
3952         /*
3953          * WORKAROUND: DWC3 revison 2.20a with hibernation support
3954          * have a known issue which can cause USB CV TD.9.23 to fail
3955          * randomly.
3956          *
3957          * Because of this issue, core could generate bogus hibernation
3958          * events which SW needs to ignore.
3959          *
3960          * Refers to:
3961          *
3962          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3963          * Device Fallback from SuperSpeed
3964          */
3965         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
3966                 return;
3967
3968         /* enter hibernation here */
3969 }
3970
3971 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
3972                 const struct dwc3_event_devt *event)
3973 {
3974         switch (event->type) {
3975         case DWC3_DEVICE_EVENT_DISCONNECT:
3976                 dwc3_gadget_disconnect_interrupt(dwc);
3977                 break;
3978         case DWC3_DEVICE_EVENT_RESET:
3979                 dwc3_gadget_reset_interrupt(dwc);
3980                 break;
3981         case DWC3_DEVICE_EVENT_CONNECT_DONE:
3982                 dwc3_gadget_conndone_interrupt(dwc);
3983                 break;
3984         case DWC3_DEVICE_EVENT_WAKEUP:
3985                 dwc3_gadget_wakeup_interrupt(dwc);
3986                 break;
3987         case DWC3_DEVICE_EVENT_HIBER_REQ:
3988                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3989                                         "unexpected hibernation event\n"))
3990                         break;
3991
3992                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3993                 break;
3994         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3995                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3996                 break;
3997         case DWC3_DEVICE_EVENT_SUSPEND:
3998                 /* It changed to be suspend event for version 2.30a and above */
3999                 if (!DWC3_VER_IS_PRIOR(DWC3, 230A)) {
4000                         /*
4001                          * Ignore suspend event until the gadget enters into
4002                          * USB_STATE_CONFIGURED state.
4003                          */
4004                         if (dwc->gadget->state >= USB_STATE_CONFIGURED)
4005                                 dwc3_gadget_suspend_interrupt(dwc,
4006                                                 event->event_info);
4007                 }
4008                 break;
4009         case DWC3_DEVICE_EVENT_SOF:
4010         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
4011         case DWC3_DEVICE_EVENT_CMD_CMPL:
4012         case DWC3_DEVICE_EVENT_OVERFLOW:
4013                 break;
4014         default:
4015                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
4016         }
4017 }
4018
4019 static void dwc3_process_event_entry(struct dwc3 *dwc,
4020                 const union dwc3_event *event)
4021 {
4022         trace_dwc3_event(event->raw, dwc);
4023
4024         if (!event->type.is_devspec)
4025                 dwc3_endpoint_interrupt(dwc, &event->depevt);
4026         else if (event->type.type == DWC3_EVENT_TYPE_DEV)
4027                 dwc3_gadget_interrupt(dwc, &event->devt);
4028         else
4029                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
4030 }
4031
4032 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
4033 {
4034         struct dwc3 *dwc = evt->dwc;
4035         irqreturn_t ret = IRQ_NONE;
4036         int left;
4037         u32 reg;
4038
4039         left = evt->count;
4040
4041         if (!(evt->flags & DWC3_EVENT_PENDING))
4042                 return IRQ_NONE;
4043
4044         while (left > 0) {
4045                 union dwc3_event event;
4046
4047                 event.raw = *(u32 *) (evt->cache + evt->lpos);
4048
4049                 dwc3_process_event_entry(dwc, &event);
4050
4051                 /*
4052                  * FIXME we wrap around correctly to the next entry as
4053                  * almost all entries are 4 bytes in size. There is one
4054                  * entry which has 12 bytes which is a regular entry
4055                  * followed by 8 bytes data. ATM I don't know how
4056                  * things are organized if we get next to the a
4057                  * boundary so I worry about that once we try to handle
4058                  * that.
4059                  */
4060                 evt->lpos = (evt->lpos + 4) % evt->length;
4061                 left -= 4;
4062         }
4063
4064         evt->count = 0;
4065         evt->flags &= ~DWC3_EVENT_PENDING;
4066         ret = IRQ_HANDLED;
4067
4068         /* Unmask interrupt */
4069         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
4070         reg &= ~DWC3_GEVNTSIZ_INTMASK;
4071         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
4072
4073         if (dwc->imod_interval) {
4074                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
4075                 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
4076         }
4077
4078         return ret;
4079 }
4080
4081 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
4082 {
4083         struct dwc3_event_buffer *evt = _evt;
4084         struct dwc3 *dwc = evt->dwc;
4085         unsigned long flags;
4086         irqreturn_t ret = IRQ_NONE;
4087
4088         spin_lock_irqsave(&dwc->lock, flags);
4089         ret = dwc3_process_event_buf(evt);
4090         spin_unlock_irqrestore(&dwc->lock, flags);
4091
4092         return ret;
4093 }
4094
4095 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
4096 {
4097         struct dwc3 *dwc = evt->dwc;
4098         u32 amount;
4099         u32 count;
4100         u32 reg;
4101
4102         if (pm_runtime_suspended(dwc->dev)) {
4103                 pm_runtime_get(dwc->dev);
4104                 disable_irq_nosync(dwc->irq_gadget);
4105                 dwc->pending_events = true;
4106                 return IRQ_HANDLED;
4107         }
4108
4109         /*
4110          * With PCIe legacy interrupt, test shows that top-half irq handler can
4111          * be called again after HW interrupt deassertion. Check if bottom-half
4112          * irq event handler completes before caching new event to prevent
4113          * losing events.
4114          */
4115         if (evt->flags & DWC3_EVENT_PENDING)
4116                 return IRQ_HANDLED;
4117
4118         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
4119         count &= DWC3_GEVNTCOUNT_MASK;
4120         if (!count)
4121                 return IRQ_NONE;
4122
4123         evt->count = count;
4124         evt->flags |= DWC3_EVENT_PENDING;
4125
4126         /* Mask interrupt */
4127         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
4128         reg |= DWC3_GEVNTSIZ_INTMASK;
4129         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
4130
4131         amount = min(count, evt->length - evt->lpos);
4132         memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
4133
4134         if (amount < count)
4135                 memcpy(evt->cache, evt->buf, count - amount);
4136
4137         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
4138
4139         return IRQ_WAKE_THREAD;
4140 }
4141
4142 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
4143 {
4144         struct dwc3_event_buffer        *evt = _evt;
4145
4146         return dwc3_check_event_buf(evt);
4147 }
4148
4149 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
4150 {
4151         struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
4152         int irq;
4153
4154         irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
4155         if (irq > 0)
4156                 goto out;
4157
4158         if (irq == -EPROBE_DEFER)
4159                 goto out;
4160
4161         irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
4162         if (irq > 0)
4163                 goto out;
4164
4165         if (irq == -EPROBE_DEFER)
4166                 goto out;
4167
4168         irq = platform_get_irq(dwc3_pdev, 0);
4169         if (irq > 0)
4170                 goto out;
4171
4172         if (!irq)
4173                 irq = -EINVAL;
4174
4175 out:
4176         return irq;
4177 }
4178
4179 static void dwc_gadget_release(struct device *dev)
4180 {
4181         struct usb_gadget *gadget = container_of(dev, struct usb_gadget, dev);
4182
4183         kfree(gadget);
4184 }
4185
4186 /**
4187  * dwc3_gadget_init - initializes gadget related registers
4188  * @dwc: pointer to our controller context structure
4189  *
4190  * Returns 0 on success otherwise negative errno.
4191  */
4192 int dwc3_gadget_init(struct dwc3 *dwc)
4193 {
4194         int ret;
4195         int irq;
4196         struct device *dev;
4197
4198         irq = dwc3_gadget_get_irq(dwc);
4199         if (irq < 0) {
4200                 ret = irq;
4201                 goto err0;
4202         }
4203
4204         dwc->irq_gadget = irq;
4205
4206         dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
4207                                           sizeof(*dwc->ep0_trb) * 2,
4208                                           &dwc->ep0_trb_addr, GFP_KERNEL);
4209         if (!dwc->ep0_trb) {
4210                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
4211                 ret = -ENOMEM;
4212                 goto err0;
4213         }
4214
4215         dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
4216         if (!dwc->setup_buf) {
4217                 ret = -ENOMEM;
4218                 goto err1;
4219         }
4220
4221         dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
4222                         &dwc->bounce_addr, GFP_KERNEL);
4223         if (!dwc->bounce) {
4224                 ret = -ENOMEM;
4225                 goto err2;
4226         }
4227
4228         init_completion(&dwc->ep0_in_setup);
4229         dwc->gadget = kzalloc(sizeof(struct usb_gadget), GFP_KERNEL);
4230         if (!dwc->gadget) {
4231                 ret = -ENOMEM;
4232                 goto err3;
4233         }
4234
4235
4236         usb_initialize_gadget(dwc->dev, dwc->gadget, dwc_gadget_release);
4237         dev                             = &dwc->gadget->dev;
4238         dev->platform_data              = dwc;
4239         dwc->gadget->ops                = &dwc3_gadget_ops;
4240         dwc->gadget->speed              = USB_SPEED_UNKNOWN;
4241         dwc->gadget->ssp_rate           = USB_SSP_GEN_UNKNOWN;
4242         dwc->gadget->sg_supported       = true;
4243         dwc->gadget->name               = "dwc3-gadget";
4244         dwc->gadget->lpm_capable        = !dwc->usb2_gadget_lpm_disable;
4245
4246         /*
4247          * FIXME We might be setting max_speed to <SUPER, however versions
4248          * <2.20a of dwc3 have an issue with metastability (documented
4249          * elsewhere in this driver) which tells us we can't set max speed to
4250          * anything lower than SUPER.
4251          *
4252          * Because gadget.max_speed is only used by composite.c and function
4253          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
4254          * to happen so we avoid sending SuperSpeed Capability descriptor
4255          * together with our BOS descriptor as that could confuse host into
4256          * thinking we can handle super speed.
4257          *
4258          * Note that, in fact, we won't even support GetBOS requests when speed
4259          * is less than super speed because we don't have means, yet, to tell
4260          * composite.c that we are USB 2.0 + LPM ECN.
4261          */
4262         if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
4263             !dwc->dis_metastability_quirk)
4264                 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
4265                                 dwc->revision);
4266
4267         dwc->gadget->max_speed          = dwc->maximum_speed;
4268         dwc->gadget->max_ssp_rate       = dwc->max_ssp_rate;
4269
4270         /*
4271          * REVISIT: Here we should clear all pending IRQs to be
4272          * sure we're starting from a well known location.
4273          */
4274
4275         ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
4276         if (ret)
4277                 goto err4;
4278
4279         ret = usb_add_gadget(dwc->gadget);
4280         if (ret) {
4281                 dev_err(dwc->dev, "failed to add gadget\n");
4282                 goto err5;
4283         }
4284
4285         if (DWC3_IP_IS(DWC32) && dwc->maximum_speed == USB_SPEED_SUPER_PLUS)
4286                 dwc3_gadget_set_ssp_rate(dwc->gadget, dwc->max_ssp_rate);
4287         else
4288                 dwc3_gadget_set_speed(dwc->gadget, dwc->maximum_speed);
4289
4290         return 0;
4291
4292 err5:
4293         dwc3_gadget_free_endpoints(dwc);
4294 err4:
4295         usb_put_gadget(dwc->gadget);
4296         dwc->gadget = NULL;
4297 err3:
4298         dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4299                         dwc->bounce_addr);
4300
4301 err2:
4302         kfree(dwc->setup_buf);
4303
4304 err1:
4305         dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4306                         dwc->ep0_trb, dwc->ep0_trb_addr);
4307
4308 err0:
4309         return ret;
4310 }
4311
4312 /* -------------------------------------------------------------------------- */
4313
4314 void dwc3_gadget_exit(struct dwc3 *dwc)
4315 {
4316         if (!dwc->gadget)
4317                 return;
4318
4319         usb_del_gadget(dwc->gadget);
4320         dwc3_gadget_free_endpoints(dwc);
4321         usb_put_gadget(dwc->gadget);
4322         dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4323                           dwc->bounce_addr);
4324         kfree(dwc->setup_buf);
4325         dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4326                           dwc->ep0_trb, dwc->ep0_trb_addr);
4327 }
4328
4329 int dwc3_gadget_suspend(struct dwc3 *dwc)
4330 {
4331         if (!dwc->gadget_driver)
4332                 return 0;
4333
4334         dwc3_gadget_run_stop(dwc, false, false);
4335         dwc3_disconnect_gadget(dwc);
4336         __dwc3_gadget_stop(dwc);
4337
4338         return 0;
4339 }
4340
4341 int dwc3_gadget_resume(struct dwc3 *dwc)
4342 {
4343         int                     ret;
4344
4345         if (!dwc->gadget_driver)
4346                 return 0;
4347
4348         ret = __dwc3_gadget_start(dwc);
4349         if (ret < 0)
4350                 goto err0;
4351
4352         ret = dwc3_gadget_run_stop(dwc, true, false);
4353         if (ret < 0)
4354                 goto err1;
4355
4356         return 0;
4357
4358 err1:
4359         __dwc3_gadget_stop(dwc);
4360
4361 err0:
4362         return ret;
4363 }
4364
4365 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
4366 {
4367         if (dwc->pending_events) {
4368                 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
4369                 dwc->pending_events = false;
4370                 enable_irq(dwc->irq_gadget);
4371         }
4372 }